A manufacturing method of a copper pillar with an anti-welding layer window of an FCCSP carrier plate and the FCCSP carrier plate

Abstract

The application discloses a manufacturing method of a windowed copper column of a solder resist layer of an FCCSP carrier plate and the FCCSP carrier plate, and comprises the following steps: providing a substrate; coating a photosensitive ink on the surface of the substrate, and sequentially performing pre-baking, exposure, development and post-baking treatment; processing a blind hole with an inner diameter less than 20 um by UV laser in a spiral scanning track and exposing a copper circuit layer on the substrate; performing plasma cleaning on the blind hole; sequentially performing whole-hole processing, surface adjustment treatment, colloid palladium activation and chemical copper plating on the cleaned blind hole, wherein the chemical solution for the surface adjustment treatment comprises a cationic surfactant and an organic silane coupling agent; attaching a photosensitive dry film on the surface of the copper plating layer; and forming a copper column bump in the electroplating window by using a gantry type electroplating device in cooperation with a pulse power source. The application forms a blind hole with a diameter less than 20 um on the solder resist layer by using a UV laser spiral scanning track, and combines a special chemical copper plating process, so that the precision of the micro windowing and the coverage rate of the surface chemical copper plating of the solder resist layer are improved.

Description

Technical Field

[0001] This invention relates to the field of packaging substrate technology, specifically to a method for manufacturing a solder resist layer with a copper pillar and an FCCSP carrier, as well as the FCCSP carrier itself. Background Technology

[0002] In the manufacturing process of FCCSP substrate, copper pillar bumps serve as the interconnection structure between the chip and the substrate. The spacing between copper pillar bumps has been reduced to 40um or even smaller. Therefore, higher requirements are placed on the solder mask opening, the coverage of chemical copper plating, and the uniformity of copper pillar electroplating in the process.

[0003] An existing invention patent with publication number CN120914104A discloses a method for processing copper pillar bumps in FCCSP, which uses plasma to roughen the solder resist layer to form a "honeycomb structure," and then uses this roughened surface for chemical copper deposition. However, the plasma roughening in this method is a physical bombardment process, and the uniformity of the processing is greatly affected by the power density distribution of the equipment. For high-density micro-windowed areas, uneven roughening is prone to occur, resulting in poor local copper coverage or differences in adhesion.

[0004] The existing invention patent with publication number CN121487591A proposes a route of first exposing, developing, and opening windows, and then laser correction. However, this method is complicated. Due to the light diffraction effect during ultraviolet exposure and the effects of resin swelling and chemical diffusion during development, the window size is enlarged to a certain extent, making it difficult to stably meet the sub-20um processing requirements. Furthermore, there is a risk of loss of alignment accuracy between the two positioning steps.

[0005] Therefore, the current FCCSP substrate still has shortcomings in achieving small solder resist openings and high-quality chemical copper plating, making it difficult to improve the processing requirements of uniform copper pillar plating in small areas. Summary of the Invention

[0006] To overcome the above shortcomings, the purpose of this invention is to provide a method for manufacturing copper pillars with open windows in the solder resist layer of an FCCSP carrier board, as well as the FCCSP carrier board itself. This invention uses a UV laser spiral scanning trajectory to form blind holes smaller than 20 μm on the solder resist layer, and combines this with a special chemical copper plating process to improve the precision of the micro-openings and the coverage of the chemical copper plating on the surface of the solder resist layer.

[0007] Technical solution: This invention discloses a method for manufacturing a copper column with a solder resist layer for an FCCSP carrier plate, comprising the following steps: A substrate is provided, wherein the substrate has a copper circuit layer; Photosensitive ink is coated on the surface of the substrate, and the photosensitive ink is subjected to pre-baking, exposure, development and post-baking processes in sequence to form a solder resist layer covering the surface of the substrate and to form solder resist openings through development. The solder resist layer in the area corresponding to the solder resist opening is ablated using a UV laser. The UV laser processes the blind hole with an inner diameter of less than 20 μm using a spiral scanning trajectory and exposes the copper circuit layer on the substrate. Plasma cleaning is performed on the bottom and sidewalls of the blind hole to remove the adhesive residue left by UV laser ablation. The cleaned blind holes are sequentially subjected to hole shaping, surface conditioning, colloidal palladium activation, and chemical copper plating, thereby forming a continuous copper plating layer on the inner wall of the blind holes and the surface of the solder resist layer. The chemical solution used for surface conditioning includes cationic surfactants and organosilane coupling agents, thereby forming an activation layer with colloidal palladium adsorption capacity. A photosensitive dry film is attached to the surface of the copper plating layer, and then exposed and developed to form an electroplating window. A gantry-type electroplating device, in conjunction with a pulse power supply, forms copper column protrusions within the electroplating window. The photosensitive dry film is removed and the exposed copper plating layer is etched away to form the independent copper pillar bumps.

[0008] Furthermore, in the plasma cleaning step for blind holes, a mixture of oxygen and trace amounts of fluorine-based gas is used as the working gas, the plasma cleaning power is 1000-2000W, and the processing time is 10-20 minutes.

[0009] Furthermore, the chemical solution used for the surface conditioning treatment includes a cationic surfactant at a concentration of 2-8 g / L and an organosilane coupling agent at a concentration of 0.5-2.0 wt%.

[0010] Furthermore, the thickness of the copper plating layer formed by the chemical copper plating is 0.3-0.8 μm.

[0011] Furthermore, in the step of “forming copper pillar bumps in the electroplating window using a gantry electroplating device in conjunction with a pulse power supply”, the electroplating solution used for electroplating includes 60-90 g / L copper sulfate, 180-240 g / L sulfuric acid and 40-70 ppm chloride ions.

[0012] Furthermore, in the step of "forming copper pillar bumps in the electroplating window using a gantry electroplating device in conjunction with a pulse power supply", electroplating is performed using a stepped current ramp method. The initial current density of electroplating is 0.2 ASD, which is gradually increased to 1.5-2.0 ASD. The pulse power supply outputs positive and negative pulses. The width of the positive pulse is 1-10 ms, and the width of the negative pulse is 0.5-2 ms.

[0013] Furthermore, in the step of "forming copper pillar protrusions in the electroplating window using a gantry electroplating device in conjunction with a pulse power supply", the electroplating solution also includes a leveling agent and a refining agent, and the ratio of the leveling agent to the refining agent is 1:2-1:3.

[0014] Furthermore, in the step of "removing the photosensitive dry film", an alkaline stripping solution is used to remove the photosensitive dry film, wherein the stripping solution is a sodium hydroxide solution with a mass concentration of 3%-5%.

[0015] Furthermore, the etching solution used to "remove the exposed copper plating layer" includes copper chloride and hydrochloric acid, and etching is performed by spraying or immersion at a temperature of 50-60°C for a time of 1-3 minutes.

[0016] The present invention also discloses an FCCSP carrier board, which is manufactured by any one of the manufacturing methods described above.

[0017] The beneficial effects of this invention are as follows: (1) The present invention uses a UV laser with a wavelength of 355nm to ablate the cured solder resist layer and forms small blind holes by spiral scanning trajectory. It achieves high-precision window opening with a diameter of less than 20um in a single process, avoiding the accumulation of multiple errors caused by secondary laser correction after development and opening, and improving the consistency of window size.

[0018] (2) The present invention uses a surface conditioning chemical solution including cationic surfactant and organosilane coupling agent to activate the surface of the solder resist layer. A uniform and stable active layer is constructed on the surface of the solder resist layer by chemical means rather than physical roughening, which improves the adsorption capacity of colloidal palladium on the surface of the solder resist layer and the sidewall of the blind hole, solves the problem of difficult adsorption of colloidal palladium on the surface of the solder resist layer, and realizes continuous and uniform chemical copper conductive seed layer deposition.

[0019] (3) The present invention uses gantry electroplating combined with pulse power supply and cathode swing mode to electroplat copper pillars, optimizes the current distribution and ion mass transfer process under micro-windowing, reduces the risk of local current concentration, improves the uniformity of copper pillar growth, and makes the formed copper pillar bumps have high uniformity and structural density. Attached Figure Description

[0020] The accompanying drawings described herein are for illustrative purposes only and are not intended to limit the scope of the invention in any way. Furthermore, the shapes and proportions of the components in the drawings are merely illustrative to aid in understanding the invention and are not intended to specifically limit the shapes and proportions of the components. Those skilled in the art, guided by the teachings of this invention, can select various possible shapes and proportions to implement the invention according to specific circumstances. In the drawings: Figure 1 This is a schematic diagram of the substrate structure in the FCCSP carrier plate described in this invention; Figure 2 This is a schematic diagram illustrating the formation of a solder resist layer and solder resist openings on the substrate surface as described in this invention; Figure 3 This is a schematic diagram of the carrier plate structure for forming blind holes by laser ablation according to the present invention; Figure 4 This is a schematic diagram of the carrier plate structure after plasma cleaning of blind holes according to the present invention; Figure 5 This is a schematic diagram of the carrier board structure for forming a copper plating layer after hole preparation, surface adjustment, colloidal palladium activation, and chemical copper plating as described in this invention. Figure 6 This is a schematic diagram of the carrier board structure after attaching a photosensitive dry film to the surface of the copper plating layer according to the present invention. Figure 7 This is a schematic diagram of the carrier plate structure after the photosensitive dry film has been exposed and developed according to the present invention. Figure 8 This is a schematic diagram of the carrier plate structure after the copper column protrusions are formed in the electroplating window using a gantry-type electroplating device as described in this invention. Figure 9 This is a schematic diagram of the carrier plate structure for removing the photosensitive dry film according to the present invention; Figure 10 This is a schematic diagram of the carrier board structure for the etched copper plating layer described in this invention; Figure 11 This is a schematic diagram illustrating the working principle of UV laser ablation and blind hole formation described in this invention. Figure 12 This is a schematic diagram of the UV laser spiral scanning trajectory described in this invention; Figure 13 This is a schematic diagram of the process of electroplating copper using the gantry electroplating device described in this invention in conjunction with a pulse power supply.

[0021] In the diagram: 1. Substrate; 11. Copper circuit layer; 2. Solder resist layer; 21. Solder resist opening; 22. Blind via; 3. Copper plating layer; 4. Photosensitive dry film; 41. Electroplating window; 5. Copper pillar bump; 6. Gantry electroplating device. Detailed Implementation

[0022] The present invention will be further explained below with reference to the accompanying drawings and specific embodiments.

[0023] In the description of this invention, it should be understood that the terms "upper," "lower," "front," "rear," "left," "right," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances. The embodiments of this invention will now be described according to its overall structure.

[0024] like Figures 1 to 13 As shown, this invention discloses a method for manufacturing a windowed copper pillar in the solder resist layer 2 of an FCCSP carrier board, comprising the following steps: A substrate 1 is provided, wherein the substrate 1 has a copper circuit layer 11, which serves as a subsequent electrical connection structure and is located on one side of the substrate 1. The substrate 1 is then cut, and burrs on the surface of the substrate 1 are removed. The surface of the substrate 1 is then cleaned to ensure that the surface of the substrate 1 has good adhesion to the layer structures generated in subsequent processes.

[0025] A photosensitive ink is coated onto the surface of the substrate 1. The photosensitive ink is then subjected to pre-baking, exposure, development, and post-baking processes to form a solder resist layer 2 covering the surface of the substrate 1 and solder resist openings 21 formed through development. It is understood that the photosensitive ink is coated on the side of the substrate 1 with the copper circuit layer 11, forming an ink layer with a thickness of 15-25 μm. After coating, the ink layer is pre-baked to allow for preliminary curing of the photosensitive ink, improving the adhesion between the photosensitive ink and the substrate 1. Then, the ink layer is exposed using an exposure device; preferably, the exposure energy is 200 mJ / cm². 2 Then, a sodium carbonate solution with a mass concentration of 0.8-1.2% is used for development to remove the ink layer in the unexposed areas, thereby forming a cured solder resist layer 2 and the pre-set solder resist opening area 21 on the solder resist layer 2. After development, the substrate 1 with the solder resist layer 2 is subjected to a post-bake treatment at a temperature of 150-180℃, so that the solder resist layer 2 can have high mechanical strength.

[0026] The solder resist layer 2 in the area corresponding to the solder resist opening 21 is ablated using a UV laser. The UV laser processes the area with a spiral scanning trajectory to form a blind via 22 with an inner diameter of less than 20 μm, exposing the copper circuit layer 11 on the substrate 1. Preferably, the UV laser is a 355 nm ultraviolet laser. UV lasers are cold processing methods with high photon energy, which can directly break the chemical bonds in the resin molecules of the solder resist layer 2, allowing the solder resist layer 2 to be removed by photochemical decomposition. Since the ablation process of the solder resist layer 2 in this application mainly relies on molecular bond breaking rather than thermal melting, the heat-affected zone is small, thereby reducing the possibility of problems such as resin carbonization, via wall melting, and edge deformation. It also improves the processing accuracy, ultimately forming a blind via 22 and exposing the bottom copper circuit layer 11. The UV laser ablates the resist layer 2 according to a spiral scanning trajectory. The spiral scanning trajectory is the scanning path formed by the laser spot continuously rotating around the center of the target window and gradually moving radially. This application uses a spiral scanning method instead of the traditional single-point repeated ablation method, so that the laser energy gradually covers the area to be processed along the continuous path, thereby improving the size consistency and hole wall quality of fine windows with an inner diameter of less than 20um.

[0027] Plasma cleaning is performed on the bottom and sidewalls of the blind via 22 to remove residual adhesive residue after UV laser ablation. When the UV laser ablates the solder resist layer 2, it inevitably produces debris and adhesive residue. If not cleaned promptly, this residue will settle at the bottom of the blind via 22, affecting subsequent copper plating. Therefore, plasma cleaning is used to clean the inner walls and bottom of the blind via 22, removing surface residue to facilitate subsequent operations.

[0028] Furthermore, during plasma cleaning of the blind hole 22, a mixture of oxygen and trace amounts of fluorine-based gas is used as the working gas, with oxygen as the primary reactant and the trace amounts of fluorine-based gas as the auxiliary activating gas. The active oxygen free radicals generated by the oxygen plasma react with the resin debris and adhesive residue produced after the solder resist layer 2 is ablated, and the trace amounts of fluorine-based active particles further break down the organic polymer, thereby improving the removal efficiency of residual adhesive residue on the inner wall of the blind hole 22 and enhancing the cleanliness of the inside of the blind hole 22. The plasma cleaning power is preferably 1000–2000W to ensure thorough removal of residues. The plasma cleaning time is preferably 10–20 minutes to effectively remove residues from the blind hole 22 while maintaining the stability of the hole wall morphology. When the cleaning time is less than 10 minutes, the residual adhesive residue inside the blind hole 22 may not be completely removed; when the processing time exceeds 20 minutes, the improvement in cleaning effect is limited, but it may additionally increase the surface roughness of the solder resist layer 2.

[0029] The cleaned blind vias 22 are sequentially subjected to via shaping, surface conditioning, colloidal palladium activation, and chemical copper plating, thereby forming a continuous copper plating layer 3 on the inner wall of the blind vias 22 and the surface of the solder resist layer 2. The chemical solution used for surface conditioning includes a cationic surfactant and an organosilane coupling agent, thereby forming an activated layer with colloidal palladium adsorption capacity on the solder resist layer 2. Further via shaping of the blind vias 22 removes micro-contaminants from the via walls and improves the wetting properties of the liquid inside the blind vias 22, allowing the chemical solution to fully penetrate the interior of the blind vias 22. The surface conditioning treatment uses a chemical solution containing a cationic surfactant and an organosilane coupling agent. The cationic surfactant forms a uniformly distributed positively charged layer on the surface of the solder resist layer 2, thereby improving the catalyst adsorption capacity of the solder resist layer 2 surface. The organosilane coupling agent can combine with the polar groups on the surface of the solder resist layer 2, forming a stable functionalized layer on the surface and providing active sites conducive to colloidal palladium adsorption. Since the solder resist layer 2 usually has a high cross-linking density and low surface activity after high temperature curing, this application effectively solves the problem of the difficulty in uniform adsorption of colloidal palladium through special surface conditioning treatment.

[0030] Specifically, the chemical solution used for surface conditioning includes a cationic surfactant at a concentration of 2-8 g / L and an organosilane coupling agent at a concentration of 0.5-2.0 wt%. Through the synergistic effect of the two, an activation layer is formed on the surface of the solder resist layer 2, which is conducive to the adsorption of colloidal palladium. In feasible embodiments, the cationic surfactant includes one or more of hexadecyltrimethylammonium bromide, hexadecyltrimethylammonium chloride, and dodecyltrimethylammonium chloride; the organosilane coupling agent includes one or more of aminosilane coupling agents, epoxysilane coupling agents, and mercaptosilane coupling agents. The cationic surfactant can uniformly adhere to the surface of the solder resist layer 2 through molecular adsorption, with the lipophilic groups aligning towards the resin surface of the solder resist layer 2 and the positively charged hydrophilic groups distributed towards the solution side, thereby forming a uniform positively charged layer on the surface of the solder resist layer 2. The Pd-Sn colloidal particles in the colloidal palladium activation solution are usually negatively charged; therefore, the positively charged layer can enhance the electrostatic adsorption of colloidal palladium particles on the surface of the solder resist layer 2. The organosilane coupling agent can react with the polar groups on the surface of solder resist layer 2. Specifically, after hydrolysis, the organosilane coupling agent forms silanol groups, which can undergo a condensation reaction with the residual hydroxyl groups on the surface of solder resist layer 2, thereby forming a stable Si-O bond structure, firmly binding the coupling agent to the surface of solder resist layer 2. Simultaneously, the amino groups at the terminal of the organosilane coupling agent molecule undergo a protonation reaction in an acidic colloidal palladium activation solution to form -NH3. + Group. -NH3 +The functional groups not only electrostatically attract negatively charged Pd-Sn colloidal particles, but also coordinate with palladium ions through the lone pair electrons of nitrogen atoms, further enhancing the adsorption density and stability of colloidal palladium particles on the surface of solder resist layer 2. Furthermore, during surface conditioning, the pH of the chemical solution used for surface conditioning is controlled between 7.5 and 9.0. When the pH is below 7.5, the adsorption of cationic surfactants decreases, and the organosilane coupling agent is prone to premature condensation, which is detrimental to the formation of a uniform functional layer on the surface of solder resist layer 2. When the pH is above 9.0, the hydrolysis and condensation reaction rates of the organosilane coupling agent are too rapid, thus affecting the uniformity of surface activation. Preferably, the surface conditioning temperature is controlled at 40-55℃, and the treatment time is 3-8 minutes.

[0031] After surface conditioning, colloidal palladium activation treatment is performed. Colloidal palladium particles are adsorbed on the surface of the surface-conditioned solder resist layer 2 and the inner wall of the blind via 22, acting as a catalyst for subsequent chemical copper plating. During chemical copper plating, under the catalysis of colloidal palladium, copper ions undergo a reduction reaction and deposit on the bottom and sidewalls of the blind via 22 and the surface of the solder resist layer 2, forming a continuous conductive copper plating layer 3. The thickness of the chemically deposited copper plating layer 3 is 0.3-0.8 μm. The copper plating layer 3 achieves electrical connection between the copper circuit layer 11 at the bottom of the blind via 22 and the surface of the solder resist layer 2. Furthermore, as a conductive seed layer for subsequent electroplating of copper, the copper plating layer 3 also avoids localized current concentration and uneven plating.

[0032] A photosensitive dry film 4 is attached to the surface of the copper plating layer 3. Preferably, the lamination temperature is 100-120℃ and the lamination pressure is 3-5 kg / cm². 2 This allows the photosensitive dry film 4 to firmly adhere to the surface of the copper plating layer 3. After lamination, exposure and development are performed to form the electroplating window 41. Preferably, the developing line speed is controlled at 1.0-1.2 m / min, and the spray pressure is controlled at 0.8-1.0 kg / cm². 2 The development temperature range is 25-30℃. If the linear speed is too high, the uncured photosensitive dry film 4 may not be completely removed; if the linear speed is too slow, the edges of the cured pattern may be eroded. The photosensitive dry film 4 is used to form the electroplating area for the subsequent copper pillars, exposing the predetermined positions to the electroplating solution, thereby ensuring that the copper pillars grow according to the position and size of the electroplating window 41. Exposure causes the corresponding area of ​​the photosensitive dry film 4 to cure, and development removes the uncured parts, ultimately forming the electroplating window 41 corresponding to the position of the blind via 22. That is, the electroplating window 41 formed at this time is connected to the blind via 22, and the inner diameter of the electroplating window 41 is larger than the inner diameter of the blind via 22, thus providing a growth area for the copper pillars.

[0033] After the electroplating window 41 is formed, a gantry electroplating device 6, in conjunction with a pulse power supply, deposits copper ions within the electroplating window 41. As copper ions are continuously deposited, a copper pillar bump 5 structure is eventually formed within the electroplating window 41. Preferably, the electroplating solution includes 60–90 g / L copper sulfate, 180–240 g / L sulfuric acid, and 40–70 ppm chloride ions. Copper sulfate serves as the primary source of copper ions, providing metallic copper for the growth of the copper pillar bump 5. Sulfuric acid provides conductivity to the electroplating solution and maintains the stability of the electroplating solution system. Chloride ions improve the crystallization state of the electroplated copper, enhancing the smoothness and density of the copper pillar bump 5 surface.

[0034] During electroplating, a stepped current increase method is adopted. Specifically, at the beginning of electroplating, a low current density of 0.2 ASD is used to allow copper ions to be uniformly deposited on the surface of the copper plating layer 3 formed by chemical copper deposition, thereby establishing a continuous and stable conductive growth interface. As the height of the copper pillars gradually increases and the conductive area continues to expand, the current density is gradually increased, eventually reaching 1.5-2.0 ASD. By using a stepped current increase method, the problem of excessively high local potential caused by a sudden large current in the electroplating window 41 is avoided, preventing problems such as scorching at the top of the copper pillar bumps 5 and dendrite growth.

[0035] Simultaneously, a pulse power supply is used in conjunction with the electroplating process. The pulse power supply outputs forward and reverse pulses. The forward pulse width is 1-10ms, and the reverse pulse width is 0.5-2ms. During the forward pulse phase, copper ions are reduced and deposited on the cathode surface to form a copper layer. During the reverse pulse phase, local protrusions preferentially undergo micro-dissolution, thereby weakening the local current concentration effect and improving the uniformity of current distribution. By redistributing the current through periodic reverse pulses, protrusions are eliminated, and the uniform growth of copper pillar bumps 5 is promoted.

[0036] Preferably, the electroplating process employs a cathode oscillation method to assist electroplating. The cathode oscillation involves the cathode clamp supporting the substrate 1 performing periodic reciprocating motion within the electroplating tank, with an oscillation frequency of 20-60 times / min. The cathode oscillation drives the flow of the electroplating solution, continuously renewing the copper ion concentration in the electroplating solution surrounding the copper pillar, breaking down the ion-depleted layer formed within the electroplating window 41, increasing the copper ion replenishment rate, thereby improving the uniformity of current distribution, enhancing the consistency of copper pillar growth, and ultimately resulting in a copper pillar bump 5 with a height uniformity difference of less than 5%.

[0037] Furthermore, the electroplating solution also includes a leveling agent and a refining agent, with a mass ratio of 1:2 to 1:3. The leveling agent is used to adjust the deposition rate of copper ions on the cathode surface and suppress excessive growth at the top or edge of the copper pillar. When there are local current density differences within the electroplating window 41, copper is preferentially deposited in high-current areas, forming a protruding structure. By adding the leveling agent, the local copper ion reduction rate can be reduced, keeping the copper pillar surface flat. The refining agent is used to improve the formation of crystal nuclei during the copper deposition process, increasing the number of crystal nuclei and reducing the size of the formed copper grains, thus improving the density and mechanical strength of the copper pillar structure.

[0038] The photosensitive dry film 4 is removed and the exposed copper plating layer 3 is etched away to form independent copper pillar bumps 5. Specifically, this application treats the photosensitive dry film 4 with an alkaline stripping solution, preferably a sodium hydroxide solution with a mass concentration of 3-5%. During the stripping process, the sodium hydroxide solution can penetrate into the interior of the photosensitive dry film 4, causing the photosensitive dry film 4 to swell and destroy the polymer cross-linking structure in the photosensitive dry film 4, allowing the photosensitive dry film 4 to peel off from the surface of the copper plating layer 3. Optionally, in this embodiment, the stripping temperature is 50-60°C, and the stripping solution and the photosensitive dry film 4 can be fully contacted for 1-3 minutes by spraying or immersion to achieve the removal of the photosensitive dry film 4.

[0039] After removing the photosensitive dry film 4, the exposed copper plating layer 3 is selectively etched to remove the residual copper plating layer 3 from the non-copper pillar bump 5 area, thus making the copper pillar bumps 5 independent of each other. Specifically, in this embodiment, an etching solution containing copper chloride and hydrochloric acid is used to etch the exposed copper plating layer 3. Etching can be performed by spraying or immersion, with an etching temperature of 50-60℃ and an etching time of 1-3 minutes. This ensures etching efficiency while avoiding damage to the sidewalls of the copper pillar bumps 5 due to over-etching.

[0040] Through the above steps, this application uses UV laser to process the area of ​​the solder resist opening 21, thereby forming a blind hole 22 with an inner diameter of less than 20 μm. The UV laser avoids repeated burning at a single point by using a spiral scanning trajectory processing method, that is, the radius of the spiral trajectory is less than 20 μm, and the laser beam removes the material of the solder resist layer 2 layer by layer along the preset path, which effectively controls the hole diameter error and improves the flatness of the hole wall.

[0041] This invention also features a unique surface conditioning process. In existing FCCSP carrier board processes, the solder resist layer 2, after high-temperature curing, forms a highly cross-linked resin structure with low surface energy and a lack of sufficient active functional groups. Therefore, colloidal palladium is difficult to adsorb uniformly, easily leading to incomplete chemical copper plating coverage or even missed plating. This invention employs a special surface conditioning chemical solution containing cationic surfactants and organosilane coupling agents. Specifically, the cationic surfactant forms a uniformly distributed positively charged layer on the surface of the solder resist layer 2, increasing surface energy and enhancing the electrostatic adsorption capacity for colloidal palladium particles; the organosilane coupling agent binds to the polar groups on the surface of the solder resist layer 2, constructing a stable functionalized layer on the surface and providing active sites for easy binding of colloidal palladium.

[0042] The present invention also discloses an FCCSP carrier plate, which is manufactured according to the above-described manufacturing method.

[0043] The technical solution of the present invention has been described above with reference to the preferred embodiments shown in the accompanying drawings. However, it will be readily understood by those skilled in the art that the scope of protection of the present invention is obviously not limited to these specific embodiments. Without departing from the principles of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after such changes or substitutions will all fall within the scope of protection of the present invention.

Claims

1. A method for manufacturing a copper column with a solder resist layer for an FCCSP carrier plate, characterized in that, Includes the following steps: A substrate is provided, wherein the substrate has a copper circuit layer; Photosensitive ink is coated on the surface of the substrate, and the photosensitive ink is subjected to pre-baking, exposure, development and post-baking processes in sequence to form a solder resist layer covering the surface of the substrate and to form solder resist openings through development. The solder resist layer in the area corresponding to the solder resist opening is ablated using a UV laser. The UV laser processes the blind hole with an inner diameter of less than 20 μm using a spiral scanning trajectory and exposes the copper circuit layer on the substrate. Plasma cleaning is performed on the bottom and sidewalls of the blind hole to remove the adhesive residue left by UV laser ablation. The cleaned blind holes are sequentially subjected to hole shaping, surface conditioning, colloidal palladium activation, and chemical copper plating, thereby forming a continuous copper plating layer on the inner wall of the blind holes and the surface of the solder resist layer. The chemical solution used for surface conditioning includes cationic surfactants and organosilane coupling agents, thereby forming an activation layer with colloidal palladium adsorption capacity. A photosensitive dry film is attached to the surface of the copper plating layer, and then exposed and developed to form an electroplating window. A gantry-type electroplating device, in conjunction with a pulse power supply, forms copper column protrusions within the electroplating window. The photosensitive dry film is removed and the exposed copper plating layer is etched away to form the independent copper pillar bumps.

2. The method for manufacturing the solder resist layer of the FCCSP carrier plate with a windowed copper pillar according to claim 1, characterized in that, In the plasma cleaning step for blind holes, a mixture of oxygen and trace amounts of fluorine-based gas is used as the working gas. The plasma cleaning power is 1000-2000W, and the processing time is 10-20 minutes.

3. The method for manufacturing the solder resist layer of the FCCSP carrier board with a windowed copper pillar according to claim 1, characterized in that, The chemical solution used for the surface conditioning treatment includes a cationic surfactant at a concentration of 2-8 g / L and an organosilane coupling agent at a concentration of 0.5-2.0 wt%.

4. The method for manufacturing the solder resist layer of the FCCSP carrier plate with a windowed copper pillar according to claim 1, characterized in that, The thickness of the copper plating layer formed by the chemical copper plating is 0.3-0.8 μm.

5. The method for manufacturing the solder resist layer of the FCCSP carrier plate with a windowed copper column according to claim 1, characterized in that, In the step of "forming copper pillar bumps in the electroplating window using a gantry electroplating device in conjunction with a pulse power supply", the electroplating solution used for electroplating includes 60-90 g / L copper sulfate, 180-240 g / L sulfuric acid and 40-70 ppm chloride ions.

6. The method for manufacturing the solder resist layer of the FCCSP carrier plate with a windowed copper pillar according to claim 5, characterized in that, In the step of "forming copper pillar bumps in the electroplating window using a gantry electroplating device and a pulse power supply", electroplating is performed using a stepped current ramp method. The initial current density of electroplating is 0.2 ASD, which is gradually increased to 1.5-2.0 ASD. The pulse power supply outputs positive and negative pulses. The width of the positive pulse is 1-10 ms, and the width of the negative pulse is 0.5-2 ms.

7. The method for manufacturing the solder resist layer of the FCCSP carrier plate with a windowed copper pillar according to claim 5, characterized in that, In the step of "forming copper pillar protrusions in the electroplating window using a gantry electroplating device in conjunction with a pulse power supply", the electroplating solution also includes a leveling agent and a refining agent, and the ratio of the leveling agent to the refining agent is 1:2-1:

3.

8. The method for manufacturing the solder resist layer of the FCCSP carrier board with a windowed copper pillar according to claim 1, characterized in that, In the step of "removing the photosensitive dry film", the photosensitive dry film is removed using an alkaline stripping solution, which is a sodium hydroxide solution with a mass concentration of 3%-5%.

9. The method for manufacturing the solder resist layer of the FCCSP carrier board with a windowed copper pillar according to claim 1, characterized in that, The etching solution used to "remove the exposed copper plating layer" includes copper chloride and hydrochloric acid, and etching is carried out by spraying or immersion at a temperature of 50-60°C for a time of 1-3 minutes.

10. An FCCSP carrier board, characterized in that, The FCCSP carrier plate is manufactured by the manufacturing method described in any one of claims 1-9.

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