Substrate via package structure and method of manufacturing the same

Abstract

The application relates to the field of wireless communication technology and provides a substrate via packaging structure and a manufacturing method thereof, which comprises the following steps: S1, performing film pressing treatment on the upper and lower surfaces of a peelable carrier to form two layers of resin-coated copper layers; S2, performing exposure and development on the film-coated layer to obtain a via window; S3, performing drilling on the via window to obtain a via; S4, sequentially performing chemical copper plating and electroplating copper treatment on the via, and finally completely filling the via with electroplated copper; S5, attaching a reinforcing layer to the surface of the electroplated copper and the surface of the film-coated layer to obtain a substrate prototype; S6, separating the first copper layers of the upper and lower layers of the peelable carrier from the plate core to obtain two coreless semi-finished substrate; and S7, performing pressing dry film on the surfaces of the first copper layers of the two coreless semi-finished substrates close to each other to obtain a semi-finished substrate and package to obtain the substrate via packaging structure. The application has low manufacturing cost, simple production process and good heat dissipation effect.

Description

Technical Field

[0001] This invention relates to the field of wireless communication technology, and in particular to a substrate through-hole packaging structure and its manufacturing method. Background Technology

[0002] Currently, there are three main materials used in the field of packaging substrates: BT material, ABF material, and MIS material. 1. BT material: Bismalleimide Triazine, developed by Mitsubishi Gas Chemicals of Japan, has high heat resistance and dimensional stability.

[0003] 2. ABF material: Ajinomoto Build-up Film, developed by Ajinomoto Corporation of Japan, is a key multilayer film for packaging high-end central processing units (CPUs) and graphics processing units (GPUs).

[0004] 3. MIS Material: Molded Interconnect Substrate, a new type of packaging substrate technology that includes a pre-encapsulated structure, commonly used in power and analog chips.

[0005] Among them, there are four main substrate manufacturing processes based on BT materials: Tenting, Modified Semi-Additive Process (mSAP), Embedded Trace Substrate (ETS), and Via Post. The first two are the current mainstream processes. For the fabrication of through-holes: Tenting uses mechanical drilling + hole plugging or brown laser coating; mSAP uses windowed laser coating or brown laser coating; and ETS uses windowed laser coating.

[0006] In related technologies, taking a conventional four-layer board (1+2+1 stacked structure, BT material, inner layer Tenting process, outer layer mSAP process) as an example, such as... Figure 1As shown, after the core material 01 is prepared, it undergoes baking and dehumidification treatment, followed by inner layer drilling, including tool holes and through holes 02. Then, it undergoes micro-etching and acid pickling to increase adhesion. Horizontal copper plating and vertical copper plating are then performed to create copper through holes 03. After completion, dry film is applied, followed by exposure, development, rapid etching, and film removal of the inner layer circuitry to complete the copper layer fabrication on both sides of the core material 04. Then, Automated Optical Inspection (AOI) is performed, followed by pre-lamination treatment and lamination, X-ray drilling (X-ray scanning system), edge milling, and the fabrication of the inner layer circuitry is completed.

[0007] After completing the inner layer circuitry, the outer layer circuitry is fabricated. Tool holes and through-holes (05) are also fabricated using a combination of mechanical and laser methods. After plasma cleaning, micro-etching and acid pickling are performed to increase adhesion, followed by horizontal copper plating. Next, pre-filming treatment is performed, dry film is applied, and then the outer layer circuitry is exposed, developed, and vertically electroplated to complete copper plating of the through-holes (06) and the outermost copper layer (07). Then, rapid etching and film removal are performed, followed by automated optical inspection.

[0008] Final stage: First, apply the surface solder resist layer 08, followed by electroless nickel plating 09 and gold plating 010. After cutting the board, perform electrical testing, and then apply the organic solderability preservative (OSP) coating 011. After external inspection, good products are transferred to marking and cleaning, and finally packaged and stored.

[0009] Due to limitations in its drilling process, the diameter of vias remains >80um. However, current 5G communication, automotive electronics, and high-performance computing terminals place higher demands on the wiring density, signal integrity, and integration of printed circuit boards. Reducing via diameter and increasing the number of vias have become the core paths to improve circuit density.

[0010] However, due to different materials and manufacturing processes, different drilling techniques are used in the substrate manufacturing process, such as mechanical drilling and brown laser engraving. These drilling techniques have the following shortcomings: First, physical drilling cannot meet the process requirements for small-diameter holes; Although mechanical drilling has a low cost per hole, the current minimum mass-produced drill bit diameter is ≥80um, resulting in larger drilled holes, shorter lifespan, and poor hole positioning accuracy. This also makes it impossible to meet the development needs of high-density processes within a limited area.

[0011] Second, the process is complex and requires a large investment in equipment; Laser / copper pillar interconnects have small apertures, short paths, and high density, but the complexity of equipment and processes is significantly increased. In particular, the production time of laser conduction technology increases with the number of holes, and the cost is also high. Summary of the Invention

[0012] To address the shortcomings of the existing technologies, this invention proposes a method for manufacturing a substrate through-hole packaging structure, thereby solving the problems of high manufacturing costs, complicated manufacturing processes, and low production efficiency of existing substrates.

[0013] To solve the above-mentioned technical problems, the present invention adopts the following technical solution: In a first aspect, embodiments of the present invention provide a method for manufacturing a substrate through-hole encapsulation structure, the method comprising the following steps: S1. A peelable carrier is provided, which includes a core board and two copper layers respectively coated and fixed on both sides of the core board. The upper and lower surfaces of the peelable carrier are respectively subjected to a pressing treatment to form two resin-coated copper layers. S2. Clean the surfaces of the two resin-coated copper layers to remove oil and oxide layers, and coat the surfaces of the two resin-coated copper layers to obtain two coating layers. Then expose and develop the two coating layers to obtain through-hole windows. S3. Drill holes at the opening positions of the through holes to obtain through holes; wherein, the through holes sequentially penetrate the corresponding coating layer and the resin-coated copper layer until they reach the surface of the two copper layers of the peelable carrier; S4. Perform chemical copper plating and electroplating copper treatment on the through hole in sequence, and finally completely fill the through hole with electroplated copper. S5. Grind the surface of the electroplated copper to make the surface of the electroplated copper flush with the surface of the coating layer, and at the same time attach a reinforcing layer to the surface of the electroplated copper and the surface of the coating layer to obtain a preliminary substrate sample. S6. Pull the substrate sample at a constant speed along its length or width direction so that the copper layers on the upper and lower sides of the peelable carrier are separated from the core, and two coreless semi-finished substrates are obtained. S7. Apply a dry film to the copper layers of the two coreless semi-finished substrates that are close to each other, and fabricate a circuit structure layer according to the mSAP process to obtain a semi-finished substrate; encapsulate the semi-finished substrate with plastic, remove the reinforcing layer, and perform electrical performance testing after encapsulation to obtain the through-hole encapsulation structure of the substrate.

[0014] Preferably, the resin-coated copper layer includes a resin layer that adheres to the side of the copper layer away from the core and a copper layer that adheres to and is fixed to the side of the resin layer away from the peelable carrier. Step S1 specifically includes the following sub-steps: Pretreatment: The upper and lower surfaces of the peelable carrier are etched with a browning solution to remove the two copper layers, and the removal amount of the two copper layers is controlled to be 0.2~1.5μm respectively, forming a uniform rough surface; Lamination and alignment: The two resin layers are respectively bonded to the predetermined areas of the two copper layers to complete the pre-fixation and obtain the initial carrier. Vacuum lamination: The primary carrier is placed in a vacuum laminator, and the heating, pressurization, resin flow filling and curing processes are completed in sequence to obtain a resin-cured body; Post-processing: The cured resin body is cooled and depressurized, and then cooled to room temperature before proceeding to the next step.

[0015] Preferably, the heating process specifically involves: raising the room temperature to 170℃~250℃, maintaining the temperature for curing for 60~90 minutes, and a heating rate ≤5℃ / min; The pressure of the pressurization process is controlled at 15~30 kg / cm², and the vacuum degree is maintained at ≤5 mbar throughout the process; The thickness difference after pressing in the curing process is ≤5μm; The cooling process has a cooling rate of ≤3℃ / min.

[0016] Preferably, each copper layer includes a first copper layer and a second copper layer that are stacked and bonded together, with the two second copper layers bonded and fixed between the upper and lower surfaces of the core and the two first copper layers, respectively. Wherein, the thickness of the second copper layer is 10~18μm, and the thickness of the first copper layer is 3~5μm; step S7 is performed on the surface of the first copper layer near the second copper layer.

[0017] Preferably, step S2 includes the following sub-steps: The resin-coated copper layer is cleaned to remove oil and oxide layers. A dry film or a photosensitive material of a predetermined thickness is then laminated onto the surface of the resin-coated copper layer. A laser direct imaging exposure machine is used to directly transfer the pattern to a predetermined position on the dry film or the photosensitive material. Then, acid etching is used to completely remove the exposed copper layer at the predetermined position, exposing the resin layer below the removed copper layer, thus obtaining the through-hole window. The windowed area of ​​the through-hole window is then roughened by micro-etching to remove etching residue. The size of the through-hole window is 2-5 μm larger than the size of the laser hole in the laser direct imaging exposure machine, the lateral etching amount is ≤12 μm, and the deviation between the through-hole window and the inner target is <15 μm.

[0018] Preferably, step S3 specifically includes the following sub-steps: Based on the thickness of the resin-copper foil layer, a suitable laser type and corresponding parameters are selected, and under correct alignment, the coordinates of the inner target are identified by an X-ray scanning system. The resin area exposed at the through-hole opening is then ablated to form a micro-through-hole that penetrates the dielectric layer. After the micro-holes are opened, the residual resin carbides inside the holes are removed by plasma or chemical desmearing agents, and then the hole diameter and hole wall quality are fully inspected by a two-dimensional imaging instrument and the X-ray scanning system. The hole wall roughness Ra ≤ 0.5 μm.

[0019] Preferably, step S4 specifically includes: Palladium catalyst sites are deposited on the walls of the through holes, and a 0.5~1μm thick conductive copper layer is formed by chemical copper plating to achieve full conductivity of the hole walls; Next, the conductive copper layer on the hole wall is thickened to 5~8μm by low-current whole-board electroplating, providing a basic conductive layer for subsequent hole plugging; Finally, a highly dispersible copper plating solution is used, and copper ions are uniformly deposited from the bottom of the through hole upwards through pulse electroplating to completely fill the through hole.

[0020] Preferably, step S7 specifically includes the following steps: Dry films are laminated onto the copper layers of the two coreless semi-finished substrates that are close to each other; and the following processes are performed in sequence: first exposure → first development → copper electroplating → film removal → flash etching → solder resist lamination → second exposure → second development → nickel-gold or nickel-gold surface treatment → film removal → board separation → electrical testing → OSP treatment → marking → cleaning → packaging, to obtain the through-hole encapsulation structure of the substrate.

[0021] Preferably, step S7 specifically includes the following steps: Dry film is laminated onto the copper layers of the two coreless semi-finished substrates that are close to each other; and the following processes are performed in sequence: first exposure → first development → copper electroplating → film removal → flash etching → solder resist lamination → second exposure → second development, to obtain the semi-finished substrate. The semi-finished substrate is encapsulated in plastic and the reinforcing layer is removed. The surface of the semi-finished substrate after the reinforcing layer is removed is treated with nickel-gold or nickel-gold surface coating. For products with completed surfaces, production continues according to the post-packaging process; wherein, the post-packaging process includes product marking, finished product cutting, and finished product inspection in sequence; The electrical performance of the single, well-packaged product is tested, and the tested products are packaged and stored. The entire packaging process is completed, resulting in the through-hole packaging structure of the substrate.

[0022] Secondly, embodiments of the present invention provide a substrate through-hole packaging structure for use in radio frequency semiconductors, wherein the substrate is manufactured by the above-described method for manufacturing the substrate through-hole packaging structure.

[0023] Compared with related technologies, in the embodiments of the present invention, the substrate through-hole packaging structure obtained by the above steps S1-S7, by first creating the through-hole layer on one side of a peelable carrier with two peelable copper layers, and then peeling it off before fabricating the circuit on the other side, achieves a coreless structure. Under the same function, it is thinner, has a shorter heat dissipation distance, and is faster. At the same time, it requires less equipment investment, simplifies the production process, and can achieve high efficiency and quality in mass production. Attached Figure Description

[0024] The present invention will now be described in detail with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and more readily understood through the detailed description following the accompanying drawings. In the drawings: Figure 1 This is a schematic diagram of the substrate structure of the related technology; Figure 2 A flowchart illustrating a method for manufacturing a substrate through-hole packaging structure provided in an embodiment of the present invention; Figure 3 A schematic diagram of the structure of a peelable carrier for a method of manufacturing a substrate through-hole packaging structure provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the structure obtained by step S1 in the manufacturing method of the substrate through-hole packaging structure provided in the embodiment of the present invention. Figure 5 A schematic diagram of the structure obtained by steps S2-S3 in the manufacturing method of the substrate through-hole packaging structure provided in the embodiment of the present invention; Figure 6 A schematic diagram of the structure obtained by steps S4-S6 in the manufacturing method of the substrate through-hole packaging structure provided in the embodiment of the present invention; Figure 7 A schematic diagram of the structure obtained by the lamination dry film process in step S7 of the manufacturing method of the substrate through-hole packaging structure provided in the embodiment of the present invention; Figure 8 A schematic diagram of the structure obtained by the bonding of the solder resist layer in step S7 of the manufacturing method of the substrate through-hole packaging structure provided in the embodiment of the present invention; Figure 9 A schematic diagram of the structure obtained by surface nickel-palladium-gold plating and OSP process in step S7 of the manufacturing method of the substrate through-hole packaging structure provided in the embodiment of the present invention. Figure 10 This is a schematic diagram of the substrate through-hole packaging structure provided in an embodiment of the present invention; Figure 11 for Figure 10 A magnified view of part A; Figure 12 for Figure 10 A magnified view of part B.

[0025] Among them, 100 is a substrate through-hole encapsulation structure, 1 is a peelable carrier, 101 is a board core, 102 is a copper layer, 1021 is a first copper layer, 1022 is a second copper layer, 2 is a resin-coated copper foil layer, 21 is a resin layer, 22 is a copper foil layer, 3 is a film layer, 4 is a through hole, 5 is a copper pillar, 6 is a reinforcing layer, 7 is a dry film layer, 8 is a nickel layer, 9 is a palladium layer, 10 is a gold layer, 11 is a conductive copper layer, 12 is a protective layer, 13 is a first groove, 14 is a second groove, 15 is an electroplated copper layer, and 16 is a solder resist layer. Detailed Implementation

[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein in the specification of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application; the terms "comprising" and "having," and any variations thereof, in the specification, claims, and foregoing drawings of this application, are intended to cover non-exclusive inclusion. The terms "first," "second," etc., in the specification, claims, or foregoing drawings of this application are used to distinguish different objects, not to describe a particular order.

[0027] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0028] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0029] Example 1 Please see Figures 2-9 As shown, this embodiment of the invention provides a method for manufacturing a substrate through-hole packaging structure, the method comprising the following steps: S1. Provide a peelable carrier 1 (Detach Core), which includes a core 101 and two copper layers 102 respectively coated and fixed on both sides of the core 101. The upper and lower surfaces of the peelable carrier 1 are respectively subjected to a lamination process to form two resin-coated copper layers 2.

[0030] In the PCB (Printed Circuit Board) field, "Detach Core" is a well-known term. It does not refer to a specific type of board material, but rather to a type of "Detachable Core Substrate" or "Separable Core". For example, it can be understood as a temporary "skeleton" used to create a "coreless board".

[0031] Its core working principle and function are as follows: Essentially, it is a temporary carrier: it is a temporary core board that serves as a substrate in the early stages of production, supporting the fabrication of circuitry and insulation layers layer by layer. Its structure typically includes a middle carrier layer, metal foils on both sides (which eventually become the outer copper foil of the PCB), and a release layer or primer layer between the two.

[0032] Its core process is "splitting into two": after all the circuit layers are made on both sides of the core board, the last step is to "disassemble the board"; split the temporary core board in two from the middle (or through the peeling layer) to separate it into two independent "coreless substrates" without a thick core layer.

[0033] Key design considerations: To ensure smooth separation and prevent product warping, these core boards are designed with strict matching of the coefficient of thermal expansion (CTE) of each layer of material, and the primer layer is modified (e.g., kept in a semi-cured state during lamination) to ensure adhesion and peelability.

[0034] The biggest advantage of this process is that it can produce thinner and lighter PCBs while meeting the requirements of high layer count, high-density wiring and fine lines, making it very suitable for high-end applications such as smartphones and SiP (System-in-Package).

[0035] The lamination process employs RCC lamination (Resin Coated Copper Lamination, also known as "resin-coated copper foil"), where pre-coated resin copper foil is bonded to the upper and lower surfaces of a temporary carrier under high temperature and pressure, forming a composite resin-coated copper foil layer 2 consisting of a resin layer 21 and a copper foil layer 22. A peelable interface (a weak bonding interface, typically achieved through carrier surface passivation or release treatment) is formed between the resin layer 21 and the carrier copper foil layer 22, laying the structural foundation for the subsequent peeling step S6. Furthermore, the temporary carrier can be recycled and reused, further reducing costs.

[0036] By creating a through hole 4 on one side of the peelable carrier 1, and then peeling it off before fabricating the circuit on the other side, a coreless structure 101 is achieved. This results in a thinner, shorter, and faster heat dissipation process while achieving the same function.

[0037] S2. Clean the surfaces of the two resin-coated copper layers 2 to remove oil and oxide layers, and coat the surfaces of the two resin-coated copper layers 2 to obtain two coating layers 3. Then expose and develop the coating layers 3 to obtain through-hole windows.

[0038] First, the copper layer 22 with resin-coated copper layer 2 undergoes pretreatment cleaning (usually micro-etching + degreasing) to remove surface oil and oxide layers, ensuring adhesion of the subsequent dry film. Then, a dry film (i.e., coating layer 3) is attached to the copper layer 22. Through exposure and development photolithography processes, the designed via 4 position pattern is transferred onto the dry film to form via openings; that is, the dry film at the opening position is removed, exposing the underlying copper layer 22, while the dry film in the remaining area is retained as a drilling mask. By defining the position of the via 4 using photolithography, the positional accuracy is high (± several μm), providing a geometric basis for the high-density arrangement of the via 4 array.

[0039] Specifically, the standard photolithography process is used to precisely define the positions of vias 4 on the dry film with a positioning accuracy down to the micrometer level, providing geometric assurance for the high-density array arrangement of vias 4. This process is fully compatible with the photolithography equipment of existing mSAP / Tenting production lines, eliminating the need for separate production lines and minimizing changes to the PCB manufacturer's production line layout. Due to its strong compatibility with production lines, demanders have a relatively wider range of PCB manufacturers to choose from, and the supply channels are no longer limited, making the risk of supply disruption manageable.

[0040] S3. Drill holes at the opening positions of the through holes to obtain through holes 4; wherein, the through holes 4 sequentially penetrate the corresponding coating layer 3 and the resin-coated copper skin layer 2 until they reach the surface of the two copper layers 102 of the peelable carrier 1.

[0041] In this process, using the dry film window formed in step S2 as a mask, laser drilling (UV laser or CO2 laser) or plasma etching is employed to penetrate the coating layer 3 (dry film) and the resin-coated copper layer 2 from top to bottom, stopping when the bottom of the hole reaches the copper surface of the peelable carrier 1. The depth of the through-hole 4 is only equal to the thickness of the resin-coated copper layer 2 (typically on the order of 10~30μm), much smaller than the overall board thickness of a traditional through-hole. The bottom of the hole uses the copper layer 22 of the peelable carrier 1 as a natural stop layer, ensuring that the copper layer 22 at the bottom of the hole is completely exposed, providing a seed surface for subsequent copper plating.

[0042] Specifically, on a limited substrate area, by reasonably reducing the number of vias and increasing the number of vias 4, the density of the circuitry can be improved by at least 10% compared to the original for the same unit. On this basis, further reducing the diameter of vias 4 (diameter ≤ 30um) can save more space for arranging components, resulting in higher and denser integration within the unit. Due to the reduction in aperture, the unit size can be further reduced to achieve the same function, thus achieving a smaller package size.

[0043] Of course, depending on customer and design requirements, corresponding buried vias can be used to develop multilayer stacked substrates and advanced via technology, which can realize vertical interconnection between layers, greatly shorten the signal transmission path, reduce crosstalk, and also help improve signal integrity.

[0044] S4. The through hole 4 is subjected to chemical copper plating and electroplating copper treatment in sequence, and finally the through hole 4 is completely filled by electroplating copper.

[0045] Among them, electroless copper plating (PTH) involves depositing a thin copper seed layer (typically 0.5–1 μm) on the resin insulating surface of the inner wall of through hole 4 through a chemical reaction, making the insulating hole wall conductive.

[0046] Electroplating Copper: Using the copper skin layer 22 at the bottom of the hole and the seed layer on the hole wall as cathodes, an electric current is applied to the electroplating solution, causing copper ions to be deposited and grown simultaneously from the bottom and sidewalls in the through hole 4. Through the super-filling effect, the through hole 4 is completely filled from bottom to top, forming a solid copper pillar 5.

[0047] In this process, a conductive seed layer is formed on the hole wall by chemical copper plating, followed by electroplating of copper to completely fill the through hole 4, forming a solid copper pillar 5 vertical interconnect structure. The thermal conductivity of the copper pillar 5 is much higher than that of the resin substrate, which significantly shortens the heat dissipation path and improves heat dissipation efficiency; the through hole 4 is shallow and the amount of copper filling is small, which reduces copper consumption and electroplating time, and keeps costs under control; the interconnect resistance of the copper pillar 5 is extremely low, which helps to reduce insertion loss and improve signal integrity.

[0048] S5. Grind the surface of the electroplated copper to make the surface of the electroplated copper flush with the surface of the coating layer 3, and at the same time attach a reinforcing layer 6 to the surface of the electroplated copper and the surface of the coating layer 3 to obtain a preliminary substrate sample.

[0049] In this process, excess copper layer that overflows from the electroplated surface is removed by chemical mechanical polishing (CMP) or mechanical grinding, so that the top surface of the copper pillar 5 and the surface of the coating layer 3 are coplanar and flush, with the surface roughness controlled at the nanometer level. Subsequently, an additional reinforcing layer 6 (usually a high-temperature resistant support tape or temporary adhesive film) is applied to the flat surface. Its function is to temporarily replace the temporary carrier plate after the temporary carrier plate is peeled off in step S6, providing mechanical rigidity support for the coreless substrate and preventing the ultrathin substrate from warping or breaking in subsequent processes.

[0050] Among them, grinding makes the top surface of the copper pillar 5 and the surface of the coating layer 3 coplanar and flush, providing a flat foundation for subsequent fine circuit fabrication, ensuring the uniformity of circuit thickness and the accuracy of impedance control; the reinforcing layer 6 temporarily replaces the carrier board to provide mechanical support, solving the process problem of easy warping and breakage after the coreless substrate is peeled off, enabling the ultra-thin substrate to be smoothly transferred to subsequent processes, and ensuring the process feasibility of the coreless structure.

[0051] S6. Pull the substrate sample at a constant speed along its length or width direction to separate the copper layer 102 on the upper and lower sides of the peelable carrier 1 from the core 101, and obtain two coreless semi-finished substrates.

[0052] In step S1, utilizing the peelable interface (a weak bonding interface, with peel strength typically controlled in the range of 0.1–0.5 N / cm) formed between the copper layer 102 and the resin-coated copper layer 2 during RCC lamination, a uniform tensile force is applied horizontally to completely peel the copper layer 102 from the surface of the core 101. After peeling, the resin-coated copper layer 2 + copper pillar 5 structure, originally held by the peelable carrier 1, is fully exposed, forming a coreless semi-finished substrate without any core layer. The reinforcing layer 6 provides temporary mechanical support at this stage.

[0053] Specifically, by using a peelable interface, the peelable carrier 1 can be completely peeled off, directly achieving a coreless 101 structure. The substrate thickness can be reduced by more than 50%, and the heat dissipation path is no longer blocked by the low thermal conductivity core layer, significantly optimizing the heat dissipation distance and speed. The peeling process only requires adding a station to the existing production line, with minimal changes to the production line layout, low investment threshold, wide selection of board manufacturers, and controllable supply disruption risk. The temporary carrier board can be recycled and reused, further reducing material costs.

[0054] S7. Apply dry film to the surfaces of the copper layers 102 of the two coreless semi-finished substrates that are close to each other, and fabricate the circuit structure layer according to the mSAP process (modified semi-additive process) to obtain the semi-finished substrate; encapsulate the semi-finished substrate and remove the reinforcing layer 6; perform electrical performance testing after encapsulation; if the test is qualified, package and put into storage to obtain the through-hole encapsulation structure of the substrate.

[0055] After the reinforcing layer 6 is bonded, the peelable carrier 1 is slowly and uniformly pulled horizontally to completely separate the copper layer 102 on the opposite side to be peeled from the peelable interface, while retaining the functional layer on the other side. After peeling, a weak acidic micro-etching solution is used to remove the residual adhesive of the peeling layer on the board surface. After washing and drying, a coreless semi-finished substrate is obtained.

[0056] The circuit structure layer is fabricated directly using mSAP technology, which is fully compatible with existing high-end substrate production lines. Board manufacturers require no major modifications, and supply channels are diversified. The molding process replaces the reinforcing layer 6, providing permanent rigidity and solving the mechanical strength problem of coreless substrates. Combined with microvias and mSAP fine-linewidth technology, the line density is increased by at least 10% for the same unit area, allowing for further reduction in unit size and smaller packages. Furthermore, it can be used in conjunction with buried vias to develop multilayer stacking and advanced via technologies, achieving vertical interconnection between layers, shortening signal transmission paths, reducing crosstalk, and improving signal integrity. This makes it highly adaptable to future high-density integration and high-frequency, high-speed applications.

[0057] Specifically, the substrate coreless 101 obtained through the above steps is thinner and has a relatively lower cost; for applications with extremely stringent requirements on packaging thickness, the substrate through-hole packaging structure of the present invention is more suitable, providing higher redundancy for the packaging structure.

[0058] In this embodiment, the resin-coated copper layer 2 includes a resin layer 21 that adheres to the side of the copper layer 102 away from the core board 101, and a copper layer 22 that is adhered to and fixed to the resin layer 21. The resin layer 21 is used to increase the adhesion and fixation performance with the copper layer 102 of the peelable carrier 1, which facilitates the subsequent overall separation of the copper layer 102 from the core board 101.

[0059] Step S1 specifically includes the following sub-steps: Pretreatment: The upper and lower surfaces of the peelable carrier 1 are etched with a browning solution to remove two copper layers 102, and the removal amount of the two copper layers 102 is controlled to be 0.2~1.5μm respectively, forming a uniform rough surface.

[0060] In this process, a browning solution (a chemical treatment solution containing sulfuric acid, hydrogen peroxide and organic additives) is used to perform micro-etching on the surfaces of the two copper layers 102 on the upper and lower sides of the peelable carrier 1. By controlling the etching time and the concentration of the solution, the amount of copper layer 102 removed on both sides is precisely controlled to be 0.2~1.5μm, forming a uniformly distributed micron-level micro-rough morphology on the copper surface.

[0061] Specifically, by forming a uniform micro-rough structure in the copper layer 22, the bonding force between the peelable carrier 1 and the copper layer 22 is improved through the mechanical interlocking effect; at the same time, the amount of removal is strictly controlled within the range of 0.2 to 1.5 μm; if the amount of removal is insufficient, the roughness will be insufficient and the bonding force will be too weak, and if the amount of removal is too large, the anchoring effect will be too strong and the peeling strength will exceed the standard.

[0062] Simultaneously removing the oxide layer, oil, and impurities from the copper layer 22 ensures a clean and activated copper surface, which facilitates uniform bonding between the resin and the copper layer 22. Furthermore, the uniform surface roughness ensures stable and controllable interfacial separation force during subsequent peeling, preventing localized peeling difficulties or residue.

[0063] Lamination and alignment: The two resin layers 21 are respectively bonded to the predetermined areas of the two copper layers 102 to complete the pre-fixation and obtain the initial product carrier. The initial product carrier consists of two resin-coated copper layers 2 and the peelable carrier 1.

[0064] In this process, two resin layers 21 are aligned and bonded to predetermined areas of two copper layers 102. Positioning pins or an optical alignment system are used to ensure the positional accuracy of the resin-attached copper layer 2 and the two upper and lower copper layers 102. The initial viscosity of the resin at room temperature is used to complete the pre-fixation, preventing interlayer displacement caused by resin flow during subsequent vacuum lamination.

[0065] Specifically, this lays the geometric foundation for the subsequent alignment of the vias 4 on both sides and the accuracy of interlayer interconnection, avoiding misalignment of vias 4 or interconnection failure due to stack offset, and ensuring alignment accuracy.

[0066] By utilizing the initial viscosity of the resin, interlayer pre-positioning is achieved, preventing interlayer slippage caused by resin flow during vacuum lamination, improving lamination yield, and providing pre-fixation to prevent displacement.

[0067] The symmetrical stacked design arranges the resin-copper foil layer 2 symmetrically on both the upper and lower sides, which helps to balance the residual stress in subsequent processes and reduce the risk of substrate warping and deformation.

[0068] Vacuum lamination: The obtained initial carrier is placed in a vacuum laminator, and the heating, pressurization, resin flow filling and curing processes are completed in sequence to obtain a resin cured body.

[0069] The process involves placing the pre-stacked resin-coated copper layer 2 and the temporary carrier board into a vacuum laminator, where four stages of the process are completed sequentially under vacuum: Heating: causing the RCC resin to gradually transform from the B-stage (semi-cured) glassy state to the viscous flow state; Pressurization: applying pressure to promote full resin flow; Resin flow filling: the viscous flow resin fills and penetrates the micro-rough structure of the copper layer 22 under pressure, forming mechanical interlocking, while the vacuum environment eliminates interlayer bubbles; Curing: continuing to heat the resin to cause a cross-linking curing reaction (transforming from the B-stage to the C-stage fully cured state), forming a structurally stable resin cured body.

[0070] Specifically, by precisely controlling the lamination temperature, pressure, and time curves, the filling depth and cross-linking degree of the resin on the rough structure of the copper layer 22 are adjusted, so that the bonding strength between the copper and resin interfaces is stabilized within the peelable range, ensuring that no delamination occurs during the process flow and that complete separation is achieved during the S6 peeling.

[0071] The vacuum environment effectively eliminates interlayer bubbles, ensuring the density and insulation reliability of the resin-coated copper layer 2 and avoiding void defects; through simultaneous double-sided lamination, the structure is symmetrical and the residual stress is balanced, significantly reducing the risk of substrate warping.

[0072] Post-processing: After cooling and depressurizing the cured resin body, and then cooling it to room temperature, it is ready for the next process.

[0073] After the resin has cured, the cured resin body is slowly cooled to room temperature by gradient cooling and gradual depressurization to avoid internal stress caused by rapid cooling and pressure. Then the board surface is cleaned (usually by plasma cleaning or wet cleaning) to remove excess glue, debris and surface contaminants generated during the lamination process, so that the board surface is clean and provides qualified surface conditions for the S2 coating and exposure process.

[0074] Specifically, slow cooling and depressurization effectively release lamination stress, reducing residual stress caused by thermal expansion coefficient (CTE) mismatch between the cured resin and the copper layer, thus lowering the risk of substrate warpage and delamination in subsequent processes. Board surface cleaning ensures uniform adhesion and stable exposure and development accuracy during step S2 dry film application, avoiding photolithography defects caused by surface contamination; a stable and clean board is then transferred to the next process, ensuring continuity and yield consistency throughout the entire process chain, and smooth process transitions.

[0075] In this embodiment, the heating process specifically involves raising the room temperature to 170℃~250℃, maintaining the temperature for curing for 60~90 minutes, and a heating rate ≤5℃ / min. The temperature range of 170℃~250℃ is the optimal temperature window for the crosslinking reaction of the epoxy resin system (RCC resin) from the B-stage semi-cured state to the C-stage fully cured state. If the temperature is too low, the crosslinking reaction will be insufficient, resulting in inadequate resin curing and substandard mechanical strength and insulation properties. If the temperature is too high, the curing reaction will be too vigorous, the resin flow window will be too narrow, and excessive internal stress or even thermal degradation of the resin may occur. The 60~90 min constant-temperature curing ensures sufficient crosslinking of the resin, allowing the degree of curing to reach a stable plateau (typically ≥95%), and ensuring that the resin's glass transition temperature (Tg), modulus, insulation strength, and other properties reach the design values. Heating rate ≤ 5℃ / min: Slow gradient heating ensures that the resin has sufficient time to flow and fill from the glassy state to the viscous state before entering the rapid curing stage, allowing the resin to penetrate evenly into the micro-rough structure of the copper layer 22. Heating too quickly will cause the surface layer of the resin to cross-link and cure first, while the interior is still flowing, forming an uneven "shell-core" curing, generating internal stress and residual bubbles.

[0076] The pressure of the pressurization process is controlled at 15~30 kg / cm², and the vacuum degree is maintained at ≤5 mbar throughout the process.

[0077] Lamination pressure is the core driving force for resin flow and filling. If the pressure is too low, the resin flow will be insufficient, failing to fully penetrate the microscopic rough structure of the copper layer 22, resulting in weak mechanical anchoring, insufficient interfacial bonding, and a tendency for voids to appear. If the pressure is too high, excessive resin loss will lead to a thinner resin-coated copper layer 2, poor in-plane uniformity, and may even cause plastic deformation of the temporary carrier. 15~30 kg / cm² is the optimal pressure range for RCC lamination, balancing filling effect and thickness control. A vacuum degree ≤5 mbar continuously extracts interlayer air, resin volatiles, and moisture throughout the lamination process in a high-vacuum environment, fundamentally avoiding the formation of bubbles and voids. Insufficient vacuum (excessive pressure) will cause residual gas to be compressed and trapped within the resin-coated copper layer 2, forming bubble defects that severely affect insulation reliability and bonding uniformity.

[0078] The thickness difference after lamination in the curing process is ≤5μm; this indicator reflects the uniformity of resin flow and filling, the uniformity of pressure distribution, and the flatness of the temporary carrier board. Excessive thickness difference means that the resin-coated copper layer 2 is uneven in thickness in different areas of the board surface, which will directly lead to a chain of problems such as inconsistent depth of subsequent through holes 4, reduced grinding flatness yield, and damage to circuit fabrication accuracy.

[0079] The cooling process has a cooling rate of ≤3℃ / min. Slow cooling allows sufficient time for internal stress to be gradually released through the viscoelastic relaxation of the resin, avoiding stress concentration.

[0080] In this embodiment, each copper layer 102 includes a first copper layer 1021 and a second copper layer 1022 that are stacked and bonded together. The two second copper layers 1022 are respectively bonded and fixed between the upper and lower surfaces of the core 101 and the two first copper layers 1021. The thickness of the second copper layer 1022 is 10~18μm, and the thickness of the first copper layer 1021 is 3~5μm. Step S7 is performed on the surface of the first copper layer 1021 near the second copper layer 1022. The core 101 and the first copper layer 1021 are connected by the second copper layer 1022. The adhesion between the first copper layer 1021 and the second copper layer 1022 is less than the adhesion between the first copper layer 1021 and the resin layer 21, which facilitates the separation of the first copper layer 1021 and the second copper layer 1022 in the subsequent process step S6.

[0081] In this embodiment, step S2 includes the following sub-steps: The resin-coated copper layer 2 is cleaned to remove oil and oxide layers. A dry film or a photosensitive material of a predetermined thickness is then laminated onto the surface of the resin-coated copper layer 2. The pattern is directly transferred to a predetermined position on the dry film or the photosensitive material using a laser direct imaging (LDI) machine. Then, the copper layer 22 in the predetermined position is completely removed by acid etching, exposing the resin layer 21 below the removed copper layer 22, thus obtaining the through-hole window. The window area of ​​the through-hole window is then roughened by micro-etching to remove etching residue.

[0082] Specifically, the cleanliness of the copper layer 22 ensures uniform and reliable adhesion between the dry film or photosensitive material and the copper layer 22, avoiding defects such as film bubbles and residual film during development; at the same time, it can also ensure the yield and accuracy of photolithography pattern transfer from the source.

[0083] A dry film photoresist or a liquid photosensitive material (such as photoresist) of a predetermined thickness is laminated onto the cleaned copper layer 22 to form a uniform photosensitive layer, which serves as the photosensitive medium for subsequent LDI exposure. The predetermined thickness control ensures the steepness of the pattern sidewalls and dimensional accuracy after exposure and development.

[0084] Using a laser direct imaging exposure machine (LDI), the through-hole window pattern designed in the engineering drawing is directly transferred to a predetermined position on the photosensitive material by scanning and exposing with a laser beam. There is no need for traditional film, and the inner target can be directly identified for automatic alignment.

[0085] The exposed copper foil area is completely etched away using an acidic etching solution (usually copper chloride or an alkaline etching system) until the underlying resin-coated copper layer 2 is exposed, forming a through-hole window pattern. This provides an etching mask for subsequent laser drilling. Precise through-hole window positions are formed, with the bottom of the window extending directly to the resin-coated copper layer 2, providing a clear starting surface and positioning reference for laser drilling in step S3.

[0086] The via opening size is 2-5 μm larger than the laser aperture size of the LDI laser direct imaging exposure machine. This compensates for the energy distribution characteristics of the LDI laser spot, ensuring that the final actual opening size meets design requirements and avoiding difficulties in subsequent drilling due to undersized openings. The lateral etching depth is ≤12 μm. This depth ensures steep opening edges, precise dimensions, and minimal pattern transfer distortion, facilitating precise size control of the openings. A small lateral etching depth also means less loss of copper bridge width between adjacent openings, allowing for smaller opening spacing and supporting higher-density via arrays, directly increasing substrate wiring density. The deviation between the via opening and the inner layer target is <15 μm. This alignment ensures precise alignment between the via opening and the inner layer pads / circuit, providing a reliable positional basis for subsequent vertical interconnection between the vias and the inner layer, avoiding interconnect failures caused by alignment deviations.

[0087] Among them, the amount of undercut refers to the amount of copper foil that is not protected by the resist layer not only vertically downward during the acid etching process, but also penetrates laterally along the edge of the resist layer, resulting in the hollowing out of the side of the circuit.

[0088] An inner layer target (or alignment mark) is a pre-made alignment mark / reference point on the inner core board (or the next outermost circuit layer) for interlayer alignment during processes such as lamination, exposure, and drilling.

[0089] In this embodiment, step S3 specifically includes the following sub-steps: Based on the thickness of the resin-coated copper layer 2, a suitable laser type and matching parameters are selected. Under correct alignment, the coordinates of the inner target are identified by an X-ray scanning system (X-Ray Alignment System, hereinafter referred to as X-Ray Alignment Machine). The resin area exposed at the through-hole opening is ablated to form a micro-through-hole that penetrates the dielectric layer. After the micro-holes are opened, the residual resin carbides inside the holes are removed by plasma or chemical desmearing agents, and then the hole diameter and hole wall quality are fully inspected by a two-dimensional imaging instrument and the X-ray scanning system. The hole wall roughness Ra ≤ 0.5 μm.

[0090] Specifically, leveraging the penetrating power of X-rays and their high contrast with metals like copper, the precise coordinates of the inner copper target are scanned and identified. A global coordinate system is established, enabling high-precision automatic alignment of via 4 with the inner target. X-rays can directly identify the inner copper pattern covered by resin, unaffected by surface obstruction. Direct X-ray identification of the actual inner copper target avoids errors caused by surface expansion and contraction, and alignment mark misalignment, resulting in alignment accuracy far exceeding optical alignment, ensuring precise alignment of via 4 with the inner pads. Laser processing of microvias enables the core interconnect structure of the coreless substrate.

[0091] The holes are treated with plasma (dry method) or chemical solutions (wet method, such as potassium permanganate / sodium permanganate solution) to oxidize and remove residual resin carbides, exposing clean resin hole walls and the copper layer at the bottom of the holes. This thoroughly removes resin residue from the hole walls, exposing a clean resin surface. Plasma treatment can also slightly roughen the hole walls, further increasing the mechanical anchoring points for electroless copper plating and improving the adhesion of the copper layer. Both plasma and chemical methods can be flexibly selected according to the production line configuration, ensuring strong production line compatibility.

[0092] In this embodiment, step S4 specifically includes: Palladium catalyst sites are deposited on the walls of the vias 4, and a 0.5-1 μm thick conductive copper layer 11 is formed by electroless copper plating, achieving full conductivity of the via walls. First, palladium (Pd) catalyst sites are deposited on the resin surface of the via walls through an activation process, serving as the starting point for the autocatalytic reaction of electroless copper plating; then, the substrate is immersed in the electroless copper plating solution, and with palladium as the catalytic core, a copper layer is autocatalytically deposited on the resin surface of the via walls through a redox reaction, forming a uniform conductive copper layer 11 with a thickness of 0.5-1 μm, making the originally insulating resin via walls fully conductive.

[0093] Next, low-current electroplating is used to thicken the conductive copper layer on the hole walls to 5-8 μm, providing a basic conductive layer for subsequent hole filling. Specifically, using a chemically plated copper layer as the conductive substrate, low current density is employed to electroplat the entire board, uniformly thickening the copper layer on the hole walls from 0.5-1 μm to 5-8 μm. The slow and uniform copper ion deposition rate at low current density avoids edge effects (burning) and abnormal thickening of the hole openings caused by high current, providing a dense, uniform, and reliable basic conductive layer for subsequent pulse-filling electroplating.

[0094] Finally, a highly dispersible copper plating solution is used, and pulse plating is employed to allow copper ions to uniformly deposit from the bottom of the through-hole 4 upwards, completely filling the through-hole 4. Specifically, a highly dispersible (high throwing power) copper plating solution is used in conjunction with pulse plating technology. The pulsed current, through alternating waveforms of forward deposition and reverse etching, combined with the synergistic effect of special additives (accelerators, inhibitors, and leveling agents) in the plating solution, produces a super-filling (bottom-up filling) effect; copper ions preferentially deposit at the bottom of the hole and grow uniformly from bottom to top, ultimately completely filling the through-hole 4, forming a solid copper pillar 5 without voids or depressions.

[0095] In this embodiment, the copper layer 22 with resin-coated copper layer 2 is insulated from the copper pillar 5, or the contact points are insulated. Furthermore, the spaced-apart copper pillars 5 are not connected to each other to prevent short circuits.

[0096] In this embodiment, step S7 specifically includes the following steps: Dry film is laminated onto the surfaces of the copper layers 102 of the two coreless semi-finished substrates that are close to each other; and the following processes are performed sequentially: first exposure → first development → copper electroplating → film removal → flash etching → solder resist lamination → second exposure → second development → nickel-gold or nickel-gold surface treatment → film removal → board separation → electrical testing → OSP treatment → marking → cleaning → packaging, to obtain the through-hole package structure 100 of the substrate. Specifically, dry film lamination is performed on the surface of the first copper layer 1021.

[0097] The solder mask layer 16 is obtained by applying a solder mask film to expose the pad area to be soldered. The remaining circuit area is completely covered and protected by the solder mask layer 16, thereby preventing solder from flowing in the non-pad area during soldering and causing bridging and short circuits.

[0098] Specifically, the mSAP additive process and the coreless substrate structure work in synergy. The coreless structure eliminates the thickness bottleneck caused by the core 101, while mSAP achieves high-density wiring on a limited ultra-thin substrate area with its fine linewidth / spacing capabilities. Together, they achieve the structural advantages of "thinner thickness and denser wiring." The rectangular cross-section lines formed by the additive process have steep edges and a flat surface, resulting in excellent signal transmission characteristics, further strengthening the inherent advantages of the coreless substrate in terms of "fast heat dissipation and short signal path."

[0099] In one embodiment of the present invention, step S7 specifically includes the following steps: Dry films are laminated onto the surfaces of the copper layers 102 of the two coreless semi-finished substrates that are close to each other; and the following processes are performed in sequence: first exposure → first development → copper electroplating → film removal → flash etching → solder resist lamination → second exposure → second development, to obtain the semi-finished substrate.

[0100] The process of removing the film involves using an alkaline film-removing solution (such as NaOH) to peel off the remaining dry film mask, exposing the unplated original copper layer underneath.

[0101] Flash etching is a rapid, thin-layer etching process using a micro-etching solution (such as a sodium persulfate / sulfuric acid system) to remove the seed layer copper between electroplated patterns, thus achieving electrical isolation between the circuits / pads. The flash etching time is strictly controlled to remove only the thin layer of base copper without damaging the already thickened copper plating.

[0102] The semi-finished substrate is encapsulated in plastic and the reinforcing layer 6 is removed. The surface of the semi-finished substrate after removing the reinforcing layer 6 is treated with nickel-gold or nickel-gold plating. For products with completed surfaces, production continues according to the post-packaging process; wherein, the post-packaging process includes product marking, finished product cutting, and finished product inspection in sequence; The electrical performance of the single packaged product with good appearance is tested. The tested good products are then packaged and stored. The entire packaging process is completed, and the substrate through-hole packaging structure 100 is obtained.

[0103] The substrate produced in this way has no core layer, is thinner, and has a relatively lower cost. For applications with extremely stringent requirements on packaging thickness, the substrate structure of this invention is more suitable, leaving more redundancy for the packaging structure.

[0104] In this embodiment, the surface treatment is located in the middle region of the through-hole encapsulation structure 100 of the substrate. Specifically, the surface treatment is as follows: a nickel layer 8, a palladium layer 9, and a gold layer 10 are sequentially electroplated on the electroplated copper.

[0105] Specifically, qualified semi-finished substrates are encapsulated. After molding, the reinforcing layer 6 is removed, followed by surface cleaning and baking. Different surface treatments are then applied according to process requirements, such as nickel-palladium plating or nickel-palladium-gold plating. For the finished products, production continues according to post-encapsulation processes, such as product marking, finished product cutting, and finished product inspection. Electrical performance is tested on individually encapsulated, aesthetically pleasing products, and those that pass testing are packaged and stored, completing the entire encapsulation process. This results in high product quality and high production efficiency.

[0106] Example 2 Please see Figures 10-12 As shown, this embodiment of the invention provides a substrate through-hole packaging structure 100, which is used in radio frequency semiconductors. The substrate through-hole packaging structure 100 is obtained by the above-described method for manufacturing substrate through-hole packaging structures.

[0107] The substrate through-hole packaging structure 100 includes a first copper layer 1021, a resin-coated copper foil layer 2 stacked and fixed to the first copper layer 1021, a plurality of through holes 4 forming intervals through the resin-coated copper foil layer 2, copper pillars 5 electroplated on the inner walls of the through holes 4, a reinforcing layer 6 bonded to the side of the resin-coated copper foil layer 2 away from the first copper layer 1021, a dry film layer 7 laminated to the side of the first copper layer 1021 away from the resin-coated copper foil layer 2, a plurality of first grooves 13 and second grooves 14 formed by the recesses of the dry film layer 7, a copper plating layer 15 in the first grooves 13 and the second grooves 14, a nickel layer 8, a palladium layer 9 and a gold layer 10 sequentially electroplated on the copper plating layer 15 in the first groove 13, and a protective layer 12 that completely covers the copper plating layer 15 in the second groove 14.

[0108] Specifically, the first copper layer 1021 serves as one conductive layer of the substrate through-hole encapsulation structure 100 and is also the bottom connection surface of the copper pillar 5; the resin-coated copper layer 2 is an insulating dielectric layer, replacing the insulating function of the traditional core; the copper pillar 5 penetrates the resin-coated copper layer 2, with one end connected to the first copper layer 1021 and the other end extending to the other surface of the resin-coated copper layer 2, achieving vertical electrical interconnection between the upper and lower surfaces of the resin-coated copper layer 2. By removing the traditional core, the thickness of the substrate through-hole encapsulation structure 100 is significantly reduced, the heat dissipation path is shortened, and the heat dissipation efficiency is improved; the solid copper pillar 5 has low resistance, good thermal conductivity, low signal transmission loss, and excellent high-frequency performance. The reinforcing layer 6 is attached to the side of the resin-coated copper layer 2 away from the first copper layer 1021, temporarily replacing the mechanical support function of the core 101 during the coreless substrate fabrication process, preventing the ultra-thin resin-coated copper layer 2 from warping, deforming, or breaking during peeling off the carrier board and subsequent processing; it is removed after molding or other permanent support structures are formed.

[0109] By laminating a dry film layer 7 onto the side of the first copper layer 1021 away from the resin-coated copper foil layer 2, and by exposure and development, the dry film layer 7 is locally recessed to form a first groove 13 and a second groove 14, exposing the carrier copper foil layer 22 at the bottom of the groove. Three metal layers—nickel layer 8 (Ni), palladium layer 9 (Pd), and gold layer 10 (Au)—are sequentially electroplated within the first groove 13. The nickel layer 8 serves as a barrier layer to prevent copper diffusion, the palladium layer 9 serves as an intermediate layer for oxidation resistance and enhanced soldering reliability, and the gold layer 10 serves as the outermost protective and wetting layer.

[0110] After electroplating a nickel layer 8 in the second groove 14, a protective layer 12 (usually an OSP organic solder resist film or other passivation protective layer 12) is applied to the entire surface of the nickel layer 8 to protect the nickel layer 8 from oxidation and maintain solderability. The protective layer 12 effectively prevents oxidation of the nickel surface, ensuring wettability and reliability during soldering.

[0111] In this embodiment, the resin-coated copper layer 2 includes two resin layers 21 that adhere to the upper and lower surfaces of the peelable carrier 1, and two copper layers 22 that are respectively adhered to and fixed to the two resin layers 21. The two resin layers 21 form peelable interfaces with the first copper layer 1021, and the two copper layers 22 provide conductive substrates for the subsequent fabrication of double-sided vias 4 and circuit layers. The upper and lower copper layers 22 and the two resin layers 21 provide a symmetrical processing substrate for the fabrication of double-sided vias 4, and the copper pillars 5 can be independently processed on both sides, laying the structural foundation for double-sided interconnection and multi-layer stacking.

[0112] It should be noted that the various embodiments described above with reference to the accompanying drawings are merely illustrative of the present invention and not intended to limit its scope. Those skilled in the art should understand that any modifications or equivalent substitutions made to the present invention without departing from its spirit and scope should be included within the scope of the present invention. Furthermore, unless the context otherwise requires, words appearing in the singular include those in the plural, and vice versa. Additionally, unless specifically stated otherwise, all or part of any embodiment may be used in conjunction with all or part of any other embodiment.

Claims

1. A method for manufacturing a substrate through-hole packaging structure, characterized in that, The manufacturing method of the substrate through-hole packaging structure includes the following steps: S1. A peelable carrier is provided, which includes a core board and two copper layers respectively coated and fixed on both sides of the core board. The upper and lower surfaces of the peelable carrier are respectively subjected to a pressing treatment to form two resin-coated copper layers. S2. Clean the surfaces of the two resin-coated copper layers to remove oil and oxide layers, and coat the surfaces of the two resin-coated copper layers to obtain two coating layers. Then expose and develop the two coating layers to obtain through-hole windows. S3. Drill holes at the opening positions of the through holes to obtain through holes; wherein, the through holes sequentially penetrate the corresponding coating layer and the resin-coated copper layer until they reach the surface of the two copper layers of the peelable carrier; S4. Perform chemical copper plating and electroplating copper treatment on the through hole in sequence, and finally completely fill the through hole with electroplated copper. S5. Grind the surface of the electroplated copper to make the surface of the electroplated copper flush with the surface of the coating layer, and at the same time attach a reinforcing layer to the surface of the electroplated copper and the surface of the coating layer to obtain a preliminary substrate sample. S6. Pull the substrate sample at a constant speed along its length or width direction so that the copper layers on the upper and lower sides of the peelable carrier are separated from the core, and two coreless semi-finished substrates are obtained. S7. Apply a dry film to the copper layers of the two coreless semi-finished substrates that are close to each other, and fabricate a circuit structure layer according to the mSAP process to obtain a semi-finished substrate; encapsulate the semi-finished substrate with plastic, remove the reinforcing layer, and perform electrical performance testing after encapsulation to obtain the through-hole encapsulation structure of the substrate.

2. The method for manufacturing a substrate through-hole packaging structure according to claim 1, characterized in that, The resin-coated copper foil layer includes a resin layer that adheres to the side of the copper layer away from the core board and a copper foil layer that adheres to and is fixed to the side of the resin layer away from the peelable carrier. Step S1 specifically includes the following sub-steps: Pretreatment: The upper and lower surfaces of the peelable carrier are etched with a browning solution to remove the two copper layers, and the removal amount of the two copper layers is controlled to be 0.2~1.5μm respectively, forming a uniform rough surface; Lamination and alignment: The two resin layers are respectively bonded to the predetermined areas of the two copper layers to complete the pre-fixation and obtain the initial carrier. Vacuum lamination: The primary carrier is placed in a vacuum laminator, and the heating, pressurization, resin flow filling and curing processes are completed in sequence to obtain a resin-cured body; Post-processing: The cured resin body is cooled and depressurized, and then cooled to room temperature before proceeding to the next step.

3. The method for manufacturing a substrate through-hole packaging structure according to claim 2, characterized in that, The heating process specifically involves raising the room temperature to 170℃~250℃, maintaining the temperature for curing for 60~90 minutes, and a heating rate ≤5℃ / min. The pressure of the pressurization process is controlled at 15~30 kg / cm², and the vacuum degree is maintained at ≤5 mbar throughout the process; The thickness difference after pressing in the curing process is ≤5μm; The cooling process has a cooling rate of ≤3℃ / min.

4. The method for manufacturing a substrate through-hole packaging structure according to claim 2, characterized in that, Each copper layer includes a first copper layer and a second copper layer that are stacked and bonded together. The two second copper layers are respectively bonded and fixed between the upper and lower surfaces of the core and the two first copper layers. Wherein, the thickness of the second copper layer is 10~18μm, and the thickness of the first copper layer is 3~5μm; step S7 is performed on the surface of the first copper layer near the second copper layer.

5. The method for manufacturing a substrate through-hole packaging structure according to claim 2, characterized in that, Step S2 includes the following sub-steps: The resin-coated copper layer is cleaned to remove oil and oxide layers, and then a dry film is pressed onto the surface of the resin-coated copper layer or a photosensitive material of a predetermined thickness is coated. The pattern is directly transferred to a predetermined position on the dry film or the photosensitive material using a laser direct imaging exposure machine. Then, the copper layer exposed at the predetermined position is completely removed by acid etching to expose the resin layer below the removed copper layer, thus obtaining the through-hole window. The window area of ​​the through-hole window is then roughened by micro-etching to remove etching residue. The size of the through-hole window is 2-5 μm larger than the size of the laser hole in the laser direct imaging exposure machine, the lateral etching amount is ≤12 μm, and the deviation between the through-hole window and the inner target is <15 μm.

6. The method for manufacturing a substrate through-hole packaging structure according to claim 1, characterized in that, Step S3 specifically includes the following sub-steps: Based on the thickness of the resin-copper foil layer, a suitable laser type and corresponding parameters are selected, and under correct alignment, the coordinates of the inner target are identified by an X-ray scanning system. The resin area exposed at the through-hole opening is then ablated to form a micro-through-hole that penetrates the dielectric layer. After the micro-holes are opened, the residual resin carbides inside the holes are removed by plasma or chemical desmearing agents, and then the hole diameter and hole wall quality are fully inspected by a two-dimensional imaging instrument and the X-ray scanning system. The hole wall roughness Ra ≤ 0.5 μm.

7. The method for manufacturing a substrate through-hole packaging structure according to claim 6, characterized in that, Step S4 is as follows: Palladium catalyst sites are deposited on the walls of the through holes, and a 0.5~1μm thick conductive copper layer is formed by chemical copper plating to achieve full conductivity of the hole walls; Next, the conductive copper layer on the hole wall is thickened to 5~8μm by low-current whole-board electroplating, providing a basic conductive layer for subsequent hole plugging; Finally, a highly dispersible copper plating solution is used, and copper ions are uniformly deposited from the bottom of the through hole upwards through pulse electroplating to completely fill the through hole.

8. The method for manufacturing a substrate through-hole packaging structure according to claim 1, characterized in that, Step S7 specifically includes the following steps: Dry films are laminated onto the copper layers of the two coreless semi-finished substrates that are close to each other; and the following processes are performed in sequence: first exposure → first development → copper electroplating → film removal → flash etching → solder resist lamination → second exposure → second development → nickel-gold or nickel-gold surface treatment → film removal → board separation → electrical testing → OSP treatment → marking → cleaning → packaging, to obtain the through-hole encapsulation structure of the substrate.

9. The method for manufacturing a substrate through-hole packaging structure according to claim 1, characterized in that, Step S7 specifically includes the following steps: Dry film is laminated onto the copper layers of the two coreless semi-finished substrates that are close to each other; and the following processes are performed in sequence: first exposure → first development → copper electroplating → film removal → flash etching → solder resist lamination → second exposure → second development, to obtain the semi-finished substrate. The semi-finished substrate is encapsulated in plastic and the reinforcing layer is removed. The surface of the semi-finished substrate after the reinforcing layer is removed is treated with nickel-gold or nickel-gold surface coating. For products with completed surfaces, production continues according to the post-packaging process; wherein, the post-packaging process includes product marking, finished product cutting, and finished product inspection in sequence; The electrical performance of the single, well-packaged product is tested, and the tested products are packaged and stored. The entire packaging process is completed, resulting in the through-hole packaging structure of the substrate.

10. A substrate through-hole packaging structure, used in radio frequency semiconductors, characterized in that, The substrate is manufactured by the method of manufacturing the substrate through-hole packaging structure according to any one of claims 1-9.

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