Semiconductor structure

Abstract

The application provides a semiconductor structure. In the semiconductor structure, a substrate includes a substrate body, a conductive part and an auxiliary connecting part arranged on the same side of the substrate body and spaced apart, and the conductive part includes a first region and a second region. An electrical connecting piece is of an integrated structure and includes a first pin and a bearing part; the first pin is attached to the first region. A first semiconductor element is attached to the second region. The first region and the auxiliary connecting part are located on different sides of the second region. A second semiconductor element is attached to the bearing part. One end of a first lead wire is connected to the first semiconductor element, and the other end is connected to the second semiconductor element. One end of a second lead wire is connected to the bearing part, and the other end is connected to the auxiliary connecting part; the cross-sectional area of the second lead wire is larger than that of the first lead wire. A plastic sealing layer encapsulates the substrate, the electrical connecting piece, the first semiconductor element, the second semiconductor element, the first lead wire and the second lead wire, and each pin is at least partially exposed from the plastic sealing layer.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure. Background Technology

[0002] Common semiconductor packaging technologies, such as chip packaging technology, typically include the following process: First, the leads of the lead frame and the field-effect transistor are mounted on the metal layer (usually a copper layer) of the substrate; then, the chip is mounted on the base island of the lead frame; then, the chip's pads are electrically connected to the gate of the MOSFET using leads; finally, a molding compound is formed, which encapsulates the substrate, chip, lead frame, and leads.

[0003] During the handling of semiconductor structures obtained using the above-mentioned packaging technology, the neck of the lead (the position with the smallest cross-section of the lead) is prone to breakage, affecting the product yield. Summary of the Invention

[0004] This application provides a semiconductor structure. The semiconductor structure includes:

[0005] A substrate includes a substrate body and a conductive portion and an auxiliary connection portion located on one side of the substrate body; the conductive portion and the auxiliary connection portion are located on the same side of the substrate body and are arranged at intervals; the conductive portion includes a first region and a second region.

[0006] The electrical connector is an integral structure, including multiple pins and a carrier portion; the multiple pins include a first pin, which is attached to a first region of the conductive portion;

[0007] A first semiconductor element is mounted on a second region of the conductive portion; the first region and the auxiliary connection portion are located on different sides of the second region;

[0008] A second semiconductor element is mounted on the carrier portion;

[0009] The first lead has one end connected to the first semiconductor element and the other end connected to the second semiconductor element;

[0010] The second lead has one end connected to the bearing part and the other end connected to the auxiliary connection part; the cross-sectional area of ​​the second lead is larger than that of the first lead.

[0011] A molding compound encapsulates the substrate, the electrical connector, the first semiconductor element, the second semiconductor element, the first lead, and the second lead, with each of the pins at least partially exposed by the molding compound.

[0012] In one embodiment, the first region and the auxiliary connection portion are located on opposite sides of the second region.

[0013] In one embodiment, the conductive layer includes at least two auxiliary connection portions, the semiconductor structure includes at least two second leads, and each of the auxiliary connection portions is connected to the carrier portion through the second leads.

[0014] In one embodiment, the orthographic projection of the first lead on the plane of the substrate body facing the conductive layer does not overlap with the orthographic projection of the second lead on the same plane.

[0015] In one embodiment, the distance between the orthographic projection of the first lead on the plane and the orthographic projection of the second lead on the plane is greater than or equal to 100 μm.

[0016] In one embodiment, the cross-sectional area of ​​the second lead ranges from 56.52 μm. 2 ~157μm 2 .

[0017] In one embodiment, the support portion is located on the side of the auxiliary connection portion away from the second region.

[0018] In one embodiment, the first semiconductor element includes a control electrode, a first electrode, and a second electrode, the control electrode and the first electrode being located on the surface of the first semiconductor element away from the substrate; the first lead is connected to the control electrode; the semiconductor structure further includes a third lead that electrically connects the first electrode and one of the pins; the material of the third lead is the same as the material of the second lead.

[0019] In one embodiment, the maximum distance between the second lead and the substrate body is less than the maximum distance between the first lead and the substrate body.

[0020] In one embodiment, the second lead is made of aluminum, and the first lead is made of copper.

[0021] In one embodiment, the semiconductor structure further includes a fast recovery diode and a third lead; the fast recovery diode is mounted on the conductive portion, the anode of the fast recovery diode is disposed on the surface of the fast recovery diode away from the substrate, and the cathode is disposed on the surface of the fast recovery diode facing the substrate and electrically connected to the auxiliary connection portion; the first semiconductor element includes a control electrode, a first electrode, and a second electrode, the control electrode and the first electrode are disposed on the surface of the first semiconductor element away from the substrate, and the second electrode is disposed on the surface of the first semiconductor element facing the substrate and electrically connected to the auxiliary connection portion; the first lead is connected to the control electrode; the anode of each fast recovery diode is electrically connected to the first electrode of one of the first semiconductor elements through the third lead; and / or,

[0022] The substrate further includes a metal heat dissipation layer located on the side of the substrate body away from the conductive layer; the surface of the metal heat dissipation layer away from the substrate body exposes the molding layer.

[0023] The main technical effects achieved by the embodiments of this application are:

[0024] The semiconductor structure provided in this application embodiment has a first pin connected to a first region of the conductive part, and a second lead connected to an auxiliary connection part and a carrier part, respectively. The first region of the conductive part used to mount the first pin and the auxiliary connection part are located on different sides of the second region of the conductive part used to mount the first semiconductor element. That is, the two regions of the substrate located on different sides of the second region of the conductive part are respectively connected to the electrical connector of the integrated structure. Since the cross-sectional area of ​​the second lead is larger than that of the first lead, the second lead is less prone to breakage. This allows the two ends of the substrate to be fixed to the electrical connector, thereby effectively preventing the substrate from shaking relative to the electrical connector during the movement of the semiconductor structure. This avoids the problem of the neck of the first lead breaking due to the shaking of the substrate relative to the electrical connector, and improves the yield of the semiconductor structure. Attached Figure Description

[0025] Figure 1 This is a top view of a portion of the semiconductor structure provided in an exemplary embodiment of this application;

[0026] Figure 2 This is a partial cross-sectional view of a semiconductor structure provided in an exemplary embodiment of this application;

[0027] Figure 3 This is a flowchart of a method for preparing a semiconductor structure provided in an exemplary embodiment of this application. Specific Implementation

[0028] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0029] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0030] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0031] This application provides a semiconductor structure. For example... Figure 1 and Figure 2 As shown, the semiconductor structure includes a substrate 10, an electrical connector 20, a first semiconductor element 30, a second semiconductor element 40, a first lead 60, a second lead 50, and a molding compound 70.

[0032] The substrate 10 includes a substrate body 11, a conductive portion 121, and an auxiliary connection portion 122. The conductive portion 121 and the auxiliary connection portion 122 are located on the same side of the substrate body 11 and are arranged at intervals. The conductive portion 121 includes a first region 1211 and a second region 1212. The electrical connector 20 is an integral structure, including multiple pins 21 and a carrier portion 22. The multiple pins 21 include a first pin 211, which is attached to the first region 1211 of the conductive portion 121. The first semiconductor element 30 is attached to the second region 1212 of the auxiliary connection portion 122. The second semiconductor element 40 is attached to the carrier portion 22. One end of the first lead 60 is connected to the first semiconductor element 30, and the other end is connected to the second semiconductor element 40. Specifically, the second semiconductor element 40 includes multiple pads, and the first lead 60 is connected to one pad of the second semiconductor element 40. One end of the second lead 50 is connected to the carrier portion 22, and the other end is connected to the auxiliary connection portion 122; the cross-sectional area of ​​the second lead 50 is larger than the cross-sectional area of ​​the first lead 60. The molding compound 70 encapsulates the substrate 10, the electrical connector 20, the first semiconductor element 30, the second semiconductor element 40, the first lead 60, and the second lead 50, and each of the pins 21 is at least partially exposed by the molding compound 70.

[0033] The semiconductor structure provided in this application embodiment has a first pin 211 connected to the first region 1211 of the conductive part 121, and a second lead 50 connected to the auxiliary connection part 122 and the carrier part 22 respectively. The first region 1211 and the second conductive part 122 are located on different sides of the second region 1212. That is, the substrate 10 is connected to the integrated electrical connector 20 at two positions on different sides of the second region 1212. Since the cross-sectional area of ​​the second lead 50 for auxiliary connection is larger than the cross-sectional area of ​​the first lead 60 for electrical connection, the second lead 50 is less prone to breakage. This allows the two ends of the substrate 10 to be fixed to the electrical connector 20, thereby effectively preventing the substrate 10 from shaking relative to the electrical connector 20 during the movement of the semiconductor structure. This avoids the problem of the neck of the first lead 60 breaking due to the shaking of the substrate 10 relative to the electrical connector 20, and improves the yield of the semiconductor structure. Compared with the scheme where the cross-sectional area of ​​the first lead 60 and the cross-sectional area of ​​the second lead 50 are the same, it can save costs while meeting electrical performance requirements.

[0034] In one embodiment, the conductive part 121 and the auxiliary connecting part 122 may be made of the same material, and both may be formed simultaneously in the same process step. Figure 1In the embodiment shown, the substrate 10 includes a conductive layer 12 located on one side of the substrate body 11, and the conductive portion 121 and the auxiliary connection portion 122 are each part of the conductive layer 12.

[0035] In this embodiment of the application, the electrical connector 20 being an integral structure means that all components of the electrical connector 20 are connected together. For example, all pins 21 and the carrier portion 22 of the electrical connector 20 are indirectly connected through other structures.

[0036] In one embodiment, such as Figure 1 and Figure 2 As shown, the electrical connector 20 is a lead frame, and the support portion 22 is the base island of the lead frame. The support portion 22 and the pin 21 are spaced apart. The lead frame 20 also includes a frame, and the support portion 22 and the pin 21 are respectively connected to the frame. The support portion 22 and the pin 21 are both located on the side of the conductive layer 12 away from the substrate body 11. In other embodiments, the electrical connector 20 may be a circuit board, which includes a main body, the pins are located on the main body, and the support portion 22 is the part of the main body where the pins and other components are not provided.

[0037] In one embodiment, such as Figure 1 As shown, the electrical connector 20 further includes a second pin 212 and a third pin 213. The second pin 212 is located on the side of the second region 1212 of the conductive portion 121 away from the first region 1211 and is electrically connected to the pad of the second semiconductor element 40. Each of the third pins 213 is at least partially located on the side of the first region 1211 away from the second region 1212.

[0038] In one embodiment, the first semiconductor element 30 may be a metal-oxide-semiconductor field-effect transistor. For example... Figure 1 As shown, the first semiconductor element 30 includes a control electrode 31, a first electrode 32, and a second electrode. The control electrode 31 of the first semiconductor element 30 is connected to a first lead. The first electrode can be the source electrode, and the second electrode can be the drain electrode. The control electrode and the first electrode are disposed on the surface of the first semiconductor element 30 away from the substrate 10, and the second electrode is disposed on the surface of the first semiconductor element 30 facing the substrate 10.

[0039] In one embodiment, such as Figure 2As shown, the first pin 211 is attached to the first region 1211 of the conductive portion 121 via a conductive adhesive 81, and the first semiconductor element 30 is attached to the second region 1212 of the conductive portion 121 via a conductive adhesive 82. The first pin 211 is electrically connected to the conductive portion 121 via the conductive adhesive 81, and the second electrode of the first semiconductor element 30 is electrically connected to the conductive portion 121 via the conductive adhesive 82. In some embodiments, the conductive adhesive 81 and the conductive adhesive 82 can be obtained by curing solder paste. Solder paste has good thermal conductivity, which helps to transfer the heat generated by the first semiconductor element 30 to the substrate 10.

[0040] In one embodiment, the second semiconductor element 40 may be a chip.

[0041] In one embodiment, such as Figure 2 As shown, the second semiconductor element 40 can be attached to one side of the carrier portion 22 using an adhesive 85. In some embodiments, the adhesive 85 may be a conductive adhesive, for example, the adhesive 85 may be obtained by curing silver paste. Alternatively, the adhesive 85 may be a non-conductive adhesive.

[0042] In one embodiment, such as Figure 1 As shown, the support portion 22 is located on the side of the auxiliary connection portion 122 away from the second region 1212. This arrangement allows for a smaller distance between the auxiliary connection portion 122 and the support portion 22, thereby reducing the length of the second lead 50 and helping to avoid the risk of the second lead 50 coming into contact with other leads.

[0043] In one embodiment, such as Figure 2 As shown, in the thickness direction X of the substrate body 11, the maximum distance between the second lead 50 and the substrate body 11 is less than the maximum distance between the first lead 60 and the substrate body 11. Since the first lead 60 is used to connect the control electrode 31 of the first semiconductor element 30 and the pad of the second semiconductor element 40, it is necessary to avoid short circuit problems caused by the first lead 60 contacting other conductive structures. Therefore, the height of the first lead 60 needs to be made larger to better avoid contact with other conductive structures, such as other pads of the second semiconductor element 40. The second lead 50 is used to connect the auxiliary connection part 122 and the carrier part 22. Making it shorter helps to prevent the substrate 10 from shaking relative to the electrical connector 20.

[0044] In one embodiment, such as Figure 1 and Figure 2As shown, the conductive portion 121 further includes a third region 1213, and the semiconductor structure further includes a fast recovery diode 83 and a third lead 84. The fast recovery diode 83 is mounted on the third region 1213 of the conductive portion 121. The anode 831 of the fast recovery diode 83 is located on the surface of the fast recovery diode 83 away from the substrate 10, and the cathode is located on the surface of the fast recovery diode 83 facing the substrate 10 and electrically connected to the conductive portion 121. The anode of each fast recovery diode 83 is electrically connected to the first electrode of a first semiconductor element 30 through the third lead 84, and the cathode of each fast recovery diode 83 is electrically connected to the second electrode of a first semiconductor element 30 through an auxiliary connection portion 122. With this configuration, when the first semiconductor element 30 is turned off, the fast recovery diode 83 can provide a low-impedance path for current flow, protecting the first semiconductor element 30 from voltage spikes.

[0045] In one embodiment, such as Figure 1 As shown, in the same conductive part 121, the third region 1213 is located between the first region 1211 and the second region 1212.

[0046] In one embodiment, such as Figure 1 As shown, the conductive layer 12 includes multiple conductive portions 121: conductive portions 123, 124, 125, and 126. Each conductive portion includes a first region 1211, and each first region 1211 of the conductive portion is fitted with a first pin 211. Specifically, the first pin 2111 is fitted on the conductive portion 123, the first pin 2112 is fitted on the conductive portion 124, the first pin 2113 is fitted on the conductive portion 125, and the first pin 2114 is fitted on the conductive portion 126. In all conductive portions 121, the first region 1211 is located on the same side of the second region 1212. In one embodiment, as... Figure 1 As shown, each conductive part 121 includes a second region 1212 and a third region 1213. A first semiconductor element 30 is mounted on the second region 1212 of each conductive part 121, and a fast recovery diode 83 is mounted on the third region 1213 of each conductive part 121. A first semiconductor element 30 and a fast recovery diode 83 mounted on the same conductive part 121 are electrically connected. Figure 1In the illustrated embodiment, three first semiconductor elements 30 and three fast recovery diodes 83 are mounted on the conductive portion 123. Each first semiconductor element 30 corresponds to one fast recovery diode 83, and each first semiconductor element 30 is electrically connected to its corresponding fast recovery diode 83 via a third lead 84. Specifically, the conductive portion 123 is mounted with first semiconductor elements 301, 302, and 303 and three fast recovery diodes 83. The first electrode of the first semiconductor element 301, the first electrode of the first semiconductor element 302, and the first electrode of the first semiconductor element 303 are electrically connected to the anode of different fast recovery diodes 83 via different third leads 84. A first semiconductor element 304 and a fast recovery diode 83 are mounted on the conductive part 124. The first electrode of the first semiconductor element 304 is electrically connected to the anode of the fast recovery diode 83 through a third lead 84. A first semiconductor element 305 and a fast recovery diode 83 are mounted on the conductive part 125. The first electrode of the first semiconductor element 305 is electrically connected to the anode of the fast recovery diode 83 through a third lead 84. A first semiconductor element 306 and a fast recovery diode 83 are mounted on the conductive part 126. The first electrode of the first semiconductor element 306 is electrically connected to the anode of the fast recovery diode 83 through a third lead 84.

[0047] Furthermore, such as Figure 1 As shown, one end of the third lead 84 connected to the first electrode of the first semiconductor element 301 is connected to the first pin 2112; one end of the third lead 84 connected to the first electrode of the first semiconductor element 302 is connected to the first pin 2113; one end of the third lead 84 connected to the first electrode of the first semiconductor element 303 is connected to the first pin 2114; one end of the third lead 84 connected to the first electrode of the first semiconductor element 304 is connected to the third pin 2131; one end of the third lead 84 connected to the first electrode of the first semiconductor element 305 is connected to the third pin 2132; and one end of the third lead 84 connected to the first electrode of the first semiconductor element 306 is connected to the third pin 2133. Thus, the first semiconductor element 30 and the fast recovery diode 83 together form an inverter circuit. In other embodiments, the connection relationship between the first semiconductor element 30 and the fast recovery diode 83 may differ. Figure 1 .

[0048] In one embodiment, the first electrode of the first semiconductor element 30 is connected to the anode of the fast recovery diode 83 via two third leads 84. This avoids the problem of the third leads 84 being burned out due to excessive current flowing through them.

[0049] In one embodiment, such as Figure 1As shown, one end of the third lead 84 is connected to the first pin 211 or the third pin 213, and the other end is connected to the first electrode of the first semiconductor element 10. The middle portion is connected to the anode of the fast recovery diode 83. In other embodiments, the third lead 84 may include two sub-leads, one of which is connected to the first pin 211 or the third pin 213 at one end and to the anode of the fast recovery diode 83 at the other end; the other sub-lead is connected to the anode of the fast recovery diode 83 at one end and to the first electrode of the first semiconductor element 10 at the other end.

[0050] In one embodiment, such as Figure 1 As shown, the electrical connector 20 includes two carrier portions 22, and the semiconductor structure includes two second semiconductor elements 40, with one second semiconductor element 40 mounted on each carrier portion 22. The control electrodes of the first semiconductor elements 301, 302, and 303 are connected to the same second semiconductor element 40 via first leads 60, and the control electrodes of the first semiconductor elements 304, 305, and 306 are connected to another second semiconductor element 40 via first leads 60.

[0051] In one embodiment, such as Figure 2 As shown, the substrate 10 further includes a metal heat dissipation layer 13 located on the side of the substrate body 11 away from the conductive layer 12; the surface of the metal heat dissipation layer 13 away from the substrate body 11 exposes the molding compound layer 70. This improves the heat dissipation performance of the semiconductor structure. In some embodiments, the substrate 10 is a DBC (Directed Bonding Copper) substrate, including a ceramic substrate and two copper film layers, the two copper film layers being located on opposite sides of the ceramic substrate, one of which is the conductive layer 12, and the other is the metal heat dissipation layer 13.

[0052] In one embodiment, the substrate 10 includes a central region and an edge region. The first region 1211 of the conductive portion 121 and the auxiliary connection portion 122 are both located in the edge region, while the second region 1212 and the third region 1213 of the conductive portion 121 may be located in the central region.

[0053] In one embodiment, such as Figure 1 and Figure 2As shown, the first region 1211 of the conductive portion 121 and the auxiliary connection portion 122 are located on opposite sides of the second region 1212 of the conductive portion 121. The first region 1211 of the conductive portion 121 is connected to the first pin 211, and the auxiliary connection portion 122 is connected to the carrier portion 22 through the second lead 50. That is, the opposite sides of the substrate 10 are respectively connected to the integrated electrical connector 20, which can effectively prevent the substrate 10 from shaking relative to the electrical connector 20, thereby reducing the risk of the first lead 60 breaking.

[0054] In one embodiment, such as Figure 1 and Figure 2 As shown, the conductive layer 12 includes at least two auxiliary connection portions 122, and the semiconductor structure includes at least two second leads 50. Each auxiliary connection portion 122 is connected to the carrier portion 22 via the second lead 50. This arrangement further prevents the substrate 10 from shaking relative to the electrical connector 20, thereby reducing the risk of the first lead 60 breaking.

[0055] In one embodiment, such as Figure 1 As shown, the conductive layer 12 includes two auxiliary connection portions 122, which are respectively connected to different carrier portions 22. In other embodiments, the substrate 10 may have three or more auxiliary connection portions 122 if space permits.

[0056] In one embodiment, such as Figure 1 As shown, the orthographic projection of the first lead 60 on the plane of the substrate body 11 facing the conductive layer 12 does not overlap with the orthographic projection of the second lead 50 on the same plane. This arrangement avoids the problem of short circuits occurring when the first lead 60 and the second lead 50 come into contact during the formation of the molding compound 70 due to the impact of the molding compound on them.

[0057] Furthermore, the distance between the orthographic projection of the first lead 60 on the plane of the substrate body 11 facing the conductive layer 12 and the orthographic projection of the second lead 50 on the same plane is greater than or equal to 100 μm. This arrangement further avoids the problem of short circuits occurring when the first lead 60 and the second lead 50 come into contact during the formation of the molding compound 70 due to the impact of the molding compound on the first lead 60 and the second lead 50.

[0058] In one embodiment, the material of the third lead 84 is the same as that of the second lead 50. This configuration allows the third lead 84 and the second lead 50 to be soldered to their respective structures in the same process step, simplifying the semiconductor structure manufacturing process.

[0059] In one embodiment, the cross-sectional area of ​​the third lead 84 is greater than the cross-sectional area of ​​the first lead 60. This cross-sectional area can be either the maximum or the average cross-sectional area. This configuration provides better current conduction capability for the third lead 84. In some embodiments, the cross-sectional area of ​​the third lead 84 is substantially the same as the cross-sectional area of ​​the second lead 50.

[0060] In one embodiment, the second lead 50 is made of aluminum. This provides the second lead 50 with good toughness, making it less prone to breakage even with a large cross-sectional area, effectively preventing the substrate 10 from shaking relative to the electrical connector 20.

[0061] In one embodiment, the first lead 60 is made of copper.

[0062] In one embodiment, the cross-sectional area of ​​the first lead 60 is approximately 14.13 μm. 2 The cross-sectional area of ​​the second lead is in the range of 56.52 μm. 2 ~157μm 2 With this configuration, the second lead 50 is less likely to break, preventing the substrate 10 from shaking relative to the electrical connector 20.

[0063] In one embodiment, the cross-sections of the first lead 60 and the second lead 50 are both circular, the diameter of the first lead 60 is approximately 9 μm, and the diameter of the second lead 50 ranges from 12 μm to 20 μm.

[0064] This application also provides a method for manufacturing a semiconductor structure. For example... Figure 3 As shown, the manufacturing method includes the following steps 110 to 150.

[0065] In step 110, a substrate and an electrical connector are provided; the substrate includes a substrate body and a conductive layer located on one side of the substrate body, the conductive layer includes conductive portions and auxiliary connecting portions arranged at intervals; the conductive portions include a first region and a second region; the electrical connector is an integral structure, including multiple pins and a carrier portion; the multiple pins include a first pin.

[0066] In step 120, the pins of the electrical connector are attached to the first region of the conductive portion, and the first semiconductor element is attached to the second region of the conductive portion.

[0067] In one embodiment, step 120 may include the following process:

[0068] First, solder paste is applied to a first region and a second region of the conductive portion, respectively. Then, the first pin of the electrical connector is mounted on the first region, and the first semiconductor element is mounted on the second region. Subsequently, the solder paste is cured. In some embodiments, a screen printing process can be used to apply the solder paste to the first and second regions of the conductive portion. In some embodiments, the first pin of the electrical connector can be mounted on the first region of the conductive portion first, and then the first semiconductor element can be mounted on the second region of the conductive portion. In other embodiments, the first semiconductor element can be mounted on the second region of the conductive portion first, and then the first pin of the electrical connector can be mounted on the first region of the conductive portion. In some embodiments, a reflow soldering process can be used to cure the solder paste.

[0069] In one embodiment, the manufacturing method further includes the step of mounting a fast recovery diode on a third region of the conductive portion. Specifically, the third region is provided with solder paste, and the fast recovery diode is mounted on the third region using the solder paste. This step can be performed simultaneously with step 120.

[0070] In step 130, the second semiconductor element is mounted on the carrier.

[0071] In one embodiment, step 130 may include the following process:

[0072] First, silver paste is applied to the carrier portion; then, a second semiconductor device is mounted on the area of ​​the carrier portion where the silver paste is applied; subsequently, the silver paste is cured. In some embodiments, a dispensing process can be used to apply the silver paste to the carrier portion. In some embodiments, a reflow soldering process can be used to cure the silver paste.

[0073] In step 140, the carrier part is connected to the auxiliary connecting part using a second lead.

[0074] In one embodiment, a cold welding process can be used to weld the second lead to the carrier portion and the auxiliary connection portion respectively.

[0075] In one embodiment, the manufacturing method further includes: using a third lead to electrically connect the anode of the fast recovery diode to the first electrode and the first pin of the first semiconductor element, respectively.

[0076] In one embodiment, a cold soldering process can be used to solder the third lead to the anode of the fast recovery diode, the first electrode of the first semiconductor element, and the first or second pin, respectively. This step can be completed in the same process step as step 140.

[0077] In step 150, the control electrode is connected to the second semiconductor element using a first lead; the cross-sectional area of ​​the second lead is larger than that of the first lead.

[0078] In one embodiment, a thermal soldering process can be used to solder the first lead to the control electrode of the first semiconductor element and the second semiconductor element, respectively.

[0079] In step 160, a molding compound is formed that encapsulates the substrate, the electrical connector, the first semiconductor element, the second semiconductor element, the first lead, and the second lead, with the pins at least partially exposed by the molding compound.

[0080] In one embodiment, before forming the molding compound, some pretreatment steps, such as chemical cleaning or plasma cleaning, can be performed to remove impurities from the surfaces of the second semiconductor element, the substrate, the first semiconductor element, and the electrical connector, so that the molding compound can be more closely connected to the second semiconductor element, the substrate, the first semiconductor element, and the electrical connector, and delamination or cracking will not occur.

[0081] In one embodiment, the material of the encapsulation layer can be a polymer resin, resin composite material, polymer composite material, etc. For example, the encapsulation layer can be a resin with fillers, wherein the fillers can be inorganic particles. The encapsulation layer can be formed by injection molding, compression molding, or transfer molding.

[0082] The embodiments of the semiconductor structure provided in this application and the embodiments of the semiconductor structure manufacturing method belong to the same inventive concept. The relevant details and beneficial effects can be referred to each other, and will not be repeated here.

[0083] It should be noted that the dimensions of layers and regions may be exaggerated in the accompanying drawings for clarity. Furthermore, it is understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element, or there may be intermediate layers. Additionally, it is understood that when an element or layer is referred to as being "below" another element or layer, it can be directly below the other element, or there may be more than one intermediate layer or element. Furthermore, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it can be the only layer between the two layers or two elements, or there may be more than one intermediate layer or element. Similar reference numerals throughout indicate similar elements.

[0084] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0085] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A semiconductor structure, characterized in that, The semiconductor structure includes: A substrate includes a substrate body, a conductive portion, and an auxiliary connection portion; the conductive portion and the auxiliary connection portion are located on the same side of the substrate body and are arranged at intervals; the conductive portion includes a first region and a second region. The electrical connector is an integral structure, including multiple pins and a carrier portion; the multiple pins include a first pin, which is attached to a first region of the conductive portion; A first semiconductor element is mounted on a second region of the conductive portion; the first region and the auxiliary connection portion are located on different sides of the second region; A second semiconductor element is mounted on the carrier portion; The first lead has one end connected to the first semiconductor element and the other end connected to the second semiconductor element; The second lead has one end connected to the bearing part and the other end connected to the auxiliary connection part; the cross-sectional area of ​​the second lead is larger than that of the first lead. A molding compound encapsulates the substrate, the electrical connector, the first semiconductor element, the second semiconductor element, the first lead, and the second lead, with each of the pins at least partially exposed by the molding compound.

2. The semiconductor structure according to claim 1, characterized in that, The first region and the auxiliary connecting portion are located on opposite sides of the second region.

3. The semiconductor structure according to claim 1, characterized in that, The conductive layer includes at least two auxiliary connection portions, and the semiconductor structure includes at least two second leads. Each of the auxiliary connection portions is connected to the carrier portion through the second leads.

4. The semiconductor structure according to claim 1, characterized in that, The orthographic projection of the first lead on the plane of the substrate body facing the conductive layer does not overlap with the orthographic projection of the second lead on the same plane.

5. The semiconductor structure according to claim 4, characterized in that, The distance between the orthographic projection of the first lead on the plane and the orthographic projection of the second lead on the plane is greater than or equal to 100 μm.

6. The semiconductor structure according to claim 1, characterized in that, The cross-sectional area of ​​the second lead is in the range of 56.52 μm. 2 ~157μm 2 .

7. The semiconductor structure according to claim 1, characterized in that, The first semiconductor element includes a control electrode, a first electrode, and a second electrode, wherein the control electrode and the first electrode are located on the surface of the first semiconductor element away from the substrate; a first lead is connected to the control electrode; the semiconductor structure further includes a third lead that electrically connects the first electrode and one of the pins; the material of the third lead is the same as the material of the second lead; and / or, The supporting part is located on the side of the auxiliary connecting part away from the second region.

8. The semiconductor structure according to claim 1, characterized in that, In the thickness direction of the substrate body, the maximum distance between the second lead and the substrate body is less than the maximum distance between the first lead and the substrate body.

9. The semiconductor structure according to claim 1, characterized in that, The second lead is made of aluminum, and the first lead is made of copper.

10. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes a fast recovery diode and a third lead; the fast recovery diode is mounted on the conductive portion, the anode of the fast recovery diode is located on the surface of the fast recovery diode away from the substrate, and the cathode is located on the surface of the fast recovery diode facing the substrate and electrically connected to the auxiliary connection portion; the first semiconductor element includes a control electrode, a first electrode, and a second electrode, the control electrode and the first electrode are located on the surface of the first semiconductor element away from the substrate, and the second electrode is located on the surface of the first semiconductor element facing the substrate and electrically connected to the auxiliary connection portion; the first lead is connected to the control electrode; the anode of each fast recovery diode is electrically connected to the first electrode of one of the first semiconductor elements through the third lead; and / or, The substrate further includes a metal heat dissipation layer located on the side of the substrate body away from the conductive layer; the surface of the metal heat dissipation layer away from the substrate body exposes the molding layer.

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