A power device package structure, a preparation method and a power module

Abstract

The application provides a power device packaging structure, a preparation method and a power module, and relates to the technical field of semiconductors. The packaging structure comprises an adhesive film layer, a functional layer and an encapsulation layer; the adhesive film layer has adhesion on at least one side and adheres to the functional layer; the functional layer is used for limiting and electrically connecting a power device; and the encapsulation layer covers the functional layer. The functional layer comprises a chip, a chip positioning frame and an interconnection via; the back surface of the chip and the chip positioning frame are adhered to the adhesive film layer; the interconnection via is filled with a conductive structure and extends to the adhesive surface of the adhesive film layer. The adhesive film layer is a flexible film and is attached to the functional layer without a gap; the back surface of the chip, the surface of the chip positioning frame, the surface of the conductive structure and the adhesive surface of the adhesive film layer are coplanar; the adhesive film layer is a removable temporary bearing layer, and after removal, the back surface of the chip is directly exposed to the bottom of the packaging structure. The packaging structure does not need a lead frame and a bottom plate, does not need to calculate a deformation amount and set different thickness pads, simplifies the process and reduces the cost.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a power device packaging structure, fabrication method, and power module. Background Technology

[0002] The typical process flow for power device packaging includes steps such as chip mounting, wire bonding, molding, lead plating, and lead trimming. The packaging structure of power devices is a key factor affecting their performance and reliability.

[0003] In related technologies, power devices typically employ a structure combining a lead frame and a base plate. The back of the chip is soldered to the base plate, and the front electrodes of the chip are electrically connected to the lead frame via wire bonding. To improve the bonding quality at the bonding points, some solutions include multiple support points on the base plate corresponding to the bonding points of the lead frame. By calculating the deformation of the base plate and the lead frame, the required gap compensation for each point is determined, and pads of different thicknesses are placed at corresponding positions on the lead frame or the base plate to ensure good adhesion and bonding conditions between the lead frame and the base plate after compression.

[0004] However, the above solution requires high precision in frame design, with frame bonding points needing to precisely correspond to multiple support points on the base plate. Simultaneously, it's necessary to simulate and calculate the base plate deformation and its location, and based on this, calculate the curvature difference between the frame and the base plate to obtain the corresponding gap values ​​for different bonding points. Because the pad thickness varies at different bonding points, the pad processing and assembly process is complex, increasing the difficulty and cost of packaging manufacturing. Summary of the Invention

[0005] This application provides a power device packaging structure, fabrication method, and power module, which at least solves the problems of high frame design accuracy requirements, complex base plate deformation calculation, and processing difficulties caused by inconsistent pad thickness at different bonding points in related technologies.

[0006] To address the above problems, the embodiments of this application adopt the following technical solutions: In a first aspect, embodiments of this application provide a power device packaging structure, including: an adhesive thin film layer, a functional layer, and an encapsulation layer; At least one side of the adhesive film layer is adhesive for adhering the functional layer; The functional layer is adhered to the adhesive side of the adhesive film layer to limit the power device and achieve electrical connection; The encapsulation layer covers the functional layer to form encapsulation protection; The functional layer includes a chip, a chip positioning frame, and interconnect vias. The back side of the chip is adhered to the adhesive film layer. The chip positioning frame is adhered to the adhesive film layer. The interconnect vias are filled with conductive structures. The interconnect vias extend to the surface of the adhesive film layer with the adhesive side. The adhesive film layer is a flexible film, and it is tightly bonded to the functional layer without any gaps. The back side of the chip, the surface of the chip positioning frame near the adhesive film layer, the surface of the conductive structure near the adhesive film layer, and the surface of the adhesive film layer near the chip positioning frame are all located on the same plane. The adhesive film layer is a removable temporary carrier layer, and after the adhesive film layer is removed, the back side of the chip is directly exposed to the bottom of the power device packaging structure.

[0007] Secondly, embodiments of this application provide a method for fabricating a power device packaging structure, comprising: An adhesive film layer is provided, wherein at least one side of the adhesive film layer is adhesive for adhering a functional layer; A functional layer is formed and adhered to the adhesive side of the adhesive film layer for limiting the power device and realizing electrical connection; An encapsulation layer is formed, which covers the functional layer to form encapsulation protection; The functional layer includes a chip, a chip positioning frame, and interconnect vias, and the formation of the functional layer includes: The chip positioning frame is adhered to the adhesive side of the adhesive film layer, and the chip positioning frame has spaced chip receiving grooves; the back side of the chip is adhered to the adhesive film layer; interconnecting vias are formed, and the interconnecting vias extend to the surface of the adhesive side of the adhesive film layer; a conductive structure is formed, and the conductive structure fills the interior of the interconnecting vias. The adhesive film layer is a flexible film, and it is tightly bonded to the functional layer without any gaps. The back side of the chip, the surface of the chip positioning frame near the adhesive film layer, the surface of the conductive structure near the adhesive film layer, and the surface of the adhesive film layer near the chip positioning frame are all located on the same plane. The adhesive film layer is a removable temporary support layer. After the adhesive film layer is removed, the back side of the chip is directly exposed to the bottom of the power device packaging structure.

[0008] Thirdly, embodiments of this application provide a power module, including a power device packaging structure as described in any one of the first aspects; the power device packaging structure is prepared by the method described in any one of the second aspects.

[0009] Beneficial effects In this application, an adhesive thin film layer, a functional layer, and an encapsulation layer are provided. At least one side of the adhesive thin film layer is adhesive, the functional layer is adhered to the adhesive side of the adhesive thin film layer, and the encapsulation layer covers the functional layer. The functional layer includes a chip, a chip positioning frame, interconnect vias, and conductive structures filling the interconnect vias. The back side of the chip and the chip positioning frame are adhered to the adhesive thin film layer, and the interconnect vias extend to the surface of the adhesive side of the adhesive thin film layer. The adhesive thin film layer is a flexible thin film and is tightly bonded to the functional layer without gaps. The back side of the chip, the surface of the chip positioning frame near the adhesive thin film layer, the surface of the conductive structure near the adhesive thin film layer, and the surface of the adhesive thin film layer near the chip positioning frame are located on the same plane. The adhesive thin film layer is a removable temporary carrier layer. After the adhesive thin film layer is removed, the back side of the chip is directly exposed to the bottom of the power device packaging structure. Since the functional layers are uniformly supported and kept flat by the same flexible film, and the back side of the chip is directly exposed to the bottom of the power device packaging structure after the adhesive film layer is removed, the back side of the chip, the surface of the chip positioning frame near the adhesive film layer, and the surface of the conductive structure near the adhesive film layer are all on the same plane. Therefore, there is no need to set up a traditional lead frame and a rigid base plate, nor is it necessary to calculate the deformation of the base plate and the curvature difference between the frame and the base plate. There is no need to set up pads of different thicknesses for different bonding points, thereby simplifying the packaging structure and manufacturing process, and reducing processing complexity and manufacturing costs. Attached Figure Description

[0010] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 A cross-sectional schematic diagram of a power device packaging structure provided for an embodiment of this application; Figure 2 A schematic diagram of a chip top view structure provided for an embodiment of this application; Figure 3 Another schematic diagram of a chip top view structure provided for an embodiment of this application; Figure 4 A schematic flowchart illustrating the steps of a method for fabricating a power device packaging structure, provided for an embodiment of this application; Figure 5 This is a schematic diagram of the structure of a power module provided in an embodiment of this application. Detailed Implementation

[0011] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0012] In the embodiments of this application, the terms "first", "second", "third", "fourth" are used to distinguish the same or similar items with essentially the same function and effect, only for the purpose of clearly describing the technical solution of the embodiments of this application, and should not be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated.

[0013] In the embodiments of this application, the terms "upper" and "lower" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0014] In the description of this specification, the terms "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this application. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0015] In the embodiments of this application, "multiple" means two or more, and "at least one" means one or more, unless otherwise explicitly specified.

[0016] The features such as "parallel," "perpendicular," and "identical" used in the embodiments of this application include features in the strict sense of "parallel," "perpendicular," and "identical," as well as cases where "approximately parallel," "approximately perpendicular," and "approximately identical" include certain tolerances. Taking into account the measurement and the tolerances associated with the measurement of a specific quantity (e.g., limitations of the measurement system), they represent the acceptable deviation range for a specific value as determined by a person skilled in the art. For example, "approximately" can mean within one or more standard deviations, or within 10% or 5% of the value.

[0017] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open and encompassing, that is, "including, but not limited to".

[0018] In the field of power device packaging technology, packaging structures (such as TO-247, TO-3P, TO-220, etc.) typically need to secure the chip, provide electrical interconnection, and offer external protection. The chip mounting, wire bonding, molding, lead plating, and lead trimming processes during packaging directly affect the electrical connection reliability, heat dissipation capacity, and subsequent assembly methods of power devices.

[0019] In related technologies, power devices typically employ a package structure combining a leadframe and a base plate. The back of the chip is fixed to the base plate by soldering, while the front electrodes of the chip are electrically connected to the leadframe via wire bonding. To improve bonding quality, some solutions include multiple support points on the base plate corresponding to the bonding points of the leadframe. By calculating the deformation and curvature difference between the base plate and the leadframe, the gap compensation amount for each bonding point is determined. Pads of different thicknesses are then placed at corresponding positions on the leadframe or base plate to ensure tight, gapless contact at each bonding point after the leadframe and base plate are pressed together. This prevents localized suspension or uneven gaps caused by base plate deformation, thus providing stable support for wire bonding and ensuring bonding quality.

[0020] However, the above scheme requires high precision in frame design, and the frame bonding points need to precisely correspond to multiple support points on the base plate. Simultaneously, it is necessary to simulate and calculate the base plate deformation and deformation location, and based on this, calculate the curvature difference between the frame and the base plate to obtain the corresponding gap values ​​for different bonding points. Because the pad thickness varies at different bonding points, the pad processing and assembly process is complex, increasing the difficulty and cost of packaging manufacturing, and limiting the development of power device packaging structures towards simpler designs and higher heat dissipation efficiency.

[0021] Based on this, embodiments of this application provide a power device packaging structure, such as... Figure 1 As shown, the power device packaging structure includes: an adhesive thin film layer 1, a functional layer 2, and an encapsulation layer 3; at least one side of the adhesive thin film layer 1 is adhesive for adhering the functional layer 2; the functional layer 2 is adhered to the adhesive side of the adhesive thin film layer 1 for limiting the power device and achieving electrical connection; the encapsulation layer 3 covers the functional layer 2 for forming encapsulation protection; wherein, the adhesive thin film layer 1 is a flexible thin film, and the adhesive thin film layer 1 and the functional layer 2 are tightly bonded without gaps.

[0022] In this embodiment, the adhesive thin film layer 1, the functional layer 2, and the encapsulation layer 3 are arranged sequentially from bottom to top along the thickness direction of the device. The adhesive thin film layer 1 is located at the bottom of the entire encapsulation structure, serving as the substrate supporting the functional layer 2. The functional layer 2 adheres to the adhesive side of the adhesive thin film layer 1 and is located between the adhesive thin film layer 1 and the encapsulation layer 3. The encapsulation layer 3 covers the exposed surface of the functional layer 2, forming the external protective structure of the device.

[0023] For example, the adhesive film layer 1 can be a flexible adhesive film such as a wafer blue film or a UV film, or it can be other adhesive polymer films.

[0024] The choice of blue film or UV film as the adhesive thin film layer 1 is based on the fact that both are flexible films, which can achieve a gapless and tight fit with the bottom surface of the functional layer 2, replacing the traditional rigid base plate and avoiding gap differences caused by base plate deformation. On the other hand, both are widely used in the semiconductor packaging field, have low cost, and mature technology, which can simplify the packaging process and reduce manufacturing costs while ensuring the load-bearing and positioning functions.

[0025] The adhesive surface of the adhesive film layer 1 is used to adhere the functional layer 2, ensuring the functional layer 2 remains stable during the encapsulation process. Because the adhesive film layer 1 is a flexible film, when the functional layer 2 is adhered to it, the adhesive film layer 1 can completely adhere to the bottom surface of the functional layer 2, avoiding the gaps or localized voids common in rigid base plates, thus achieving a gapless and tight fit. The adhesive film layer 1 serves as a temporary support and positioning element during the encapsulation process, replacing the rigid base plate and lead frame in traditional encapsulation structures and simplifying the bottom support structure.

[0026] Functional layer 2 may include chip 21 and conductive structures that enable electrical connection between chip 21 and external circuitry. Functional layer 2 is held in place by the adhesive properties of adhesive film layer 1, confining the power device within functional layer 2 to prevent displacement during subsequent molding. Simultaneously, the conductive structures formed within functional layer 2 lead the electrodes of the power chip 21 to the bottom or side of the package structure, achieving electrical connection. In this embodiment, functional layer 2 is a general description; its specific internal structure can be configured according to the type of power device and packaging requirements, and may include, for example, a chip positioning frame 22, a filling structure 23, and interconnect vias 24, but is not limited to these.

[0027] For example, the chip 21 in the functional layer 2 can be a power device such as an insulated gate bipolar transistor (IGBT) or a fast recovery diode (FRD), or it can be other types of power semiconductor chips.

[0028] Encapsulation layer 3 can cover the side surface of functional layer 2 away from adhesive film layer 1, and encapsulation layer 3 can also cover the side peripheral surface of functional layer 2, isolating the power chip 21, conductive structure, etc. inside functional layer 2 from the external environment, playing the role of moisture protection, dust protection, and mechanical damage protection, while ensuring that the package has sufficient mechanical strength and insulation performance.

[0029] For example, the encapsulation layer 3 can be formed by means of thermosetting molding materials such as epoxy resin, through molding or potting.

[0030] After the encapsulation layer 3 is formed, it can be removed according to subsequent mounting requirements. When the adhesive film layer 1 is removed, the bottom surface of the functional layer 2 is exposed, and the back side of the chip 21 is directly exposed to the bottom of the package, forming a heat dissipation surface and a mounting surface. As a result, the device can be surface-mounted on the PFC circuit board without the need for through-hole mounting, reducing assembly height, saving circuit board space, and facilitating the miniaturization and high-density integration of power modules.

[0031] In the embodiments of this application, by providing at least one side of the adhesive film layer 1 to be adhesive to adhere the functional layer 2, the functional layer 2 is adhered to the adhesive side of the adhesive film layer 1 to limit the power device and achieve electrical connection. An encapsulation layer 3 is provided to cover the functional layer 2 to form encapsulation protection. Simultaneously, the adhesive film layer 1 is a flexible film and is tightly bonded to the functional layer 2 without gaps. This embodiment has the following beneficial effects: Firstly, since the adhesive film layer 1 is a flexible film and is tightly bonded to the functional layer 2 without any gaps, the entire functional layer 2 is directly supported and uniformly carried by the flexible film. Therefore, the traditional lead frame and rigid base plate are no longer needed in the packaging structure. Consequently, the bottom surface of the functional layer 2 will not experience height differences at different locations due to base plate deformation. This eliminates the correspondence between frame bonding points and base plate support points, and eliminates the need to calculate base plate deformation and the curvature difference between the frame and the base plate. Furthermore, it eliminates the need for pads of different thicknesses at different bonding points. Therefore, the accuracy requirements for frame design are reduced, simulation calculations and pad processing are eliminated, the packaging structure and manufacturing process are simplified, production efficiency is improved, and manufacturing costs are reduced.

[0032] Secondly, since the adhesive film layer 1 is a flexible film, it can adapt to the slight unevenness of the bottom surface of the functional layer 2 during the packaging process, ensuring that the functional layer 2 and the adhesive film layer 1 always maintain a tight, gapless fit, avoiding stress concentration caused by local suspension or poor contact. This reduces the risk of damage or delamination of the chip 21 due to uneven stress during the packaging process, improving the reliability and yield of the packaging structure.

[0033] Thirdly, since the back of the power chip 21 is directly attached to the adhesive film layer 1, the adhesive film layer 1 can be removed according to subsequent mounting requirements. After removal, the back of the power chip 21 is directly exposed on the bottom of the package, forming a heat dissipation surface. This allows the heat generated during the operation of the chip 21 to be directly conducted to the outside, improving heat dissipation capacity. At the same time, the exposed bottom surface forms a mounting surface, allowing the device to be surface-mounted onto the PFC circuit board without the need for through-hole mounting. This reduces assembly height, saves circuit board space, and facilitates the miniaturization and high-density integration of the power module.

[0034] Optionally, in some power device package structures provided in this application, such as Figure 1 As shown, the functional layer 2 includes a chip 21, a chip positioning frame 22, and a filling structure 23; the chip positioning frame 22 is adhered to the adhesive film layer 1 and has chip receiving grooves G spaced apart; the chip 21 is disposed in the chip receiving grooves G, and the back side of the chip 21 is adhered to the adhesive film layer 1; the filling structure 23 covers the chip 21 and the chip positioning frame 22 and fills the chip receiving grooves G.

[0035] The chip positioning frame 22 is adhered to the adhesive side surface of the adhesive film layer 1. The chip positioning frame 22 has a plurality of spaced chip receiving slots G, which are through slots that penetrate the upper and lower surfaces of the chip positioning frame 22, so that the back side of the chip 21 can directly contact the adhesive film layer 1 after being placed in the slot.

[0036] For example, two chip receiving slots G can be provided on the chip positioning frame 22, one chip receiving slot G for accommodating the IGBT chip 21 and the other chip receiving slot G for accommodating the FRD chip 21, thereby integrating different types of power chips 21 in the same package structure to form a power module combining IGBT and FRD. Of course, more chip receiving slots G can also be provided according to the circuit design needs to accommodate multiple power chips 21 of the same or different types, so as to improve the integration and applicability of the package structure.

[0037] For example, the chip positioning frame 22 can be made of an insulating resin material, such as epoxy resin, polyimide, etc., or other polymer materials with insulating properties.

[0038] The opening shape and size of the chip receiving slot G can be set according to the packaging requirements of chip 21. In some examples, the opening size of the chip receiving slot G can match the outer dimensions of chip 21, so that after chip 21 is placed in the slot, there is essentially no gap or direct contact between the sidewall of chip 21 and the slot wall of chip receiving slot G in the direction parallel to the surface of adhesive thin film layer 1. This helps to improve the positioning accuracy of chip 21, reduce the amount of filling structure 23, make the structure of functional layer 2 more compact, and make the relative position between chip 21 and positioning frame more stable, which is beneficial to the subsequent alignment processing of interconnect vias 24.

[0039] In other examples, the opening size of the chip receiving slot G can be slightly larger than the external dimensions of the chip 21, so that after the chip 21 is placed in the slot, a certain gap is formed between the sidewall of the chip 21 and the slot wall of the chip receiving slot G. This gap is filled by the filler structure 23. This arrangement can reduce the alignment difficulty during chip 21 mounting, avoid the chip 21 being unable to be placed in the slot due to dimensional tolerances of the chip 21 or the positioning frame, or stress damage caused by hard contact during chip 21 mounting. At the same time, the filler structure 23 filling the gap can buffer stress and improve the mechanical stress resistance of the package structure.

[0040] The back side of chip 21 is directly attached and fixed by the adhesive film layer 1, which keeps chip 21 in a stable position during the packaging process. The front side of chip 21 faces away from the adhesive film layer 1 so that electrodes can be brought out later through the filling structure 23 and the conductive structure.

[0041] The filling structure 23 covers the chip 21 and the chip positioning frame 22, and fills the chip receiving groove G. When there is a gap between the sidewall of the chip 21 and the wall of the chip receiving groove G, the filling structure 23 fills the gap; when there is no gap or direct contact between the sidewall of the chip 21 and the wall of the chip receiving groove G, the filling structure 23 mainly covers the front surface of the chip 21 and the top surface of the chip positioning frame 22. The filling structure 23 can be made of insulating materials such as epoxy resin, and formed by coating, potting or molding. The filling structure 23 not only fixes the chip 21 and prevents the chip 21 from shifting in subsequent processes, but also protects the front electrode of the chip 21 from the influence of the external environment, and provides a supporting foundation for the subsequent formation of interconnect vias 24 and encapsulation layer 3.

[0042] The back surface of chip 21, the surface of chip positioning frame 22 near adhesive film layer 1, and the surface of adhesive film layer 1 near chip positioning frame 22 are all located on the same plane. Since chip 21 and chip positioning frame 22 are both directly adhered to the same adhesive film layer 1, and adhesive film layer 1 is a flexible film that fits tightly against functional layer 2 without gaps, the back surface of chip 21 and the bottom surface of chip positioning frame 22 can remain coplanar through adhesive film layer 1. Thus, when adhesive film layer 1 is removed, the back surface of chip 21 and the bottom surface of chip positioning frame 22 together form a flat mounting surface, facilitating the surface mounting of the device onto the circuit board.

[0043] In the embodiments of this application, by setting the functional layer 2 to include a chip 21, a chip positioning frame 22, and a filling structure 23, the chip positioning frame 22 is adhered to the adhesive film layer 1 and has spaced chip receiving grooves G. The chip 21 is disposed in the chip receiving grooves G and its back side is adhered to the adhesive film layer 1. The filling structure 23 covers the chip 21 and the chip positioning frame 22 and fills the chip receiving grooves G. The back side of the chip 21, the side surface of the chip positioning frame 22 near the adhesive film layer 1, and the side surface of the adhesive film layer 1 near the chip positioning frame 22 are all located on the same plane. This embodiment has the following beneficial effects: Firstly, the back surface of chip 21, the surface of chip positioning frame 22 near adhesive film layer 1, and the surface of adhesive film layer 1 near chip positioning frame 22 are all located on the same plane, so that chip 21 and chip positioning frame 22 are kept coplanar by flexible adhesive film layer 1. When adhesive film layer 1 is removed, the back surface of chip 21 and the bottom surface of chip positioning frame 22 together form a flat mounting surface, which facilitates the device to be mounted on the circuit board by surface mounting, reduces the assembly height, and saves circuit board space.

[0044] Secondly, since the chip 21 and the chip positioning frame 22 are directly supported by a flexible adhesive film, the packaging structure does not require a traditional lead frame and a rigid base plate. This avoids the gap difference problem caused by base plate deformation when the frame and base plate mate, eliminates the need to calculate base plate deformation and curvature differences, and eliminates the need for pads of different thicknesses, simplifying the packaging structure and reducing manufacturing costs. Simultaneously, the filling structure 23 fills the chip receiving slot G and covers the chip 21 and the chip positioning frame 22, integrating the chip 21, positioning frame, and filling structure 23 into a unified functional layer 2. This achieves reliable positioning of the chip 21, protects the front electrode of the chip 21, and improves packaging reliability.

[0045] Optionally, in some power device package structures provided in this application, such as Figure 1 As shown, the functional layer 2 also includes interconnect vias 24; the interconnect vias 24 extend from the front electrode of the chip 21 through the filling structure 23 and the chip positioning frame 22 to the surface of the adhesive thin film layer 1 with the adhesive side; the interconnect vias 24 are filled with conductive structures, one end of which is electrically connected to the front electrode of the chip 21, and the other end extends to the surface of the adhesive thin film layer 1 with the adhesive side.

[0046] Interconnect vias 24 are formed within the fill structure 23 and the chip positioning frame 22, with their starting ends located at the front electrode of the chip 21 and their ends extending to the surface of the adhesive thin film layer 1 on the adhesive side. The front electrode of the chip 21 can be the pad area on the front side of the chip 21.

[0047] For example, such as Figure 2As shown, the front side of the IGBT chip 21 can have a PAD area and a gate area, where the PAD area can be the emitter pad and the gate area can be the gate pad. Figure 3 As shown, the front side of the FRD chip 21 can have a PAD area, i.e., an anode pad. The starting ends of the interconnect vias 24 can correspond to the PAD area, gate area, and PAD area of ​​the IGBT chip 21, respectively, thereby leading each electrode to the bottom of the package structure to achieve electrical connection.

[0048] The interconnect vias 24 can be formed by laser grooving, mechanical drilling, or photolithography. For example, a laser can be used to create grooves along a predetermined path on the filling structure 23 and the chip positioning frame 22, forming vias extending from the front electrode of the chip 21 to the adhesive side surface of the adhesive thin film layer 1. The specific shape and path of the interconnect vias 24 can be set according to actual packaging requirements. For example, they can extend in a direction perpendicular to the surface of the adhesive thin film layer 1, or include bending sections to accommodate the positional offset between the electrodes of the chip 21 and the bottom pads. The number and position of the interconnect vias 24 can be set according to the distribution of the front electrodes of the chip 21 to achieve independent lead-out of different electrodes. The cross-sectional shape of the interconnect vias 24 can be rectangular, circular, or other shapes, which can be set according to the actual processing conditions and the filling requirements of the conductive structure.

[0049] The conductive structure fills the interior of the interconnect vias 24. The conductive structure can be made of conductive metal materials, such as copper or aluminum, and is formed through thin-film deposition, electroplating, electroless plating, or conductive paste filling. One end of the conductive structure is electrically connected to the front electrode of the chip 21, and the other end extends to the surface of the adhesive side of the adhesive thin film layer 1, forming a conductive end face located at the bottom of the package structure. After the adhesive thin film layer 1 is removed, this conductive end face is exposed on the bottom surface of the functional layer 2 and can serve as a mounting pad for soldering to corresponding pads on the circuit board.

[0050] The conductive structure forms a continuous conductive path within the interconnect via 24, replacing wire bonding in traditional packaging structures. Since the conductive structure is formed directly inside the fill structure 23 and the chip positioning frame 22, no bonding wires are needed. This avoids problems such as bond point detachment and poor soldering that may occur during wire bonding. At the same time, it reduces the length of the conductive loop and parasitic parameters, which helps to reduce stray inductance and capacitive coupling during the operation of power devices and improve electrical performance.

[0051] Both the interconnect vias 24 and the conductive structure are formed inside the functional layer 2, integrated with the chip positioning frame 22 and the fill structure 23. The bottom end face of the conductive structure and the surface of the chip positioning frame 22 near the adhesive film layer 1 can be on the same plane, so as to form a flat mounting surface after the adhesive film layer 1 is removed. In this way, the power device package structure can achieve electrical connection while still maintaining a flat bottom, which is convenient for surface mount installation.

[0052] In this embodiment, by setting interconnect vias 24 extending from the front electrode of chip 21 through filling structure 23 and chip positioning frame 22 to the surface of adhesive film layer 1 with adhesive side, and filling the interconnect vias 24 with conductive structures, one end of the conductive structure is electrically connected to the front electrode of chip 21, and the other end extends to the surface of adhesive film layer 1 with adhesive side. This embodiment has the following beneficial effects: Firstly, the conductive structure is formed within the interconnect via 24, directly connecting the front electrode of the chip 21 to the bottom of the package structure, replacing traditional wire bonding. This avoids stray inductance and capacitive coupling problems caused by bonding wires, which is beneficial for improving the switching characteristics and high-frequency performance of power devices and enhancing electrical reliability.

[0053] Secondly, the interconnect vias 24 and conductive structures are integrated within the fill structure 23 and the chip positioning frame 22, eliminating the need for additional lead frames and bonding equipment. This simplifies the packaging structure and manufacturing process, reducing production costs. Simultaneously, the end face formed at the bottom of the conductive structure can serve as a mounting pad, facilitating surface-mount device installation, reducing assembly height, and promoting miniaturization and high-density integration of power modules.

[0054] Optionally, in some power device package structures provided in this application, such as Figure 1 As shown, the interconnect via 24 includes a first vertical channel 241, a second vertical channel 242, and a lateral channel 243. Along the thickness direction of the adhesive thin film layer 1, the first vertical channel 241 extends from the front electrode of the chip 21 into the filling structure 23. Along the thickness direction of the adhesive thin film layer 1, the second vertical channel 242 extends from the surface of the adhesive thin film layer 1 having an adhesive side, through the chip positioning frame 22, and into the filling structure 23. The lateral channel 243 is located in the filling structure 23, extends in a direction parallel to the surface of the adhesive thin film layer 1, and one end of the lateral channel 243 is connected to the first vertical channel 241, and the other end of the lateral channel 243 is connected to the second vertical channel 242.

[0055] The first vertical channel 241 extends along the thickness direction of the adhesive thin film layer 1, with its starting end located at the front electrode of the chip 21, and extends upward from the front electrode of the chip 21 into the filling structure 23. The first vertical channel 241 is used to lead the front electrode of the chip 21 from the surface of the chip 21 into the interior of the filling structure 23, so that the electrode can be connected to the subsequently formed conductive structure. The bottom end of the first vertical channel 241 directly exposes the front electrode of the chip 21 so that the conductive structure can be reliably electrically connected to the electrode after its formation.

[0056] The second vertical channel 242 extends along the thickness direction of the adhesive film layer 1, with its starting end located on the surface of the adhesive side of the adhesive film layer 1, and extends upward through the chip positioning frame 22 into the filling structure 23. The second vertical channel 242 is used to connect the conductive end face of the bottom of the package structure with the conductive path inside the filling structure 23, so that current can be transmitted from the front electrode of the chip 21 through the filling structure 23 to the bottom of the package structure. The bottom end of the second vertical channel 242 opens at the surface of the adhesive side of the adhesive film layer 1. When the adhesive film layer 1 is removed, the conductive end face corresponding to the opening is exposed on the bottom surface of the functional layer 2, forming a bottom mounting pad.

[0057] The lateral channel 243 is located within the filling structure 23. The lateral channel 243 connects the first vertical channel 241 and the second vertical channel 242, forming a continuous conductive path between them within the filling structure 23. Since the first vertical channel 241 and the second vertical channel 242 are located at different horizontal positions, the lateral channel 243 can accommodate the positional offset between the front electrode and the bottom pad of the chip 21, making the overall path of the interconnect via 24 more flexible and eliminating the need for the front electrode and the bottom pad of the chip 21 to be on the same vertical line.

[0058] For example, when the front electrode of chip 21 is located in the middle region of chip 21, and the bottom pad needs to be set in the region where chip positioning frame 22 is located, the first vertical channel 241 can extend upward from the front electrode of chip 21 into the filling structure 23, the second vertical channel 242 can penetrate downward from the bottom surface of chip positioning frame 22 and extend into the filling structure 23, and the horizontal channel 243 connects the first vertical channel 241 and the second vertical channel 242 in the horizontal direction in the filling structure 23, thereby forming a complete interconnection path.

[0059] The formation methods of the first vertical channel 241, the second vertical channel 242, and the horizontal channel 243, as well as the material and formation method of the conductive structure filling each channel, are the same as those in the aforementioned embodiments, and will not be repeated here.

[0060] For example, the first vertical channel 241, the second vertical channel 242, and the horizontal channel 243 can be integrally formed in the same step, or they can be formed in stages. For example, the vertical channel and the horizontal channel 243 can be formed on the filling structure 23 and the chip positioning frame 22 respectively, and then connected to each other. The cross-sectional shape of the first vertical channel 241, the second vertical channel 242, and the horizontal channel 243 can be rectangular, circular, or other shapes, which can be set according to the actual processing conditions and the filling requirements of the conductive structure.

[0061] In the embodiments of this application, by providing interconnect vias 24 including a first vertical channel 241, a second vertical channel 242, and a horizontal channel 243, the first vertical channel 241 extends from the front electrode of the chip 21 into the filling structure 23, the surface of the self-adhesive thin film layer 1 of the second vertical channel 242 penetrates the chip positioning frame 22 and extends into the filling structure 23, and the horizontal channel 243 is located within the filling structure 23 and connects the first vertical channel 241 and the second vertical channel 242. This embodiment has the following beneficial effects: Firstly, by connecting the first vertical channel 241 and the second vertical channel 242 through the horizontal channel 243, the connection path between the front electrode of the chip 21 and the bottom pad is no longer limited to the same vertical position. It can be flexibly adjusted according to the actual packaging layout, which reduces the alignment difficulty of chip 21 mounting and through-hole processing, and improves the adaptability and design flexibility of the packaging structure.

[0062] Secondly, each channel of the interconnect via 24 is provided with a conductive structure, forming a continuous conductive path extending from the front electrode of the chip 21 through the filling structure 23 and the chip positioning frame 22 to the bottom of the package structure. This replaces the traditional wire bonding, avoids stray inductance and capacitive coupling problems caused by the bonding wire, improves the electrical performance of the power device, and simplifies the package structure and reduces manufacturing costs.

[0063] Embodiments of this application provide a method for fabricating a power device packaging structure, such as... Figure 4 As shown, the method includes steps 101-103: Step 101: Provide an adhesive film, at least one side of which is adhesive for adhering the functional layer.

[0064] The adhesive film can be a flexible adhesive film such as the blue film or UV film for wafers described in the foregoing embodiments. Its material, flexibility characteristics, and adhesive properties on at least one side are the same as those in the foregoing structural embodiments, and will not be repeated here.

[0065] In practice, the adhesive film can be laid flat on a metal frame using a casting machine, with the adhesive side facing upwards, to facilitate the subsequent bonding of the chip positioning frame and the chip. The adhesive film is flexible, enabling a seamless and tight fit with the bottom surface of the subsequently formed functional layer, providing flexible support for the functional layer and replacing traditional rigid base plates and lead frames, thus avoiding gap differences caused by base plate deformation.

[0066] Step 102: Form a functional layer. The functional layer is adhered to the adhesive side of the adhesive film layer to limit the power device and realize electrical connection.

[0067] The composition and functions of the functional layer have been described in the previous structural embodiments and will not be repeated here.

[0068] The specific process of forming the functional layer may include adhering a chip positioning frame to an adhesive thin film layer, mounting the chip in a chip receiving slot so that the back side of the chip adheres to the adhesive thin film layer, forming a filling structure covering the chip and the chip positioning frame, and forming interconnect vias and conductive structures, etc. These specific sub-steps will be further described in detail in the embodiments corresponding to the dependent method claims in the following descriptions; here, only a general description is provided.

[0069] After the functional layer is adhered to the adhesive film layer, since the adhesive film is a flexible film, a gapless and tight fit is formed between the bottom surface of the functional layer and the adhesive film layer. The power device is reliably confined inside the functional layer and is electrically connected through the conductive structure, providing a structural basis for subsequent encapsulation.

[0070] Step 103: Form an encapsulation layer that covers the functional layer to form a protective encapsulation. The adhesive film layer is a flexible film, and it is tightly bonded to the functional layer without any gaps.

[0071] The encapsulation layer can be made of thermosetting molding materials such as epoxy resin, formed through molding, potting, or other methods. The encapsulation layer covers the side of the functional layer away from the adhesive film layer and the peripheral surface of the functional layer, isolating the power chip, conductive structures, etc., inside the functional layer from the external environment. This provides protection against moisture, dust, and mechanical damage, while ensuring the package has sufficient mechanical strength and insulation properties. The materials, formation methods, and functions of the encapsulation layer are the same as in the aforementioned structural embodiments and will not be repeated here.

[0072] It should be noted that steps 101 to 103 above can be executed sequentially, or the order of some steps can be adjusted according to actual process needs, as long as the power device packaging structure of this application embodiment can be formed in the end.

[0073] By providing an adhesive film and making at least one side of the adhesive film layer adhesive to adhere to the functional layer, forming the functional layer and adhering it to the adhesive side of the adhesive film layer to limit the power device and achieve electrical connection, and forming an encapsulation layer to cover the functional layer to form encapsulation protection, while making the adhesive film layer a flexible film and tightly bonded to the functional layer without gaps, the preparation method of this embodiment has the following beneficial effects: Firstly, because the adhesive film layer is a flexible film, the functional layer can be directly adhered to it during the fabrication process. The adhesive film layer serves to support and position the functional layer, eliminating the need for traditional lead frames and rigid base plates. This eliminates the assembly process between the frame and the base plate. Since there is no need to calculate the base plate deformation or the curvature difference between the frame and the base plate, and there is no need to process pads of different thicknesses for different bonding points, the packaging manufacturing process is simplified, the requirements for frame design precision are reduced, production efficiency is improved, and manufacturing costs are lowered.

[0074] Secondly, because the adhesive film layer is a flexible film, the bottom surface of the functional layer can naturally adhere to the adhesive film layer during the formation of the functional layer. This eliminates the need for strict control of the substrate flatness and the need for gap compensation using spacers. The flexible film can adapt to minor unevenness on the bottom surface of the functional layer, avoiding chip damage or delamination caused by localized suspension or stress concentration, thus improving process tolerance and packaging yield.

[0075] Thirdly, after the encapsulation layer is formed, the adhesive film layer can be removed according to subsequent mounting requirements. After removal, the back of the power chip is directly exposed on the bottom of the package, forming a heat dissipation surface and a mounting surface. This fabrication method allows the device to be mounted on the PFC circuit board in a surface mount manner, eliminating the need for through-hole mounting, reducing assembly height, saving circuit board space, and facilitating the miniaturization and high-density integration of power modules.

[0076] Optionally, in some of the power device packaging structure fabrication methods provided in this application, step 102 may include sub-steps 1021 to 1023.

[0077] Step 1021: Adhere the chip positioning frame to the adhesive side of the adhesive film layer. The chip positioning frame has chip receiving slots spaced apart.

[0078] The chip positioning frame can be made of insulating resin materials, such as epoxy resin, polyimide and other polymer materials with insulating properties.

[0079] The chip positioning frame can be formed by cutting and shaping to create spaced chip receiving slots. Specifically, an insulating resin board can be prepared first, and then cut on the insulating resin board according to the device design layout requirements to form multiple through slots that penetrate the upper and lower surfaces of the chip positioning frame. These through slots are the chip receiving slots.

[0080] For example, the cutting process can be laser cutting, mechanical cutting, etc. When using laser cutting, the chip receiving slot can be precisely machined on the insulating resin board by controlling the laser path and energy, offering advantages such as high processing accuracy and good edge quality. When using mechanical cutting, the chip receiving slot can be formed through milling or punching, which is a simpler and lower-cost process. Of course, the chip receiving slot can also be formed using other methods such as molding, as long as the size and shape of the slot meet the chip mounting requirements.

[0081] After cutting and shaping, the number and layout of chip receiving slots can be set according to actual packaging requirements. For example, two chip receiving slots can be set on the chip positioning frame, one for accommodating IGBT chips and the other for accommodating FRD chips; or more chip receiving slots can be set to accommodate multiple power chips of the same or different types, thereby improving the integration and applicability of the packaging structure.

[0082] After the chip positioning frame is fabricated, it is adhered to the adhesive surface of the adhesive film layer, ensuring a tight bond between the bottom surface of the chip positioning frame and the adhesive film layer. The adhesive surface of the adhesive film layer reliably secures the chip positioning frame. After the chip positioning frame is adhered, any excess adhesive film outside the chip positioning frame can be cut and removed, forming a resin frame with adhesive film support at the bottom, facilitating subsequent chip mounting.

[0083] Step 1022: Mount the chip in the chip receiving slot and adhere the back of the chip to the adhesive film layer.

[0084] The chip can be a power chip such as an IGBT or FRD. Its type and the definitions of the front and back sides are the same as those in the aforementioned structural embodiments, and will not be repeated here.

[0085] In practice, the adhesive film with the chip positioning frame is placed in the track of the mounting equipment. The placement area is set according to the position of the chip receiving slot. The mounting equipment then mounts the chips one by one into the corresponding chip receiving slots, ensuring that the back of the chip directly contacts and adheres to the adhesive surface of the adhesive film layer. During the mounting process, the alignment system of the mounting equipment ensures the positional accuracy of the chip within the receiving slot.

[0086] Parameters such as placement pressure and placement temperature can be set according to the adhesion characteristics of the adhesive film layer and the chip size to ensure reliable adhesion between the back of the chip and the adhesive film layer, while avoiding damage to the chip during the placement process. When multiple chips need to be placed, the placement order and placement parameters can be set separately according to the chip type. For example, IGBT chips can be placed first, followed by FRD chips, or they can be placed sequentially according to a preset circuit layout.

[0087] Step 1023: Form a filling structure that covers the chip and the chip positioning frame and fills the chip receiving slot.

[0088] For example, the filling structure can be made of insulating materials such as epoxy resin, such as bisphenol A type epoxy resin, alicyclic epoxy resin, etc. Inorganic fillers can also be added as needed to adjust the coefficient of thermal expansion and mechanical strength.

[0089] In practice, after chip mounting, a filling structure can be formed on the chip and chip positioning frame using methods such as coating, potting, or molding. The filling material is injected from the side of the chip positioning frame away from the adhesive film layer, covering the surface of the chip and chip positioning frame away from the adhesive film layer, and filling the gap between the chip sidewall and the chip receiving groove wall. During the filling process, vacuum potting technology can be used to reduce air bubbles inside the filling structure and improve the filling density.

[0090] After the filler material is filled, the filled structure needs to be cured. The curing method depends on the type of filler material used. For example, when the filler structure uses thermosetting epoxy resin, heat curing can be used. The device is placed in an oven or curing furnace and held at a preset temperature for a certain time to allow the epoxy resin to undergo a cross-linking reaction and fully cure. When the filler structure uses UV-curable resin, it can be cured by ultraviolet irradiation. Curing treatment can set the shape of the filler structure, improve its mechanical strength and insulation performance, and release the internal stress generated during the filling process, reducing the risk of deformation in subsequent processes.

[0091] After the filler structure has cured, the surface of the filler structure away from the adhesive film layer can be ground or polished to obtain a smooth surface, providing a good process basis for the subsequent formation of interconnects and encapsulation layers.

[0092] In the embodiments of this application, by adhering the chip positioning frame to the adhesive side of the adhesive film layer, mounting the chip in the chip receiving groove and adhering the back side of the chip to the adhesive film layer, and forming a filling structure to cover the chip and the chip positioning frame and fill the chip receiving groove, at least the following advantages are achieved: Firstly, during the formation of the functional layer, both the chip positioning frame and the chip are directly adhered to the adhesive thin film layer, eliminating the need for prior chip backside soldering and substrate assembly, as well as the installation of lead frames and alignment of bonding points. This eliminates the need for chip soldering and frame assembly processes found in traditional methods, simplifying the operation and reducing equipment requirements and process complexity. Furthermore, since there is no need for a mating mechanism between the frame and the substrate, the fabrication process eliminates the need to calculate substrate deformation and curvature differences, and to process pads of varying thicknesses, thus shortening the process cycle and improving production efficiency.

[0093] Secondly, during chip mounting, the chip is positioned using pre-drilled chip receiving slots on the chip positioning frame. The mounting equipment simply places the chip into the corresponding slot to complete the mounting, eliminating the need for high-precision bonding point alignment. The opening size of the chip receiving slot can be slightly larger than the chip's external dimensions, providing a certain tolerance for chip mounting, reducing the difficulty of alignment, minimizing the risk of chip damage due to alignment deviations, and improving the mounting yield.

[0094] Thirdly, the formation process of the filling structure is simple, and can be completed through coating, potting, or molding. The filling material can naturally fill the gap between the chip sidewalls and the chip wall in the chip receiving groove, and cover the chip surface away from the adhesive thin film layer. After the filling structure is cured, the chip, chip positioning frame, and filling structure are integrated into a whole, and the chip position is fixed. There is no need to set up additional clamping structures or pads to compensate for the gaps, which provides a flat process foundation for the subsequent formation of interconnects and encapsulation layers.

[0095] Optionally, in some of the methods for fabricating power device packaging structures provided in this application, steps 104 and 105 may be included after step 102.

[0096] Step 104: Form interconnect vias. The interconnect vias extend from the front electrode of the chip through the filling structure and the chip positioning frame to the surface of the adhesive thin film layer on the adhesive side.

[0097] Interconnect vias can be formed by laser grooving, mechanical drilling, or photolithography.

[0098] For example, when using laser grooving, a grooving is performed along a predetermined path on the filling structure and the chip positioning frame using a laser to form a through hole extending from the front electrode of the chip to the adhesive side surface of the adhesive thin film layer.

[0099] In practice, after the filler structure has solidified, laser grooving can be performed starting from the front electrode of the chip and along the thickness direction of the adhesive film layer. One end of the grooving depth reaches the metal layer surface of the front electrode, exposing it; the other end extends along a preset path, passing through the filler structure and the chip positioning frame until it reaches the adhesive side of the adhesive film layer. During the grooving process, the grooving depth can be controlled using laser positioning, for example, by detecting reflection signals or energy changes during laser processing to determine whether the grooving has reached the front electrode surface, thus avoiding damage to the front electrode.

[0100] For example, the interconnect via may include a first vertical channel, a second vertical channel, and a lateral channel. The first vertical channel extends from the front electrode of the chip into the filling structure along the thickness direction of the adhesive thin film layer; the second vertical channel extends from the surface of the adhesive thin film layer having an adhesive side along the thickness direction of the adhesive thin film layer, through the chip positioning frame, and into the filling structure; the lateral channel is located within the filling structure, extends in a direction parallel to the surface of the adhesive thin film layer, and one end of the lateral channel communicates with the first vertical channel, while the other end communicates with the second vertical channel.

[0101] The formation of the first vertical channel, the second vertical channel, and the transverse channel can be done in stages or as a single integral process. For example, the first vertical channel can be formed within the filling structure first by laser grooving, exposing the front electrode of the chip at its bottom. Then, the second vertical channel can be formed within the chip positioning frame and the filling structure by laser grooving, with its bottom opening onto the adhesive side of the adhesive film layer. Finally, the transverse channel can be formed within the filling structure by laser grooving, connecting the first and second vertical channels. Alternatively, depending on the actual processing conditions, all three channels can be formed simultaneously in a single laser scan.

[0102] The specific shape and path of interconnect vias can be set according to actual packaging requirements. For example, when the front electrode and the bottom pad of the chip are not in the same vertical position, a horizontal offset connection between them can be achieved through a lateral channel, making the overall path of the interconnect vias more flexible. The number and position of interconnect vias can be set according to the distribution of the front electrode of the chip to achieve independent lead-out of different electrodes. The cross-sectional shape of interconnect vias can be rectangular, circular, or other shapes.

[0103] Step 105: Form a conductive structure, which fills the interior of the interconnect via.

[0104] The conductive structure can be made of conductive metal materials, such as copper or aluminum. It can be formed by thin-film deposition, electroplating, electroless plating, or conductive paste filling. For example, a copper metal layer can be deposited within interconnect vias using thin-film deposition technology to form a conductive path between the front electrode of the chip and the bottom of the package structure.

[0105] In practice, after the interconnect is formed, a conductive structure can be formed within the interconnect through thin film deposition, electroplating, or electroless plating. This conductive structure covers the inner wall of the interconnect and fills its interior. One end of the conductive structure is electrically connected to the front electrode of the chip, and the other end extends to the adhesive side of the adhesive film layer, forming a conductive end face at the bottom of the package structure. After the adhesive film layer is removed, this conductive end face is exposed on the bottom surface of the functional layer and can serve as a mounting pad for soldering to the corresponding pad on the circuit board.

[0106] The conductive structure forms a continuous conductive path within the interconnect vias, replacing wire bonding in traditional packaging structures. Since the conductive structure is formed directly within the fill structure and chip positioning frame, no bonding wires are needed. This avoids problems such as bond point detachment and poor soldering that can occur during wire bonding. It also reduces the length of the conductive loop and parasitic parameters, which helps reduce stray inductance and capacitive coupling during power device operation, thus improving electrical performance.

[0107] In the embodiments of this application, by forming interconnect vias, the interconnect vias extend from the front electrode of the chip through the filling structure and the chip positioning frame to the surface of the adhesive thin film layer on the adhesive side, and a conductive structure is formed within the interconnect vias, so that the conductive structure fills the interior of the interconnect vias. The preparation method of this embodiment has the following beneficial effects: Firstly, when forming interconnect vias, laser grooving and other methods are used to directly process the vias within the filling structure and chip positioning frame. The processing path and depth can be precisely controlled by laser positioning, eliminating the need for precise alignment between the lead frame and the substrate, as required by traditional wire bonding processes, and eliminating the need to calculate substrate deformation and curvature differences to determine bonding points. This simplifies the via processing steps, reduces the precision requirements for frame design, and shortens the process cycle.

[0108] Secondly, when forming the conductive structure, conductive metal is directly filled into the interconnect vias through thin film deposition, electroplating, or chemical plating. This allows the conductive structure to form an integrated conductive path with the front electrode of the chip and the bottom of the package structure in one go. There is no need to perform bonding operations point by point between the chip electrode and the lead frame. This eliminates the need for lead bonding equipment and bonding wire materials, simplifies the process, and reduces equipment investment and material costs.

[0109] Thirdly, since the interconnect vias and conductive structures are formed within the filling structure and chip positioning frame, the processing order of each channel and the filling order of the conductive structures can be flexibly adjusted according to actual process conditions. For example, the first vertical channel and the second vertical channel can be formed first, followed by the formation of horizontal channels for connection, and finally the conductive structures can be filled uniformly. In this way, the fabrication process has high process flexibility, making it easy to adapt to different chip layouts and electrode positions, thereby improving the applicability of the process and the yield.

[0110] Embodiments of this application provide a power module, such as Figure 5 As shown, it includes the power device packaging structure as described in any of the preceding embodiments; the power device packaging structure is prepared by the preparation method of the power device packaging structure described in any of the preceding embodiments.

[0111] For example, the power module can be a power factor correction (PFC) power module, a motor drive power module, a power conversion power module, an inverter power module, an uninterruptible power supply (UPS) power module, a photovoltaic inverter power module, a vehicle power supply power module, a switching power supply power module, a frequency converter power module, or a household appliance power module, etc. The following description uses the application of a power module to a PFC circuit board as an example.

[0112] In this embodiment, the power device package structure can be mounted on the circuit board via surface mount technology (SMT). Specifically, the adhesive film layer of the power device package structure can be removed according to subsequent mounting requirements, exposing the bottom surface of the functional layer and directly exposing the back side of the power chip to the bottom of the package. At this time, the conductive structure extends to the end of the adhesive film layer with the adhesive side surface to form a mounting pad on the bottom surface of the functional layer. This mounting pad is electrically connected to the corresponding pad on the circuit board through solder or other connecting materials, thereby fixing the power device package structure onto the circuit board to form a power module.

[0113] The specific structure, function, and fabrication method of the power device packaging structure in the power module have been described in detail in the previous embodiments and will not be repeated here. The beneficial effects of the power module are the same as those of the aforementioned power device packaging structure and fabrication method, and will not be repeated here either.

[0114] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A power device packaging structure, characterized in that, include: Adhesive film layer, functional layer and encapsulation layer; At least one side of the adhesive film layer is adhesive for adhering the functional layer; The functional layer is adhered to the adhesive side of the adhesive film layer to limit the power device and achieve electrical connection; The encapsulation layer covers the functional layer to form encapsulation protection; The functional layer includes a chip, a chip positioning frame, and interconnect vias. The back side of the chip is adhered to the adhesive film layer. The chip positioning frame is adhered to the adhesive film layer. The interconnect vias are filled with conductive structures. The interconnect vias extend to the surface of the adhesive film layer with the adhesive side. The adhesive film layer is a flexible film, and it is tightly bonded to the functional layer without any gaps. The back side of the chip, the surface of the chip positioning frame near the adhesive film layer, the surface of the conductive structure near the adhesive film layer, and the surface of the adhesive film layer near the chip positioning frame are all located on the same plane. The adhesive film layer is a removable temporary carrier layer, and after the adhesive film layer is removed, the back side of the chip is directly exposed to the bottom of the power device packaging structure.

2. The power device packaging structure according to claim 1, characterized in that, The functional layer also includes a filling structure; The chip positioning frame has spaced chip receiving slots. The chip is disposed within the chip receiving slot; The filling structure covers the chip and the chip positioning frame, and fills the chip receiving slot.

3. The power device packaging structure according to claim 2, characterized in that, The interconnecting via extends from the front electrode of the chip, through the filling structure and the chip positioning frame, to the surface of the adhesive film layer with the adhesive side. The interconnect is filled with a conductive structure, one end of which is electrically connected to the front electrode of the chip, and the other end extends to the surface of the adhesive film layer on the adhesive side.

4. The power device packaging structure according to claim 3, characterized in that, The interconnecting via includes a first vertical channel, a second vertical channel, and a horizontal channel; Along the thickness direction of the adhesive thin film layer, the first vertical channel extends from the front electrode of the chip into the filling structure; Along the thickness direction of the adhesive film layer, the second vertical channel extends from the surface of the adhesive film layer having an adhesive side, through the chip positioning frame, and into the filling structure; The transverse channel is located within the filling structure and extends in a direction parallel to the surface of the adhesive film layer. One end of the transverse channel is connected to the first vertical channel, and the other end of the transverse channel is connected to the second vertical channel.

5. The power device packaging structure according to claim 1, characterized in that, The adhesive thin film layer is a blue film or a UV film for wafers.

6. A method for fabricating a power device packaging structure, characterized in that, include: An adhesive film layer is provided, wherein at least one side of the adhesive film layer is adhesive for adhering a functional layer; A functional layer is formed, which is adhered to the adhesive side of the adhesive film layer for limiting the power device and realizing electrical connection; An encapsulation layer is formed, which covers the functional layer to form encapsulation protection; The functional layer includes a chip, a chip positioning frame, and interconnect vias, and the formation of the functional layer includes: The chip positioning frame is adhered to the adhesive side of the adhesive film layer, and the chip positioning frame has spaced chip receiving grooves; the back side of the chip is adhered to the adhesive film layer; interconnecting vias are formed, and the interconnecting vias extend to the surface of the adhesive side of the adhesive film layer; a conductive structure is formed, and the conductive structure fills the interior of the interconnecting vias. The adhesive film layer is a flexible film, and it is tightly bonded to the functional layer without any gaps. The back side of the chip, the surface of the chip positioning frame near the adhesive film layer, the surface of the conductive structure near the adhesive film layer, and the surface of the adhesive film layer near the chip positioning frame are all located on the same plane. The adhesive film layer is a removable temporary support layer. After the adhesive film layer is removed, the back side of the chip is directly exposed to the bottom of the power device packaging structure.

7. The preparation method according to claim 6, characterized in that, The functional layer includes a filling structure, and the formation of the functional layer includes: The filling structure is formed, which covers the chip and the chip positioning frame and fills the chip receiving slot.

8. The preparation method according to claim 7, characterized in that, After forming the filling structure, the method further includes: Interconnect vias are formed, which extend from the front electrode of the chip, through the filling structure and the chip positioning frame, to the surface of the adhesive film layer having an adhesive side.

9. A power module, characterized in that, Includes the power device packaging structure as described in any one of claims 1 to 5; the power device packaging structure is prepared by the method for preparing the power device packaging structure as described in any one of claims 6 to 8.

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