A board-level RDL packaging structure and a preparation method thereof

Abstract

The application provides a board-level RDL packaging structure and a preparation method thereof. The board-level RDL packaging structure comprises a chip body and a substrate; a surface of the chip body facing the substrate comprises a central functional area and a peripheral non-functional area, the central functional area is provided with electrode pads, the peripheral non-functional area is provided with an insulating layer, a plurality of through holes are formed in the insulating layer, and a redistribution structure is arranged in the through holes; a connecting pad is arranged on a surface of the substrate close to the chip body; the redistribution structure comprises a seed layer, a conductive layer and a protective layer arranged in sequence from bottom to top, the seed layer is electrically connected with the electrode pads, and a micro bump is arranged on a surface of the protective layer away from the conductive layer; a blind hole corresponding to the micro bump is arranged on the connecting pad, the blind hole is filled with a conductive material, and the micro bump is electrically connected with the connecting pad through the conductive material. By arranging the three-dimensional redistribution structure, the wiring density is greatly increased, more signal lines are accommodated in a limited space, the signal transmission path is effectively shortened, and the signal transmission speed is significantly improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging, and in particular to a board-level RDL packaging structure and its fabrication method. Background Technology

[0002] Throughout the development of the semiconductor industry, increasing chip integration has been a key factor driving the miniaturization and multifunctionality of electronic devices. Moore's Law, as a fundamental law of the semiconductor industry, has powerfully guided the continuous improvement of chip integration. With continuous technological advancements and increasingly refined chip manufacturing processes, more functional units can be integrated into a limited chip area. This not only improves chip performance but also provides strong support for the innovation and development of electronic products. For example, the powerful computing capabilities, rich functionality, and compact size of devices such as smartphones and tablets are largely due to the continuous improvement in chip integration.

[0003] However, the significant increase in chip integration has also brought unprecedented challenges to chip packaging technology. On the one hand, from an electrical performance perspective, the number of chip I / O ports has increased dramatically. This leads to more complex connections between the chip and external circuits, and increases the difficulty of signal transmission. Achieving efficient and reliable electrical connections within a limited space, while avoiding signal interference and transmission delays, has become one of the key challenges that packaging technology must address. On the other hand, in terms of heat dissipation, highly integrated chips generate a large amount of heat during operation. As chip area continues to shrink while power density continues to rise, the accumulation of heat will cause the chip temperature to rise continuously, leading to a series of problems such as decreased chip performance, increased power consumption, and even potential thermal failure, severely affecting the chip's lifespan and reliability.

[0004] Traditional wiring methods are no longer sufficient to meet the ever-increasing demands of signal transmission. Conventional two-dimensional planar wiring, within a limited space, reaches near-limited wiring density, leading to increased signal transmission delays. As chip operating frequencies continue to rise, the problem of deteriorating signal integrity becomes increasingly prominent; phenomena such as signal reflection and crosstalk significantly impact signal quality and transmission efficiency. Simultaneously, electromagnetic interference is becoming more severe. A large number of signal lines concentrated in a confined space are prone to electromagnetic coupling, causing interference between different signals, affecting normal chip operation, and potentially even causing system instability. These problems severely restrict further improvements in chip performance and the reliable operation of electronic devices. Therefore, there is an urgent need to develop more advanced chip packaging technologies to address these challenges. Summary of the Invention

[0005] In view of the defects and shortcomings of existing chip packaging technologies, this application provides a board-level RDL packaging structure and its fabrication method. This board-level RDL packaging structure overcomes the limitations of traditional two-dimensional planar wiring by creating multiple vias in the insulating layer of the non-functional area around the chip body and setting a three-dimensional rewiring structure within the vias. This significantly increases wiring density, accommodates more signal lines in a limited space, effectively shortens the signal transmission path, significantly improves signal transmission speed, and reduces transmission delay. Simultaneously, the optimized wiring design effectively suppresses electromagnetic interference and reduces crosstalk between signals, thereby improving the integrity and reliability of signal transmission.

[0006] One embodiment of this application provides a board-level RDL packaging structure, including a chip body and a substrate; the surface of the chip body facing the substrate includes a central functional area and a peripheral non-functional area, the central functional area is provided with electrode pads, the peripheral non-functional area is provided with an insulating layer, the insulating layer has a plurality of through holes, and a redistribution structure is provided in the through holes; the surface of the substrate near the chip body is provided with connection pads.

[0007] The redistribution structure includes a seed layer, a conductive layer, and a protective layer arranged sequentially from bottom to top. The seed layer is electrically connected to the electrode pads, and the protective layer has microbumps on its surface away from the conductive layer.

[0008] The connection pad has blind holes corresponding to the microbumps, and the blind holes are filled with conductive material. The microbumps are electrically connected to the connection pads through the conductive material.

[0009] In one embodiment, the seed layer is made of titanium-copper alloy, the conductive layer is made of electroplated copper, and the protective layer is made of titanium nitride.

[0010] In one embodiment, the microbumps are made of a tin-silver-copper alloy, and the surface of the microbumps has a chemically plated nickel-gold layer.

[0011] In one embodiment, the thickness of the electroless nickel-gold plating layer is between 5 μm and 10 μm.

[0012] In one implementation, the micro-bumps are conical in shape.

[0013] In one implementation, the distance between the edge of the central functional area near the peripheral non-functional area and the edge of the peripheral non-functional area near the central functional area is between 5 μm and 10 μm.

[0014] In one embodiment, the material of the insulating layer is selected from one or more of polyimide, benzocyclobutene and its derivatives.

[0015] As one implementation, the substrate region surrounding the blind via is locally metallized.

[0016] According to another embodiment of this application, a method for fabricating a board-level RDL packaging structure is provided, comprising the following steps:

[0017] The chip body is cleaned and dried, and the electrode pads of the chip body are surface activated. The area of ​​the electrode pads on the chip body is the central functional area, and the area surrounding the central functional area is the peripheral non-functional area.

[0018] An insulating layer is deposited in the surrounding non-functional area, and multiple through holes are formed in the insulating layer;

[0019] A rewiring structure is formed within the through-hole, and the rewiring structure includes, from bottom to top, a seed layer, a conductive layer, and a protective layer.

[0020] Micro-bumps are formed above the redistribution structure;

[0021] Blind holes are formed on the connection pads of the substrate, and the blind holes are filled with conductive material;

[0022] The microbumps on the chip body are aligned with the blind vias on the substrate and then bonded.

[0023] In one implementation, a seed layer, a conductive layer, and a protective layer are sequentially disposed from bottom to top within the through-hole to form a rewiring structure, specifically including the following steps:

[0024] A titanium-copper alloy seed layer is sputtered into the via at a sputtering power of 300W to 500W for 10 to 15 minutes. Photoresist is then applied, and a wiring pattern defining the redistribution structure is photolithographically formed. The exposure time is 30 to 40 seconds, and the exposure energy is 120 mJ / cm². 2 ~180mJ / cm 2 After development, a conductive copper plating layer is formed. The plating solution contains 0.1%–0.5% silver salt, the temperature of the plating solution is 25℃–35℃, and the current density is 1A / dm³. 2 ~3A / dm 2 After electroplating, the photoresist is removed, and a titanium nitride protective layer is deposited by CVD at 700℃~800℃ for 20 minutes~30 minutes. Then, an aluminum oxide thin film is deposited by ALD process at 200℃~300℃ for 5~10 cycles. Titanium nitride is generated by reacting with a gas source at high temperature and deposited on the surface of the conductive layer.

[0025] As described above, the board-level RDL packaging structure and its fabrication method of this application have the following beneficial effects:

[0026] The board-level RDL packaging structure of this application, by setting an insulating layer in the non-functional area around the chip body, and opening multiple vias in the insulating layer, and adopting a three-dimensional wiring design for the RDL layer in the vias, breaks through the limitations of traditional two-dimensional planar wiring, greatly increases the wiring density, accommodates more signal lines in a limited space, effectively shortens the signal transmission path, significantly improves the signal transmission speed, and reduces transmission delay; at the same time, the optimized wiring design effectively suppresses electromagnetic interference, reduces crosstalk between signals, and thus improves the integrity and reliability of signal transmission. Attached Figure Description

[0027] Figure 1 The diagram shown is a top view of the board-level RDL packaging structure provided in this application embodiment.

[0028] Figure 2 Displayed as Figure 1 A schematic diagram of the cross-sectional structure along the AA′ direction.

[0029] Figure 3 The diagram shown is a cross-sectional view of the substrate in the board-level RDL packaging structure provided in this application embodiment.

[0030] Figure 4 The flowchart shown is a method for fabricating a board-level RDL packaging structure provided in an embodiment of this application.

[0031] Component designation explanation

[0032] 10, Chip body; 20, Insulating layer; 30, Substrate; 110, Central functional area; 120, Peripheral non-functional area; 111, Electrode pad; 210, Via; 220, Rewiring structure; 221, Seed layer; 222, Conductive layer; 223, Protective layer; 230, Microbump; 310, Connector pad. Detailed Implementation

[0033] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0034] Please see Figures 1 to 4It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape, and size of components in the actual embodiment. In actual implementation, the type, quantity, and proportion of each component can be arbitrarily changed, and the component layout may also be more complex. The following embodiments will now be described in detail.

[0035] This embodiment provides a board-level RDL packaging structure, such as Figures 1 to 3 As shown, the board-level RDL packaging structure includes a chip body 10 and a substrate 30.

[0036] like Figure 1 and Figure 2 As shown, the surface of the chip body 10 facing the substrate 30 includes a central functional area 110 and a peripheral non-functional area 120. The central functional area 110 is provided with electrode pads 111, and the peripheral non-functional area 120 is provided with an insulating layer 20. Multiple through holes 210 are formed in the insulating layer 20, and redistribution structures 220 are provided in the through holes 210.

[0037] like Figure 2 As shown, the redistribution structure 220 includes a seed layer 221, a conductive layer 222, and a protective layer 223 arranged sequentially from bottom to top. The seed layer 221 is electrically connected to the electrode pads 111, and the protective layer 223 has microbumps 230 on its surface facing away from the conductive layer 222. The seed layer 221 is electrically connected to the electrode pads 111 of the central functional area 110, providing a good adhesion base for the subsequent conductive layer 222 and assisting in conductivity. The conductive layer 222, as the main conductive path, is responsible for rewiring and transmitting the electrical signals transmitted by the electrode pads 111 to meet the needs of chip connection to external systems. The protective layer 223 is disposed above the conductive layer 222, protecting the conductive layer 222 from external environmental corrosion, ensuring the long-term stability and reliability of the redistribution structure 220, and realizing three-dimensional wiring.

[0038] like Figure 3As shown, a connection pad 310 is provided on the surface of the substrate 30 near the chip body 10. Blind vias corresponding to the microbumps 230 are provided on the connection pads 310. The blind vias are filled with conductive material, and the microbumps 230 are electrically connected to the connection pads 310 through the conductive material. The microbumps 230 are positioned above the redistribution structure 220, serving as the electrical connection medium between the chip and the substrate 30. The blind vias on the connection pads 310 of the substrate 30 correspond to the microbumps 230, and the conductive material filling the blind vias forms a stable electrical connection with the microbumps 230. When an external signal or power is transmitted through the substrate 30 to the connection pads 310, the electrical signal is transmitted through the conductive material in the blind vias to the microbumps 230, and then from the microbumps 230 to the electrode pads 111 through the redistribution structure 220, thereby realizing the electrical connection between the chip and the external circuit and enabling the operation of various chip functions. Blind vias serve as electrical connection channels between the substrate 30 and the microbumps 230. After being filled with conductive material, they can significantly reduce resistance, improve current transmission efficiency, ensure a more stable and reliable electrical connection between the chip body 10 and the substrate 30, reduce signal transmission losses and delays, and thus improve the electrical performance of the entire packaging structure.

[0039] The central functional area 110 of the chip body 10 is the area that realizes the core functions of the chip. The electrode pads 111 set in the central functional area 110 serve as the starting point of electrical connection and are responsible for transmitting electrical signals generated inside the chip. The insulating layer 20 is set on the surface of the surrounding non-functional area 120 to provide electrical isolation and prevent short circuits between the chip body 10 and the outside world. The through-holes 210 opened in the insulating layer 20 provide the possibility for realizing three-dimensional wiring design.

[0040] The board-level RDL packaging structure of this embodiment breaks through the limitations of traditional two-dimensional planar wiring by setting an insulating layer in the non-functional area around the chip body, setting multiple vias in the insulating layer, and using a three-dimensional wiring design for the RDL layer in the vias. This significantly increases the wiring density, accommodates more signal lines in a limited space, effectively shortens the signal transmission path, significantly improves the signal transmission speed, and reduces transmission delay. At the same time, the optimized wiring design effectively suppresses electromagnetic interference, reduces crosstalk between signals, and improves the integrity and reliability of signal transmission.

[0041] In an optional embodiment, the seed layer 221 is made of titanium-copper alloy, the conductive layer 222 is made of electroplated copper, and the protective layer 223 is made of titanium nitride. The structural design and material selection of the redistribution structure 220 take thermal conductivity into account, enabling it to quickly transfer heat from the chip body 10 to the substrate 30.

[0042] In an optional embodiment, the microbump 230 is made of a tin-silver-copper alloy, and the surface of the microbump 230 has a chemically plated nickel-gold layer. The tin-silver-copper alloy material of the microbump 230 has good conductivity, which can efficiently conduct electrical signals; the chemically plated nickel-gold layer on its surface further enhances the oxidation resistance and welding performance of the microbump 230, ensuring a reliable electrical connection.

[0043] In an optional embodiment, the thickness of the electroless nickel-gold plating layer is between 5 μm and 10 μm. Optionally, the microbump 230 is conical in shape, that is, the area of ​​the surface of the microbump 230 near the protective layer 223 is larger than the area of ​​the surface of the microbump 230 away from the protective layer 223, and the diameter of the sidewall of the microbump 230 gradually decreases from the end near the protective layer 223 to the end away from the protective layer 223.

[0044] In an optional embodiment, the distance between the edge of the central functional area 110 near the peripheral non-functional area 120 and the edge of the peripheral non-functional area 120 near the central functional area 110 is between 5 μm and 10 μm. This reasonable spacing ensures the uniformity of the electric field distribution around the central functional area 110, effectively reducing the possibility of electric field distortion and partial discharge, helping to improve the electrical insulation performance of the chip, reducing the risk of leakage, and enabling the chip to operate stably in complex electrical environments.

[0045] In an optional embodiment, the material of the insulating layer 20 is selected from one or more of polyimide, benzocyclobutene, and their derivatives. The insulating layer 20 is made of a low dielectric constant material, which, while ensuring good electrical insulation performance, has high mechanical strength and flexibility, and can effectively buffer the stress between the chip body 10 and the substrate 30, thereby improving the mechanical stability of the packaging structure.

[0046] In an optional embodiment, the substrate 30 area surrounding the blind via is locally metallized, and the substrate 30 is made of FR-4 material. FR-4 material has certain heat dissipation performance, and the local metallization treatment around the blind via further enhances the heat conduction capability, allowing heat to be transferred more efficiently from the chip to the external environment, avoiding heat accumulation inside the chip, thereby reducing the chip's operating temperature and improving the chip's reliability and lifespan. The use of FR-4 material for the substrate 30 also enhances the connection strength between the substrate 30 and the microbumps 230, enabling the entire package structure to better resist deformation and damage when subjected to external forces, improving mechanical reliability and reducing the risk of electrical connection failure due to external forces.

[0047] In an optional embodiment, the wiring pattern of the rewiring structure 220 is produced by double exposure technology during the photolithography process to improve the accuracy and resolution of the wiring pattern.

[0048] This embodiment also provides a method for preparing a board-level RDL packaging structure, such as... Figure 4 As shown, it includes the following steps:

[0049] S100: The chip body 10 is cleaned and dried, and the electrode pads 111 of the chip body 10 are surface activated. The area of ​​the electrode pads 111 on the chip body 10 is the central functional area 110, and the area around the central functional area 110 is the peripheral non-functional area 120.

[0050] S200, deposit an insulating layer 20 in the surrounding non-functional area 120, and open multiple through holes 210 on the insulating layer 20;

[0051] S300, a redistribution structure 220 is formed in the through hole 210. The redistribution structure 220 includes a seed layer 221, a conductive layer 222 and a protective layer 223 from bottom to top.

[0052] S400, Micro-bumps 230 are formed above the redistribution structure 220;

[0053] S500: A blind hole is formed on the connection pad 310 of the substrate 30, and the blind hole is filled with conductive material.

[0054] S600: Align the microbumps 230 on the chip body 10 with the blind holes on the substrate 30 and bond them together.

[0055] The purpose of cleaning and drying the chip body 10 in step S100 is to ensure that the surface of the chip body 10 is clean and free of impurities, laying the foundation for subsequent processes.

[0056] The chip body 10 is cleaned using a combination of deionized water rinsing, organic solvent ultrasonic cleaning, and plasma cleaning to remove particulate contaminants, organic residues, and metal ion impurities from its surface, ensuring a surface cleanliness level of 10 or higher. This combined cleaning method effectively removes various contaminants from the chip body 10 surface, guaranteeing a high level of cleanliness and providing a solid foundation for subsequent processes.

[0057] Optionally, the surface roughness of the chip body 10 is less than 0.5 nm after chemical mechanical polishing. Chemical mechanical polishing can effectively reduce the surface roughness of the chip body 10, allowing the subsequently deposited thin film to adhere better and improving the adhesion between layers.

[0058] In an optional embodiment, step S200 specifically includes the following steps: depositing an insulating layer 20 on the front side of the chip body 10 through processes such as spin coating and chemical vapor deposition; forming an insulating layer 20 with a predetermined pattern using photolithography and etching techniques, i.e., deposited on the peripheral non-functional area 120 and on the edge of part of the central functional area 110, and opening vias 210 in the insulating layer 20; forming a predetermined pattern using photolithography and etching techniques, where photolithography is used to transfer the designed pattern onto photoresist using a mask, and after exposure and development, the etching process removes the insulating material not protected by the photoresist, thereby forming an insulating layer 20 deposited on the peripheral non-functional area 120 and on the edge of part of the central functional area 110 with vias 210, providing a basic structure for the subsequent fabrication of the rewiring structure 220, and simultaneously achieving electrical isolation between different areas of the chip.

[0059] In an optional embodiment, step S300 specifically includes the following steps: sputtering a titanium-copper alloy seed layer in the through-hole 210 of the insulating layer 20 at a sputtering power of 300W to 500W for 10 to 15 minutes; coating with photoresist and photolithographically defining the wiring pattern of the redistribution structure 220; exposure time of 30 to 40 seconds; and exposure energy of 120 mJ / cm². 2 ~180mJ / cm 2 After development, a conductive copper plating layer is formed. The plating solution contains 0.1%–0.5% silver salt, the temperature of the plating solution is 25℃–35℃, and the current density is 1A / dm³. 2 ~3A / dm 2 After electroplating, the photoresist is removed, and a titanium nitride protective layer is deposited by CVD at 700℃~800℃ for 20 minutes~30 minutes. Then, an aluminum oxide thin film is deposited by ALD process at 200℃~300℃ for 5~10 cycles. Titanium nitride is generated by the reaction of a gaseous source at high temperature and deposited on the surface of conductive layer 222 to play a protective role. ALD is based on the self-limiting reaction principle, which can precisely control the film thickness and quality, further enhancing the protective and insulating properties.

[0060] In an optional embodiment, step S400 specifically includes the following steps: coating photoresist on the redistribution structure 220, photolithographically defining the position and shape of the microbumps 230, exposure time of 25 to 35 seconds, and exposure energy of 110 mJ / cm². 2 ~160mJ / cm 2 After development, a tin-silver-copper alloy is electroplated to form micro-bumps (230). The electroplating temperature is 20℃~30℃, and the current density is 0.5A / dm². 2 ~1.5A / dm 2After electroplating, the photoresist is removed, and electroless nickel-gold plating is performed. The nickel layer thickness is 3μm to 5μm, and the gold layer thickness is 2μm to 5μm. Setting the nickel layer thickness between 3μm and 5μm ensures performance while avoiding excessive thickness that could affect subsequent connections. Electroless gold plating enhances the conductivity and oxidation resistance of the microbumps 230. The gold layer thickness between 2μm and 5μm ensures good electrical performance and surface quality, enabling the microbumps 230 to reliably achieve electrical connections between the chip body 10 and the substrate 30.

[0061] In an optional embodiment, step S500 specifically includes the following steps: creating blind holes on the surface of the substrate 30 using laser drilling at a laser power of 10W to 20W, a pulse frequency of 10kHz to 20kHz, and a drilling speed of 1mm / s to 2mm / s; filling the blind holes with conductive silver paste and curing it. The conductive silver paste has good conductivity and, after curing, can form a stable conductive path in the blind holes, forming an electrical channel after contacting the microbumps 230.

[0062] In an optional embodiment, step S600 specifically includes the following steps: precisely aligning the microbumps 230 on the chip body 10 with the blind vias on the substrate 30, and hot-press bonding them at 230℃~250℃ and 1MPa~3MPa pressure for 5 to 10 minutes. After bonding, the electrical connections and mechanical properties of the package structure are tested. The electrical connection test ensures that electrical parameters such as the resistance of each connection point meet the requirements, and the mechanical property test evaluates the reliability of the package structure under different environments and external forces, ensuring product quality and stability.

[0063] Mechanical performance testing includes the steps of performing reliability testing on the package structure, which includes at least one of high temperature aging test, damp heat test, and mechanical shock test.

[0064] The high-temperature aging test is conducted at 150℃~180℃ for 24 hours~48 hours; the damp heat test is conducted at 85℃ and 85% relative humidity for 168 hours~240 hours; the mechanical impact test is conducted with an acceleration of 100g~200g and a pulse duration of 5ms~10ms.

[0065] These tests ensure that the packaging structure meets the reliability requirements for actual use.

[0066] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A board-level RDL packaging structure, characterized in that, It includes a chip body and a substrate; the surface of the chip body facing the substrate includes a central functional area and a peripheral non-functional area, the central functional area is provided with electrode pads, the peripheral non-functional area is provided with an insulating layer, the insulating layer has multiple through holes, and a rewiring structure is provided in the through holes; The substrate has connection pads on its surface near the chip body. The redistribution structure includes a seed layer, a conductive layer, and a protective layer arranged sequentially from bottom to top. The seed layer is electrically connected to the electrode pads, and the protective layer has microbumps on its surface away from the conductive layer. The connection pad has blind holes corresponding to the microbumps, and the blind holes are filled with conductive material. The microbumps are electrically connected to the connection pads through the conductive material.

2. The board-level RDL packaging structure according to claim 1, characterized in that, The seed layer is made of titanium-copper alloy, the conductive layer is made of electroplated copper, and the protective layer is made of titanium nitride.

3. The board-level RDL packaging structure according to claim 1, characterized in that, The microbumps are made of a tin-silver-copper alloy, and the surface of the microbumps has a chemically plated nickel-gold layer.

4. The board-level RDL packaging structure according to claim 3, characterized in that, The thickness of the electroless nickel-gold plating layer is between 5 μm and 10 μm.

5. The board-level RDL packaging structure according to any one of claims 1 to 4, characterized in that, The micro-bumps are conical in shape.

6. The board-level RDL packaging structure according to claim 1, characterized in that, The distance between the edge of the central functional area near the edge of the surrounding non-functional area and the edge of the surrounding non-functional area near the central functional area is between 5 μm and 10 μm.

7. The board-level RDL packaging structure according to claim 1, characterized in that, The material of the insulating layer is selected from one or more of polyimide, benzocyclobutene and its derivatives.

8. The board-level RDL packaging structure according to claim 1, characterized in that, The substrate region surrounding the blind via is locally metallized.

9. A method for preparing the board-level RDL packaging structure according to claims 1 to 8, characterized in that, Includes the following steps: The chip body is cleaned and dried, and the electrode pads of the chip body are surface activated. The area of ​​the electrode pads on the chip body is the central functional area, and the area surrounding the central functional area is the peripheral non-functional area. An insulating layer is deposited in the surrounding non-functional area, and multiple through holes are formed in the insulating layer; A rewiring structure is formed within the through-hole, and the rewiring structure includes, from bottom to top, a seed layer, a conductive layer, and a protective layer. Micro-bumps are formed above the redistribution structure; Blind holes are formed on the connection pads of the substrate, and the blind holes are filled with conductive material; The microbumps on the chip body are aligned with the blind vias on the substrate and then bonded.

10. The preparation method according to claim 9, characterized in that, A seed layer, a conductive layer, and a protective layer are sequentially disposed from bottom to top within the through-hole to form a rewiring structure, specifically including the following steps: A titanium-copper alloy seed layer is sputtered into the via at a sputtering power of 300W to 500W for 10 to 15 minutes. Photoresist is then applied, and a wiring pattern defining the redistribution structure is photolithographically formed. The exposure time is 30 to 40 seconds, and the exposure energy is... 120mJ / cm 2 ~180mJ / cm 2 After development, a conductive copper plating layer is formed. The plating solution contains 0.1%–0.5% silver salt, the temperature of the plating solution is 25℃–35℃, and the current density is 1A / dm³. 2 ~3A / dm 2 After electroplating, the photoresist is removed, and a titanium nitride protective layer is deposited by CVD at 700℃~800℃ for 20 minutes~30 minutes. Then, an aluminum oxide thin film is deposited by ALD process at 200℃~300℃ for 5~10 cycles. Titanium nitride is generated by reacting with a gas source at high temperature and deposited on the surface of the conductive layer.

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