A semiconductor package structure and fabrication method

Abstract

The application provides a semiconductor packaging structure and a manufacturing method, which can reduce the number of solder joints and packaging layers, and increase production efficiency. The semiconductor packaging structure comprises a first multi-layer circuit layer, a second multi-layer circuit layer, a silicon bridge composite layer, a chip packaging layer, a solder resist ink layer and a plurality of tin balls. The silicon bridge composite layer comprises a plurality of groups of silicon bridges, a plurality of copper columns and a first plastic encapsulation body. The plurality of groups of silicon bridges comprise a first silicon bridge with a TSV structure. The chip packaging layer comprises a chip group, a filling layer and a second plastic encapsulation body. The chip group comprises at least one computing and storage chip. The solder resist ink layer is arranged with a plurality of tin balls in a downward protruding manner. The tin balls are used for soldering of a printed circuit board. The first silicon bridge and the copper column are used for signal communication between the first multi-layer circuit layer and the second multi-layer circuit layer.

Description

Technical Field

[0001] This invention relates to the technical field of semiconductor device packaging, specifically to a semiconductor packaging structure, and also provides a method for manufacturing the packaging structure. Background Technology

[0002] In existing technologies, large-size AI chips can adopt the COWOS-L structure based on 'chip' technology, in which computing and storage chips are connected to a molding intermediate layer, which contains silicon bridges to support high-speed interconnection of the chips above.

[0003] In the existing technology, the intermediate layer is connected to the organic ABF substrate through a C4 bump structure. The substrate needs to be soldered onto the PCB board in the end. With the increase in package size, the wafer utilization rate is getting lower and lower. Moreover, the multi-layer structure and multiple solder joints increase the manufacturing complexity and signal transmission reflection.

[0004] Therefore, there is an urgent need to develop a packaging structure that can reduce the number of solder joints and packaging layers, thereby improving production efficiency. Summary of the Invention

[0005] To address the aforementioned problems, this invention provides a semiconductor packaging structure that can reduce the number of solder joints and packaging layers, thereby increasing production efficiency.

[0006] A semiconductor packaging structure, characterized in that it comprises: First multi-layer circuit layer; The second multi-layer circuit layer; A silicon bridge composite layer includes several sets of silicon bridges, several copper pillars, and a first molding compound, wherein the several sets of silicon bridges include a first silicon bridge with a TSV structure. A chip packaging layer includes a chipset, a filler layer, and a second molding compound, wherein the chipset includes at least one computing and storage chip; Solder resist ink layer; And several tin balls; The chip packaging layer, the first multilayer circuit layer, the silicon bridge composite layer, the second multilayer circuit layer, and the solder resist ink layer are sequentially stacked and composited. The solder resist ink layer has a plurality of protruding solder balls arranged on it. The solder balls are used for soldering the printed circuit board. The first silicon bridge and copper pillars are used to connect the signals between the first multilayer circuit layer and the second multilayer circuit layer.

[0007] Its further features are: A reinforcing ring is provided on the upper surface of the first multilayer circuit layer corresponding to the peripheral area of ​​the chipset. The second molding compound fills the area formed by the chipset and the reinforcing ring. The reinforcing ring is used to improve the overall rigidity. When the number of layers of the second multilayer circuit layer is large, the silicon bridge group includes at least one set of second silicon bridges without TSV structure. The second silicon bridge is obtained by wafer processing. Part of the dense wiring of the second multilayer circuit layer is integrated into the second silicon bridge, which reduces the number of wiring layers of the second multilayer circuit layer, thereby reducing yield damage and warping in the process. The second silicon bridge achieves power grounding through a horizontal line, so the first silicon bridge does not need to have a TSV structure, which reduces the manufacturing cost of the silicon bridge's TSV structure.

[0008] A method for fabricating a semiconductor packaging structure, characterized in that: First, the silicon bridge is pre-encapsulated and embedded in the molding compound through temporary bonding. Then, high copper pillars are fabricated on a double-sided separable substrate, and the pre-encapsulated silicon bridge is mounted. Next, a second multilayer circuit layer is fabricated, which replaces the substrate circuitry through design. Then, the two sets of semi-finished products are separated and polished using a temporary substrate to complete the rewiring of the first multilayer circuit layer. Computing and memory chips are then mounted, followed by chip packaging layer fabrication and processing to obtain solder balls.

[0009] Its further features are: The specific production steps are as follows: S1, the silicon bridge of the incoming material is mounted on a temporary carrier, the temporary carrier is covered with a temporary bonding film, and the silicon bridge is provided with a TSV structure. S2, the embedded silicon bridge is encapsulated using molding compound; S3, after removing the temporary carrier board, attach the DAF film to the other side and cut it into individual pre-sealed silicon bridges; S4, a convex copper pillar is formed on one side of the double-sided separable temporary carrier plate; S5, pre-sealed silicone bridge mounting on one side of the double-sided separable temporary carrier board; S6, the pre-sealed silicon bridge is encapsulated on one side of the double-sided separable temporary carrier through a molding compound; S7 uses a planarization process to expose the TSV structure of the copper pillars and silicon bridges, forming a silicon bridge composite layer; S8. Repeat steps S4-S7 on the other side of the double-sided separable temporary carrier to obtain another set of silicon bridge composite layers. S9, a second multilayer circuit layer is formed on each group of silicon bridge composite layers, thereby forming a double-sided second multilayer circuit layer. Each group of second multilayer circuit layers contains circuits, organic materials such as ABF. S10, a solder resist ink layer is formed on each of the second multilayer circuit layers, and chemical plating is performed to protect the second multilayer circuit layer; S11, one layer of solder resist ink is bonded to a temporary carrier, then the double-sided separable carrier is removed, and another layer of solder resist ink is bonded to another temporary carrier. S12, planarize the side of the silicon bridge composite layer away from the temporary carrier, and expose the metal copper pillars of the silicon bridge; S13, the first multi-layer circuit is created by rewiring, which is used to connect the chipset; S14, each chip in the chipset is fixed to the corresponding position of the first multilayer circuit layer by soldering. S16, followed by underfilling, molding and planarization processes to form the surface layer of the computing and storage chip; S17, Remove the temporary carrier board; S18, a number of solder balls are placed on the back of a solder resist ink layer.

[0010] Its further characteristic is: After step S14, step S15 is also provided, in which a reinforcing ring is provided on the upper surface of the first multilayer circuit layer corresponding to the outer periphery of the chipset to improve the overall rigidity.

[0011] With the present invention, a substrate is no longer required. The circuitry of the substrate is directly integrated through the second multilayer circuit layer, which can reduce the number of solder joints and the number of packaging layers, thereby reducing packaging costs and improving packaging yield. Attached Figure Description

[0012] Figure 1 This is a specific embodiment of the present invention; Figure 2 This is a specific embodiment two of the present invention; Figure 3 This is a specific embodiment three of the present invention: Figure 4 This is a simplified structural diagram of step S1 of the present invention; Figure 5 This is a simplified structural diagram of step S2 of the present invention; Figure 6 This is a simplified structural diagram of step S3 of the present invention; Figure 7 This is a simplified structural diagram of step S4 of the present invention; Figure 8 This is a simplified structural diagram of step S5 of the present invention; Figure 9 This is a simplified structural diagram of step S6 of the present invention; Figure 10 This is a simplified structural diagram of step S7 of the present invention; Figure 11 This is a simplified structural diagram of step S8 of the present invention; Figure 12 This is a simplified structural diagram of step S9 of the present invention; Figure 13 This is a simplified structural diagram of step S10 of the present invention; Figure 14 This is a simplified structural diagram of step S11 of the present invention; Figure 15 This is a simplified structural diagram of step S12 of the present invention; Figure 16 This is a simplified structural diagram of step S13 of the present invention; Figure 17 This is a simplified structural diagram of step S14 of the present invention; Figure 18 This is a simplified structural diagram of step S15 of the present invention; Figure 19 This is a simplified structural diagram of step S16 of the present invention; Figure 20 This is a simplified structural diagram of step S17 of the present invention; Figure 21 This is a simplified structural diagram of step S18 of the present invention. Detailed Implementation

[0013] A semiconductor packaging structure, see Figures 1-3 It includes a first multilayer circuit layer 12, a second multilayer circuit layer 9, a silicon bridge composite layer 19, a chip packaging layer 20, a solder resist ink layer 10, and a number of solder balls 16. The silicon bridge composite layer 19 includes several sets of silicon bridges, several copper pillars 5, and a first molding compound 8. Among the several sets of silicon bridges, there is a first silicon bridge 1 with a TSV structure. Chip packaging layer 20 includes chipset, fill layer 17, and second molding compound 18. Chipet includes at least one computing and storage chip 13. The chip packaging layer 20, the first multilayer circuit layer 12, the silicon bridge composite layer 19, the second multilayer circuit layer 9, and the solder resist ink layer 10 are stacked in sequence. The solder resist ink layer 10 has a number of protruding solder balls 16 arranged on it. The solder balls 16 are used for soldering the printed circuit board. The first silicon bridge 1 and the copper pillar 5 are used to connect the signals between the first multilayer circuit layer 12 and the second multilayer circuit layer 9.

[0014] Specific Implementation Example 1, see Figure 1 It includes two sets of first silicon bridges 1, a reinforcing ring 15 on the upper surface of the first multilayer circuit layer 12 corresponding to the peripheral area of ​​the chipset, and a second molding compound 18 molding the area formed by the three computing and storage chips 13 and the reinforcing ring 15. The reinforcing ring 15 is used to improve the overall rigidity.

[0015] See Specific Implementation Example 2 Figure 2 When the number of layers of the second multilayer circuit layer 9 is relatively large, the silicon bridge group includes two sets of first silicon bridges 1 and two sets of second silicon bridges 21 without TSV structure. The second silicon bridges 21 are obtained by wafer processing to achieve wiring of less than 1 micrometer. Some of the dense wiring of the second multilayer circuit layer 9 is integrated into the second silicon bridges 21, which reduces the number of wiring layers of the second multilayer circuit layer 9, thereby reducing yield damage and warping in the process.

[0016] In the third specific embodiment, based on the structure of the second specific embodiment, the second silicon bridge 21 realizes the power grounding function through a horizontal line. At this time, the first silicon bridge 1 does not need to set a TSV structure, which reduces the manufacturing cost of the silicon bridge's TSV structure.

[0017] A method for fabricating a semiconductor packaging structure: First, a silicon bridge is pre-encapsulated and embedded in a molding compound through temporary bonding. Then, high copper pillars 5 are fabricated on a double-sided separable substrate 6, and the pre-encapsulated silicon bridge 7 is mounted. Next, a second multilayer circuit layer 9 is fabricated, which replaces the substrate circuitry through design. Then, the two sets of semi-finished products are separated and polished using a temporary substrate 11 to complete the redistribution fabrication of the first multilayer circuit layer 12. Computing and storage chips 13 are then mounted. Subsequently, a chip packaging layer 20 is fabricated, and solder balls 16 are obtained.

[0018] The specific fabrication steps for the packaging method with a reinforcing ring and only a package structure containing three computing and storage chips 13 are as follows (see below). Figures 4-21 : S1, the first silicon bridge 1 of the incoming material is attached to the first temporary carrier 2, the first temporary carrier 2 is attached with a temporary bonding film, and the first silicon bridge 1 is provided with a TSV structure. S2, the pre-embedded first silicon bridge 1 is encapsulated using molding compound 3; S3, after removing the first temporary carrier board 2, attach the DAF film 4 to the other side and cut it into individual pre-sealed silicon bridges 7; S4, A convex copper pillar 5 is formed on one side of the double-sided separable temporary carrier plate 6; S5, Pre-sealed silicon bridge 7 is mounted on one side of the double-sided separable temporary carrier board 6; S6, the pre-sealed silicon bridge 7 is encapsulated on one side of the double-sided separable temporary carrier board 6 through the first encapsulator 8; S7, The TSV structure of the copper pillar 5 and the first silicon bridge 1 is exposed by a planarization process to form a silicon bridge composite layer 19; S8. Repeat steps S4-S7 on the other side of the double-sided separable temporary carrier 6 to obtain another set of silicon bridge composite layers 19. S9, a second multilayer circuit layer 9 is formed on each group of silicon bridge composite layers 19, thereby forming a double-sided second multilayer circuit layer 9. Each group of first multilayer circuit layers 9 contains circuits, organic materials such as ABF. S10, a solder resist ink layer 10 is formed on each first multilayer circuit layer 9, and chemical plating is performed to protect the second multilayer circuit layer 9; S11, one layer of solder resist ink 10 is bonded to the second temporary carrier 11, then the double-sided separable carrier 6 is removed, and another layer of solder resist ink 10 is bonded to another second temporary carrier 11. S12, the side of the silicon bridge composite layer 19 away from the second temporary carrier 11 is flattened, exposing the metal copper pillars of the first silicon bridge 1 and the copper pillars 5. S13, the first multilayer circuit layer 12 is made by rewiring to connect the chipset; S14, the three computing and storage chips 13 are fixed to the corresponding positions of the first multilayer circuit layer 12 by soldering, and the solder joints 14 are obtained by reflow and TCB. S15, a reinforcing ring 15 is provided on the upper surface of the first multilayer circuit layer 12 corresponding to the outer periphery of the chipset to improve the overall rigidity; S16, then bottom filling and molding are performed to obtain filling layer 17 and second molding body 18, and planarization process is performed to form the surface layer of computing and storage chip; S17, Remove the second temporary carrier plate 11; S18, a plurality of solder balls 16 are disposed on the back side of a solder resist ink layer 10.

[0019] It no longer requires a substrate, and the circuitry of the substrate is directly integrated through the second multilayer circuit layer. This reduces the number of solder joints and packaging layers, thereby reducing packaging costs and improving packaging yield.

[0020] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0021] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A semiconductor packaging structure, characterized in that, It includes: First multi-layer circuit layer; The second multi-layer circuit layer; A silicon bridge composite layer includes several sets of silicon bridges, several copper pillars, and a first molding compound, wherein the several sets of silicon bridges include a first silicon bridge with a TSV structure. A chip packaging layer includes a chipset, a filler layer, and a second molding compound, wherein the chipset includes at least one computing and storage chip; Solder resist ink layer; And several tin balls; The chip packaging layer, the first multilayer circuit layer, the silicon bridge composite layer, the second multilayer circuit layer, and the solder resist ink layer are sequentially stacked and composited. The solder resist ink layer has a plurality of protruding solder balls arranged on it. The solder balls are used for soldering the printed circuit board. The first silicon bridge and copper pillars are used to connect the signals between the first multilayer circuit layer and the second multilayer circuit layer.

2. The semiconductor packaging structure according to claim 1, characterized in that: A reinforcing ring is provided on the upper surface of the first multilayer circuit layer corresponding to the peripheral area of ​​the chipset, and the second molding compound fills the area formed by the chipset and the reinforcing ring.

3. A semiconductor packaging structure according to claim 1, characterized in that: When the number of layers of the original second multilayer circuit layer is large, the silicon bridge group includes at least one set of second silicon bridges without TSV structure. The second silicon bridge is obtained by wafer processing, and part of the dense wiring of the second multilayer circuit layer is integrated into the second silicon bridge.

4. A semiconductor packaging structure according to claim 3, characterized in that: The second silicon bridge achieves power grounding through a horizontal line, so the first silicon bridge does not need to be equipped with a TSV structure.

5. A method for fabricating a semiconductor package structure, used to fabricate a semiconductor package structure as described in any one of claims 1-4, characterized in that: First, the silicon bridge is pre-encapsulated and embedded in the molding compound through temporary bonding. Then, high copper pillars are fabricated on a double-sided separable substrate, and the pre-encapsulated silicon bridge is mounted. Next, a second multilayer circuit layer is fabricated, which replaces the substrate circuitry through design. Then, the two sets of semi-finished products are separated and polished using a temporary substrate to complete the rewiring of the first multilayer circuit layer. Computing and memory chips are then mounted, followed by chip packaging layer fabrication and processing to obtain solder balls.

6. The method for fabricating a semiconductor packaging structure according to claim 5, characterized in that, The specific production steps are as follows: S1, the silicon bridge of the incoming material is mounted on a temporary carrier, the temporary carrier is covered with a temporary bonding film, and the silicon bridge is provided with a TSV structure. S2, the embedded silicon bridge is encapsulated using molding compound; S3, after removing the temporary carrier board, attach the DAF film to the other side and cut it into individual pre-sealed silicon bridges; S4, a convex copper pillar is formed on one side of the double-sided separable temporary carrier plate; S5, pre-sealed silicone bridge mounting on one side of the double-sided separable temporary carrier board; S6, the pre-sealed silicon bridge is encapsulated on one side of the double-sided separable temporary carrier through a molding compound; S7 uses a planarization process to expose the TSV structure of the copper pillars and silicon bridges, forming a silicon bridge composite layer; S8. Repeat steps S4-S7 on the other side of the double-sided separable temporary carrier to obtain another set of silicon bridge composite layers. S9, a second multilayer circuit layer is formed on each group of silicon bridge composite layers, thereby forming a double-sided second multilayer circuit layer. Each group of second multilayer circuit layers contains circuits, organic materials such as ABF. S10, a solder resist ink layer is formed on each of the second multilayer circuit layers, and chemical plating is performed to protect the second multilayer circuit layer; S11, one layer of solder resist ink is bonded to a temporary carrier, then the double-sided separable carrier is removed, and another layer of solder resist ink is bonded to another temporary carrier. S12, planarize the side of the silicon bridge composite layer away from the temporary carrier, and expose the metal copper pillars of the silicon bridge; S13, the first multi-layer circuit is created by rewiring, which is used to connect the chipset; S14, each chip in the chipset is fixed to the corresponding position of the first multilayer circuit layer by soldering. S16, followed by underfilling, molding and planarization processes to form the surface layer of the computing and storage chip; S17, Remove the temporary carrier board; S18, a number of solder balls are placed on the back of a solder resist ink layer.

7. The method for fabricating a semiconductor packaging structure according to claim 6, characterized in that, After step S14, step S15 is also provided, in which a reinforcing ring is provided on the upper surface of the first multilayer circuit layer corresponding to the outer periphery of the chipset.

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