Chip bonding structure and method of manufacturing the same

Abstract

The application provides a chip bonding structure and a preparation method thereof. The chip bonding structure comprises a metal bonding layer and an isolation structure. The metal bonding layer is located between a first electrode in a first chip and a second electrode in a second chip. The metal bonding layer comprises at least one first bonding structure and a second bonding structure. The first bonding structure is electrically connected to one of the first electrode and the second electrode. The isolation structure is located between the first bonding structure and the adjacent second bonding structure. At least part of the height of the isolation structure is a cavity. The preparation method is used for preparing the chip bonding structure.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a chip bonding structure and its fabrication method. Background Technology

[0002] Chip bonding involves stacking multiple chips and using a bonding process to connect the metal and insulating layers at corresponding positions between adjacent chip layers, achieving electrical signal interconnection and enhancing connection strength. Chip bonding can improve chip integration, reduce size, increase functionality, and improve performance, and is widely used in processors, memory, and image sensors.

[0003] In existing chip bonding structures, the bonding layer includes metal bonding structures and insulating bonding structures (such as silicon oxide bonding structures). To ensure bonding quality, the bonding process requires extremely high surface roughness and cleanliness of the insulating bonding structure. Before bonding, the surface of the insulating bonding structure needs to undergo processes such as chemical mechanical polishing, chemical solution treatment, and plasma activation treatment, which makes the chip bonding process quite complex. Summary of the Invention

[0004] This application provides a chip bonding structure and its fabrication method.

[0005] The first aspect of this application provides a chip bonding structure, including:

[0006] A metal bonding layer is located between the first electrode in the first chip and the second electrode in the second chip. The metal bonding layer includes a plurality of at least one first bonding structure and a second bonding structure. Each first bonding structure is electrically connected to a first electrode and a second electrode, respectively, and the second bonding structure is not electrically connected to the first electrode and the second electrode.

[0007] An isolation structure is located between the first bonding structure and the adjacent second bonding structure; at least a portion of the height of the isolation structure is a cavity.

[0008] In one embodiment, the second bonding structure includes a plurality of at least one shielding structure, each of the at least one shielding structure surrounding a first bonding structure; the shielding structure is configured to connect a constant electrical signal.

[0009] In one embodiment, the isolation structure is a cavity penetrating the metal bonding layer.

[0010] In one embodiment, the isolation structure includes a first insulating portion and a cavity located on the side of the first insulating portion facing the second chip.

[0011] In one embodiment, the isolation structure further includes a second insulating portion, and the cavity is located between the first insulating portion and the second insulating portion.

[0012] A second aspect of this application provides a method for fabricating a chip bonding structure, the method comprising:

[0013] A first sub-metal bonding layer is formed on a first chip, the first sub-metal bonding layer including at least one first bonding portion and a second bonding portion; the first bonding portion is electrically connected to a first electrode in the first chip; a second sub-metal bonding layer is formed on a second chip, the second sub-metal bonding layer including at least one third bonding portion and a fourth bonding portion; the third bonding portion is electrically connected to a second electrode in the second chip, and the fourth bonding portion is not electrically connected to the second electrode;

[0014] A first sub-metal bonding layer and a second sub-metal bonding layer are bonded together, such that the first bonding portion is bonded to the third bonding portion to form a first bonding structure, and the second bonding portion is bonded to the fourth bonding portion to form a second bonding structure, thereby obtaining a metal bonding layer including the first bonding structure and the second bonding structure; an isolation structure is formed between the second bonding structure and the adjacent first bonding structure, and at least a portion of the height of the isolation structure is a cavity.

[0015] In one embodiment, the first bonding portion and the adjacent second bonding portion are connected by a cavity penetrating the first sub-metal bonding layer, the third bonding portion and the adjacent fourth bonding portion are connected by a cavity penetrating the second sub-metal bonding layer, and the isolation structure is a cavity penetrating the metal bonding layer.

[0016] In one embodiment, before bonding the first sub-metal bonding layer and the second sub-metal bonding layer, the method for fabricating the chip bonding structure further includes: forming a first insulating portion between the second bonding portion and the adjacent first bonding portion, wherein the surface of the first insulating portion away from the first chip is lower than the surface of the first sub-metal bonding layer away from the first chip;

[0017] The isolation structure formed after bonding the first sub-metal bonding layer and the second sub-metal bonding layer includes a first insulating portion and a cavity located on the side of the first insulating portion facing the second chip.

[0018] In one embodiment, before bonding the first sub-metal bonding layer and the second sub-metal bonding layer, the method for fabricating the chip bonding structure further includes: forming a second insulating portion between the third bonding portion and the adjacent fourth bonding portion, wherein the surface of the second insulating portion away from the second chip is lower than the surface of the second sub-metal bonding layer away from the second chip;

[0019] The isolation structure formed after bonding the first sub-metal bonding layer and the second sub-metal bonding layer includes a first insulating portion, a second insulating portion, and a cavity located between the first insulating portion and the second insulating portion.

[0020] In one embodiment, the second bonding portion includes a plurality of first shielding rings, each first shielding ring surrounding one of the first bonding portions; the fourth bonding portion includes a plurality of second shielding rings, each second shielding ring surrounding one of the third bonding portions; after the first sub-metal bonding layer and the second sub-metal bonding layer are bonded, each first shielding ring is bonded to one of the second shielding rings to form a shielding structure; the shielding structure is configured to connect a constant electrical signal.

[0021] The chip bonding structure and fabrication method provided in this application can enhance the bonding strength between the first chip and the second chip, improve the reliability of the chip bonding structure, and reduce the complexity of the fabrication process.

[0022] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0023] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0024] Figure 1 This is a schematic diagram of a chip bonding structure provided in an embodiment of this application;

[0025] Figure 2 This is a schematic diagram of a chip bonding structure provided in another embodiment of this application;

[0026] Figures 3 to 15 A process flow diagram of a method for fabricating a chip bonding structure according to an embodiment of this application;

[0027] Figure 16 This is a schematic diagram of the process flow for fabricating a chip bonding structure according to an embodiment of this application. Detailed Implementation

[0028] The technical solutions in the embodiments (or "implementations") of this application will be clearly and completely described herein with reference to the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements.

[0029] If the embodiments of this application contain terms relating to directional indications or positional relationships (such as up, down, left, right, front, back, inside, outside, top, bottom, center, vertical, horizontal, longitudinal, transverse, length, width, counterclockwise, clockwise, axial, radial, circumferential, etc.), such terms are only used to explain the relative positional relationships and movements between components in a specific posture (as shown in the attached figures); if the specific posture changes, the directional indications or positional relationships will also change accordingly. Furthermore, the terms "first" and "second" used in the embodiments of this application are only for descriptive convenience and should not be construed as indicating or implying relative importance.

[0030] The chip bonding structure and its fabrication method according to embodiments of this application will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the features of the following embodiments and implementation methods can complement or combine with each other.

[0031] This application provides a chip bonding structure, such as... Figure 1 and Figure 2 As shown, the chip bonding structure includes a first chip 10, a second chip 20, a metal bonding layer 30, and an isolation structure 40.

[0032] The first chip 10 includes multiple first electrodes 104. The second chip 20 includes multiple second electrodes 204. A metal bonding layer 30 is located between the first electrodes 104 and the second electrodes 204, and includes multiple first bonding structures 303 and second bonding structures 304. Each first bonding structure 303 is electrically connected to one first electrode 104 and one second electrode 204, respectively, and the second bonding structures 304 are not electrically connected to either the first electrode 104 or the second electrode 204. An isolation structure 40 is located between the first bonding structure 303 and the adjacent second bonding structure 304, and at least a portion of the isolation structure 40 is a cavity 401. The cavity 401 refers to a space that is not filled with solid material; it may be filled with gas or a vacuum.

[0033] The metal bonding layer 30 can be obtained by a bonding process. Specifically, before the first chip 10 and the second chip 20 are bonded, a first sub-metal bonding layer is provided on one side of the first chip 10 and a second sub-metal bonding layer is provided on one side of the second chip 20. In the bonding process, the first sub-metal bonding layer and the second sub-metal bonding layer form the metal bonding layer 30.

[0034] The first bonding structure 303 and the second bonding structure 304 of the metal bonding layer 30 are both made of metal materials, and both are structures formed in the bonding process between the first chip 10 and the second chip 20. The first bonding structure 303 can realize the electrical connection between the first chip 10 and the second chip 20. Both the first bonding structure 303 and the second bonding structure 304 can realize the bonding between the first chip 10 and the second chip 20, which can make the bonding area between the first chip 10 and the second chip 20 larger and ensure the bonding quality. Compared with the second bonding structure 304 being made of insulating material, this can enhance the bonding strength between the first chip 10 and the second chip 20 and improve the reliability of the chip bonding structure. Furthermore, the second bonding structure 304 and the first bonding structure 303 can be formed simultaneously. Since the material of the second bonding structure 304 is metal, the surface requirements for the second bonding structure 304 are lower during the bonding process, and no special surface treatment is needed. This helps reduce the bonding difficulty between the first chip 10 and the second chip 20. Compared to a scheme where the material of the second bonding structure 304 is an insulating material, the metal material of the second bonding structure 304 increases the area of ​​the metal bonding layer between the first chip 10 and the second chip 20, thereby improving the heat dissipation performance of the chip bonding structure. Compared to a scheme where the material of the isolation structure 40 is a bonded insulating structure, since at least a portion of the height of the isolation structure 40 is a cavity 401, if the isolation structure 40 includes insulating material, the insulating material does not need to be bonded. Therefore, no surface treatment of the insulating material is required before bonding, saving the process steps of surface treatment of the insulating material and simplifying the complexity of the fabrication process. When the isolation structure does not include insulating material and is entirely a cavity, the process steps of surface treatment of the insulating material can be saved, further simplifying the complexity of the fabrication process.

[0035] In one embodiment, such as Figure 1 and Figure 2 As shown, the first chip 10 includes a first substrate 101, with a first implantation region 1021 and a second implantation region 1022. The first implantation region 1021 and the second implantation region 1022 have different conductivity types. For example, the first implantation region 1021 and the second implantation region 1022 may be N-type and P-type, respectively. The first implantation region 1021 and the second implantation region 1022 are electrically connected to the first electrode 104.

[0036] The second chip 20 includes a second substrate 201, which has a third implantation region 2021 and a fourth implantation region 2022. The third implantation region 2021 and the fourth implantation region 2022 have different conductivity types. For example, the third implantation region 2021 is N-type and the fourth implantation region 2022 is P-type. The third implantation region 2021 and the fourth implantation region 2022 are electrically connected to the second electrode 204.

[0037] In one embodiment, such as Figure 1 and Figure 2 As shown, the first chip 10 further includes a first dielectric layer 103 located on one side of the first substrate 101, the first dielectric layer 103 covering the first injection region 1021 and the second injection region 1022; the first dielectric layer 103 is provided with a plurality of openings, and each first electrode 104 is located in one opening.

[0038] The second chip 20 also includes a second dielectric layer 203 located on one side of the second substrate 201, the second dielectric layer 203 covering the third injection region 2021 and the fourth injection region 2022; the second dielectric layer 203 is provided with a plurality of openings, and each second electrode 204 is located in one opening.

[0039] In one embodiment, such as Figure 1 and Figure 2 As shown, the chip bonding structure further includes a first redistribution layer 11 located between the first dielectric layer 103 and the metal bonding layer 30. The first redistribution layer 11 includes a plurality of first redistribution lines 111 and a plurality of first conductive pillars 112, with each first redistribution line 111 electrically connected to a first conductive pillar 112. The first redistribution lines 111 are electrically connected to the first electrode 104, and the first conductive pillars 112 are connected to the first bonding structure 303, thereby realizing the electrical connection between the first bonding structure 303 and the first chip 10.

[0040] In one embodiment, such as Figure 1 and Figure 2 As shown, the chip bonding structure further includes a second redistribution layer 21 located between the second dielectric layer 203 and the metal bonding layer 30. The second redistribution layer 21 includes a plurality of second redistribution lines 211 and a plurality of second conductive pillars 212, with each second redistribution line 211 electrically connected to a second conductive pillar 212. The second redistribution lines 211 are electrically connected to the second electrode 204, and the second conductive pillars 212 are connected to the first bonding structure 303, thereby achieving an electrical connection between the first bonding structure 303 and the second chip 20.

[0041] In one embodiment, such as Figure 1 and Figure 2 As shown, the second bonding structure 304 includes multiple shielding structures 3041, each shielding structure 3041 surrounding a first bonding structure 303. The shielding structures are configured to connect to a constant electrical signal. Each shielding structure 3041 has an annular isolation structure 40 between itself and the first bonding structure 303 located within it. The shielding structures 3041 can prevent other signals from interfering with the signal transmission of the first bonding structure 303, thereby ensuring the independence and stability of the signal transmission of the first bonding structure 303. Figure 1 and Figure 2In the embodiment shown, adjacent shielding structures are connected, and the second bonding structure 304 is an integral structure. Figure 1 In the diagram, the dashed line is the boundary line between adjacent shielding structures 3041. This dashed line is only used to indicate the boundary of the shielding structure 3041 and does not actually exist.

[0042] In one embodiment, the distance between the metal interconnect layers of two adjacent chip layers is very small, which can easily lead to signal crosstalk between the two chip layers, affecting the normal function and performance of the chip. Figure 1 and Figure 2 In this configuration, the first chip 10 and the second chip 20 are connected by a metal bonding layer 30. Due to the small thickness of the metal bonding layer 30, the distance between the first rewiring 111 of the first chip 10 and the second rewiring 211 of the second chip 20 is small, making signal crosstalk between the first rewiring 111 and the second rewiring 211 likely to occur during signal transmission. The shielding structure 3041 of the second bonding structure 304 is located between the first rewiring 111 and the second rewiring 211, which can prevent signal interference between the first rewiring 111 and the second rewiring 211 and improve the working stability of the first chip 10 and the second chip 20.

[0043] Furthermore, the first redistribution layer 11 also includes a third conductive post 113 connected to the ground line, and the second bonding structure 304 is connected to the ground line through the third conductive post 113. This allows the shielding structure to be connected to a stable electrical signal without the need for additional wires, which helps to simplify the complexity of the chip bonding structure.

[0044] Furthermore, the second redistribution layer 21 also includes a fourth conductive post 213 connected to the ground line, and the second bonding structure 304 is connected to the ground line through the fourth conductive post 213. This allows the shielding structure to be connected to a stable electrical signal without the need for additional wires, which helps to simplify the complexity of the chip bonding structure.

[0045] In one embodiment, such as Figure 1 As shown, the isolation structure 40 is a cavity 401 penetrating the metal bonding layer 30. The cavity 401 can isolate adjacent first bonding structures 303 and second bonding structures 304, preventing short circuits between them. In this embodiment, the cavity 401 is an annular cavity structure surrounding the first bonding structure 303.

[0046] In one embodiment, such as Figure 2As shown, the isolation structure 40 includes a first insulating portion 402 and a cavity 401 located on the side of the first insulating portion 402 facing the second chip 20. If the isolation structure 40 only includes the first insulating portion 402 and the cavity 401, the first insulating portion 402 does not need to be bonded to other structures, thus eliminating the need for processing the surface of the first insulating portion 402 facing the second chip 20, thereby simplifying the process flow. If the isolation structure 40 also includes a second insulating portion located on the side of the cavity 401 away from the first insulating portion 402, the surfaces of both the first insulating portion 402 and the second insulating portion 403 do not need to be processed, further simplifying the process flow. By providing the first insulating portion 402, the first sub-metal bonding layer can be reinforced before the first chip 10 and the second chip 20 are bonded, preventing the first sub-metal bonding layer from separating from adjacent film layers.

[0047] Furthermore, the isolation structure 40 also includes a second insulating portion 403, and the cavity 401 is located between the first insulating portion 402 and the second insulating portion 403. With the cavity 401 between the first insulating portion 402 and the second insulating portion 403, bonding between them is unnecessary. This reduces the processing steps on the surface of the first insulating portion 402 facing the second chip 20 and the surface of the second insulating portion 403 facing the first chip 10. It also eliminates concerns about bonding quality at the contact surface between the first and second insulating portions 402 and 403, simplifying the process and reducing bonding difficulty. By providing the second insulating portion 403, the second sub-metal bonding layer can be reinforced before bonding the first chip 10 and the second chip 20, preventing separation of the second sub-metal bonding layer from adjacent film layers.

[0048] In this embodiment, the first insulating part 402 and the second insulating part 403 are both annular structures surrounding the first bonding structure 303, and the cavity 401 is an annular cavity surrounding the first bonding structure 303.

[0049] This application also provides a method for fabricating a chip bonding structure, such as... Figure 16 As shown, the preparation method includes:

[0050] Step S500: As Figure 3 and Figure 8 As shown, a first chip 10 and a second chip 20 are provided. The first chip 10 includes a plurality of first electrodes 104, and the second chip 20 includes a plurality of second electrodes 204.

[0051] Step S510: As Figure 6 and Figure 7As shown, a first sub-metal bonding layer is formed on the first chip 10. The first sub-metal bonding layer includes a plurality of first bonding portions 301 and second bonding portions 302; each first bonding portion 301 is electrically connected to a first electrode 104, and the second bonding portion 302 is not electrically connected to the first electrode 104; as shown Figure 8 As shown, a second sub-metal bonding layer is formed on the second chip 20. The second sub-metal bonding layer includes a plurality of third bonding portions 301' and fourth bonding portions 302'. Each of the third bonding portions 301' is electrically connected to a second electrode 204, and the fourth bonding portion 302' is not electrically connected to the second electrode 204.

[0052] Step S520: As Figure 9 As shown, a first sub-metal bonding layer and a second sub-metal bonding layer are bonded together, such that each of the first bonding portions 301 is bonded to a third bonding portion 301' to form a first bonding structure 303, and the second bonding portion 302 is bonded to a fourth bonding portion 302' to form a second bonding structure 304, resulting in a metal bonding layer 30 including the first bonding structure 303 and the second bonding structure 304. An isolation structure 40 is formed between the second bonding structure 304 and the adjacent first bonding structure 303, and at least a portion of the isolation structure 40 is a cavity 401.

[0053] In one embodiment, such as Figure 3 As shown, the first chip 10 includes a first substrate 101, with a first injection region 1021 and a second injection region 1022. The first injection region 1021 and the second injection region 1022 have different conductivity types. For example, the first injection region 1021 and the second injection region 1022 may have N-type and P-type conductivity, respectively. The first injection region 1021 and the second injection region 1022 are electrically connected to a first electrode 104. The first chip also includes a first dielectric layer 103 located on one side of the first substrate 101, covering the first injection region 1021 and the second injection region 1022. The first dielectric layer 103 has multiple openings, with each first electrode 104 located within one opening.

[0054] In one embodiment, such as Figure 4 As shown, prior to step S510, the fabrication method further includes forming a first redistribution layer 11 on the side of the first dielectric layer 103 away from the first substrate 101.

[0055] The steps for forming the first redistribution layer 11 include the following: First, a first redistribution dielectric layer 114 is formed on the first dielectric layer 103. Through-holes are formed on the first redistribution dielectric layer 114 to expose the first electrode 104, and first redistribution wiring 111 is formed in each through-hole, so that the first redistribution wiring 111 is connected to the first electrode 104. Then, a second redistribution dielectric layer 115 is formed on the first redistribution dielectric layer 114, and multiple through-holes are formed on the second redistribution dielectric layer 115 to partially expose the first redistribution wiring 111. First conductive pillars 112 are formed in the through-holes exposing the first redistribution wiring 111, and third conductive pillars 113 are formed in the other through-holes.

[0056] The materials of the first redistribution dielectric layer 114 and the second redistribution dielectric layer 115 can be silicon dioxide or silicon carbonitride, etc.; the materials of the first redistribution 111 and the first conductive post 112 can be copper or other metallic materials.

[0057] In one embodiment, the third conductive post 113 is connected to the ground wire, which allows the second bonding structure 304 to be connected to the ground wire through the third conductive post 113.

[0058] In one embodiment, such as Figure 5 As shown, before forming the first sub-metal bonding layer on the first chip 10 after forming the first redistribution layer 11, the fabrication method further includes the following step: forming an electroplating seed layer 50 on the side of the first redistribution layer 11 away from the first substrate 101. Before forming the electroplating seed layer 50, a metal adhesion layer and a diffusion barrier layer can be formed sequentially on the first redistribution layer 11, with the electroplating seed layer 50 formed on the side of the diffusion barrier layer away from the first chip 10. The metal adhesion layer can improve the adhesion of the electroplating seed layer 50 on the first redistribution layer 11, and the diffusion barrier layer can prevent the metal material of the electroplating seed layer 50 from diffusing into the first redistribution layer 11. The metal adhesion layer can be made of titanium or titanium nitride, and its thickness ranges from 20 nm to 50 nm, for example, 25 nm, 35 nm, 45 nm, etc. The diffusion barrier layer can be made of tantalum or tantalum nitride, and its thickness ranges from 20 nm to 50 nm, for example, 25 nm, 35 nm, 45 nm, etc. The material of the electroplated seed layer 50 is copper, etc., and its thickness ranges from 100nm to 200nm, for example, it can be 120nm, 150nm, 180nm, etc.

[0059] In one embodiment, such as Figure 5As shown, after forming the electroplating seed layer 50, the preparation method further includes: coating photoresist on the side of the electroplating seed layer 50 away from the first substrate 101, and performing a patterning process on the photoresist to form a mask layer 60. The thickness of the mask layer 60 ranges from 2μm to 5μm, for example, it can be 3.5μm, 4.0μm, 4.5μm, etc.

[0060] In one embodiment, such as Figure 6 As shown, in step S510, a first sub-metal bonding layer is formed on the first chip 10. The first sub-metal bonding layer includes a plurality of first bonding portions 301 and second bonding portions 302. Specifically, the first sub-metal bonding layer is prepared on the electroplating seed layer 50 by an electroplating process. The thickness of the first sub-metal bonding layer is less than or equal to the thickness of the mask layer 60. Afterwards, as... Figure 7 As shown, the mask layer 60 is removed, and the electroplating seed layer ( Figure 7 The exposed area (not shown) is removed. The mask layer 60 prepared by photoresist can be removed by plasma etching, and the exposed part of the electroplating seed layer 50 and the diffusion barrier layer and metal adhesion layer in the corresponding area below it can be removed by wet etching to form a first sub-cavity 4011. The first sub-cavity 4011 divides the first sub-metal bonding layer into a plurality of first bonding portions 301 and second bonding portions 302.

[0061] In one embodiment, the step of forming the second sub-metal bonding layer on the second chip 20 is similar to the step of forming the first sub-metal bonding layer on the first chip 10, and will not be described again. After forming the second sub-metal bonding layer on the second chip 20, the following can be obtained: Figure 8 The structure shown. (As illustrated) Figure 8 As shown, the second sub-metal bonding layer includes a third bonding portion 301' and a fourth bonding portion 302', and the gap between the fourth bonding portion 302' and the adjacent third bonding portion 301' is the second sub-cavity 4012.

[0062] In one embodiment, before step S520, Figure 7 The first sub-metal bonding layer in the structure shown is Figure 8 After the first sub-metal bonding layer in the structure shown is aligned, the following is obtained: Figure 9 The structure shown. (As illustrated) Figure 9 As shown, each first bonding portion 301 is opposite to and in contact with a third bonding portion 301', and the second bonding portion 302 is opposite to and in contact with the fourth bonding portion 302'. The first sub-cavity 4011 and the second sub-cavity 4012 are connected to form a cavity 401. Step 520 yields the following result: Figure 1 The chip bonding structure shown.

[0063] In one embodiment, prior to step S520, the fabrication method further includes: forming a first insulating portion between the second bonding portion and an adjacent first bonding portion, wherein the surface of the first insulating portion away from the first chip is lower than the surface of the first sub-metal bonding layer away from the first chip. This step may include multiple process steps, some of which are performed before S520 and some of which are performed after S520. Specifically, this step and step S520 may include the following processes:

[0064] First, such as Figure 10 As shown, multiple first insulating portions 402 are formed. The first insulating portions 402 are annular. When the material of the first insulating portion 402 is silicon dioxide, a single layer of silicon dioxide can be formed first. Using photoresist as a mask, the silicon dioxide layer is etched using reactive ion etching. Then, plasma etching is used to remove the photoresist mask, forming the first insulating portion 402. The thickness of the first insulating portion 402 ranges from 2μm to 5μm, for example, it can be 3.5μm, 4.0μm, 4.5μm, etc.

[0065] Subsequently, as Figure 11 As shown, a first sub-metal bonding layer is formed, and the first sub-metal bonding layer extends beyond the first insulating portion 402 away from the surface of the first chip 10.

[0066] Prior to this step, a physical vapor deposition technique can be used to sequentially form a metal adhesion layer, a diffusion barrier layer, and an electroplating seed layer; these layers are all continuous. The materials and thicknesses of the metal adhesion layer, diffusion barrier layer, and electroplating seed layer can be the same as in the aforementioned embodiments. In this step, an electroplating process can be used to form the first sub-metal bonding layer.

[0067] Subsequently, as Figure 12 As shown, the portion of the first sub-metal bonding layer that extends beyond the first insulating portion 402 is removed.

[0068] Chemical mechanical polishing (CMP) can be used to remove the portion of the first sub-metal bonding layer that extends beyond the first insulating portion 402. The chemical solution can be an acidic copper polishing slurry with hydrofluoric acid added. In this way, the first insulating portion 402 separates the first bonding portion 301 and the second bonding portion 302, preventing them from being electrically connected.

[0069] Subsequently, as Figure 13 As shown, the first insulating portion 402 is thinned so that the surface of the first insulating portion 402 away from the first chip 10 is lower than the surface of the first sub-metal bonding layer away from the first chip 10.

[0070] The first insulating portion 402 can be thinned by chemical mechanical polishing, so that the surface of the first insulating portion 402 away from the first chip 10 is recessed relative to the surfaces of the first bonding portion 301 and the second bonding portion 302 away from the first chip 10.

[0071] Further, prior to step S520, the fabrication method further includes: forming a second insulating portion 403 between the third bonding portion 301' and the adjacent fourth bonding portion 302', wherein the surface of the second insulating portion 403 away from the second chip 20 is lower than the surface of the second sub-metal bonding layer away from the second chip 20.

[0072] This step yields the following result: Figure 14 The structure shown. (As illustrated) Figure 14 As shown, the surface of the second insulating portion 403 away from the second chip 20 is recessed relative to the surfaces of the third bonding portion 301' and the fourth bonding portion 302' away from the second chip 20.

[0073] In this embodiment, before step S520, the Figure 13 and Figure 14 After aligning the structures shown, the following is obtained: Figure 15 The structure shown. (As illustrated) Figure 15 As shown, a cavity 401 is formed between the first insulating part 402 and the second insulating part 403. After step S520, the following can be obtained: Figure 2 The structure shown forms an isolation structure 40, which includes a first insulating portion 402, a second insulating portion 403, and a cavity 401 located between the first insulating portion 402 and the second insulating portion 403.

[0074] In one embodiment, such as Figure 9 and Figure 15 As shown, the second bonding portion 302 includes a plurality of first shielding rings 3021, each first shielding ring 3021 surrounding one of the first bonding portions 301; the fourth bonding portion 302' includes a plurality of second shielding rings 3021', each second shielding ring 3021' surrounding one of the third bonding portions 301'. After the first sub-metal bonding layer and the second sub-metal bonding layer are bonded, each first shielding ring 3021 and one second shielding ring 3021' are bonded to form a shielding structure, as shown. Figure 1 and Figure 2 As shown, the shielding structure 3041 is configured to connect to a constant electrical signal.

[0075] In one embodiment, the materials of the first and second sub-metal bonding layers are copper or copper-tin alloys. The thickness of the first sub-metal bonding layer ranges from 3 μm to 5 μm, for example, 3.5 μm, 4.0 μm, 4.5 μm, etc. When the materials of the first and second sub-metal bonding layers are copper, the bonding process pressure is 5 MPa to 10 MPa, the bonding temperature is 300°C to 350°C, and the bonding time is 30 min to 60 min, performed in a formic acid or acetic acid gas atmosphere. After bonding, annealing is performed at 350°C in a nitrogen atmosphere for 60 min. The final result is as follows: Figure 1 and Figure 2 The chip bonding structure.

[0076] The embodiments of the chip bonding structure preparation method provided in this application and the embodiments of the chip bonding structure belong to the same inventive concept. The relevant details and beneficial effects can be referred to each other and will not be repeated here.

[0077] It should be noted that the technical solutions or features described in the above embodiments can be combined or supplemented with each other without conflict. The scope of protection of this application is not limited to the precise structures described in the above embodiments and shown in the accompanying drawings; all modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A chip bonding structure, characterized in that, include: A metal bonding layer is located between a first electrode in a first chip and a second electrode in a second chip. The metal bonding layer includes at least one first bonding structure and a second bonding structure. The first bonding structure is electrically connected to a first electrode and a second electrode. An isolation structure is located between the first bonding structure and the adjacent second bonding structure; at least a portion of the height of the isolation structure is a cavity.

2. The chip bonding structure according to claim 1, characterized in that, The second bonding structure includes at least one shielding structure surrounding a first bonding structure; the shielding structure is configured to connect a constant electrical signal.

3. The chip bonding structure according to claim 1, characterized in that, The isolation structure is a cavity that penetrates the metal bonding layer.

4. The chip bonding structure according to claim 1, characterized in that, The isolation structure includes a first insulating portion and a cavity located on the side of the first insulating portion facing the second chip.

5. The chip bonding structure according to claim 4, characterized in that, The isolation structure further includes a second insulating portion, and the cavity is located between the first insulating portion and the second insulating portion.

6. A method for fabricating a chip bonding structure, characterized in that, include: A first sub-metal bonding layer is formed on a first chip, the first sub-metal bonding layer including at least one first bonding portion and a second bonding portion; the first bonding portion is electrically connected to a first electrode in the first chip; a second sub-metal bonding layer is formed on a second chip, the second sub-metal bonding layer including at least one third bonding portion and a fourth bonding portion; the third bonding portion is electrically connected to a second electrode in the second chip; A first sub-metal bonding layer and a second sub-metal bonding layer are bonded together, such that the first bonding portion is bonded to the third bonding portion to form a first bonding structure, and the second bonding portion is bonded to the fourth bonding portion to form a second bonding structure, thereby obtaining a metal bonding layer including the first bonding structure and the second bonding structure; an isolation structure is formed between the second bonding structure and the adjacent first bonding structure, and at least a portion of the height of the isolation structure is a cavity.

7. The preparation method according to claim 6, characterized in that, The first bonding portion and the adjacent second bonding portion are connected by a cavity penetrating the first sub-metal bonding layer, the third bonding portion and the adjacent fourth bonding portion are connected by a cavity penetrating the second sub-metal bonding layer, and the isolation structure is a cavity penetrating the metal bonding layer.

8. The preparation method according to claim 6, characterized in that, Before bonding the first sub-metal bonding layer and the second sub-metal bonding layer, the method for preparing the chip bonding structure further includes: forming a first insulating portion between the second bonding portion and the adjacent first bonding portion, wherein the surface of the first insulating portion away from the first chip is lower than the surface of the first sub-metal bonding layer away from the first chip; The isolation structure formed after bonding the first sub-metal bonding layer and the second sub-metal bonding layer includes a first insulating portion and a cavity located on the side of the first insulating portion facing the second chip.

9. The preparation method according to claim 8, characterized in that, Before bonding the first sub-metal bonding layer and the second sub-metal bonding layer, the method for fabricating the chip bonding structure further includes: forming a second insulating portion between the third bonding portion and the adjacent fourth bonding portion, wherein the surface of the second insulating portion away from the second chip is lower than the surface of the second sub-metal bonding layer away from the second chip; The isolation structure formed after bonding the first sub-metal bonding layer and the second sub-metal bonding layer includes a first insulating portion, a second insulating portion, and a cavity located between the first insulating portion and the second insulating portion.

10. The preparation method according to claim 6, characterized in that, The second bonding portion includes a plurality of first shielding rings, each first shielding ring surrounding one of the first bonding portions; the fourth bonding portion includes a plurality of second shielding rings, each second shielding ring surrounding one of the third bonding portions; after the first sub-metal bonding layer and the second sub-metal bonding layer are bonded, each first shielding ring is bonded to one of the second shielding rings to form a shielding structure; the shielding structure is configured to connect a constant electrical signal.

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