Chip package substrate, method for manufacturing the same, and chip package structure

Abstract

Embodiments of the present application provide a chip packaging carrier, a preparation method thereof and a chip packaging structure. The preparation method of the chip packaging carrier comprises: placing a chip packaging carrier product in a chemical plating liquid, focusing a pulsed laser to a position corresponding to a middle position of a depth direction of the through hole and making a distance between a focal spot and a seed layer less than or equal to a preset value, so as to form a seed additional part at the middle position of the depth direction of the through hole corresponding to the seed layer; performing electroplating by using a pulsed current to form a plugging part inside the seed additional part, so as to obtain two blind holes separated by the plugging part and the seed additional part; and forming a first conductive column core part and a second conductive column core part respectively located in one of the blind holes by using direct current electroplating. The present application can improve the preparation efficiency and the process yield.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and in particular to a chip packaging substrate, its preparation method and chip packaging structure. Background Technology

[0002] Glass-based chip packaging substrates are becoming increasingly popular as a strong contender for next-generation packaging substrates. However, in the process of industrialization, the metallization and filling of glass through-holes has always been a recognized technical bottleneck in the industry. Filling glass through-holes is difficult and yields low results, especially for high aspect ratio glass through-hole designs, which cannot meet mass production requirements. Summary of the Invention

[0003] This application provides a chip packaging substrate, its preparation method, and chip packaging structure, aiming to improve the via filling quality of high aspect ratio through holes to improve product manufacturing yield.

[0004] In a first aspect, some embodiments of this application provide a chip packaging carrier board, which includes a glass adapter plate, a first conductive post, a second conductive post, a first circuit structure, and a second circuit structure.

[0005] The glass adapter plate has a first surface and a second surface opposite to the first surface. A plurality of through holes are formed on the glass adapter plate, which penetrate the first surface and the second surface. The through holes include a first opening segment that penetrates the first surface and a second opening segment that penetrates the second surface, and the second opening segment communicates with the first opening segment.

[0006] The first conductive post is located within the first opening section. The first conductive post includes a first seed portion formed on the wall of the first opening section and a first conductive post core portion located inside the first seed portion.

[0007] The second conductive post is located within the second opening section. The second conductive post includes a second seed portion formed on the wall of the second opening section and a second conductive post core portion located inside the second seed portion.

[0008] The first circuit structure is located on one side of the glass adapter plate corresponding to the first surface.

[0009] The second circuit structure is located on one side of the glass adapter plate corresponding to the second surface.

[0010] In this configuration, the second seed portion is connected to the first seed portion, a seed attachment portion is formed at the connection between the second seed portion and the first seed portion, a sealing portion is formed on the inner side of the seed attachment portion, the first conductive pillar core portion contacts the seed attachment portion and the sealing portion located on the inner side of the seed attachment portion, the second conductive pillar core portion contacts the seed attachment portion and the sealing portion, the first circuit structure is electrically connected to the first conductive pillar, and the second circuit structure is electrically connected to the second conductive pillar.

[0011] In some embodiments of the chip packaging substrate, the size of the first opening segment gradually decreases in the direction from the first surface to the second surface, and the size of the second opening segment gradually decreases in the direction from the second surface to the first surface.

[0012] Preferably, the seed attachment protrudes relative to the first seed portion / second seed portion and the protrusion size is 2 micrometers to 12 micrometers.

[0013] Preferably, the projection of the seed attachment onto the first surface is annular.

[0014] In some embodiments, the chip packaging substrate further includes a seed layer, the seed layer including a first seed portion and a second seed portion, the seed layer including a first sublayer and a second sublayer located inside the first sublayer, the first sublayer being made of titanium, and the second sublayer being made of copper.

[0015] Preferably, the materials of the seed attachment, the first conductive post core, and the second conductive post core all include copper metal.

[0016] Preferably, the thickness of the first sublayer is 50-100 nanometers, and the thickness of the second sublayer is 100-200 nanometers.

[0017] Secondly, some embodiments of this application provide a method for preparing a chip packaging substrate, the method comprising:

[0018] A through hole is made in the glass adapter plate to connect the first surface and the second surface, thus forming the glass adapter plate; A seed layer is formed on the sidewall of the through hole; A chip packaging substrate is placed in a chemical plating liquid, and a pulsed laser is focused to a position corresponding to the middle position of the via depth direction, with the distance between the focal spot and the seed layer being less than or equal to a preset value, so as to form a seed attachment at the middle position of the seed layer corresponding to the via depth direction. Electroplating is performed using pulsed current to form a sealing portion inside the seed attachment, thereby obtaining two blind holes separated by the sealing portion and the seed attachment; A first conductive pillar core and a second conductive pillar core are respectively located within one of the blind holes by electroplating using direct current.

[0019] In some embodiments of the chip packaging substrate preparation method, when the distance between the focal spot and the seed layer is less than or equal to a preset value, the focal spot moves circumferentially in the through hole.

[0020] Preferably, when the distance between the focal spot and the seed layer is less than or equal to a preset value, the focal spot is moved circumferentially in the through hole.

[0021] Preferably, when the focal spot moves circumferentially in the through hole, the distance between the focal spot and the seed layer changes repeatedly within a preset range.

[0022] Preferably, the preset value ranges from 1 to 10 micrometers, and the preset range of the distance between the focal spot and the seed layer is 20% to 100% of the preset value.

[0023] In some embodiments of the chip packaging substrate preparation method, the step of opening a through hole through the first surface and the second surface on the glass transition substrate includes: opening a first opening segment from the first surface and opening a second opening segment from the second surface, and making the second opening segment communicate with the first opening segment to form the through hole, wherein the second opening segment and the first opening segment are connected at the middle position in the depth direction of the through hole.

[0024] In some embodiments of the chip packaging substrate preparation method, the step of opening a first opening segment from the first surface and opening a second opening segment from the second surface includes: using a pulsed laser to irradiate a glass transfer substrate from the first surface to modify the material portion corresponding to the first opening, and irradiating the glass transfer substrate from the second surface to modify the material portion corresponding to the second opening. The first opening segment and the second opening segment are obtained by removing the modified material using an etching solution; Preferably, the etching solution includes hydrofluoric acid.

[0025] In some embodiments of the chip packaging substrate preparation method, each liter of the chemical plating liquid comprises: 5-8 grams of copper sulfate pentahydrate (CuSO4·5H2O), 25-35 grams of sodium hypophosphite (NaH2PO2·H2O), 1-2 grams of nickel sulfate hexahydrate (NiSO4·6H2O), 15-25 grams of sodium citrate C6H5Na3O7·2H2O, 5-10 grams of sodium hydroxide (NaOH), and 1-5 milligrams of thiourea (CH4N2S). Preferably, the pH value of the electroless plating solution is 10-11; The pulsed laser is a nanosecond pulsed laser with a wavelength of 1064 nanometers or 532 nanometers.

[0026] In some embodiments of the chip packaging substrate preparation method, when electroplating with pulsed current to form a sealing portion inside the seed attachment portion, a first electroplating solution is used, wherein each liter of the first electroplating solution includes raw material: 100-290 g of CuSO4. 5H2O, 20-60 g of concentrated sulfuric acid (98%), 30-70 mg of potassium chloride / sodium chloride, 5-15 mL of leveling agent, 8-20 mL of inhibitor, 1-5 mL of brightener, and the remainder is deionized water.

[0027] Thirdly, some embodiments of this application provide a chip packaging structure, which includes the chip packaging carrier board described above, or includes a chip packaging carrier board prepared according to the method described above.

[0028] This application provides a chip packaging substrate, its preparation method, and chip packaging structure. After forming a seed layer on the sidewall of a via, a pulsed laser is focused to the middle position corresponding to the depth direction of the via, and the distance between the focal spot and the seed layer is less than or equal to a preset value, thereby forming a seed attachment at the middle position of the seed layer corresponding to the depth direction of the via. Then, a sealing part is formed inside the seed attachment by electroplating using a pulsed current, thereby obtaining two blind holes separated by the sealing part and the seed attachment. Subsequently, efficient electroplating can be performed to form a first conductive pillar core and a second conductive pillar core, which can effectively avoid defects such as filling voids and surface depressions during electroplating, thereby improving both preparation efficiency and process yield. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments or exemplary embodiments of this application, the drawings used in the description of the embodiments or exemplary embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is a side cross-sectional view of a chip packaging structure provided in some embodiments of this application; Figures 2-7 This application provides side cross-sectional schematic diagrams illustrating several process states in a method for fabricating a chip packaging carrier according to some embodiments of the present application. Figure 3 , Figure 5 and Figure 7 It includes enlarged views of local structures in the diagram. Figure 7This corresponds to a side cross-sectional view of the chip packaging carrier board; Figure 8 A top view schematic diagram of a partial structure in a chip packaging carrier provided for some embodiments of this application; Figure 9 This is a schematic diagram of the movement trajectory of a focal spot in the seed attachment stage of a chip packaging substrate preparation method provided in some embodiments of this application; Figure 10 This is a side cross-sectional view of a chip packaging carrier provided for some embodiments of this application, which includes enlarged views of some parts of the structure in the figure; Figure 11 This is a side cross-sectional view of another chip packaging structure provided in some embodiments of this application.

[0031] Explanation of reference numerals in the attached figures: Glass adapter plate 20, first surface 21, second surface 22, through hole 23, first opening section 231, second opening section 232. First conductive post 30, first conductive post core 31, second conductive post 32, second conductive post core 33, seed attachment part 34, sealing part 35. Seed layer 50, first seed section 51, second seed section 52, first daughter layer 53, second daughter layer 56. First wiring layer 60, first circuit structure layer 61, first circuit structure 611, first dielectric layer 62. Second wiring layer 70, second circuit structure layer 71, second circuit structure 711, second dielectric layer 72. Chip 91, package layer 92, protective layer 93, solder ball 96, focal spot movement trajectory GZ Detailed Implementation To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of this application.

[0032] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, this does not indicate any order, quantity, or importance, but is merely used to distinguish different components. These terms are used only to distinguish one element from another. For example, without departing from the scope of this application, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. Words such as “comprising” or “including” mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, without excluding other elements or objects.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0034] The following is in conjunction with the attached Figures 1-10 The technical solution of this application will be described in detail.

[0035] In the field of chip packaging substrate fabrication technology, through-holes in glass adapters are prone to problems such as voids during the filling process, especially for high aspect ratio through-holes that meet the needs of high-density packaging. The process yield is low and it is difficult to support the requirements of large-scale mass production.

[0036] To address at least one of the above problems, in a first aspect, some embodiments of this application provide a chip packaging substrate, please refer to... Figures 2-7 and Figure 10 The chip packaging substrate includes: The glass transition plate 20 has a first surface 21 and a second surface 22 opposite to the first surface 21. A plurality of through holes 23 are formed on the glass transition plate 20, which penetrate the first surface 21 and the second surface 22. The through holes 23 include a first opening section 231 that penetrates the first surface 21 and a second opening section 232 that penetrates the second surface 22. The second opening section 232 communicates with the first opening section 231. The first conductive post 30 is located inside the first opening section 231. The first conductive post 30 includes a first seed part 51 formed on the hole wall of the first opening section 231 and a first conductive post core part 31 located inside the first seed part 51. The second conductive post 32 is located inside the second opening section 232. The second conductive post 32 includes a second seed portion 52 formed on the hole wall of the second opening section 232 and a second conductive post core portion 33 located inside the second seed portion 52. The first circuit structure 611 is located on one side of the glass transition plate 20 corresponding to the first surface 21; and, The second circuit structure 711 is located on one side of the corresponding second surface 22 of the glass adapter plate 20; The second seed section 52 is connected to the first seed section 51. A seed attachment section 34 is formed at the connection between the second seed section 52 and the first seed section 51. A sealing section 35 is formed inside the seed attachment section 34. The first conductive post core section 31 is in contact with the seed attachment section 34 and the sealing section 35 located inside the seed attachment section 34. The second conductive post core section 33 is in contact with the seed attachment section 34 and the sealing section 35. The first circuit structure 611 is electrically connected to the first conductive post 30. The second circuit structure 711 is electrically connected to the second conductive post 32.

[0037] The chip packaging substrate provided in this application embodiment has a seed attachment 34 formed at the connection between the second seed portion 52 and the first seed portion 51, and a sealing portion 35 formed inside the seed attachment 34. The first conductive pillar core portion 31 contacts the seed attachment portion 34 and the sealing portion 35 located inside the seed attachment portion 34, and the second conductive pillar core portion 33 contacts the seed attachment portion 34 and the sealing portion 35. Thus, during the product manufacturing process, the through hole 23 structure on the glass adapter plate 20 with a large aspect ratio and no bottom wall can be divided into two blind hole structures with a small aspect ratio and bottom wall. In this way, the holes can be filled in the blind hole filling method, which not only has high filling efficiency, but also effectively avoids problems such as filling voids and surface depressions. This can achieve better dense filling inside the through hole 23, improve the overall manufacturing yield, and adapt to the technology development trend towards high-density packaging.

[0038] It should be noted that, please refer to Figure 1 , Figure 7 , Figure 10 and Figure 11 A first wiring layer 60 may be formed on one side of the glass transition plate 20 corresponding to the first surface 21. The first wiring layer 60 includes at least one first circuit structure layer 61 and at least one first dielectric layer 62 disposed on the glass transition plate 20. The first circuit structure layer 61 includes a plurality of first circuit structures 611. A second wiring layer 70 may be formed on one side of the glass transition plate 20 corresponding to the second surface 22. The second wiring layer 70 includes at least one second circuit structure layer 71 and at least one second dielectric layer 72 disposed on the glass transition plate 20. The second circuit structure layer 71 includes a plurality of second circuit structures 711.

[0039] It should be noted that the corresponding first seed part 51 and second seed part 52 constitute the seed layer 50.

[0040] In some embodiments of this application, the chip packaging carrier board is provided. Please refer to... Figures 1-7 and Figure 11The size of the first opening segment 231 gradually decreases in the direction from the first surface 21 to the second surface 22, and the size of the second opening segment 232 gradually decreases in the direction from the second surface 22 to the first surface 21.

[0041] The chip packaging substrate provided in this application embodiment has a first opening segment 231 whose size gradually decreases in the direction from the first surface 21 to the second surface 22, and a second opening segment 232 whose size gradually decreases in the direction from the second surface 22 to the first surface 21. On the one hand, the first opening segment 231 and the second opening segment 232 are easier to manufacture. On the other hand, it makes it easier for the seed attachment 34 and the sealing part 35 to seal the through hole 23 at the connection position between the second opening segment 232 and the first opening segment 231. Thus, in the subsequent corresponding manufacturing steps, the first conductive pillar core 31 and the second conductive pillar core 33 can be formed by blind hole filling. In this way, not only is the filling efficiency high, but problems such as filling voids and surface depressions can also be effectively avoided, thereby achieving better dense filling inside the through hole 23 and improving the overall manufacturing yield.

[0042] Please refer to Figure 8 In some embodiments of this application, the chip packaging substrate provided has a seed attachment 34 that protrudes relative to the first seed portion 51 / second seed portion 52 and the protrusion size TD is 2 micrometers to 12 micrometers.

[0043] Please refer to Figure 8 In some embodiments of this application, the seed attachment 34 is projected in a ring shape onto the first surface 21 in the chip packaging substrate.

[0044] The chip packaging substrate provided in this application embodiment has a 2-12 micrometer protrusion formed by the seed attachment 34 relative to the first seed 51 / second seed 52. This protrusion size of the seed attachment 34 is suitable for formation by laser-assisted chemical plating and is also conducive to the subsequent formation of the sealing part 35 by electroplating, so as to seal the through hole 23 and divide the through hole 23 into two blind holes.

[0045] In some embodiments of this application, the chip packaging carrier board is provided. Please refer to... Figures 3-6 The chip packaging substrate includes a seed layer 50, which includes a first seed portion 51 and a second seed portion 52. The seed layer 50 also includes a first sublayer 53 and a second sublayer 56 located inside the first sublayer 53. The material of the first sublayer 53 includes titanium, and the material of the second sublayer 56 includes copper.

[0046] The chip packaging substrate provided in this embodiment includes a seed layer 50 comprising a first sub-layer 53 and a second sub-layer 56 located inside the first sub-layer 53. The first sub-layer 53 is made of titanium, and the second sub-layer 56 is made of copper. The titanium first sub-layer 53 has strong adhesion to the glass adapter plate 20 and can suppress the propagation of microcracks on the wall of the via 23. The copper second sub-layer 56 can better bond with the subsequently formed first conductive pillar core 31.

[0047] In some embodiments of this application, the seed attachment 34, the first conductive pillar core 31, and the second conductive pillar core 33 are all made of copper metal.

[0048] In some embodiments of this application, the thickness of the first sublayer 53 is 50-100 nanometers, and the thickness of the second sublayer 56 is 100-200 nanometers.

[0049] The chip packaging substrate provided in this application embodiment has copper metal as the material of the seed attachment 34, the first conductive pillar core 31 and the second conductive pillar core 33. The second sublayer 56 with copper metal material has stronger bonding force and better conductivity.

[0050] Secondly, some embodiments of this application provide a method for preparing a chip packaging substrate, please refer to... Figures 2-9 The methods for preparing chip packaging substrates include: A through hole 23 is made in the glass transition plate to pass through the first surface 21 and the second surface 22, forming a glass transition plate 20; A seed layer 50 is formed on the sidewall of the through hole 23; The chip packaging substrate is placed in a chemical plating liquid, and a pulsed laser is focused to the middle position corresponding to the depth direction of the via 23, and the distance between the focal spot and the seed layer 50 is less than or equal to a preset value, so as to form a seed attachment 34 at the middle position of the seed layer 50 corresponding to the depth direction of the via 23. Electroplating is performed using pulsed current to form a sealing portion 35 inside the seed attachment portion 34, thereby obtaining two blind holes separated by the sealing portion 35 and the seed attachment portion 34. A first conductive core portion 31 and a second conductive core portion 33 are respectively located in a blind hole by electroplating using direct current.

[0051] The chip packaging substrate preparation method provided in this application embodiment involves forming a seed layer 50 on the sidewall of the through-hole 23, then placing the chip packaging substrate in a chemical plating liquid, focusing a pulsed laser at the middle position corresponding to the depth direction of the through-hole 23, and positioning the focal spot at a distance from the seed layer 50 less than or equal to a preset value, to form a seed attachment 34 at the middle position of the seed layer 50 corresponding to the depth direction of the through-hole 23; then using pulsed current electroplating to form a sealing portion 35 inside the seed attachment 34, thereby obtaining a substrate consisting of the sealing portion 35 and the seed layer 23. The additional part 34 separates two blind holes; this allows for efficient electroplating (after forming the blind holes, DC current electroplating is used to fill the blind holes from both sides to form the first conductive pillar core 31 and the second conductive pillar core 33, which can improve electroplating efficiency). The formation of the first conductive pillar core 31 and the second conductive pillar core 33 can effectively avoid defects such as filling voids and surface depressions during electroplating (using pulsed current electroplating to form the sealing part 35 can effectively avoid sealing the opening of the through hole 23 when the middle is not completely filled, thus avoiding the formation of voids), thereby improving the process yield. Among them, by focusing the pulsed laser to the middle position corresponding to the depth direction of the through hole 23, the electroless plating liquid can be locally heated to activate the endothermic electroless plating reaction, thereby significantly improving the local deposition rate and effectively alleviating the problem of difficult component transfer corresponding to the seed layer 50 of the electroless plating liquid in deep holes.

[0052] It should be noted that the seed layer 50 can be formed by physical vapor deposition (PVD) on the sidewall of the TGV.

[0053] In the chip packaging substrate fabrication method provided in some embodiments of this application, please refer to... Figure 9 When the focal spot is positioned at a distance of 50 from the seed layer less than or equal to a preset value, the focal spot moves circumferentially within the through hole 23.

[0054] Preferably, when the focal spot moves circumferentially within the through-hole 23, the distance between the focal spot and the seed layer 50 varies repeatedly within a preset range (e.g., the movement trajectory of the focal spot can be a polygonal star shape, please refer to...). Figure 9 ).

[0055] Preferably, the preset value ranges from 1 to 10 micrometers (specifically, it can be 1 micrometer, 3 micrometers, 6 micrometers, or 10 micrometers).

[0056] Preferably, the preset value ranges from 1 to 10 micrometers (specifically, it can be 1 micrometer, 3 micrometers, 6 micrometers or 10 micrometers), and the preset variation range of the distance between the focal spot and the seed layer is 20%-100% of the preset value (e.g., if the preset value is 5 micrometers, the corresponding preset variation range is 1 micrometer-5 micrometers).

[0057] The chip packaging substrate preparation method provided in this application embodiment moves the focal spot circumferentially in the through hole 23, or further, when moving circumferentially in the through hole 23, the distance between the focal spot and the seed layer 50 changes repeatedly within a preset range, which can better induce the material components corresponding to the seed attachment 34 in the chemical plating liquid to gather on the seed layer 50 to form the seed attachment 34, thereby improving the formation efficiency and quality of the seed attachment 34.

[0058] In the chip packaging substrate fabrication method provided in some embodiments of this application, please refer to... Figure 2 The through hole 23 formed on the glass transition plate, which connects the first surface 21 and the second surface 22, includes: forming a first opening segment 231 from the first surface 21 and a second opening segment 232 from the second surface 22, and connecting the second opening segment 232 with the first opening segment 231 to form the through hole 23. The second opening segment 232 and the first opening segment 231 are connected at the middle position in the depth direction of the through hole 23.

[0059] The chip packaging substrate preparation method provided in this application provides a method for preparing a through hole 23 by dividing the through hole 23 into a first opening segment 231 formed from the first surface 21 and a second opening segment 232 formed from the second surface 22, and connecting the second opening segment 232 with the first opening segment 231 to form a through hole 23. This method has high opening process efficiency and makes it easy to form a waisted through hole 23 structure that is thick at both ends and thin in the middle. The waisted through hole 23 structure makes it easier to seal the through hole 23 at the middle position in the depth direction using the seed attachment part 34 and the sealing part 35, thereby forming two blind holes.

[0060] In the chip packaging substrate preparation method provided in some embodiments of this application, the method of opening a first opening segment 231 from the first surface 21 and opening a second opening segment 232 from the second surface 22 includes: using a pulsed laser to irradiate the glass transfer substrate from the first surface 21 to modify the material corresponding to the first opening, and irradiating the glass transfer substrate from the second surface 22 to modify the material corresponding to the second opening. The modified material is removed using an etching solution to obtain the first opening section 231 and the second opening section 232.

[0061] Preferably, the etching solution includes hydrofluoric acid.

[0062] The chip packaging substrate preparation method provided in this application embodiment can simultaneously open a first opening segment 231 from the first surface 21 and a second opening segment 232 from the second surface 22 by laser-induced modification and etching solution to remove the modified material. Accordingly, the opening efficiency is high, and it is also easy to form a waisted through-hole 23 structure that is thick at both ends and thin in the middle. The waisted through-hole 23 structure is easier to seal at the middle position of the depth direction of the through-hole 23 using the seed attachment part 34 and the sealing part 35, thereby forming two blind holes.

[0063] It should be noted that the glass via 23 (TGV) was fabricated using a laser-induced deep etching process. The laser frequency was 100kHz-500kHz, the laser single pulse energy was 10μJ-15μJ, the via diameter was 50μm-100μm, the laser pulse repetition frequency was 5-10kHz, and the scanning speed was 8mm / s-15mm / s. The laser-modified glass was then immersed in a specific etching solution to remove the modified glass. The etching solution could be hydrofluoric acid (HF).

[0064] In some embodiments of this application, the chip packaging substrate preparation method uses laser-assisted chemical plating to form the seed attachment 34. The chemical plating liquid used per liter of laser-assisted chemical plating includes: 5-8 grams (specifically 5 grams, 6 grams, 7 grams, or 8 grams) of copper sulfate pentahydrate (CuSO4·5H2O), 25-35 grams (specifically 25 grams, 28 grams, 31 grams, or 35 grams) of sodium hypophosphite (NaH2PO2·H2O), and 1-2 grams (specifically...) of sodium hypophosphite per liter of liquid. The following ingredients can be added: 1 gram, 1.3 grams, 1.6 grams, or 2 grams) of nickel sulfate hexahydrate (NiSO4·6H2O), 15-25 grams (specifically, 15 grams, 18 grams, 21 grams, or 25 grams) of sodium citrate (C6H5Na3O7·2H2O), 5-10 grams (specifically, 5 grams, 6 grams, 8 grams, or 10 grams) of sodium hydroxide (NaOH), 1-5 milligrams (specifically, 1 gram, 2 grams, 3 grams, 4 grams, or 5 grams) of thiourea (CH4N2S).

[0065] Preferably, the pH value of the chemical plating liquid is 10-11 (specifically, it can be 10, 10.5 or 11).

[0066] It should be noted that in the process of forming the seed appendage 34, sodium hypophosphite is used as a reducing agent, nickel sulfate hexahydrate is used as a catalyst, sodium citrate is used as a complexing agent, sodium hydroxide is used as a pH adjuster, and thiourea is used as a stabilizer.

[0067] In the chip packaging substrate preparation method provided in some embodiments of this application, the pulsed laser used to form the seed attachment 34 by laser-assisted chemical plating is a nanosecond pulsed laser with a wavelength of 1064 nanometers (nanometers) or 532 nanometers.

[0068] The chip packaging substrate fabrication method provided in this application, by employing the aforementioned chemical plating liquid and using a pulsed laser to form a seed attachment 34, creates initial conditions for the subsequent formation of the sealing portion 35 using electroplating. During laser-assisted chemical plating, the pulsed laser (such as a nanosecond laser) provides activation energy for the endothermic chemical plating reaction, resulting in high energy utilization efficiency and significantly improving the local deposition rate. Furthermore, using a pulsed laser avoids the runaway thermal accumulation caused by continuous heating, and the reaction temperature can be precisely controlled by adjusting the repetition frequency and single-pulse energy.

[0069] In the chip packaging substrate fabrication method provided in some embodiments of this application, please refer to... Figure 5 The first electroplating solution used in the process of forming a sealing portion inside the seed attachment by using pulsed current electroplating comprises, per liter, 100-290 g (specifically, 100 g, 150 g, 200 g, 250 g, or 290 g) of copper sulfate pentahydrate (CuSO4). The mixture consists of 5H2O, 20-60 g (specifically 20 g, 30 g, 40 g, 50 g, or 60 g) of 98% sulfuric acid, 30-70 mg (specifically 30 mg, 40 mg, 50 mg, 60 mg, or 70 mg) of potassium chloride / sodium chloride, 5-15 mL (specifically 5 mL, 8 mL, 12 mL, or 15 mL) of leveling agent, 8-20 mL (specifically 8 mL, 12 mL, 15 mL, or 20 mL) of inhibitor, 1-5 mL (specifically 1 mL, 2 mL, 3 mL, 4 mL, or 5 mL) of accelerator, and the remainder being deionized water.

[0070] Specifically, the leveling agent can be a polymer containing an azo bond + quaternary ammonium cationic structure (such as pyridine quaternary ammonium salt derivatives); the inhibitor can include at least one of PEG-4000 (polyethylene glycol with an average molecular weight of 3800-4200, preferably 4000), PEG-20000 (polyethylene glycol with an average molecular weight of 19000-21000, preferably 20000), polyoxyethylene polyoxypropylene triblock copolymer with an average molecular weight of 2900-3100 (preferably 3000), and PPG-8000 (polypropylene glycol with an average molecular weight of 7500-8500, preferably 8000); the accelerator can include at least one of sodium polydithiopropane sulfonate (SPS), sodium 3-mercaptopropane sulfonate (MPS), and sodium thiazolinyl dithiopropane sulfonate.

[0071] The chip packaging substrate preparation method provided in this application embodiment forms a blind via and then forms a sealing part 35 by electroplating based on the above-mentioned components using a pulsed current. Before the complete sealing part 35 is formed, the opening of the through hole 23 can be effectively sealed, thereby avoiding the formation of the first conductive pillar 30 / second conductive pillar 32 with voids, which can improve the process yield.

[0072] This application provides a specific embodiment of a method for preparing a chip packaging carrier, the method comprising: A through-hole 23 penetrating the first surface 21 and the second surface 22 is formed on the glass adapter plate 20 by using pulsed laser-induced deep etching. The laser frequency can be 300 kHz, the single pulse energy is 10 microjoules (μJ), and the diameter of the through-hole 23 is 60 micrometers.

[0073] A seed layer 50 is formed on the sidewall of the via 23 using physical vapor deposition. The seed layer 50 includes a first sublayer 53 made of titanium and a second sublayer 56 made of copper. The thickness of the first sublayer 53 is 60 nanometers and the thickness of the second sublayer 56 is 150 nanometers.

[0074] The chip packaging substrate is placed in a chemical plating liquid. A pulsed laser is focused to the middle position corresponding to the depth direction of the via 23, and the focal spot is positioned at a distance from the seed layer 50 less than or equal to a preset value, so as to form a seed attachment 34 at the middle position of the seed layer 50 corresponding to the depth direction of the via 23. The pulsed laser is a nano-pulse laser with a wavelength of 1064 nanometers, a repetition frequency of 7 kHz, and the focal point of the pulsed laser moves in a circle at a distance of 5 micrometers from the seed layer 50.

[0075] Electroplating is performed using a pulsed current and a first electroplating solution to form a sealing portion 35 inside the seed attachment portion 34, thereby obtaining two blind holes separated by the sealing portion 35 and the seed attachment portion 34. The forward pulse current density can be 0.5-1.5 ASD, the reverse pulse current density can be 2.5-6 ASD, the pulse frequency is 50-1000 Hz, the forward time within one pulse is 0.1-0.16 seconds, and the reverse time is 0.02-0.04 seconds. Each liter of the first electroplating solution includes the following raw materials: 150 grams of copper sulfate pentahydrate (CuSO4). 5H2O), 30g of 98% sulfuric acid, 50mg of potassium chloride / sodium chloride, 10ml of leveling agent (pyridine quaternary ammonium salt derivative), 12ml of inhibitor (polyethylene glycol with an average molecular weight of 3800-4200), 3ml of accelerator (sodium polydithiopropane sulfonate, SPS), and the remainder is deionized water.

[0076] A first conductive core portion 31 and a second conductive core portion 33 are respectively located in a blind hole by electroplating using direct current.

[0077] The chip packaging substrate fabrication method provided in this application embodiment forms a seed layer 50 on the sidewall of the via 23. When forming the seed attachment 34 using pulsed laser focusing induction, local heating of the electroless plating liquid activates the endothermic electroless plating reaction, significantly improving the local deposition rate. When forming the sealing portion 35 using pulsed current electroplating, the pulsed current effectively prevents the opening of the via 23 from being sealed due to incomplete sealing of the sealing portion 35, thus avoiding voids. After forming blind vias, direct current electroplating is used to fill the blind vias from both sides to form the first conductive pillar core 31 and the second conductive pillar core 33, improving electroplating efficiency. Therefore, the chip packaging substrate fabrication method provided in this application embodiment achieves both high yield and high efficiency.

[0078] It should be noted that the seed layer 50 can be formed by physical vapor deposition (PVD) on the sidewall of the TGV.

[0079] Thirdly, some embodiments of this application provide a chip packaging structure, please refer to... Figure 1 and Figure 10 The chip packaging structure includes the chip packaging substrate described above, or a chip packaging substrate prepared according to the method described above. The chip packaging structure also includes at least one chip 91, a packaging layer 92 covering the chip 91, a protective layer 93, and a plurality of solder balls 96 for electrical connection to an external circuit board structure.

[0080] It should be noted that the different technical features in the aforementioned different embodiments can all be used as features in the same embodiment scheme if there is no conflict.

[0081] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0082] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0083] The above embodiments merely illustrate several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A chip packaging carrier board, characterized in that, The chip packaging carrier includes: A glass adapter plate has a first surface and a second surface opposite to the first surface. A plurality of through holes are formed on the glass adapter plate, which penetrate the first surface and the second surface. The through holes include a first opening segment that penetrates the first surface and a second opening segment that penetrates the second surface, and the second opening segment communicates with the first opening segment. The first conductive post is located within the first opening section. The first conductive post includes a first seed portion formed on the wall of the first opening section and a first conductive post core portion located inside the first seed portion. The second conductive post is located within the second opening section. The second conductive post includes a second seed portion formed on the wall of the second opening section and a second conductive post core portion located inside the second seed portion. A first circuit structure is located on one side of the glass transition plate corresponding to the first surface; and, The second circuit structure is located on one side of the glass adapter plate corresponding to the second surface; In this configuration, the second seed portion is connected to the first seed portion, a seed attachment portion is formed at the connection between the second seed portion and the first seed portion, a sealing portion is formed on the inner side of the seed attachment portion, the first conductive pillar core portion contacts the seed attachment portion and the sealing portion located on the inner side of the seed attachment portion, the second conductive pillar core portion contacts the seed attachment portion and the sealing portion, the first circuit structure is electrically connected to the first conductive pillar, and the second circuit structure is electrically connected to the second conductive pillar.

2. The chip packaging carrier board according to claim 1, characterized in that, The size of the first opening segment gradually decreases in the direction from the first surface to the second surface, and the size of the second opening segment gradually decreases in the direction from the second surface to the first surface; Preferably, the seed attachment protrudes relative to the first seed portion / second seed portion and the protrusion size is 2 micrometers-12 micrometers; Preferably, the projection of the seed attachment onto the first surface is annular.

3. The chip packaging carrier board according to claim 1, characterized in that, It includes a seed layer, the seed layer includes a first seed portion and a second seed portion, the seed layer includes a first sub-layer and a second sub-layer located inside the first sub-layer, the material of the first sub-layer includes titanium metal, and the material of the second sub-layer includes copper metal; Preferably, the materials of the seed attachment, the first conductive post core, and the second conductive post core all include copper metal; Preferably, the thickness of the first sublayer is 50-100 nanometers, and the thickness of the second sublayer is 100-200 nanometers.

4. A method for preparing a chip packaging substrate, characterized in that, include: A through hole is made in the glass adapter plate to connect the first surface and the second surface, thus forming the glass adapter plate; A seed layer is formed on the sidewall of the through hole; A chip packaging substrate is placed in a chemical plating liquid, and a pulsed laser is focused to a position corresponding to the middle position of the via depth direction, with the distance between the focal spot and the seed layer being less than or equal to a preset value, so as to form a seed attachment at the middle position of the seed layer corresponding to the via depth direction. Electroplating is performed using pulsed current to form a sealing portion inside the seed attachment, thereby obtaining two blind holes separated by the sealing portion and the seed attachment; A first conductive pillar core and a second conductive pillar core are respectively located in one of the blind holes by electroplating using direct current.

5. The method for preparing a chip packaging substrate according to claim 4, characterized in that, When the distance between the focal spot and the seed layer is less than or equal to a preset value, the focal spot is moved circumferentially in the through hole; Preferably, when the focal spot moves circumferentially in the through hole, the distance between the focal spot and the seed layer changes repeatedly within a preset range; Preferably, the preset value ranges from 1 to 10 micrometers, and the preset variation range of the distance between the focal spot and the seed layer is 20% to 100% of the preset value.

6. The method for preparing a chip packaging substrate according to claim 4, characterized in that, The method of opening a through hole in the glass transition plate that penetrates the first surface and the second surface includes: opening a first opening segment from the first surface and opening a second opening segment from the second surface, and connecting the second opening segment with the first opening segment to form the through hole, wherein the second opening segment and the first opening segment are connected at the middle position in the depth direction of the through hole.

7. The method for preparing a chip packaging substrate according to claim 6, characterized in that, The process of creating a first opening segment from the first surface and a second opening segment from the second surface includes: using a pulsed laser to irradiate the glass transfer plate from the first surface to modify the material portion corresponding to the first opening, and irradiating the glass transfer plate from the second surface to modify the material portion corresponding to the second opening. The first opening segment and the second opening segment are obtained by removing the modified material using an etching solution; Preferably, the etching solution includes hydrofluoric acid.

8. The method for preparing the chip packaging substrate according to claim 6, characterized in that, Each liter of the electroless plating liquid comprises: 5-8 grams of copper sulfate pentahydrate (CuSO4·5H2O), 25-35 grams of sodium hypophosphite (NaH2PO2·H2O), 1-2 grams of nickel sulfate hexahydrate (NiSO4·6H2O), 15-25 grams of sodium citrate (C6H5Na3O7·2H2O), 5-10 grams of sodium hydroxide (NaOH), and 1-5 milligrams of thiourea (CH4N2S). Preferably, the pH value of the electroless plating solution is 10-11; The pulsed laser is a nanosecond pulsed laser with a wavelength of 1064 nanometers or 532 nanometers.

9. The method for preparing the chip packaging substrate according to claim 6, characterized in that, When electroplating with pulsed current to form a sealing portion inside the seed attachment portion, a first electroplating solution is used, and each liter of the first electroplating solution includes raw material: 100-290 g of CuSO4. 5H2O, 20-60 g of concentrated sulfuric acid (98%), 30-70 mg of potassium chloride / sodium chloride, 5-15 mL of leveling agent, 8-20 mL of inhibitor, 1-5 mL of brightener, and the remainder is deionized water.

10. A chip packaging structure, characterized in that, It includes the chip packaging substrate according to any one of claims 1-3, or the chip packaging substrate prepared by the method according to any one of claims 4-9.

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