A chip packaging structure, wafer level chip packaging structure and preparation method

Abstract

The application provides a chip packaging structure, a wafer-level chip packaging structure and a preparation method, and relates to the field of advanced packaging technology. The chip packaging structure comprises a chip structure and a cover plate. The chip structure has a first bonding ring and a second bonding ring. The sensitive structure is arranged on the inner side of the first bonding ring. The cover plate has a third bonding ring and a fourth bonding ring. The first bonding ring is directly bonded to the third bonding ring, and the second bonding ring is directly bonded to the fourth bonding ring. The wafer-level chip packaging structure comprises at least one chip packaging structure. The preparation method is used for preparing the chip packaging structure or the wafer-level chip packaging structure. The application forms an atomic-level contact at the bonding interface between the chip structure and the cover plate, and forms a sealed cavity containing the sensitive structure between the chip structure and the cover plate. The sealing stability of the chip packaging structure is significantly improved, and the air tightness and long-term reliability of the MEMS device are enhanced.

Description

Technical Field

[0001] This application relates to the field of advanced semiconductor packaging technology, and in particular to a chip packaging structure, a wafer-level chip packaging structure, and a fabrication method thereof. Background Technology

[0002] Micro-Electro-Mechanical Systems (MEMS) devices contain a large number of movable microstructures (such as cantilever beams, comb electrodes, micromirrors, etc.). These structures are extremely sensitive to the cleanliness of the working environment. Micron-sized or even submicron-sized dust particles can cause device jamming or functional failure. Therefore, hermetic packaging is a necessary means to ensure the long-term reliability of MEMS devices.

[0003] Existing packaging technologies typically achieve hermetic protection by bonding caps or sealing caps to the chip surface. However, such bonded sealing structures are unstable, resulting in low reliability of packaged MEMS devices. Summary of the Invention

[0004] The problem to be solved by this application is to provide a chip packaging structure, a wafer-level chip packaging structure and a preparation method, optimize heterogeneous integration packaging process and improve the packaging quality of the packaging structure.

[0005] To address the above problems, this application provides a chip packaging structure, including:

[0006] A chip structure having a first surface and a second surface disposed opposite to each other, the first surface having a first bonding ring and a second bonding ring, the second bonding ring surrounding the outside of the first bonding ring, the chip structure also having a sensitive structure disposed on the side of the chip structure near the first surface and located inside the first bonding ring; A cover plate has a third surface and a fourth surface disposed opposite to each other. The third surface has a third bonding ring and a fourth bonding ring. The fourth bonding ring surrounds the outside of the third bonding ring. The cover plate is disposed on the first surface of the chip structure. The first bonding ring and the third bonding ring are correspondingly bonded and connected. The second bonding ring and the fourth bonding ring are bonded and connected, so that the cover plate and the chip structure form a sealed cavity for accommodating the sensitive structure inside the first bonding ring and the third bonding ring.

[0007] In an optional embodiment, the first bonding ring and the third bonding ring comprise metal bonding rings, and the second bonding ring and the fourth bonding ring comprise insulating dielectric bonding rings; Alternatively, the first bonding ring, the third bonding ring, the second bonding ring, and the fourth bonding ring may all be metal bonding rings; Alternatively, the first bonding ring, the third bonding ring, the second bonding ring, and the fourth bonding ring may all be insulating dielectric bonding rings.

[0008] In one embodiment, the metal bonding ring includes a copper bonding ring, a gold bonding ring, a nickel bonding ring, or an aluminum bonding ring; The insulating dielectric bonding ring includes a silicon oxide bonding ring, a silicon nitride bonding ring, a silicon carbonitride bonding ring, or an organic insulating dielectric bonding ring.

[0009] In an optional embodiment, the organic insulating dielectric bonding ring includes a polyimide bonding ring, a photosensitive polyimide bonding ring, or a benzocyclobutene bonding ring.

[0010] In an optional embodiment, the surface of the first bonding ring away from the first surface is coplanar with the surface of the second bonding ring away from the first surface, and the surface of the third bonding ring away from the third surface is coplanar with the surface of the fourth bonding ring away from the third surface.

[0011] In an optional embodiment, the third surface of the cover plate is further provided with a groove, the groove being located inside the third bonding ring; When the cover plate is placed on the first surface of the chip structure, the groove is provided corresponding to the sensitive structure of the chip structure, and the sidewall and bottom wall of the groove form part of the sidewall of the sealing cavity.

[0012] In an optional embodiment, the sealed cavity is in a vacuum state, or the sealed cavity is filled with an inert gas.

[0013] In an optional embodiment, there is no gap between the first bonding ring and the second bonding ring, and there is no gap between the third bonding ring and the fourth bonding ring.

[0014] In an optional embodiment, the first bonding ring and the second bonding ring are spaced apart, and the third bonding ring and the fourth bonding ring are spaced apart.

[0015] In an optional embodiment, the first bonding ring and the second bonding ring are concentric; The third bonding ring and the fourth bonding ring are concentric, and the third bonding ring and the fourth bonding ring are respectively arranged to correspond to the first bonding ring and the second bonding ring.

[0016] In an optional embodiment, the first bonding ring has multiple rings and / or the second bonding ring has multiple rings, with the first bonding ring and the second bonding ring arranged alternately in a radial direction; The third bonding ring has multiple rings and / or the fourth bonding ring has multiple rings, with the third bonding ring and the fourth bonding ring arranged alternately in a radial direction.

[0017] In an optional embodiment, there are multiple first bonding rings and multiple second bonding rings, and the number of first bonding rings and second bonding rings is the same, and each has 2 to 4 rings; The third bonding ring and the fourth bonding ring are each multiple, and the number of the third bonding ring and the fourth bonding ring are the same, and are 2 to 4 respectively.

[0018] In an optional embodiment, a redistribution layer is provided on the second surface of the chip structure; The chip structure has a second conductive connection structure, and the two ends of the second conductive connection structure are conductively connected to the sensitive structure and the redistribution layer of the second surface of the chip structure, respectively.

[0019] In an optional embodiment, the system further includes an adapter board having a third conductive connection structure that penetrates the upper and lower surfaces of the adapter board, which are disposed opposite each other. The adapter board is disposed on the first surface of the chip structure, and the lower surface of the adapter board is connected to the first surface of the chip structure. The adapter board is located outside the first bonding ring and the second bonding ring. The chip structure has a fourth conductive connection structure, and the two ends of the fourth conductive connection structure are conductively connected to the sensitive structure and the third conductive connection structure of the adapter board, respectively.

[0020] In an optional embodiment, the sensitive structure includes a movable microstructure or a photosensitive structure; The cover plate includes a glass cover plate or a silicon cover plate. When the sensitive structure includes a photosensitive structure, the cover plate includes a transparent glass cover plate.

[0021] In an optional embodiment, the sensitive structure includes a photosensitive structure; The sensitive structure has a transparent insulating dielectric layer on the side surface near the cover plate.

[0022] In an optional embodiment, the sensitive structure includes a plurality of sensitive structures, with a spacing between adjacent sensitive structures, and a set of first bonding rings and second bonding rings respectively disposed on the outer periphery of each sensitive structure; The cover plate has multiple sets of third and fourth bonding rings corresponding to the first and second bonding rings located on the outer periphery of each of the sensitive structures.

[0023] In an optional embodiment, the sensitive structure includes a plurality of sensitive structures, with a spacing between adjacent sensitive structures, and a set of first bonding rings and second bonding rings are disposed on the outer periphery of each sensitive structure; The cover plate includes a plurality of covers, each cover plate having a set of third and fourth bonding rings corresponding to the first bonding ring and the second bonding ring located on the outer periphery of each of the sensitive structures; Alternatively, the cover plate may include at least one, wherein at least one cover plate has at least two sets of third and fourth bonding rings corresponding to the first and second bonding rings located on the periphery of the at least two sets of the sensitive structures.

[0024] This application also provides a method for fabricating a chip packaging structure, including the following steps: A chip structure is provided, the chip structure having a first surface and a second surface disposed opposite to each other, a first bonding ring and a second bonding ring disposed on the first surface, the second bonding ring surrounding the outside of the first bonding ring, and a sensitive structure disposed on the side of the chip structure near the first surface and inside the first bonding ring; A cover plate is provided, the cover plate having a third surface and a fourth surface disposed opposite to each other, a third bonding ring and a fourth bonding ring being disposed on the third surface, the fourth bonding ring surrounding the outside of the third bonding ring; The cover plate is placed on the first surface of the chip structure, so that the first bonding ring and the third bonding ring are correspondingly bonded and connected, the second bonding ring and the fourth bonding ring are bonded and connected, and the cover plate and the chip structure form a sealed cavity to accommodate the sensitive structure inside the first bonding ring and the third bonding ring.

[0025] Another aspect of this application discloses a wafer-level chip packaging structure, comprising: A chip wafer having a fifth surface and a sixth surface disposed opposite to each other, the chip wafer having at least one chip structure region on the fifth surface, the chip structure region having a sensitive structure, the sensitive structure being disposed on the side of the chip structure near the first surface, the chip structure region having a first bonding ring and a second bonding ring located on the fifth surface, the second bonding ring surrounding the outside of the first bonding ring, the first bonding ring being located on the outer periphery of the sensitive structure; A cover wafer has a seventh surface and an eighth surface disposed opposite to each other. The cover wafer has at least one cover region on the seventh surface corresponding to the chip structure region. The cover region has a third bonding ring and a fourth bonding ring located on the seventh surface. The fourth bonding ring surrounds the outside of the third bonding ring. The cover wafer covers the fifth surface of the chip wafer. The first bonding ring of the chip structure region is correspondingly bonded to the third bonding ring of the cover region. The second bonding ring of the chip structure region is bonded to the fourth bonding ring of the cover region. The cover region and the chip structure region form a sealing cavity inside the first bonding ring and the third bonding ring to accommodate the sensitive structure of the chip structure region. When the chip structure region includes multiple regions, there is a cutting channel region between adjacent chip structure regions; when the cover plate region includes multiple regions, there is a cutting channel region between adjacent cover plate regions.

[0026] This application also provides a method for fabricating a wafer-level chip packaging structure, including the following steps: A chip wafer is provided, the chip wafer having a fifth surface and a sixth surface disposed opposite to each other, the chip wafer having at least one chip structure region on the fifth surface, the chip structure region having a sensitive structure, the sensitive structure being disposed on the side of the chip structure near the first surface, a first bonding ring and a second bonding ring being formed correspondingly in the chip structure region on the fifth surface, the second bonding ring surrounding the outside of the first bonding ring, the first bonding ring being located on the outer periphery of the sensitive structure; A cover wafer is provided, the cover wafer having a seventh surface and an eighth surface disposed opposite to each other, the cover wafer having at least one cover region corresponding to the chip structure region on the seventh surface, and a third bonding ring and a fourth bonding ring being formed in the cover region on the seventh surface, the fourth bonding ring surrounding the outside of the third bonding ring; The cover plate wafer is bonded to the chip wafer. The first bonding ring of the chip structure region is correspondingly bonded to the third bonding ring of the cover plate region. The second bonding ring of the chip structure region is bonded to the fourth bonding ring of the cover plate region. The cover plate region and the chip structure region form a sealed cavity inside the first bonding ring and the third bonding ring to accommodate the sensitive structure of the chip structure region.

[0027] In an optional embodiment, the chip structure region includes multiple regions, and there is a dicing channel region between adjacent chip structure regions; the cover plate region includes multiple regions, and there is a dicing channel region between adjacent cover plate regions. It also includes cutting along the cutting channel area so that each of the chip structure areas forms a single chip package structure.

[0028] In an optional embodiment, the first bonding ring and the third bonding ring comprise metal bonding rings, and the second bonding ring and the fourth bonding ring comprise insulating dielectric bonding rings; The cover wafer and the chip wafer are bonded using a hybrid bonding process.

[0029] In an alternative embodiment, at least one of the cover plate regions is integral with the cover plate wafer, or at least one of the cover plate regions is bonded to the seventh surface of the cover plate wafer.

[0030] The advantages of the technical solution in this application are: The chip packaging structure of this application has a first bonding ring and a second bonding ring on the first surface of the chip structure, with the sensitive structure disposed inside the first bonding ring; a third bonding ring and a fourth bonding ring are nested on the third surface of the cover plate. The first and third bonding rings are directly bonded, and the second and fourth bonding rings are directly bonded, forming atomic-level contact between the bonding interface of the chip structure and the cover plate, thus creating a sealed cavity to accommodate the sensitive structure. Compared to traditional adhesive sealing, the chip packaging structure of this application avoids sealing failures caused by thermal expansion mismatch, escape of volatile organic compounds, or interface aging of the adhesive layer when forming a sealed cavity in existing technologies. This significantly improves the sealing stability of the chip packaging structure, thereby enhancing the hermeticity and long-term reliability of the MEMS device. Simultaneously, the first bonding ring is bonded to the third bonding ring, and the second bonding ring is bonded to the fourth bonding ring. This double-layer bonding structure with inner and outer double-layer bonding rings can form a multi-layer sealing structure. The inner bonding rings (the first and third bonding rings) achieve the main gas-tight connection, while the outer bonding rings (the second and fourth bonding rings) constitute an auxiliary sealing barrier. That is, the outer side of the sealing cavity has at least two layers of bonding structure, achieving multiple seals for the sealing cavity. When the inner bonding ring leaks due to microscopic defects or interface penetration, the outer bonding ring can still effectively block the leakage path, transforming the direct leakage path of a single sealing interface into a dual leakage path, significantly reducing the overall failure risk of the sealing structure. Furthermore, the chip structure and the cover plate are directly bonded to form a sealing cavity, eliminating the need for additional chip structures or sockets to participate in cavity enclosure, simplifying the packaging layers, shortening the heat conduction path, and improving the thermal stability and structural compactness of the MEMS device.

[0031] Furthermore, in one embodiment, the chip structure and the cover plate are connected by hybrid bonding: the first bonding ring and the third bonding ring achieve electrical interconnection, hermetic connection and mechanical fixation through metal-metal bonding, and the insulating dielectric bonding rings of the second bonding ring and the fourth bonding ring form a hermetic connection through dielectric-dielectric bonding. Metal bonding and dielectric bonding are completed simultaneously, without the need for additional sealing materials or adhesive layers. The bonding interface achieves atomic-level contact, and the sealing stability is significantly better than traditional bonding solutions. Attached Figure Description

[0032] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort. In addition, in the following drawings, the components are not necessarily drawn to scale, and components with similar related characteristics or features may have the same or similar reference numerals.

[0033] Figure 1 This is a schematic diagram of the chip structure provided in the chip packaging structure fabrication method provided in some embodiments of this application; Figure 2 This is a schematic diagram of the cover plate provided in the chip packaging structure fabrication method provided in some embodiments of this application; Figure 3 This is a schematic diagram of the bonding between the chip structure and the cover plate in the chip packaging structure fabrication method provided in some embodiments of this application; Figure 4 For some embodiments of this application Figure 3 A schematic diagram of the cross-sectional structure along the cutting line AA; Figure 5 In another embodiment of this application Figure 3 A schematic diagram of the cross-sectional structure along the cutting line AA; Figure 6 In another embodiment of this application Figure 3 A schematic diagram of the cross-sectional structure along the cutting line AA; Figure 7 This is a schematic diagram of the chip packaging structure provided in another embodiment of this application; Figure 8 This is a schematic diagram of the chip packaging structure provided in another embodiment of this application; Figure 9 This is an embodiment of the present application. Figure 8 Top view of the middle cover plate; Figure 10 This is another embodiment of the present application. Figure 8 Top view of the middle cover plate; Figure 11 This is a schematic diagram of the structure of the cover plate provided in another embodiment of this application; Figure 12 This is a schematic diagram of the chip wafer structure provided in the method for fabricating a wafer-level chip packaging structure provided in some embodiments of this application; Figure 13 This is a top view of the chip wafer provided in the method for fabricating a wafer-level chip packaging structure provided in some embodiments of this application. Figure 12 It is along Figure 13 (Schematic diagram of the cross-sectional structure along the BB direction of the cutting line). Figure 14 This is a schematic diagram of the cover wafer structure provided in the method for fabricating a wafer-level chip packaging structure provided in some embodiments of this application; Figure 15 This is a top view of the cover wafer provided in the method for fabricating a wafer-level chip packaging structure provided in some embodiments of this application. Figure 14 It is along Figure 15 (Schematic diagram of the cross-sectional structure along the CC direction of the cutting line). Figure 16 This is a schematic diagram of the structure after bonding the chip wafer and the cover wafer in the method for fabricating the wafer-level chip packaging structure provided in some embodiments of this application; Figure 17 This is a schematic diagram of the structure after the redistribution layer is formed (with a carrier board) for the fabrication method of the wafer-level chip packaging structure provided in some embodiments of this application. Figure 18 This is a schematic diagram of the process structure of a chip packaging structure fabrication method provided in one embodiment of this application; Figure 19 This is a schematic diagram of the process structure of a wafer-level chip packaging structure fabrication method provided in one embodiment of this application.

[0034] Explanation of reference numerals in the attached figures: 1. Chip structure; 11. First bonding ring; 12. Second bonding ring; 13. Sensitive structure; 14. Mounting groove; 15. First conductive connection structure; 16. Redistribution layer; 17. Second conductive connection structure; 18. Fourth conductive connection structure; 19. Fifth conductive connection structure; 101. Sealing cavity; 100. Chip wafer; 110. Chip structure area; 2. Cover plate; 21. Third bonding ring; 22. Fourth bonding ring; 23. Groove; 24. Adapter plate; 25. Third conductive connection structure; 26. Molding layer; 27. Blank adapter plate; 200. Cover plate wafer; 210. Cover plate area; 220. Carrier plate; 201. Dividing line. Detailed Implementation

[0035] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0036] Unless otherwise defined, all technical and scientific terms used in this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this application's specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0037] In the description of this application, it should be noted that the use of terms such as "first" and "second" to define objects (such as elements, components, regions, layers, doping types and / or parts) is merely for the purpose of distinguishing different objects, and is not necessarily used to describe a specific order or sequence, unless the context clearly indicates otherwise.

[0038] In the description of this application, it should be understood that the singular forms “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “compose” and / or “comprise” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0039] In the description of this application, it should also be noted that when a component is referred to as "on another component," "connected to another component," or "in contact with another component," it can mean not only that a component is directly on, directly connected to, or directly in contact with the other component, but also that an intermediate component can be inserted between the two components. Furthermore, "connection" includes not only fixed connections but also detachable connections or integral connections. Similarly, when an element is referred to as "electrically connected," "electrically contacted," "electrically coupled," or "electrically coupled to" another element, the two elements can be in direct electrical contact or electrical coupling, or they can be in electrical contact or electrical coupling through an intermediate component.

[0040] In the description of this application, it should also be noted that the orientation or positional relationship indicated by directional terms such as "front, back, up, down, left, right", "horizontal, vertical, horizontal" and "top, bottom" is usually based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing this application and simplifying the description. Unless otherwise stated, these directional terms do not indicate or imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the scope of protection of this application; the directional terms "inner" and "outer" refer to the inner and outer contours relative to the outline of each component itself.

[0041] Furthermore, in the description of this application, spatial relation terms such as "below," "under," "below," "below," "below," "above," "on the upper surface of," "above," etc., can be used to describe the spatial positional relationship between one element or feature shown in the figures and other elements or features. It should be understood that spatial relation terms, in addition to the orientation shown in the figures, also include different orientations of elements or features in use and operation. For example, if an element or feature in the figures is flipped or inverted, an element or feature described as "below" or "below" other elements or features will be oriented "above" other elements or features. Furthermore, elements may also include other orientations (e.g., rotated by an angle or other orientations).

[0042] The structure of the embodiments of this application should not be limited to the specific shape shown in the accompanying drawings, but includes shape deviations due to, for example, manufacturing techniques.

[0043] It is understood that in some of the accompanying drawings of this application, adjacent films with the same processing material are drawn as connected to make them resemble the actual structure.

[0044] Through experiments, the inventors discovered that the reason why the sealing structure is unstable when using adhesive caps or sealing caps is that the bonding interface between the cap or sealing cap and the chip is prone to microcracks or delamination due to factors such as mismatch of thermal expansion coefficients, interface voids, and residual volatile organic compounds, leading to attenuation of airtightness or even complete failure. At the same time, the subsequent bonding process is usually carried out one chip at a time in a non-clean environment, which further increases the risk of contamination intrusion and inconsistent sealing quality, making it difficult to meet the long-term airtightness requirements of high-reliability MEMS devices.

[0045] Therefore, this application provides a chip packaging structure, please refer to... Figure 3 The chip packaging structure includes: Chip structure 1 has a first surface and a second surface disposed opposite to each other. The first surface has a first bonding ring 11 and a second bonding ring 12. The second bonding ring 12 surrounds the outside of the first bonding ring 11. The chip structure 1 also has a sensitive structure 13. The sensitive structure 13 is disposed on the side of the chip structure 1 close to the first surface and located inside the first bonding ring 11. The cover plate 2 has a third surface and a fourth surface disposed opposite to each other. The third surface has a third bonding ring 21 and a fourth bonding ring 22. The fourth bonding ring 22 surrounds the outside of the third bonding ring 21. The cover plate 2 is disposed on the first surface of the chip structure 1. The first bonding ring 11 is correspondingly bonded to the third bonding ring 21, and the second bonding ring 12 is bonded to the fourth bonding ring 22, so that the cover plate 2 and the chip structure 1 form a sealed cavity 101 for accommodating the sensitive structure 13 inside the first bonding ring 11 and the third bonding ring 21.

[0046] The chip packaging structure of this application has a first bonding ring 11 and a second bonding ring 12 on the first surface of the chip structure 1, with the sensitive structure 13 disposed inside the first bonding ring 11; a third bonding ring 21 and a fourth bonding ring 22 are nested on the third surface of the cover plate 2. The first bonding ring 11 is directly bonded to the third bonding ring 21, and the second bonding ring 12 is directly bonded to the fourth bonding ring 22, forming an atomic-level contact between the bonding interface of the chip structure 1 and the cover plate 2, and creating a sealed cavity 101 between the chip structure 1 and the cover plate 2 to accommodate the sensitive structure 13. Compared to traditional adhesive sealing, the chip packaging structure of this application avoids the sealing failure caused by thermal expansion mismatch, escape of volatile organic compounds, or interface aging of the adhesive layer when forming the sealed cavity 101 using the prior art. This significantly improves the sealing stability of the chip packaging structure, thereby enhancing the hermeticity and long-term reliability of the MEMS device. Simultaneously, the first bonding ring 11 is bonded to the third bonding ring 21, and the second bonding ring 12 is bonded to the fourth bonding ring 22. This double-layer bonding structure with inner and outer double-layer bonding rings can form a multi-layer sealing structure. The inner bonding ring (first bonding ring 11 and third bonding ring 21) achieves the main gas-tight connection, while the outer bonding ring (second bonding ring 12 and fourth bonding ring 22) constitutes an auxiliary sealing barrier. That is, the outer side of the sealing cavity 101 has at least two layers of bonding structure, achieving multiple seals for the sealing cavity 101. When the inner bonding ring leaks due to microscopic defects or interface penetration, the outer bonding ring can still effectively block the leakage path, transforming the direct leakage path of a single sealing interface into a dual leakage path, significantly reducing the overall failure risk of the sealing structure. Furthermore, the chip structure 1 and the cover plate 2 are directly bonded to form the sealing cavity 101, eliminating the need for additional chip structure 1 or sockets to participate in the cavity enclosure. This simplifies the packaging layers, shortens the heat conduction path, and improves the thermal stability and structural compactness of the MEMS device.

[0047] In one embodiment, the first bonding ring 11 and the third bonding ring 21 comprise metal bonding rings, and the second bonding ring 12 and the fourth bonding ring 22 comprise insulating dielectric bonding rings.

[0048] At this point, the chip structure 1 and the cover plate 2 are connected via hybrid bonding: the first bonding ring 11 and the third bonding ring 21 achieve a hermetically sealed connection and mechanical fixation through metal-to-metal bonding; the insulating dielectric bonding rings of the second bonding ring 12 and the fourth bonding ring 22 form a hermetically sealed connection through dielectric-to-dielectric bonding. Metal bonding and dielectric bonding are completed simultaneously, requiring no additional sealing materials or adhesive layers. The bonding interface achieves atomic-level contact, resulting in significantly better sealing stability than traditional adhesive bonding methods. Furthermore, hybrid bonding offers higher alignment accuracy and eliminates the need for pre-plating additional metal on the bonding layer for soldering. Simultaneously, the first bonding ring 11 and the third bonding ring 21 can also achieve electrical interconnection, facilitating external wiring of the chip structure 1.

[0049] In one specific embodiment, the metal bonding ring includes a copper bonding ring, a gold bonding ring, a nickel bonding ring, or an aluminum bonding ring; The insulating dielectric bonding ring includes a silicon oxide bonding ring, a silicon nitride bonding ring, a silicon carbonitride bonding ring, or an organic insulating dielectric bonding ring.

[0050] Copper, gold, nickel, aluminum and other metal bonding rings are mixed with silicon oxide, silicon nitride, silicon carbonitride and organic insulating dielectric bonding rings. The metal rings provide low resistance conductivity and mechanical anchoring, while the insulating dielectric rings achieve high resistance isolation and interface passivation. The heterogeneous materials are matched synergistically, and the bonding connection is stable and reliable.

[0051] In one embodiment, the second bonding ring 12 and the fourth bonding ring 22 are made of the same material as the cover plate 2. When the cover plate 2 is a silicon oxide cover plate 2, the second bonding ring 12 and the fourth bonding ring 22 are silicon oxide bonding rings, and the silicon oxide bonding rings are easy to connect with the silicon oxide cover plate 2.

[0052] In one specific embodiment, when the insulating dielectric bonding ring includes an organic insulating dielectric bonding ring, the organic insulating dielectric bonding ring includes a polyimide bonding ring, a photosensitive polyimide bonding ring, or a benzocyclobutene bonding ring.

[0053] In one specific embodiment, the first bonding ring 11 and the third bonding ring 21 are both copper bonding rings, which are less expensive than gold bonding rings. The second bonding ring 12 and the fourth bonding ring 22 are both polyimide bonding rings.

[0054] In another embodiment, the first bonding ring 11, the third bonding ring 21, the second bonding ring 12, and the fourth bonding ring 22 are all metal bonding rings.

[0055] In another embodiment, the first bonding ring 11, the third bonding ring 21, the second bonding ring 12, and the fourth bonding ring 22 are all insulating dielectric bonding rings.

[0056] In one embodiment, the surface of the first bonding ring 11 away from the first surface is coplanar with the surface of the second bonding ring 12 away from the first surface, and the surface of the third bonding ring 21 away from the third surface is coplanar with the surface of the fourth bonding ring 22 away from the third surface. This arrangement ensures that the end faces of the bonding rings are flush, the bonding interface is tightly fitted, and the bonding accuracy and consistency are improved.

[0057] In one embodiment, the third surface of the cover plate 2 is further provided with a groove 23, which is located inside the third bonding ring 21; When the cover plate 2 is placed on the first surface of the chip structure 1, the groove 23 is provided corresponding to the sensitive structure 13 of the chip structure 1, and the sidewall and bottom wall of the groove 23 form part of the sidewall of the sealing cavity 101.

[0058] The groove 23 can increase the space of the sealing cavity 101, making it easier to fill with inert gas.

[0059] In one embodiment, the sidewalls and bottomwalls of the groove 23 are spaced apart from the sensitive structure 13.

[0060] The sensitive structure 13 is located on the first surface of the chip structure 1 and inside the inner bonding ring. The groove 23 structure increases the space of the sealing cavity 101 and has a gap distance with the sensitive structure 13, so that the stress is concentrated in the bonding ring area at the edge of the chip during the bonding process, effectively avoiding mechanical damage to the sensitive structure 13 by the bonding pressure.

[0061] In one embodiment, the sealed cavity 101 is in a vacuum state, or the sealed cavity 101 is filled with an inert gas (specifically, it can be one or more of nitrogen, helium, argon or neon).

[0062] In one embodiment, a mounting groove 14 is provided on the first surface of the chip structure 1, and the sensitive structure 13 is located in the mounting groove 14.

[0063] In one specific embodiment, the surface of the sensitive structure 13 away from the bottom of the mounting groove 14 is level with or lower than the first surface of the chip structure 1 (in this case, the groove 23 may not be provided on the cover plate 2).

[0064] In one embodiment, there is no gap between the first bonding ring 11 and the second bonding ring 12, and no gap between the third bonding ring 21 and the fourth bonding ring 22. In this configuration, the bonding rings are closely arranged, resulting in a compact structure, high mechanical strength, and good sealing performance.

[0065] In one embodiment, the first bonding ring 11 and the second bonding ring 12 are spaced apart, and the third bonding ring 21 and the fourth bonding ring 22 are also spaced apart. In this case, the bonding rings are discretely arranged, resulting in stress dispersion, thermal expansion buffering, and a large process tolerance.

[0066] In one embodiment, the first bonding ring 11 and the second bonding ring 12 are concentric; The third bonding ring 21 and the fourth bonding ring 22 are concentric, and the third bonding ring 21 and the fourth bonding ring 22 are respectively arranged corresponding to the first bonding ring 11 and the second bonding ring 12.

[0067] The concentric arrangement of the bonding rings facilitates bonding alignment.

[0068] In one embodiment, there are multiple first bonding rings 11 and multiple second bonding rings 12, and the first bonding rings 11 and the second bonding rings 12 are arranged alternately in the radial direction; The third bonding ring 21 has multiple rings, and the fourth bonding ring 22 has multiple rings, with the third bonding ring 21 and the fourth bonding ring 22 arranged alternately in the radial direction.

[0069] In one specific embodiment, there are multiple first bonding rings 11 and multiple second bonding rings 12, and the number of first bonding rings 11 and second bonding rings 12 is the same, and there are two of each (please refer to...). Figure 5 ), or 3 in total (please refer to) Figure 3 and Figure 4 ), or 4 in total; The third bonding ring 21 and the fourth bonding ring 22 are each in multiple quantities. The number of the third bonding ring 21 and the fourth bonding ring 22 are the same, and there are 2, 3, or 4 of each.

[0070] In one specific embodiment, there is one first bonding ring 11 and two second bonding rings 12 (see reference). Figure 6 The first bonding ring 11 and the second bonding ring 12 are arranged alternately in the radial direction; There is one third bonding ring 21 and two fourth bonding rings 22, with the third bonding ring 21 and the fourth bonding ring 22 arranged alternately in the radial direction.

[0071] In one specific embodiment, there are two first bonding rings 11 and one second bonding ring 12, and the first bonding rings 11 and the second bonding rings 12 are arranged alternately in the radial direction; There are two third bonding rings 21 and one fourth bonding ring 22, and the third bonding rings 21 and the fourth bonding ring 22 are arranged alternately in the radial direction.

[0072] Please continue to refer to this. Figure 3 In one embodiment, a redistribution layer 16 is provided on the second surface of the chip structure 1; The chip structure 1 has a second conductive connection structure 17, and the two ends of the second conductive connection structure 17 are conductively connected to the sensitive structure 13 and the redistribution layer 16 on the second surface of the chip structure 1, respectively.

[0073] The second conductive connection structure 17 leads the electrical signal of the sensitive structure 13 to the redistribution layer 16 on the second surface of the chip structure 1, thereby realizing the connection of the back circuit of the chip.

[0074] In one embodiment, please continue to refer to Figure 3 The chip structure 1 also has a fifth conductive connection structure 19, the two ends of which are conductively connected to the redistribution layer 16 and the sensitive structure 13 (specifically, the sidewall of the sensitive structure 13), respectively. The first bonding ring 11 is conductively connected to the sensitive structure 13 or other non-sensitive structure 13.

[0075] In one embodiment, please refer to Figure 8 It also includes an adapter plate 24, which has a third conductive connection structure 25. The third conductive connection structure 25 penetrates the upper and lower surfaces of the adapter plate 24 that are disposed opposite to each other. The adapter plate 24 is disposed on the first surface of the chip structure 1, and the lower surface of the adapter plate 24 is connected to the first surface of the chip structure 1. The adapter plate 24 is located outside the first bonding ring 11 and the second bonding ring 12. The chip structure 1 has a fourth conductive connection structure 18, and the two ends of the fourth conductive connection structure 18 are conductively connected to the sensitive structure 13 and the third conductive connection structure 25 of the adapter board 24, respectively.

[0076] The adapter board 24 is integrated on the outer side of the first surface of the chip structure 1. The third conductive connection structure 25 penetrates the upper and lower surfaces. The fourth conductive connection structure 18 connects the sensitive structure 13 with the third conductive connection structure 25 of the adapter board 24, thereby realizing three-dimensional vertical conduction between the sensitive structure 13 of the chip structure 1 and the external adapter board 24. This shortens the signal transmission path, increases the integration density, and reduces the package size.

[0077] In one embodiment, please refer to Figure 8 and in conjunction with references Figure 9 and Figure 10 The adapter board 24 comprises multiple adapter boards 24, which are respectively arranged around the outer periphery of the cover plate 2. In actual use, the number of adapter boards 24 is set according to the number of I / O contacts required by the chip structure 1 or the sensitive structure 13.

[0078] In one embodiment, a molding compound 26 is filled between adjacent adapter plates 24 and cover plates 2. The molding compound 26 does not cover the surface of cover plate 2 away from the sensitive structure 13.

[0079] In one embodiment, the sensitive structure 13 includes a movable microstructure or a photosensitive structure; The cover plate 2 includes a glass cover plate 2 or a silicon cover plate 2. When the sensitive structure 13 includes a photosensitive structure, the cover plate 2 includes a transparent glass cover plate 2 to facilitate light transmission.

[0080] In one embodiment, the sensitive structure 13 includes a photosensitive structure; The sensitive structure 13 has a transparent insulating dielectric layer on the side surface near the cover plate 2 to allow light to pass through.

[0081] The insulating dielectric layer can protect the sensitive structure 13 and prevent it from being contaminated during the fabrication process (e.g., thinning process).

[0082] In one embodiment, the sensitive structure 13 includes a plurality of sensitive structures, with a gap between adjacent sensitive structures 13, and a set of first bonding ring 11 and second bonding ring 12 are respectively disposed on the outer periphery of each sensitive structure 13; The cover plate 2 has multiple sets of third bonding rings 21 and fourth bonding rings 22 corresponding to the first bonding ring 11 and the second bonding ring 12 located on the outer periphery of each of the sensitive structures 13.

[0083] Multiple sensitive structures 13 are arranged at intervals, and each sensitive structure 13 is independently configured with a first bonding ring 11 and a second bonding ring 12 on its outer periphery. The cover plate 2 is provided with multiple sets of bonding rings to match the multiple sensitive structures 13, forming multiple independent sealing cavities 101. The sensitive structures 13 do not interfere with each other, single-point failure is isolated, and it is easy to improve the packaging efficiency.

[0084] In one embodiment, the sensitive structure 13 includes a plurality of sensitive structures, with a gap between adjacent sensitive structures 13, and a set of first bonding ring 11 and second bonding ring 12 are disposed on the outer periphery of each sensitive structure 13; The cover plate 2 includes a plurality of covers, each cover plate 2 having a set of third bonding rings 21 and fourth bonding rings 22 corresponding to the first bonding ring 11 and the second bonding ring 12 located on the outer periphery of each of the sensitive structures 13.

[0085] Multiple sensitive structures 13 are arranged at intervals, and each sensitive structure 13 is independently configured with a first bonding ring 11 and a second bonding ring 12 on its outer periphery. Each cover plate 2 is provided with a set of bonding rings to match a single sensitive structure 13, forming a multi-cavity independent seal of multiple cover plates 2. The physical isolation between sensitive structures 13 is thorough, and single-point failure is completely isolated. It is also convenient for step-by-step bonding and flexible replacement, thereby improving the reliability and maintainability of the system.

[0086] In one embodiment, the sensitive structure 13 includes a plurality of sensitive structures, with a gap between adjacent sensitive structures 13, and a set of first bonding ring 11 and second bonding ring 12 are disposed on the outer periphery of each sensitive structure 13; The cover plate 2 includes at least one, please refer to Figure 10At least one of the cover plates 2 has at least one groove 23, and at least two sets of third bonding rings 21 and fourth bonding rings 22 corresponding to the first bonding rings 11 and the second bonding rings 12 located on the outer periphery of the at least two sets of the sensitive structures 13, with one set of bonding rings corresponding to one groove 23.

[0087] Multiple sensitive structures 13 are arranged at intervals, and each sensitive structure 13 is independently configured with a first bonding ring 11 and a second bonding ring 12 on its outer periphery. At least one cover plate 2 is provided with at least two sets of bonding rings to match the multiple sensitive structures 13. One cover plate 2 corresponds to multiple sets of bonding rings to cover multiple sensitive structures 13, which can adapt to different integration densities and reliability requirements, and improve the versatility and scalability of the packaging solution.

[0088] This application also provides a method for fabricating a chip packaging structure, used to fabricate the aforementioned chip packaging structure. Please refer to [reference needed]. Figure 18 The preparation method includes the following steps: Please refer to step S10 for execution. Figure 1 A chip structure 1 is provided, the chip structure 1 having a first surface and a second surface disposed opposite to each other, a first bonding ring 11 and a second bonding ring 12 are disposed on the first surface, the second bonding ring 12 surrounds the outside of the first bonding ring 11, and a sensitive structure 13 is disposed on the side of the chip structure 1 close to the first surface and inside the first bonding ring 11. Please refer to step S20 for execution instructions. Figure 2 A cover plate 2 is provided, the cover plate 2 having a third surface and a fourth surface disposed opposite to each other, a third bonding ring 21 and a fourth bonding ring 22 are disposed on the third surface, the fourth bonding ring 22 surrounding the outside of the third bonding ring 21; Please refer to step S30 for execution. Figure 3 The cover plate 2 is placed on the first surface of the chip structure 1, so that the first bonding ring 11 and the third bonding ring 21 are correspondingly bonded and connected, the second bonding ring 12 and the fourth bonding ring 22 are bonded and connected, and the cover plate 2 and the chip structure 1 form a sealed cavity 101 for accommodating the sensitive structure 13 inside the first bonding ring 11 and the third bonding ring 21.

[0089] In one embodiment, please refer to Figure 3 The first bonding ring 11 and the third bonding ring 21 include metal bonding rings, and the second bonding ring 12 and the fourth bonding ring 22 include insulating dielectric bonding rings. The first bonding ring 11 and the third bonding ring 21 are connected by hybrid bonding through a hybrid bonding process, and the second bonding ring 12 and the fourth bonding ring 22 are connected by hybrid bonding through a hybrid bonding process.

[0090] This application also provides a wafer-level chip packaging structure, please refer to... Figure 17 The wafer-level chip packaging structure includes: A chip wafer 100 has a fifth surface and a sixth surface disposed opposite to each other. The chip wafer 100 has at least one chip structure region 110 on the fifth surface. The chip structure region 110 has a sensitive structure 13 disposed on the side of the chip structure 100 close to the first surface. The chip structure region 110 has a first bonding ring 11 and a second bonding ring 12 located on the fifth surface. The second bonding ring 12 surrounds the outside of the first bonding ring 11. The first bonding ring 11 is located on the outer periphery of the sensitive structure 13. A cover wafer 200 has a seventh surface and an eighth surface disposed opposite to each other. The cover wafer 200 has at least one cover region 210 on the seventh surface corresponding to the chip structure region 110. The cover region 210 has a third bonding ring 21 and a fourth bonding ring 22 located on the seventh surface. The fourth bonding ring 22 surrounds the outside of the third bonding ring 21. The cover wafer 200 covers the fifth surface of the chip wafer 100. The first bonding ring 11 of the chip structure region 110 is correspondingly bonded to the third bonding ring 21 of the cover region 210. The second bonding ring 12 of the chip structure region 110 is bonded to the fourth bonding ring 22 of the cover region 210. The cover region 210 and the chip structure region 110 form a sealed cavity 101 inside the first bonding ring 11 and the third bonding ring 21 to accommodate the sensitive structure 13 of the chip structure region 110. When the chip structure region 110 includes multiple regions, there is a cutting channel region between adjacent chip structure regions 110. When the cover plate region 210 includes multiple regions, there is a cutting channel region between adjacent cover plate regions 210.

[0091] This application also provides a method for fabricating a wafer-level chip packaging structure, used to fabricate the aforementioned wafer-level chip packaging structure, or to fabricate the aforementioned chip packaging structure. Please refer to [reference needed]. Figure 19 The preparation method includes the following steps: Step S100: A chip wafer is provided, the chip wafer having a fifth surface and a sixth surface disposed opposite to each other, the chip wafer having at least one chip structure region on the fifth surface, the chip structure region having a sensitive structure, the sensitive structure being disposed on the side of the chip structure near the first surface, a first bonding ring and a second bonding ring being formed correspondingly in the chip structure region on the fifth surface, the second bonding ring surrounding the outside of the first bonding ring, the first bonding ring being located on the outer periphery of the sensitive structure; Step S200: Provide a cover wafer having a seventh surface and an eighth surface disposed opposite to each other. The cover wafer has at least one cover region on the seventh surface corresponding to the chip structure region. A third bonding ring and a fourth bonding ring are formed in the cover region on the seventh surface. The fourth bonding ring surrounds the outside of the third bonding ring. In step S300, the cover plate wafer is bonded to the chip wafer, the first bonding ring of the chip structure region is correspondingly bonded to the third bonding ring of the cover plate region, the second bonding ring of the chip structure region is bonded to the fourth bonding ring of the cover plate region, and a sealing cavity is formed between the cover plate region and the chip structure region on the inner sides of the first bonding ring and the third bonding ring to accommodate the sensitive structure of the chip structure region.

[0092] The fabrication method of the aforementioned wafer-level chip packaging structure is described in detail below with reference to the accompanying drawings in some embodiments.

[0093] First, proceed with step S100, please refer to... Figure 12 , and in conjunction with reference Figure 13 A chip wafer 100 is provided, the chip wafer 100 having a fifth surface and a sixth surface disposed opposite to each other, the chip wafer 100 having at least one chip structure region 110 on the fifth surface, the chip structure region 110 having a sensitive structure 13, the sensitive structure 13 being disposed on the side of the chip structure 100 near the first surface, a first bonding ring 11 and a second bonding ring 12 being formed correspondingly in the chip structure region 110 on the fifth surface, the second bonding ring 12 surrounding the outside of the first bonding ring 11, the first bonding ring 11 being located on the outer periphery of the sensitive structure 13.

[0094] In one embodiment, the chip structure region 110 includes multiple regions, and a dicing channel region is provided between adjacent chip structure regions 110. The cover plate region 210 includes multiple regions, and a dicing channel region is provided between adjacent cover plate regions 210. The dicing channel regions between adjacent chip structure regions 110 are correspondingly provided with the dicing channel regions between adjacent cover plate regions 210 to facilitate subsequent cutting.

[0095] In one embodiment, the first bonding ring 11 comprises a metal bonding ring, and the second bonding ring 12 comprises an insulating dielectric bonding ring.

[0096] In one embodiment, the preparation of the first bonding ring 11 and the second bonding ring 12 includes: An insulating dielectric layer is formed on the fifth surface of the chip wafer 100; Photolithography is performed on the insulating dielectric layer to prepare an annular groove, and the insulating dielectric layer on the inner and / or outer sides of the annular groove forms the second bonding ring 12; The material filling the groove with the first bonding ring 11 forms the first bonding ring 11.

[0097] In one embodiment, a first bonding ring 11 is formed in the tank by an electroplating process or a deposition process.

[0098] In one embodiment, when an insulating dielectric layer is formed on the fifth surface of the chip wafer 100, the insulating dielectric layer covers the side of the sensitive structure 13 closest to the cover plate 2 and is not etched away during the photolithography process to create the annular groove. The insulating dielectric layer covering the side of the sensitive structure 13 closest to the cover plate 2 protects the sensitive structure 13 during subsequent planarization processes. In one specific embodiment, the sensitive structure 13 includes a photosensitive structure, and the insulating dielectric layer includes a transparent insulating dielectric layer (e.g., transparent PI, Polyimide) to facilitate light transmission.

[0099] In one embodiment, a planarization process is further performed on the first bonding ring 11 and the second bonding ring 12 of the chip wafer 100 so that the upper surface of the first bonding ring 11 (the side surface away from the chip wafer 100) and the upper surface of the second bonding ring 12 (the side surface away from the chip wafer 100) have the same horizontal position height to facilitate subsequent bonding processes.

[0100] Next, proceed to step S200, please refer to... Figure 14 , and in conjunction with reference Figure 15 A cover wafer 200 is provided, the cover wafer 200 having a seventh surface and an eighth surface disposed opposite to each other, the cover wafer 200 having at least one cover region 210 on the seventh surface corresponding to the chip structure region 110, a third bonding ring 21 and a fourth bonding ring 22 being formed in the cover region 210 on the seventh surface, the fourth bonding ring 22 surrounding the outside of the third bonding ring 21.

[0101] In one embodiment, the third bonding ring 21 includes a metal bonding ring, and the fourth bonding ring 22 includes an insulating dielectric bonding ring.

[0102] In one embodiment, the preparation of the third bonding ring 21 and the fourth bonding ring 22 includes: An insulating dielectric layer is formed on the seventh surface of the cover plate wafer 200; Photolithography is performed on the insulating dielectric layer to prepare an annular groove, and the insulating dielectric layer on the inner and / or outer sides of the annular groove forms the fourth bonding ring 22; The material filling the groove with the third bonding ring 21 forms the third bonding ring 21.

[0103] In one embodiment, a third bonding ring 21 is formed in the tank by an electroplating process or a deposition process.

[0104] In one embodiment, a groove 23 is formed on the seventh surface of the cover plate wafer 200, inside the third bonding ring 21, and the groove 23 is used to form a sealing cavity 101.

[0105] In one embodiment, a planarization process is further performed on the third bonding ring 21 and the fourth bonding ring 22 of the cover plate wafer 200 to make the upper surface of the third bonding ring 21 (the side surface away from the cover plate wafer 200) and the upper surface of the fourth bonding ring 22 (the side surface away from the cover plate wafer 200) have the same horizontal position and height to facilitate subsequent bonding processes.

[0106] In one embodiment, at least one of the cover plate regions 210 is integral with the cover plate wafer 200, or at least one of the cover plate regions 210 is bonded to the seventh surface of the cover plate wafer 200.

[0107] In another embodiment, the chip region has a fourth conductive connection structure 18, one end of which is connected to the sensitive structure 13, and the other end is exposed in the chip region of the fifth surface of the chip wafer 100, and is located outside the first bonding ring 11 and the second bonding ring 12. It also includes an adapter plate 24, on which a third conductive connection structure 25 is provided for conductive connection with the fourth conductive connection structure 18, the third conductive connection structure 25 penetrating the upper and lower surfaces of the adapter plate 24 that are disposed opposite to each other; The adapter plate 24 is disposed in the cover plate region 210 of the cover plate wafer 200 and located outside the third bonding ring 21 and the fourth bonding ring 22. When the cover plate wafer 200 is bonded to the chip wafer 100, the lower surface of the adapter plate 24 is connected to the fifth surface of the chip wafer 100, and the third conductive connection structure 25 is conductively connected to the fourth conductive connection structure 18.

[0108] Next, proceed to step S300, please refer to... Figure 16The cover plate wafer 200 is bonded to the chip wafer 100. The first bonding ring 11 of the chip structure region 110 is correspondingly bonded to the third bonding ring 21 of the cover plate region 210. The second bonding ring 12 of the chip structure region 110 is bonded to the fourth bonding ring 22 of the cover plate region 210. The cover plate region 210 and the chip structure region 110 form a sealed cavity 101 inside the first bonding ring 11 and the third bonding ring 21 to accommodate the sensitive structure 13 of the chip structure region 110.

[0109] In one embodiment, the first bonding ring 11 and the third bonding ring 21 comprise metal bonding rings, and the second bonding ring 12 and the fourth bonding ring 22 comprise insulating dielectric bonding rings. The cover plate wafer 200 is bonded to the chip wafer 100 using a hybrid bonding process.

[0110] In one embodiment, before the cover wafer 200 is bonded to the chip wafer 100, a carrier plate 220 is disposed on the side of the cover wafer 200 away from the chip wafer 100, the carrier plate 220 being able to alleviate stress distribution during bonding. After bonding, the carrier plate 220 is removed.

[0111] In one embodiment, during the hybrid bonding process, the process environment is a vacuum or contains an inert gas, and the gas pressure during hybrid bonding is between 0.5 and 1.5 atmospheres.

[0112] In one embodiment, the hybrid bonding process also includes a baking process to promote bonding connections.

[0113] In one specific embodiment, when the metal bonding ring includes a copper bonding ring and the insulating dielectric bonding ring includes a silicon oxide bonding ring, the baking process also includes temperature control to seek a dynamic balance between the redox window of copper and the thermal stability of the dielectric. Specifically, the low-temperature range (100°C–150°C) focuses on removing water and preserving the activity of hydroxyl groups to avoid residual moisture forming interface voids in the subsequent high-temperature stage; the medium-temperature range (200°C–300°C) initiates Si-O-Si covalent bonding and the reduction of oxides on the copper surface to achieve synchronous metal-dielectric bonding; the upper limit temperature (≤400°C) is determined based on the CTE (Coefficient of Thermal Expansion) of Cu and SiO2 to control the stress after bonding.

[0114] In one embodiment, please refer to Figure 17The chip structure 1 includes a second conductive connection structure 17, which is conductively connected to the sensitive structure 13. After the cover wafer 200 is bonded to the chip wafer 100, a redistribution layer 16 is formed on the sixth surface of the chip wafer 100. The redistribution layer 16 is conductively connected to the second conductive connection structure 17, and the redistribution layer 16 is used to implement the circuit lead-out of the sensitive structure 13.

[0115] In one embodiment, bumps and solder balls are also formed on the side of the redistribution layer 16 away from the chip wafer 100.

[0116] In one embodiment, the method further includes a step of cutting along the dicing channel region, so that each of the chip structure regions 110 corresponds to a single chip package structure. During cutting, the cutting is performed along the dicing line 201 within the dicing channel region.

[0117] In one embodiment, when the cover wafer 200 has a plurality of cover regions 210, and the plurality of cover regions 210 and the body of the cover wafer 200 are integrally formed, cutting is performed along the cutting line 201 in the dicing region. This includes cutting the cover wafer 200 along the cutting line 201 in the dicing region of the cover wafer 200, and cutting the chip wafer 100 along the cutting line 201 in the dicing region of the chip wafer 100. When the cover wafer 200 has a plurality of cover regions 210, and the plurality of cover regions 210 are bonded to the body of the cover wafer 200, cutting of the chip wafer 100 only needs to be performed along the cutting line 201 in the dicing region of the chip wafer 100.

[0118] In one embodiment, when multiple cover plate regions 210 are bonded to the body of the cover plate wafer 200, a blank adapter plate 27 is bonded to a position on the body of the cover plate wafer 200 where no cover plate region 210 is provided, so as to balance the stress distribution of the cover plate wafer 200 as a whole.

[0119] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0120] It should be noted that, where there is no conflict, the features in the different embodiments of this application described above can be combined with each other. Furthermore, in each of the above embodiments, the focus is on describing the differences from other embodiments; other specific descriptions of the same / similar parts between the embodiments can be referred to (or referenced) interchangeably. In addition, descriptions of well-known components and technologies have been omitted in the above description to avoid unnecessarily obscuring the concepts of this application.

[0121] Although this application has been disclosed above with reference to preferred embodiments, it is not intended to limit this application. Any person skilled in the art can make possible changes and modifications to the technical solutions of this application by utilizing the methods and techniques disclosed above without departing from the spirit and scope of this application. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall fall within the protection scope of the technical solutions of this application.

Claims

1. A chip packaging structure, characterized in that, include: A chip structure having a first surface and a second surface disposed opposite to each other, the first surface having a first bonding ring and a second bonding ring, the second bonding ring surrounding the outside of the first bonding ring, the chip structure also having a sensitive structure disposed on the side of the chip structure near the first surface and located inside the first bonding ring; A cover plate has a third surface and a fourth surface disposed opposite to each other. The third surface has a third bonding ring and a fourth bonding ring. The fourth bonding ring surrounds the outside of the third bonding ring. The cover plate is disposed on the first surface of the chip structure. The first bonding ring and the third bonding ring are correspondingly bonded and connected. The second bonding ring and the fourth bonding ring are bonded and connected, so that the cover plate and the chip structure form a sealed cavity for accommodating the sensitive structure inside the first bonding ring and the third bonding ring.

2. The chip packaging structure as described in claim 1, characterized in that, The first bonding ring and the third bonding ring include metal bonding rings, and the second bonding ring and the fourth bonding ring include insulating dielectric bonding rings; Alternatively, the first bonding ring, the third bonding ring, the second bonding ring, and the fourth bonding ring may all be metal bonding rings; Alternatively, the first bonding ring, the third bonding ring, the second bonding ring, and the fourth bonding ring may all be insulating dielectric bonding rings.

3. The chip packaging structure as described in claim 2, characterized in that, The metal bonding ring includes a copper bonding ring, a gold bonding ring, a nickel bonding ring, or an aluminum bonding ring; The insulating dielectric bonding ring includes a silicon oxide bonding ring, a silicon nitride bonding ring, a silicon carbonitride bonding ring, or an organic insulating dielectric bonding ring.

4. The chip packaging structure as described in claim 3, characterized in that, The organic insulating dielectric bonding ring includes a polyimide bonding ring, a photosensitive polyimide bonding ring, or a benzocyclobutene bonding ring.

5. A chip packaging structure as described in claim 1, characterized in that, The surface of the first bonding ring away from the first surface is coplanar with the surface of the second bonding ring away from the first surface, and the surface of the third bonding ring away from the third surface is coplanar with the surface of the fourth bonding ring away from the third surface.

6. The chip packaging structure as described in claim 1, characterized in that, The third surface of the cover plate is also provided with a groove, which is located inside the third bonding ring; When the cover plate is placed on the first surface of the chip structure, the groove is provided corresponding to the sensitive structure of the chip structure, and the sidewall and bottom wall of the groove form part of the sidewall of the sealing cavity.

7. A chip packaging structure as described in claim 1, characterized in that, The sealed cavity is either in a vacuum state or filled with an inert gas.

8. A chip packaging structure as described in claim 1, characterized in that, There is no gap between the first bonding ring and the second bonding ring, and there is no gap between the third bonding ring and the fourth bonding ring.

9. A chip packaging structure as described in claim 1, characterized in that, There is a gap between the first bonding ring and the second bonding ring, and there is a gap between the third bonding ring and the fourth bonding ring.

10. A chip packaging structure as described in claim 1, characterized in that, The first bonding ring and the second bonding ring are concentric; The third bonding ring and the fourth bonding ring are concentric, and the third bonding ring and the fourth bonding ring are respectively arranged to correspond to the first bonding ring and the second bonding ring.

11. A chip packaging structure as described in claim 10, characterized in that, The first bonding ring has multiple rings and / or the second bonding ring has multiple rings, with the first bonding ring and the second bonding ring arranged alternately in a radial direction; The third bonding ring has multiple rings and / or the fourth bonding ring has multiple rings, with the third bonding ring and the fourth bonding ring arranged alternately in a radial direction.

12. A chip packaging structure as described in claim 11, characterized in that, The first bonding ring and the second bonding ring are each in multiple quantities, and the number of the first bonding ring and the second bonding ring are the same, and are 2 to 4 respectively; The third bonding ring and the fourth bonding ring are each multiple, and the number of the third bonding ring and the fourth bonding ring are the same, and are 2 to 4 respectively.

13. A chip packaging structure as described in claim 1, characterized in that, A redistribution layer is provided on the second surface of the chip structure; The chip structure has a second conductive connection structure, and the two ends of the second conductive connection structure are conductively connected to the sensitive structure and the redistribution layer of the second surface of the chip structure, respectively.

14. A chip packaging structure as described in claim 1, characterized in that, It also includes an adapter board, which has a third conductive connection structure that penetrates the upper and lower surfaces of the adapter board that are disposed opposite each other. The adapter board is disposed on the first surface of the chip structure, and the lower surface of the adapter board is connected to the first surface of the chip structure. The adapter board is located outside the first bonding ring and the second bonding ring. The chip structure has a fourth conductive connection structure, and the two ends of the fourth conductive connection structure are conductively connected to the sensitive structure and the third conductive connection structure of the adapter board, respectively.

15. A chip packaging structure as described in claim 1, characterized in that, The sensitive structure includes a movable microstructure or a photosensitive structure; The cover plate includes a glass cover plate or a silicon cover plate. When the sensitive structure includes a photosensitive structure, the cover plate includes a transparent glass cover plate.

16. A chip packaging structure as described in claim 15, characterized in that, The sensitive structure includes a photosensitive structure; The sensitive structure has a transparent insulating dielectric layer on the side surface near the cover plate.

17. A chip packaging structure as described in claim 1, characterized in that, The sensitive structure includes multiple structures, with a spacing between adjacent sensitive structures, and each sensitive structure is provided with a set of first bonding rings and second bonding rings on its outer periphery; The cover plate has multiple sets of third and fourth bonding rings corresponding to the first and second bonding rings located on the outer periphery of each of the sensitive structures.

18. A chip packaging structure as described in claim 1, characterized in that, The sensitive structure includes multiple structures, with a spacing between adjacent sensitive structures, and each sensitive structure is provided with a set of first bonding rings and second bonding rings on its outer periphery; The cover plate includes a plurality of covers, each cover plate having a set of third and fourth bonding rings corresponding to the first bonding ring and the second bonding ring located on the outer periphery of each of the sensitive structures; Alternatively, the cover plate may include at least one, wherein at least one cover plate has at least two sets of third and fourth bonding rings corresponding to the first and second bonding rings located on the periphery of the at least two sets of the sensitive structures.

19. A method for fabricating a chip packaging structure, characterized in that, Includes the following steps: A chip structure is provided, the chip structure having a first surface and a second surface disposed opposite to each other, a first bonding ring and a second bonding ring disposed on the first surface, the second bonding ring surrounding the outside of the first bonding ring, and a sensitive structure disposed on the side of the chip structure near the first surface and inside the first bonding ring; A cover plate is provided, the cover plate having a third surface and a fourth surface disposed opposite to each other, a third bonding ring and a fourth bonding ring being disposed on the third surface, the fourth bonding ring surrounding the outside of the third bonding ring; The cover plate is placed on the first surface of the chip structure, so that the first bonding ring and the third bonding ring are correspondingly bonded and connected, the second bonding ring and the fourth bonding ring are bonded and connected, and the cover plate and the chip structure form a sealed cavity to accommodate the sensitive structure inside the first bonding ring and the third bonding ring.

20. A wafer-level chip packaging structure, characterized in that, include: A chip wafer having a fifth surface and a sixth surface disposed opposite to each other, the chip wafer having at least one chip structure region on the fifth surface, the chip structure region having a sensitive structure, the sensitive structure being disposed on the side of the chip structure near the first surface, the chip structure region having a first bonding ring and a second bonding ring located on the fifth surface, the second bonding ring surrounding the outside of the first bonding ring, the first bonding ring being located on the outer periphery of the sensitive structure; A cover wafer has a seventh surface and an eighth surface disposed opposite to each other. The cover wafer has at least one cover region on the seventh surface corresponding to the chip structure region. The cover region has a third bonding ring and a fourth bonding ring located on the seventh surface. The fourth bonding ring surrounds the outside of the third bonding ring. The cover wafer covers the fifth surface of the chip wafer. The first bonding ring of the chip structure region is correspondingly bonded to the third bonding ring of the cover region. The second bonding ring of the chip structure region is bonded to the fourth bonding ring of the cover region. The cover region and the chip structure region form a sealing cavity inside the first bonding ring and the third bonding ring to accommodate the sensitive structure of the chip structure region. When the chip structure region includes multiple regions, there is a cutting channel region between adjacent chip structure regions; when the cover plate region includes multiple regions, there is a cutting channel region between adjacent cover plate regions.

21. A method for fabricating a wafer-level chip packaging structure, characterized in that, Includes the following steps: A chip wafer is provided, the chip wafer having a fifth surface and a sixth surface disposed opposite to each other, the chip wafer having at least one chip structure region on the fifth surface, the chip structure region having a sensitive structure, the sensitive structure being disposed on the side of the chip structure near the first surface, a first bonding ring and a second bonding ring being formed correspondingly in the chip structure region on the fifth surface, the second bonding ring surrounding the outside of the first bonding ring, the first bonding ring being located on the outer periphery of the sensitive structure; A cover wafer is provided, the cover wafer having a seventh surface and an eighth surface disposed opposite to each other, the cover wafer having at least one cover region corresponding to the chip structure region on the seventh surface, and a third bonding ring and a fourth bonding ring being formed in the cover region on the seventh surface, the fourth bonding ring surrounding the outside of the third bonding ring; The cover plate wafer is bonded to the chip wafer. The first bonding ring of the chip structure region is correspondingly bonded to the third bonding ring of the cover plate region. The second bonding ring of the chip structure region is bonded to the fourth bonding ring of the cover plate region. The cover plate region and the chip structure region form a sealed cavity inside the first bonding ring and the third bonding ring to accommodate the sensitive structure of the chip structure region.

22. The method for fabricating a wafer-level chip packaging structure as described in claim 21, characterized in that, The chip structure region includes multiple regions, and there is a cutting channel region between adjacent chip structure regions; the cover plate region includes multiple regions, and there is a cutting channel region between adjacent cover plate regions. It also includes cutting along the cutting channel area so that each of the chip structure areas forms a single chip package structure.

23. The method for fabricating a wafer-level chip packaging structure as described in claim 21, characterized in that, The first bonding ring and the third bonding ring include metal bonding rings, and the second bonding ring and the fourth bonding ring include insulating dielectric bonding rings; The cover wafer and the chip wafer are bonded using a hybrid bonding process.

24. The method for fabricating a wafer-level chip packaging structure as described in claim 21, characterized in that, At least one of the cover plate regions is an integral structure with the cover plate wafer, or at least one of the cover plate regions is bonded to the seventh surface of the cover plate wafer.

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