A method for manufacturing a semiconductor structure

Abstract

The embodiment of the present disclosure provides a preparation method of a semiconductor structure, which comprises the following steps: providing a first substrate, wherein the first substrate has a plurality of first chip areas and a plurality of first cutting areas, and a plurality of first connecting terminals are arranged in each first chip area; providing a plurality of chips, wherein each chip comprises a substrate and a plurality of second connecting terminals arranged in the substrate; connecting each chip with each first chip area, so that a first gap is formed between each connected chip, and each first cutting area is exposed; forming a filling layer in the first gap; and thinning the first substrate and the substrate, so that each first connecting terminal and each second connecting terminal are exposed.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing, and more particularly to a method for preparing a semiconductor structure. Background Technology

[0002] With the rapid growth in data capacity demand, increasing packaging density to improve integration and thus obtain higher storage capacity has become an important goal of integrated circuit manufacturing at this stage. In this context, interconnecting wafers or chips with the same or different functions has the advantages of high performance, low cost and high integration.

[0003] The technology of using micro-conductive bumps to stack wafers or chips vertically and achieve electrical connection has made certain progress compared with the method of interconnecting wafers or chips using wire bonding. It can improve chip integration density, shorten signal transmission path, reduce power consumption, and reduce package size. However, with the rapid development of high-performance computing, storage and mobile devices, more efficient interconnection methods between multiple wafers or chips need to be further optimized. Summary of the Invention

[0004] This disclosure provides a method for fabricating a semiconductor structure, including:

[0005] A first substrate is provided, the first substrate having a plurality of first chip regions and a plurality of first dicing regions, and a plurality of first connection terminals being disposed in each of the first chip regions;

[0006] Multiple chips are provided, each chip including a substrate and multiple second interconnects disposed in the substrate;

[0007] Each chip is connected to each corresponding first chip area, and a first gap is formed between the connected chips, exposing each first cutting area;

[0008] A filling layer is formed in the first gap;

[0009] The first substrate and the substrate are thinned to expose each first connection terminal and each second connection terminal.

[0010] In some embodiments, a plurality of chips are provided, including:

[0011] A second substrate is provided, the second substrate including a second chip region and a second dicing region, and each second connection terminal is disposed in the second chip region;

[0012] A first protective layer is formed on the second substrate;

[0013] At least part of the second cutting area is removed to separate the second chip area into multiple chips;

[0014] After separating the second chip area, and before connecting each chip to the corresponding first chip area, the first protective layer is removed.

[0015] In some embodiments, before forming the first protective layer, a first bonding layer is formed on the surface of the second substrate, and after forming the first bonding layer, a first protective layer covering the first bonding layer is formed, and each chip is connected to each first chip region through the first bonding layer.

[0016] In some embodiments, before connecting each chip to each first chip region, each chip and each first chip region are tested to determine the classification of each chip and each first chip region.

[0017] In some embodiments, connecting each chip to a corresponding first chip region includes at least one of the following:

[0018] At least some chips of the same classification are electrically connected to at least some of the first chip region;

[0019] At least some chips with different classifications are non-electrically connected to at least some of the first chip region.

[0020] In some embodiments, including:

[0021] The first chip area includes the first chip and the second chip, and each chip includes the third chip and the fourth chip;

[0022] Connecting each chip to its corresponding first chip area includes connecting the first chip to the third chip and connecting the second chip to the fourth chip, wherein the first chip and the third chip are good chips, and the second chip and the fourth chip are defective chips.

[0023] In some embodiments, connecting each chip to a corresponding first chip region includes:

[0024] A second bonding layer is formed on the surface of the first chip and the second chip. The second bonding layer is electrically connected to the first chip and is insulated from the second chip.

[0025] A first bonding layer is formed on the surfaces of the third chip and the fourth chip. The first bonding layer is electrically connected to the third chip and is insulated from the fourth chip.

[0026] In some embodiments, a second bonding layer is formed on the surfaces of the first chip and the second chip, including:

[0027] A first bonding medium layer is formed covering the surfaces of the first chip and the second chip. A first bonding pad electrically connected to a first connection terminal of the first chip is formed in the first bonding medium layer on the surface of the first chip. A virtual bonding pad not electrically connected to the second chip is formed in the first bonding medium layer on the surface of the second chip.

[0028] In some embodiments, thinning the first substrate and the substrate includes:

[0029] Perform the first thinning process to thin each substrate and filler layer, thereby exposing each second connection terminal;

[0030] Cut each first cutting area along the filling layer to complete the separation of each chip and each first chip area;

[0031] A second thinning process is performed to thin the first substrate, thereby exposing each of the first interconnect terminals.

[0032] In some embodiments, thinning the first substrate and the substrate includes:

[0033] Cut each first cutting area along the filling layer to complete the separation of each chip and each first chip area;

[0034] Perform the first thinning process to thin each substrate so that each second connection terminal is exposed;

[0035] A second thinning process is performed to thin the first substrate, thereby exposing each of the first interconnect terminals.

[0036] In some embodiments, at least a portion of the second dicing region is removed to separate the second chip region into multiple chips, including:

[0037] A portion of the second substrate is cut along the second cutting area to form a second gap between the second chip regions;

[0038] A second protective layer is formed on the surface of the second gap;

[0039] The second substrate is thinned to separate the second chip into multiple chips.

[0040] In some embodiments, a third substrate is also provided, the third substrate having a third chip region, the third chip region being connected to each of the first connection terminals or each of the second connection terminals, the third chip region being connected to each of the first connection terminals or each of the second connection terminals via microbumps or via a direct bonding structure.

[0041] The semiconductor structure fabrication method provided in this disclosure includes: providing a first substrate having multiple first chip regions and multiple first dicing regions, with multiple first interconnect terminals disposed in each first chip region; providing multiple chips, each chip including a substrate and multiple second interconnect terminals disposed in the substrate; connecting each chip to each corresponding first chip region, forming a first gap between the connected chips, the first gap exposing each first dicing region; forming a filling layer in the first gap; and thinning the first substrate and the substrate to expose each first interconnect terminal and each second interconnect terminal. In this disclosure, the first substrate can be a wafer structure, including multiple first chip regions, and the chip structure connected thereto is a single chip structure obtained by dicing the wafer. After the multiple chip structures are bonded to each of the multiple first chip regions, a filling layer is formed in the first gap between adjacent chips before performing the thinning process on the first substrate and the substrate. This ensures that both the first substrate and the chip structure have a large thickness during the bonding operation, preventing warping of the first substrate or chip structure during bonding and helping to improve the bonding yield. In addition, compared with the method of performing a thinning process on the first substrate and the chip structure before bonding, the method of performing a thinning process after bonding the first substrate and the chip structure prevents cracks (or chips) from forming on the first substrate or the chip structure due to the thinning operation performed before bonding during the bonding process, which further helps to improve the bonding yield.

[0042] Details of one or more embodiments of this disclosure are set forth in the following drawings and description. Other features and advantages of this disclosure will become apparent from the specification and drawings. Attached Figure Description

[0043] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0044] Figure 1 A flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure;

[0045] Figures 2 to 13 A schematic diagram of a semiconductor structure corresponding to a method for fabricating a semiconductor structure according to an embodiment of this disclosure;

[0046] Figure 14 This is a schematic diagram of the semiconductor structure during the fabrication process, provided in another embodiment of this disclosure;

[0047] Figure 15This is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure. Detailed Implementation

[0048] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0049] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0050] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0051] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0052] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0053] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0054] To increase packaging density, wafer-to-wafer bonding is a method to achieve multi-wafer or multi-chip connectivity. Before bonding, pre-processing operations, such as thinning, are usually performed on the wafers. This operation method can easily cause defects such as warping or cracking after bonding, affecting the yield of the bonding structure.

[0055] Based on this, the following technical solutions are proposed for embodiments of this disclosure:

[0056] This disclosure provides a method for fabricating a semiconductor structure, such as... Figure 1 The preparation method includes the following steps:

[0057] Step S101: Provide a first substrate, the first substrate having multiple first chip regions and multiple first dicing regions, and multiple first connection terminals disposed in each first chip region;

[0058] Step S102: Provide multiple chips, each chip including a substrate and multiple second connection terminals disposed in the substrate;

[0059] Step S103: Connect each chip to each first chip area accordingly, and a first gap is formed between the connected chips, exposing each first cutting area;

[0060] Step S104: Form a filling layer in the first gap;

[0061] Step S105: Thin the first substrate and the substrate to expose each first connection terminal and each second connection terminal.

[0062] In this embodiment, the first substrate can be a wafer structure including multiple first chip regions, and the connected chip structure is a single chip structure obtained by dicing the wafer. After the multiple chip structures are bonded to the multiple first chip regions, a filling layer is formed in the first gap between adjacent chips before performing a thinning process on the first substrate and the substrate. This ensures that both the first substrate and the chip structure have a large thickness during the bonding operation, preventing warping or other phenomena during bonding and improving the bonding yield. Furthermore, compared to performing a thinning process on the first substrate and chip structure before bonding, performing a thinning process after bonding prevents cracks (or chipping) in the first substrate or chip structure caused by pre-bonding thinning during bonding, further improving the bonding yield.

[0063] It should be understood that, although Figure 1 The steps are shown sequentially as indicated by the arrows, but they are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order in which these steps are performed; they can be executed in other orders. Figure 1 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0064] To make the above-mentioned objects, features, and advantages of this disclosure more apparent and understandable, the specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. In describing the embodiments of this disclosure in detail, for ease of explanation, the schematic diagrams may be partially enlarged without adhering to general proportions, and the schematic diagrams are merely examples and should not limit the scope of protection of this disclosure.

[0065] Figures 2 to 13 A schematic diagram of a semiconductor structure corresponding to a method for fabricating a semiconductor structure according to an embodiment of this disclosure; Figure 14 This is a schematic diagram of the semiconductor structure during the fabrication process, provided in another embodiment of this disclosure; Figure 15 This is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure.

[0066] First, execute step S101, as follows: Figure 2 and Figure 3 As shown, a first substrate 10 is provided, the first substrate 10 having a plurality of first chip regions C1 and a plurality of first dicing regions Q1, and a plurality of first connection terminals 11 disposed in each of the first chip regions C1.

[0067] In some embodiments, the first substrate 10 is a wafer structure, on which a plurality of first chip regions C1 and a plurality of first dicing regions Q1 located between the plurality of first chip regions C1 are disposed. When the plurality of first chip regions C1 are subsequently separated, the position of the first dicing region Q1 can be broken to achieve separation between the plurality of first chip regions C1.

[0068] In some embodiments, the first connection end 11 can be a conductive structure, such as a through-silicon via (TSV) structure, which is filled with a conductive material, such as a conductive metal. In some specific embodiments, the conductive material may include, but is not limited to, copper and aluminum.

[0069] In some embodiments, such as Figure 2 As shown, a first interconnect structure 12 is formed above the first connection end 11. A first dielectric layer L1 is disposed around the first interconnect structure 12. The first dielectric layer L1 can form an isolation effect between adjacent first interconnect structures 12. The material of the first dielectric layer L1 includes, but is not limited to, oxides, nitrides, and oxynitrides.

[0070] Continue to refer to Figure 2 In some embodiments, the first substrate 10 may also include a first functional structure 14, which may include, but is not limited to, a capacitor structure or a transistor structure, etc., without specific limitations.

[0071] In some embodiments, the first chip region C1 may contain multiple types of chip structures, such as a first chip C11 and a second chip C12. The first chip C11 may be a chip structure with good performance in all aspects (good die), while the second chip C12 may be a chip structure with performance that does not meet the usage requirements (bad die).

[0072] In some embodiments, such as Figure 2 As shown, the determination of the chip type located in the first chip area C1 can be obtained by forming a trench structure T to open the area where the top of the first interconnect structure 12 is located, and then performing relevant test operations.

[0073] Here, the test operations may include, but are not limited to, Wafer Acceptable Test (WAT), Chip Probing, or similar tests.

[0074] In some embodiments, such as Figure 3 As shown, Figure 3 Figures (1) and (2) are schematic diagrams of the semiconductor structures provided in different embodiments, showing the virtual bonding pad 132b under different configurations; after forming the first interconnect structure 12, the fabrication method further includes:

[0075] A second bonding layer 13 is formed over the first interconnect structure 12. The second bonding layer 13 includes a first bonding medium layer 131, a first bonding pad 132a, and a virtual bonding pad 132b.

[0076] In some embodiments, the first bonding pad 132a may have normal electrical connection with the first chip region C1 below, and the virtual bonding pad 132b may be a conductive structure with normal electrical connection with the first chip region C1 below. However, it is not limited to this. The virtual bonding pad 132b may also be a virtual conductive or non-conductive structure that does not have normal electrical connection with the first chip region C1 below. Specifically, it can be flexibly selected according to the actual situation, and no specific limitation is made here.

[0077] In some embodiments, the material of the first bonding dielectric layer 131 includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, aluminum oxide, aluminum nitride, amorphous silicon, silicon carbide, or spin-coated silicon glass. The bonding layer can be a single-layer or multi-layer structure.

[0078] In some specific embodiments, such as Figure 3 As shown in Figure (1), the materials of the first bonding pad 132a and the virtual bonding pad 132b include, but are not limited to, alloys formed from one or more of copper, gold, silver, aluminum, nickel, tungsten, titanium, tin, conductive graphene, or carbon nanotubes. However, this is not the only limitation; in other embodiments, such as... Figure 3 As shown in Figure (2), the material of the virtual bonding pad 132b may also include the same material as the first bonding medium layer 131.

[0079] Perform step S102, such as Figures 4 to 7 As shown, multiple chips C2 are provided, each chip C2 including a substrate 201 and multiple second connection terminals 21 disposed in the substrate 201.

[0080] In some embodiments, such as Figure 4 As shown, a second interconnect structure 22 is also formed above the second connection end 21. A second dielectric layer L2 is disposed around the second interconnect structure 22. The second dielectric layer L2 can form an isolation effect between adjacent second interconnect structures 22. The material of the second dielectric layer L2 includes, but is not limited to, oxides, nitrides, and oxynitrides.

[0081] In some embodiments, chip C2 may further include a second functional structure 24, which may include, but is not limited to, a capacitor or a transistor structure, etc., without specific limitations.

[0082] In some embodiments, such as Figures 4 to 7 As shown, multiple chips C2 are provided, including:

[0083] A second substrate 20 is provided, the second substrate 20 includes a second chip region C2a and a second dicing region Q2, and each second connection terminal 21 is disposed in the second chip region C2a;

[0084] A first protective layer P1 is formed on the second substrate 20;

[0085] At least part of the second cutting region Q2 is removed to separate the second chip region C2a into multiple chips C2;

[0086] After separating the second chip region C2a, and before connecting each chip C2 to each corresponding first chip region C1, the first protective layer P1 is removed.

[0087] In some embodiments, the second substrate 20 may also be a wafer structure, on which a plurality of second chip regions C2a and a plurality of second dicing regions Q2 located between the plurality of second chip regions C2a are disposed. When the plurality of second chip regions C2a are subsequently separated, the location of the second dicing region Q2 can be broken to achieve separation between the plurality of second chip regions C2a.

[0088] In some embodiments, the second chip region C2a may further include a third chip C21 and a fourth chip C22, wherein the third chip C21 can be a chip structure with good performance in all aspects (good die), and the fourth chip C22 can be a chip structure with performance that does not meet the usage requirements (bad die).

[0089] In some embodiments, such as Figure 4 As shown, the determination of the chip type located in the second chip region C2a can be obtained by forming a trench structure T to open the area where the top of the second interconnect structure 22 is located, and then performing relevant test operations.

[0090] The testing operations here may include, but are not limited to, electrical performance testing.

[0091] In some embodiments, the second connection end 21 may also be a conductive structure, such as a through-silicon via (TSV) structure, which is filled with a conductive material, such as a conductive metal. In some specific embodiments, the conductive material may include, but is not limited to, copper and aluminum.

[0092] In some embodiments, the material of the first protective layer P1 may include, but is not limited to, an oxide layer, such as silicon oxide. In some embodiments, the formation process of the first protective layer P1 includes, but is not limited to, atomic layer deposition (ALD) processes.

[0093] In some embodiments, such as Figure 6 and Figure 7 As shown, at least a portion of the second cutting region Q2 is removed, separating the second chip region C2a into multiple chips C2, including:

[0094] A portion of the second substrate 20 is cut along the second cutting region Q2, forming a second gap G2 between the second chip regions C2a;

[0095] A second protective layer P2 is formed on the surface of the second gap G2;

[0096] The second substrate 20 is thinned to separate the second chip region C2a into multiple chips C2.

[0097] In some embodiments, the process of cutting a portion of the second substrate 20 along the second cutting region Q2 to form a second gap G2 between the second chip regions C2a may include:

[0098] A groove-shaped structure (not shown) is formed in the second cutting area Q2 using a laser;

[0099] After obtaining the groove structure (not shown), a plasma cutting process is used to form the second gap G2.

[0100] In some embodiments, the second protective layer P2 may cover the sidewalls and bottom of the second gap G2.

[0101] In some embodiments, the material of the second protective layer P2 may be the same as or different from that of the first protective layer P1, such as silicon oxide, silicon nitride, organic thin film, etc.

[0102] It is understood that, in the embodiments of this disclosure, by forming a second protective layer P2 in the second gap G2 between adjacent second chip regions C2a, it is possible to effectively prevent damage to the internal interconnects of the chip structure exposed by the second gap G2 when the first protective layer P1 is removed, or to prevent contamination or damage to these structures.

[0103] In some embodiments, after the operation of removing the first protective layer P1 is performed, the second protective layer P2 may be retained, but this is not limited to this. In some cases, the second protective layer P2 may also be removed. Specifically, the choice can be made flexibly according to the actual situation, and no specific limitation is made here.

[0104] In this embodiment, the presence of the second protective layer P2 ensures that the chip sidewalls surrounding the second gap G2 are not exposed during the removal of the first protective layer P1, but are well protected. This effectively increases the range of materials that can be selected for the first protective layer P1, as well as the range of removal reagents that can be used to remove the first protective layer, providing greater flexibility.

[0105] In some embodiments, such as Figure 5 As shown, Figure 5 Figures (1) and (2) in the figure are semiconductor structures provided in different embodiments, and the virtual bonding structure 232b is a schematic diagram of the structure under different settings. Before forming the first protective layer P1, a first bonding layer 23 is formed on the surface of the second substrate 20. After forming the first bonding layer 23, a first protective layer P1 covering the first bonding layer 23 is formed. Each chip C2 is connected to each first chip region C1 through the first bonding layer 23.

[0106] Understandably, in this embodiment of the present disclosure, since the first protective layer P1 is formed after the first bonding layer 23 is formed, when the material at the second cutting region Q2 is removed after the formation of the first protective layer P1, the existing structure on the surface of the second substrate 20 can be effectively protected from contamination or damage, which helps to improve the various performances of the finally obtained semiconductor structure.

[0107] A first bonding layer 23 is formed over the second interconnect structure 22. The first bonding layer 23 includes a second bonding medium layer 231, a second bonding pad 232a, and a virtual bonding structure 232b.

[0108] In some embodiments, the second bonding pad 232a may have normal electrical connection with the lower second chip region C2a, and the virtual bonding structure 232b may be a conductive structure with normal electrical connection with the lower second chip region C2a. However, it is not limited to this and may also be a virtual conductive or non-conductive structure without normal electrical connection with the lower second chip region C2a. Specifically, it can be flexibly selected according to the actual situation, and no specific limitation is made here.

[0109] In some embodiments, the material of the second bonding dielectric layer 231 includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, aluminum oxide, aluminum nitride, amorphous silicon, silicon carbide, or spin-coated silicon glass. The bonding layer can be a single-layer or multi-layer structure.

[0110] In some specific embodiments, such as Figure 5As shown in Figure (1), the materials of the second bonding pad 232a and the virtual bonding structure 232b include, but are not limited to, alloys formed from one or more of copper, gold, silver, aluminum, nickel, tungsten, titanium, tin, conductive graphene, or carbon nanotubes, but are not limited thereto. In other embodiments, such as Figure 5 As shown in Figure (2), the material of the virtual bonding structure 232b may also include the same material as the second bonding medium layer 231.

[0111] Execute step S103, such as Figure 8 As shown, each chip C2 is connected to each first chip area C1, and a first gap G1 is formed between each chip C2 after connection. The first gap G1 exposes each first cutting area Q1.

[0112] In some embodiments, before connecting each chip C2 to each first chip region C1, each chip C2 and each first chip region C1 are tested to determine the classification of each chip C2 and each first chip region C1. The classification result may include chip structures with good performance belonging to the same classification, while chip structures with poor performance belonging to the same classification.

[0113] The types of tests here may include, but are not limited to, wafer acceptability test (WAT), chip probing test, or similar tests.

[0114] In some embodiments, connecting each chip C2 to each first chip region C1 includes at least one of the following:

[0115] At least a portion of chip C2 having the same classification is electrically connected to at least a portion of the first chip region C1;

[0116] At least a portion of chip C2, which has a different classification, is non-electrically connected to at least a portion of the first chip region C1.

[0117] In some embodiments, in a technical solution where at least a portion of chip C2 and at least a portion of the first chip region C1 are electrically connected to each other of the same classification, a variety of other cases may be further included:

[0118] (1) A scheme in which all the chips C2 in good condition can be bonded to all or part of the first chip region C1 in good condition;

[0119] (2) A scheme in which all the first chip regions C1 with good performance can be bonded to all or part of the chips C2 with good performance.

[0120] (3) A scheme in which all the chips C2 in a poor performance state can be bonded to all or part of the first chip area C1 in a poor performance state;

[0121] (4) A scheme in which all of the first chip regions C1 with poor performance can be bonded to all or part of the chips C2 with poor performance.

[0122] In some specific embodiments, at least a portion of the chips C2 having the same classification may be electrically connected to at least a portion of the first chip region C1 in all regions.

[0123] However, this is not the only option. In other embodiments, chip structures of the same type can be connected together in some areas, such as the middle area, while chip structures of different types can be connected together in other areas, such as the edge area or the location where the product is prone to failure for any reason. In this way, the bonding yield can be improved to a large extent, and the probability that a good chip cannot be produced due to poor position or other possible reasons during the bonding process and is deemed to be unsuitable for use can be reduced.

[0124] In some other embodiments, considering the reduction of process operation steps, when each chip C2 is correspondingly connected to each first chip region C1, and simultaneously: chips C2 of the same category are bonded to the first chip region C1, and chips C2 of different categories are bonded to the first chip region C1, multiple cases may be further included:

[0125] (1) All the chips C2 with good performance can be bonded to the first chip region C1 with good performance, and then the remaining first chip region C1 with good performance is bonded to the chip C2 with poor performance.

[0126] (2) All the first chip regions C1 with good performance can be bonded to some chips C2 with good performance, and then the remaining chips C2 with good performance are bonded to the first chip regions C1 with poor performance.

[0127] (3) Based on any of the above situations (1) or (2), the first chip region C1 with poor performance is combined with the chip C2 with poor performance, or it may be that at least part of the first chip region C1 with poor performance is not provided with a chip structure, or it may be that the chip C2 with poor performance is not provided with a chip structure.

[0128] In some embodiments, the bonding between the first chip region C1 and the chip C2 can be achieved using a hybrid bonding method.

[0129] In some specific embodiments, the first chip area C1 includes a first chip C11 and a second chip C12, and each chip C2 includes a third chip C21 and a fourth chip C22;

[0130] Connecting each chip C2 to each first chip area C1 includes: connecting the first chip C11 to the third chip C21, and connecting the second chip C12 to the fourth chip C22, wherein the first chip C11 and the third chip C21 are good chips, and the second chip C12 and the fourth chip C22 are defective chips.

[0131] Conventional techniques typically employ wafer-to-wafer (WoW) bonding, but this method has significant limitations in practice. Under ideal pairing conditions, this technique works well, but it's unsuitable in situations with low product yields (e.g., low yields of new products) or insufficient wafer pool size. This is because, after bonding two wafers, if one has a higher yield and the other a lower yield, the bonding yield, even without considering process yield losses, will be lowered due to the presence of the lower-yield wafer. Consequently, the number of structures that truly meet usage requirements after bonding is likely limited. Therefore, it's clear that wafer-to-wafer (WoW) bonding has significant limitations.

[0132] In particular, in the event of low yield rates for new products in the future, direct wafer-to-wafer bonding will result in significant yield losses.

[0133] Furthermore, even with a large number of bonding layers, if multiple chips are bonded to a single vertical area on a multi-layered wafer, and even one chip is defective, all the stacked chips in that area, even after undergoing complete process steps, will still be deemed unsuitable for use. In other words, the more bonding layers there are, the greater the risk of a decrease in bonding yield, increasing the number of scrapped products and the time and cost of rework.

[0134] In this embodiment, a chip-to-wafer (COW) bonding method is employed. By classifying the first chip region C1 and chip C2 before bonding, the bonding process allows for various combinations, such as bonding a third chip C21 (a high-performance chip in C2) to a high-performance first chip C11 (a high-performance chip in C1), and bonding a fourth chip C22 (a low-performance chip in C2) to a low-performance second chip C12 (a low-performance chip in C1). Alternatively, different classifications of chip structures can be bonded together or left unbonded, depending on the specific circumstances. This significantly controls the arrangement of low-performance chip structures in the resulting bonded structure. In many cases, this reduces the likelihood of low-performance chip structures randomly appearing in areas containing high-performance chip structures in the vertical direction, resulting in a semiconductor structure with improved bonding yield after the subsequent dicing operation.

[0135] In some embodiments, such as Figure 3 Figures (1) and (2) in the text, and Figure 5 As shown in Figures (1) and (2), each chip C2 is connected to each first chip region C1, including:

[0136] A second bonding layer 13 is formed on the surfaces of the first chip C11 and the second chip C12. The second bonding layer 13 is electrically connected to the first chip C11 and is insulated from the second chip C12 (see details). Figure 3 (Figures (1) and (2) in the text);

[0137] A first bonding layer 23 is formed on the surfaces of the third chip C21 and the fourth chip C22. The first bonding layer 23 is electrically connected to the third chip C21 and is insulated from the fourth chip C22 (see details). Figure 5 (Figures (1) and (2) in the text).

[0138] In some embodiments, such as Figure 3 As shown in Figures (1) and (2), a second bonding layer 13 is formed on the surfaces of the first chip C11 and the second chip C12, comprising:

[0139] A first bonding dielectric layer 131 is formed covering the surfaces of the first chip C11 and the second chip C12. A first bonding pad 132a electrically connected to the first connection terminal 11 of the first chip C11 is formed in the first bonding dielectric layer 131 on the surface of the first chip C11. A virtual bonding pad 132b not electrically connected to the second chip C12 is formed in the first bonding dielectric layer 131 on the surface of the second chip C12.

[0140] In this embodiment, the second bonding layer 13 formed on the surfaces of the first chip C11 and the second chip C12 may further include a first bonding dielectric layer 131, a first bonding pad 132a, and a virtual bonding pad 132b. The first bonding pad 132a is a normal conductive structure that has an electrical connection function with the first chip C11, while the virtual bonding pad 132b is a structure that does not have an electrical connection effect with the second chip C12.

[0141] In some embodiments, the implementation of the virtual bonding pad 132b having no electrical connection with the second chip C12 can include several cases:

[0142] One situation is, such as Figure 3 As shown in Figure (2), the operation steps of forming a groove and filling conductive material are not performed at the location of the virtual bonding pad 132b. Instead, the first bonding dielectric layer 131 is directly used as the virtual bonding pad 132b to achieve the isolation effect between the virtual bonding pad 132b and the second chip C12.

[0143] In this embodiment, since the formation of the virtual bonding pad 132b on the second chip C12 does not require material etching and filling steps, but is directly replaced by the first bonding dielectric layer 131, it helps to simplify the process, save process time and improve production efficiency.

[0144] Another situation is, such as Figure 3 As shown in Figure (1), the virtual bonding pad 132b is a conductive structure, but there is a first dielectric layer L1 between it and the first interconnect structure 12 to electrically isolate them, thereby achieving the effect of electrical isolation. That is to say, here, the virtual bonding pad 132b can be a normal conductive structure, but due to the insulating material underneath it, it cannot form an electrical connection with the second chip C12.

[0145] In some embodiments, such as Figure 5 As shown in Figures (1) and (2), a first bonding layer 23 is formed on the surfaces of the third chip C21 and the fourth chip C22, comprising:

[0146] A second bonding dielectric layer 231 is formed covering the surfaces of the third chip C21 and the fourth chip C22. A second bonding pad 232a electrically connected to the second connection terminal 21 of the third chip C21 is formed in the second bonding dielectric layer 231 on the surface of the third chip C21. A virtual bonding structure 232b not electrically connected to the fourth chip C22 is formed in the second bonding dielectric layer 231 on the surface of the fourth chip C22.

[0147] In this embodiment, the configuration of the virtual bonding structure 232b can be the same as the configuration of the virtual bonding pad 132b formed on the second chip C12, for example,

[0148] In one scenario, the steps of forming a groove and filling conductive material are not performed at the location of the virtual bonding structure 232b. Instead, the second bonding dielectric layer 231 is directly used as the virtual bonding structure 232b to achieve the isolation effect between the virtual bonding structure 232b and the fourth chip C22.

[0149] In this embodiment, since the virtual bonding structure 232b on the fourth chip C22 is directly replaced by the second bonding medium layer 231, it helps to simplify the process, save process time and improve production efficiency.

[0150] Another situation is, such as Figure 5 As shown in Figure (1), the virtual bonding structure 232b is a conductive structure, but there is a second dielectric layer L2 between it and the second interconnection structure 22 to electrically isolate them, thereby achieving the effect of electrical isolation. In other words, here, the virtual bonding structure 232b can be a normal conductive structure, but due to the insulating material underneath it, it cannot form an electrical connection with the fourth chip C22.

[0151] In this embodiment of the disclosure, when both the virtual bonding pad 132b and the virtual bonding structure 232b are conductive structures, the connection between the first chip region C1 and the chip C2 can be a hybrid bonding method, wherein the first bonding medium layer 131 and the second bonding medium layer 132 are bonded together, the first bonding pad 132a and the second bonding pad 232a are bonded together, and the virtual bonding pad 132b and the virtual bonding structure 232b are bonded together.

[0152] In addition, when the virtual bonding pad 132b and the virtual bonding structure 232b are dielectric layer materials, the first bonding dielectric layer 131 and the second bonding dielectric layer 232 are bonded together, the first bonding pad 132a and the second bonding pad 232a are bonded together, and the virtual bonding pad 132b and the virtual bonding structure 232b are bonded together.

[0153] Execute step S104, such as Figure 9 As shown, a filling layer 25 is formed in the first gap G1.

[0154] In some embodiments, the material of the filling layer 25 may include, but is not limited to, oxide materials, such as silicon oxide.

[0155] Execute step S105, such as Figure 9 , Figure 10 , Figure 11 , Figure 12Figures (1) and (2) in the text and Figure 13 As shown in Figures (1) and (2), Figure 12 Figures (1) and (2) in the text, and Figure 13 Figures (1) and (2) are schematic diagrams of the structure of the chip stack ST obtained by using different thinning operation steps; the first substrate 10 and the substrate 201 are thinned so that each first connection terminal 11 and each second connection terminal 21 are exposed.

[0156] In some embodiments, such as Figure 10 , Figure 11 and Figure 13 As shown in Figures (1) and (2), thinning the first substrate 10 and substrate 201 includes:

[0157] The first thinning process is performed to thin each substrate 201 and the filler layer 25, thereby exposing each second connection terminal 21 (see details). Figure 10 or Figure 11 );

[0158] Cut each first cutting region Q1 along the filling layer 25 to complete the separation of each chip C2 and each first chip region C1 (see details). Figure 13 (1) Figure in the middle;

[0159] The second thinning step is performed to thin the first substrate 10, thereby exposing each of the first connection terminals 11 (see details). Figure 13 (as shown in Figure (2)).

[0160] In some embodiments, such as Figure 11 As shown, after thinning the substrate 201 to expose the second connection terminal 21, and before cutting each first dicing region Q1 along the filling layer 25 to complete the separation of each chip C2 and each first chip region C1, the fabrication method may further include:

[0161] A first conductive structure 26 is formed on the second connection terminal 21. The first conductive structure 26 is used to realize the connection between chip C and other wafers or chips outside the first chip area C1.

[0162] Continue to refer to Figure 11 In some embodiments, the first conductive structure 26 may include one or a combination of a contact pad structure or a microbump B structure.

[0163] Understandably, when the structure obtained after performing the cutting operation to separate each chip C2 and each first chip region C1 still needs to be bonded to other chip structures, the operation of forming the first conductive structure 26 before the cutting operation can be adopted.

[0164] In this embodiment, after the chip C2 is bonded to the first substrate 10, a thinning process is first performed on the surface of the substrate 201 of the chip C2 and the side where the filling layer 25 between the chips C2 is located, and then a cutting process is performed to separate each chip C2 from each first chip area C1. This method helps to reduce the process complexity when thinning the substrate 10 on the side where the chip C2 is located and improves production efficiency.

[0165] In other embodiments, such as Figure 9 and Figure 12 Figure (1) and Figure 12 As shown in Figure (2), the thinning of the first substrate 10 and substrate 201 can also be achieved by the following operation:

[0166] First, cut each first cutting region Q1 along the filling layer 25. After separating each chip C2 and each first chip region C1, the chip stack ST is obtained (see details). Figure 12 (Figure 1) in the middle, then:

[0167] The first thinning process is performed to thin each substrate 201, thereby exposing each second connection terminal 21 (see details). Figure 12 (2) in the middle;

[0168] The second thinning step is performed to thin the first substrate 10, thereby exposing each of the first connection terminals 11 (see details). Figure 12 (Figure 2) in the middle.

[0169] In this embodiment, after the chip C2 is bonded to the first substrate 10, a dicing process is performed first, followed by a thinning process on the substrate 201 and the first substrate 10 respectively. This ensures that the first connection end 11 and the second connection end 21 are exposed after the dicing process, which can effectively avoid contamination and damage during the dicing process.

[0170] Meanwhile, in this embodiment, the method of performing a bonding process between chip C2 and the first chip region C1 before thinning the substrate 201 or the first substrate 10 ensures that both the first substrate 10 and the chip C2 structure have a greater thickness during the bonding operation. This prevents warping of the first substrate 10 or the chip C2 structure during bonding (thinner structures are more prone to warping), thus improving the bonding yield. Furthermore, compared to performing a thinning process on the first substrate 10 and the chip C2 before bonding, performing the thinning process after bonding prevents cracks (or chipping) in the first substrate 10 or the chip C2 caused by the pre-bonding thinning operation, further contributing to improved bonding yield.

[0171] In some embodiments, such as Figure 14 As shown, after obtaining Figure 11 Following the structure shown, the fabrication method further includes providing a third substrate 30, the third substrate 30 having a third chip region C3, a third dicing region Q3 between the third chip regions C3, connecting the third chip regions C3 to each of the first connection terminals 11 or each of the second connection terminals 21, and connecting the third chip regions C3 to each of the first connection terminals 11 or each of the second connection terminals 21 to each other through microbumps B or through a direct bonding structure.

[0172] In some embodiments, a third connection terminal 31 is formed in the third substrate 30. The third connection terminal 31 may be further provided with a contact structure, such as a contact pad structure or other conductive structure. The third connection terminal 31 is connected to the second connection terminal 21 of the chip C2. The material of the third connection terminal 31 may be the same as or different from the material of the first connection terminal 11 or the second connection terminal 21, and no specific limitation is made here.

[0173] Continue to refer to Figure 14 In some specific embodiments, after the first chip region C1 is bonded to the chip C2, the bonding with the third substrate 30 can be achieved using microbumps B.

[0174] Furthermore, in some embodiments, after the bonding of the third substrate 30 is completed, the third substrate 30 is bonded to other structures, such as... Figure 15 The bonding between the intermediate substrate 50 or other wafers or chip structures can also be achieved using microbump structures.

[0175] In some embodiments, a third interconnect structure 32 is also formed on the third substrate 30, and a third dielectric layer L3 is disposed around the third interconnect structure 32.

[0176] In some embodiments, the third chip region C3 may include a fifth chip C31 and a sixth chip C32, wherein the fifth chip C31 may be a good chip and the sixth chip C32 may be a bad chip.

[0177] In some embodiments, a third bonding layer 33 is further formed on the third substrate 30. The third bonding layer includes a third bonding dielectric layer 331, a third bonding pad 332a, and a dummy bonding pad 332b. The material of the third bonding dielectric layer 331 can be the same as the material of the first bonding dielectric layer 131 or the second bonding dielectric layer 231. Meanwhile, the materials and configuration of the third bonding pad 332a and the dummy bonding pad 332b can be configured with reference to the materials and configuration of the aforementioned first bonding pad 132a (or bonding pad 232a) and the aforementioned dummy bonding pad 132b (or dummy bonding structure 232b), respectively. These will not be elaborated here.

[0178] It should be noted that, although in Figure 14 The diagram shows the third substrate 30 connected to the second connection terminal 21 on the side where chip C2 is located. In some other embodiments, the third substrate 30 may also be connected to the first connection terminal 11 on the side where the first chip region C1 is located. The specific connection can be determined according to the actual situation, and no specific limitation is made here.

[0179] In some embodiments, the way the third substrate 30 is connected to the first connection terminal 11 or the second connection terminal 21 can include various situations and is not limited to these. Figure 14 As shown, in the formation Figure 11 The structure shown is followed by a bonding operation directly with the third substrate 30. In some cases, the connection between the third substrate 30 and the first connection terminal 11 or the second connection terminal 21 may also include:

[0180] exist Figure 11 The resulting structure undergoes a cutting process to obtain Figure 13 After the chip stack ST shown in Figure (2), the chips in the chip stack ST are bonded to multiple third chip regions C3 according to whether the chip structure in the chip stack ST is a good chip.

[0181] In some embodiments, when the third chip region C3 is connected to each of the first connection terminals 11 or each of the second connection terminals 21 via microbumps B, the material of the microbumps B may include, but is not limited to, conductive metals, such as copper.

[0182] In some embodiments, each chip stack ST is correspondingly connected to each third substrate 30, including at least one of the following:

[0183] At least a portion of the chip stack ST having the same classification is electrically connected to at least a portion of the third chip region C3;

[0184] At least a portion of the chip stack ST with different classifications is non-electrically connected to at least a portion of the third chip region C3.

[0185] The considerations regarding when to use the same or different classification connections in different situations or regions can be found in the information regarding the connection between the first chip area C1 and chip C2 mentioned above, and will not be repeated here.

[0186] The direct bonding structure between the third chip area C3 and each of the first connection terminals 11 or each of the second connection terminals 21 can be understood as the connection between the corresponding third chip area C3 and... Figure 11 When bonding the chip C2 in the structure shown, the bonding can be performed by corresponding bonding of the regions containing dielectric material and corresponding bonding of the regions containing conductive material.

[0187] Understandably, when good and bad chips coexist in the same vertical area due to various possible reasons, direct bonding helps reduce the difficulty of separating the two (good and bad chips) later. After separation, the chip with good performance can be used to bond with a good chip on another wafer or directly with a chip with good performance.

[0188] In some embodiments, in forming Figure 14 Following the structure shown, further bonding processes with more wafers or chip structures can be performed, which will not be listed here. Information on the processes and related settings used can be found in any of the above embodiments.

[0189] In some embodiments, the number of layers of the chip structure stacked in the vertical direction can be greater than or equal to 2 layers, but is not limited thereto. It can also be 3, 4, 5, 6, 7, 8, 9, 10, a dozen, several dozen, or even more layers, etc. There is no specific limitation here, and it can be flexibly set according to the actual situation.

[0190] In some embodiments, such as Figure 15 As shown, in the formation Figure 14 Following the structure shown, or a multi-layered structure based on it, the preparation method further includes:

[0191] A dicing process is performed to separate multiple vertically stacked chip structures that are arranged adjacent to each other in a direction parallel to the first substrate 10 to form a chip stack ST.

[0192] After the dicing process is performed, an encapsulation compound layer 40 is formed on at least the sidewalls of the chip stack ST;

[0193] It is connected to the interposer substrate 50, which includes a second conductive structure 51 adjacent to the chip stack ST and a third conductive structure 52 away from the chip stack ST.

[0194] In some embodiments, the encapsulation compound layer 40 may also cover the top of the chip stack ST.

[0195] In some embodiments, the material of the encapsulating compound 40 may be, for example, epoxy resin, phenolic resin, polyimide, silicone, or spin-coated silicone glass. The encapsulating compound 40 can protect the encapsulation structure from external dust, moisture, and mechanical shock, thereby improving the reliability of the encapsulation structure.

[0196] In some embodiments, the second conductive structure 51 may include, but is not limited to, a microbump structure formed of a conductive material, the material of which may include, but is not limited to, copper.

[0197] In any of the above embodiments, the first chip area C1, chip C2 and the third chip area C3 may include, but are not limited to, dynamic random access memory (DRAM) chips or other types of chips, without specific limitations.

[0198] In some embodiments, the number of layers of the chip structure located on the interposer substrate 50 can be 2 layers (2-Hi structure), 4 layers (4-Hi structure), or 8 layers (8-Hi structure), or it can be a structure with more than or equal to 8 layers (8-Hi structure), such as 16 layers (16-Hi structure). Specifically, it can be flexibly selected according to the actual situation, and no specific limitation is made here.

[0199] The technical features described in the embodiments provided in this disclosure can be arbitrarily combined without conflict.

[0200] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A first substrate is provided, the first substrate having a plurality of first chip regions and a plurality of first dicing regions, and a plurality of first connection terminals being disposed in each of the first chip regions; A plurality of chips are provided, each chip including a substrate and a plurality of second connection terminals disposed in the substrate; Each chip is connected to each of the first chip regions, and a first gap is formed between the connected chips, exposing each of the first cutting regions. A filling layer is formed in the first gap; The first substrate and the substrate are thinned to expose each of the first connection terminals and each of the second connection terminals.

2. The preparation method according to claim 1, characterized in that, Multiple chips are available, including: A second substrate is provided, the second substrate including a second chip region and a second dicing region, and each of the second connection terminals is disposed in the second chip region; A first protective layer is formed on the second substrate; At least a portion of the second cutting region is removed to separate the second chip region into multiple chips; After separating the second chip region, and before connecting each chip to the corresponding first chip region, the first protective layer is removed.

3. The preparation method according to claim 2, characterized in that, Before forming the first protective layer, a first bonding layer is formed on the surface of the second substrate. After forming the first bonding layer, a first protective layer covering the first bonding layer is formed, and each chip is connected to each of the first chip regions through the first bonding layer.

4. The preparation method according to claim 1, characterized in that, Before connecting each chip to each of the first chip regions, each chip and each of the first chip regions are tested to determine the classification of each chip and each of the first chip regions.

5. The preparation method according to claim 4, characterized in that, Connecting each of the aforementioned chips to each of the first chip regions includes at least one of the following: At least a portion of the chips having the same classification are electrically connected to at least a portion of the first chip region; At least a portion of the chips with different classifications are non-electrically connected to at least a portion of the first chip region.

6. The preparation method according to claim 1, characterized in that, include: The first chip area includes a first chip and a second chip, and each of the chips includes a third chip and a fourth chip; Connecting each of the chips to the corresponding first chip area includes: connecting the first chip to the third chip, and connecting the second chip to the fourth chip, wherein the first chip and the third chip are good chips, and the second chip and the fourth chip are defective chips.

7. The preparation method according to claim 6, characterized in that, Connecting each of the aforementioned chips to the corresponding first chip region includes: A second bonding layer is formed on the surface of the first chip and the second chip, the second bonding layer is electrically connected to the first chip, and the second bonding layer is insulated from the second chip; A first bonding layer is formed on the surfaces of the third chip and the fourth chip. The first bonding layer is electrically connected to the third chip and is insulated from the fourth chip.

8. The preparation method according to claim 7, characterized in that, A second bonding layer is formed on the surfaces of the first chip and the second chip, including: A first bonding medium layer is formed covering the surfaces of the first chip and the second chip. A first bonding pad electrically connected to the first connection terminal of the first chip is formed in the first bonding medium layer on the surface of the first chip. A virtual bonding pad not electrically connected to the second chip is formed in the first bonding medium layer on the surface of the second chip.

9. The preparation method according to claim 1, characterized in that, Thinning the first substrate and the substrate includes: Perform a first thinning process to thin each of the substrates and the filler layer, thereby exposing each of the second connection terminals; Cut each of the first cutting regions along the filling layer to complete the separation of each chip and each of the first chip regions; A second thinning process is performed to thin the first substrate, thereby exposing each of the first connection terminals.

10. The preparation method according to claim 1, characterized in that, Thinning the first substrate and the substrate includes: Cut each of the first cutting regions along the filling layer to complete the separation of each chip and each of the first chip regions; Perform a first thinning process to thin each of the substrates so that each of the second connection terminals is exposed; A second thinning process is performed to thin the first substrate, thereby exposing each of the first connection terminals.

11. The preparation method according to claim 2, characterized in that, At least a portion of the second dicing region is removed to separate the second chip into a plurality of said chips, including: A portion of the second substrate is cut along the second cutting area to form a second gap between the second chip regions; A second protective layer is formed on the surface of the second gap; The second substrate is thinned to separate the second chip into multiple chips.

12. The preparation method according to claim 1, characterized in that, It also includes providing a third substrate having a third chip region, the third chip region being connected to each of the first connection terminals or each of the second connection terminals, the third chip region being connected to each of the first connection terminals or each of the second connection terminals via microbumps or via a direct bonding structure.

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