An internal structure of a half-bridge module circuit package

Abstract

The application relates to an internal structure of a half-bridge module circuit package, which comprises a bottom plate and a ceramic substrate; a chip is directly welded on a copper foil of the ceramic substrate, and the chip comprises Die1 and Die2 chips and freewheeling diodes SBD1 and SBD2 chips; the Die1 chip and the Die2 chip share a drain-source common electrode pin to respectively constitute upper and lower bridge circuits. The product packaging structure shortens the lead distance from the main power chip to the electrode pin, reduces the stray inductance to below 10 nH, lays a foundation for high-frequency operation, and simultaneously, EMI is smaller, and electromagnetic radiation is greatly reduced; the product packaging structure is consistent in the lead distance from the two chips to the gate G1 and the Kelvin electrode pin, avoids high-frequency switch abnormality caused by driving signal distortion, shares the common electrode, reduces the parasitic parameters between devices, reduces signal transmission delay, effectively reduces the volume, increases the power density, and reduces the manufacturing cost, and has a broad market prospect.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging, and more specifically to the internal structure of a novel half-bridge module circuit package. Background Technology

[0002] Silicon carbide (SiC) power devices, as wide-bandgap devices, possess advantages such as high voltage and high temperature resistance, low on-resistance, fast switching speed, and low loss. Currently, most commercial SiC devices still employ traditional silicon-based component packaging methods. For example, in practical circuit applications, high-power devices widely use half-bridge packaging, which encapsulates two switching transistors into a single module, such as the ME3 and ME2 type half-bridge modules. Traditional packaging technology is mature, low-cost, and compatible with and can replace existing Si-based devices. However, traditional packaging structures have large stray inductances, which can lead to greater voltage overshoot and oscillations at extremely high di / dt, causing increased voltage stress, losses, and electromagnetic interference problems.

[0003] like Figure 1 As shown, the ME2 (34-type half-bridge) module first solders the back of the chip to the substrate, then leads it to the side electrodes via metal bonding wires, and finally performs molding or potting. Its structure includes a heat dissipation substrate, a ceramic copper-clad laminate, the chip, bonding wires, a casing, and electrode terminals. While this package provides some heat dissipation and electrical performance, it also has the following problems: 1. The gate and Kelvin terminals of the chip are extended from the extension line of the connection between the two chips to the side. The connection distance of the G-KS signal applied to the control terminal of the chip is too long, resulting in excessive stray inductance in the circuit application. 2. The different lengths of the control electrode G-KS signal loop also hinder the further increase of the switching frequency, otherwise it is easy to cause signal distortion; 3. Excessive size is not conducive to miniaturization of equipment, so it is necessary to improve the packaging structure and increase power density. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention aims to provide a package structure with stray inductance below 10nH, similar inductance in the drive circuit, higher switching frequency, lower EMI, and smaller size, thereby improving product reliability, saving packaging costs, and truly maximizing the high performance of silicon carbide devices.

[0005] To achieve the above objectives, this case provides the following technical solution: An internal structure of a half-bridge module circuit package includes a base plate and a ceramic substrate, wherein the upper surface of the ceramic substrate is formed by etching copper foil to form a circuit. The chips are directly soldered onto the copper foil of the ceramic substrate, including Die1 chip and Die2 chip, as well as freewheeling diodes SBD1 chip and SBD2 chip; Relative to the center connection between Die1 and Die2 chips, the pins are located on the top and bottom sides of the ceramic substrate, including the drain pin, the drain-source common electrode pin, the source pin, and the parallel G1 pin, KS1 pin, G2 pin, and KS2 pin. The electrodes of the Die1 chip are connected to the drain pin, the drain-source common electrode pin, the G1 pin, and the KS1 pin, respectively, forming an upper bridge circuit; the electrodes of the Die2 chip are connected to the drain-source common electrode pin, the source pin, the G2 pin, and the KS2 pin, respectively, forming a lower bridge circuit.

[0006] Furthermore, the source S1 of the Die1 chip is connected to the drain-source common electrode pin through a wire bonding process, and the drain D2 of the Die2 chip is connected to the drain-source common electrode pin through a die bonding and soldering process, thereby realizing the connection between the upper bridge circuit and the lower bridge circuit.

[0007] Furthermore, the gate G1 and Kelvin electrode KS1 of the Die1 chip have first and second leads extending from their front sides, respectively connected to the G1 pin and the KS1 pin; similarly, the gate G2 and Kelvin electrode KS2 of the Die2 chip have first and second leads extending from their front sides, respectively connected to the G2 pin and the KS2 pin; the first and second leads are perpendicular to the direction of the center line connecting the Die1 chip and the Die2 chip.

[0008] Furthermore, the freewheeling diodes SBD1 and SBD2 are located directly above the Die1 and Die2 chips, respectively, and are parallel to and consistent with the direction of their wiring.

[0009] Compared with the ME2 type half-bridge module commonly found in the market, the advantages of this invention are: 1. The packaging structure of this product arranges the control signal electrode terminals (G1, KS1, G2, KS2) in parallel in the vertical direction of the connection between the two main power chips Die1 and Die2. This shortens the lead distance from the main power chip to the module pin and reduces the parasitic inductance of the module circuit to less than 10nH, which is far lower than the 20nH stray inductance of the ME2 type.

[0010] 2. At the same time, G1&KS1 and G2&KS2 have the same parameters, which allows the signal to remain consistent in higher frequency scenarios, reducing signal distortion and greatly reducing electromagnetic radiation.

[0011] 3. The product's packaging structure also effectively reduces the size by optimizing the electrode terminal layout and the connection method of the main power chip. The size is half that of the existing ME2 (34mm) type half-bridge module, which makes the power density of this product higher.

[0012] 4. The packaging structure of this product is also suitable for packaging next-generation semiconductor gallium oxide and diamond chips, and has broad market prospects. Attached Figure Description

[0013] Figure 1 This is a diagram of a traditional packaging structure.

[0014] Figure 2 This is a diagram of the internal structure of the half-bridge module in this application.

[0015] Figure 3 This is a schematic diagram of the pin structure of the half-bridge module circuit package of this application.

[0016] Figure 4 This is a schematic diagram of another pin structure for the half-bridge module circuit package of this application.

[0017] Figure 5 This is the circuit schematic of the half-bridge circuit in this application. Detailed Implementation

[0018] The present invention will be further described in detail below with reference to embodiments, so that those skilled in the art can implement it based on the description.

[0019] like Figure 2 As shown, this application provides an internal structure of a half-bridge module circuit package, including: It includes a base plate a and a ceramic substrate b. The base plate a serves as the heat dissipation base for the entire module and has good thermal conductivity and mechanical support capabilities. The ceramic substrate b provides electrical insulation and also enables circuit connections through the etching of copper foil c on its upper surface. The MOS chip is directly soldered onto the copper foil c of the ceramic substrate b, including Die1 chip 8 and Die2 chip 9; The pins are located on the upper and lower sides of the ceramic substrate b, including drain pin 3, drain-source common electrode pin 2, source pin 1, and parallel pins G1 pin 4, KS1 pin 5, G2 pin 6, and KS2 pin 7. And two sets of freewheeling diodes, SBD1 chip 10 and SBD2 chip 11, are soldered onto the copper foil c of the ceramic substrate b and arranged in parallel with Die1 chip 8 and Die2 chip 9.

[0020] In the above embodiment, two sets of chips, namely Die1 chip and Die2 chip, are used to construct the upper bridge circuit and the lower bridge circuit, respectively. The drain D1 of Die1 chip 8 and the cathode of a set of SBD1 chips 10 are connected to the drain pin 3 through the internal circuit of the ceramic substrate b; the source S1 of Die1 chip 8 and the anode of SBD1 chip 10 are connected to the drain-source common electrode pin 2 through aluminum wire first and then through copper foil c on the ceramic substrate b.

[0021] Similarly, the drain D2 of Die2 chip 9 and the cathode of another set of SBD2 chips 11 are connected to the drain-source common electrode pin 2 through the internal circuit of ceramic substrate b; the source S2 of Die2 chip 9 and the anode of SBD2 chip 11 are connected to the source pin 1 through aluminum wire first and then through copper foil c on ceramic substrate b.

[0022] In other words, the source S1 of Die1 chip 8 and the anode of SBD1 chip 10, and the drain D2 of Die2 chip 9 and the cathode of SBD2 chip 11, are all connected to the common drain-source electrode pin 2 by copper foil c on the ceramic substrate b, sharing a single electrode pin, forming a series connection between the upper bridge circuit and the lower bridge circuit. This method not only reduces the parasitic parameters between devices, but also effectively reduces the size of the package structure and lowers the manufacturing cost.

[0023] The gate G1 and Kelvin electrode KS1 of Die1 chip 8 are respectively led out with first lead 12 and second lead 13 on their front side, and connected to G1 pin 4 and KS1 pin 5 respectively; similarly, the gate G2 and Kelvin electrode KS2 of Die2 chip 9 are led out with first lead 12 and second lead 13 on their front side, and connected to G2 pin 6 and KS2 pin 7 respectively. Figure 2 As shown, since the gate and Kelvin are both located in the vertical direction from the connection between Die1 and Die2 chips, while the gate and Kelvin of the traditional ME2 (34mm) type half-bridge module are both located at the left or right end of the ceramic substrate, the lead distance of this application is shorter. This front lead-out method of this application also significantly shortens the signal path and reduces parasitic inductance. At the same time, the same lead path is also suitable for higher switching frequencies.

[0024] In this application, all electrode terminals (D1, S1 / D2, S2, G1, KS1, G2, KS2) are arranged in parallel on the top and bottom sides of the chip, forming a symmetrical and compact layout. This layout not only reduces the overall size of the module to half that of the existing ME2 (34-type half-bridge) module, but also significantly shortens the lead distance from the chip to the terminals, thereby effectively reducing stray inductance, which is measured to be below 10nH, far lower than the 20nH of the traditional 34-type module.

[0025] Meanwhile, due to the shortened lead path and reduced inductance, the voltage overshoot and electromagnetic radiation (EMI) of the module during high-frequency switching are effectively suppressed, improving the electromagnetic compatibility (EMC) of the system and making it suitable for applications with higher frequencies and higher power densities.

[0026] The layout orientation of the two sets of freewheeling diodes SBD1 & SBD2 is consistent with the soldering positions and wire bonding directions of the Die1 & Die2 chips, facilitating automated production and consistency control. These diodes, together with the MOS chip, form a complete half-bridge circuit, providing freewheeling current when the MOS chip is off, thus enhancing the overall reliability of the module.

[0027] This packaging structure is not only suitable for current mainstream silicon carbide (SiC) MOSFET chips, but also compatible with next-generation wide bandgap semiconductor materials, such as gallium oxide and diamond chips. It has good packaging adaptability and structural scalability, and can be widely used in fields with high power density, high frequency and high reliability requirements, such as AI server power supply HVDC, charging piles, photovoltaic inverters, new energy vehicles, and industrial motor drives.

[0028] Although the embodiments of the present invention have been disclosed above, they are not limited to the applications listed in the specification and embodiments. They can be applied to various fields suitable for the present invention, and those skilled in the art can easily make other modifications, for example, from... Figure 3 The pin structure is modified into Figure 4 The pin structure. Therefore, without departing from the general concept defined by the claims and their equivalents, the present invention is not limited to the specific details.

Claims

1. An internal structure of a half-bridge module circuit package, characterized in that, It includes a base plate (a) and a ceramic substrate (b), wherein a circuit is formed on the upper surface of the ceramic substrate (b) by etching copper foil (c); The chips are directly soldered onto the copper foil (c) of the ceramic substrate (b), including Die1 chip (8) and Die2 chip (9), as well as freewheeling diode SBD1 chip (10) and SBD2 chip (11). Relative to the center line connecting Die1 chip (8) and Die2 chip (9), the pins are set on the upper and lower sides of the ceramic substrate (b), including drain pin (3), drain-source common electrode pin (2), source pin (1) and parallel to it G1 pin (4), KS1 pin (5), G2 pin (6) and KS2 pin (7). The electrodes of the Die1 chip (8) are connected to the drain pin (3), the drain-source common electrode pin (2), the G1 pin (4), and the KS1 pin (5) respectively, forming an upper bridge circuit; the electrodes of the Die2 chip (9) are connected to the drain-source common electrode pin (2), the source pin (1), the G2 pin (6), and the KS2 pin (7) respectively, forming a lower bridge circuit.

2. The internal structure of the half-bridge module circuit package according to claim 1, characterized in that, The source S1 of the Die1 chip (8) is connected to the drain-source common electrode pin (2) through a wire bonding process, and the drain D2 of the Die2 chip (9) is connected to the drain-source common electrode pin (2) through a die bonding and soldering process, thereby realizing the connection between the upper bridge circuit and the lower bridge circuit.

3. The internal structure of the half-bridge module circuit package according to claim 1, characterized in that, The gate G1 and Kelvin KS1 of the Die1 chip (8) are respectively led out with a first lead (12) and a second lead (13) from their front side, and are respectively connected to the G1 pin (4) and the KS1 pin (5); the gate G2 and Kelvin KS2 of the Die2 chip (9) are also led out with a first lead (12) and a second lead (13) from their front side, and are respectively connected to the G2 pin (6) and the KS2 pin (7); the first lead (12) and the second lead (13) are perpendicular to the direction of the center line connecting the Die1 chip (8) and the Die2 chip (9).

4. The internal structure of the half-bridge module circuit package according to claim 2, characterized in that, The freewheeling diode SBD1 chip (10) and SBD2 chip (11) are located directly above the Die1 chip (8) and Die2 chip (9), respectively, and are aligned with the wire bonding direction of the Die1 chip (8) and Die2 chip (9).

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