Panel level semiconductor package interconnect bonding method

Abstract

The present application relates to a kind of panel level semiconductor package element bonding method, prepare large-area packaging substrate with bevel slot, each slot side wall is arranged along the base plate pad of step surface arrangement, to be packaged chip is fixed in array form on the surface of carrying fixture, keep the arrangement posture of the active face of chip upward.By carrying out distributed multi-point tension clamping to large-area packaging substrate, collect the full surface shape data of substrate under clamping state and adjust the tension of each clamping point, correct the warping deformation of large-area substrate.The corrected large-area packaging substrate and chip array complete global accurate alignment and fit, make bevel slot and the mutual engagement of single chip periphery form element step shallow cavity structure.Divide the substrate after fitting into multiple groups and carry out parallel processing partition, cooperate with the lead interconnection of layering pad in element step shallow cavity to complete element step bonding operation, realize panel level semiconductor package high precision, high consistency, low signal loss and the purpose of structure stable element step wire bonding processing.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a panel-level semiconductor packaging element-level bonding method. Background Technology

[0002] As semiconductor packaging technology iterates towards large-size panel-level mass production, high-density miniaturization, and high-frequency, high-speed transmission, the drawbacks of traditional single-chip discrete packaging processes—low efficiency and poor consistency—are becoming increasingly apparent, making them unsuitable for large-scale mass production. Currently, conventional panel-level bonding packaging often employs a planar pad layout and overall bonding process. After substrate formation, large-area board warping and uneven local stress are common problems, easily leading to subsequent alignment misalignment, bonding misalignment, and bonding accuracy failure. Simultaneously, the planar pad arrangement concentrates signal leads of different rates and functions on the same plane. Excessive wiring density can easily cause signal crosstalk, increased transmission loss, and other electrical performance defects. Conventional processing paths also suffer from localized heat accumulation, high risk of secondary deformation, and limited bonding yield. These factors make it impossible to simultaneously achieve mass production efficiency, structural stability, and high-frequency electrical performance in panel-level packaging, thus hindering the process upgrades and performance improvements of high-end panel-level semiconductor packaging products. Summary of the Invention

[0003] The main objective of this invention is to provide a panel-level semiconductor packaging unilevel bonding method. By preparing a large-area packaging substrate with an array of beveled slots and stepped layered pads, and combining it with multi-point tension deformation correction, global precise alignment bonding, and partitioned staggered parallel bonding processes, the method achieves the goal of high-precision, high-consistency, low-loss, and secondary deformation unilevel wire bonding manufacturing of panel-level semiconductor packaging.

[0004] To achieve the above objectives, the present invention provides a panel-level semiconductor packaging element-level bonding method, comprising the following steps:

[0005] A large-area packaging substrate with an array of beveled slots is prepared, and substrate pads arranged in layers along the stepped surface are arranged on the sidewalls of each slot.

[0006] The chips to be packaged are arranged in an array and fixed on the surface of the support fixture, with the active side of each chip facing upwards and the chip pads arranged accordingly.

[0007] The large-area packaging substrate is subjected to peripheral distributed multi-point tension clamping. The full surface shape data of the large-area packaging substrate after clamping is collected. The tension of each clamping point is adjusted according to the full surface shape data to correct the warping deformation of the substrate.

[0008] The corrected large-area packaging substrate is fully aligned and bonded to the chip array to be packaged on the carrier fixture. Each inclined slot is correspondingly fastened to the periphery of a single chip. The sidewall of the slot and the active surface of the chip form a primal shallow cavity. The chip pad is located at the bottom of the primal shallow cavity. The substrate pad is arranged in layers along the sidewall of the primal shallow cavity.

[0009] According to the preset partitioning rules, the large-area packaging substrate after full-area alignment and bonding is divided into multiple parallel processing partitions. Each partition simultaneously carries out wire bonding operations according to the preset travel path to complete the wire interconnection between the chip pads in the shallow cavity of each element level and the corresponding layered substrate pads.

[0010] Furthermore, the step of fabricating a large-area packaging substrate with an array of beveled slots includes:

[0011] The slot contour structure is determined by combining the external dimensions of the chip to be packaged, the mechanical constraints of packaging, and the high-frequency transmission requirements.

[0012] The morphology detection unit is pre-activated to monitor the morphology of the step surface of the slot sidewall of the substrate in real time and synchronously outputs the monitoring signal to the etching control unit. The synchronous array etching process is used to batch form the entire inclined slot array on the surface of the substrate.

[0013] The wiring is patterned stepwise along the corresponding height steps of each slot sidewall, and independent substrate pads are prepared on each step to obtain a large-area packaging substrate with a layered pad inclined slot array.

[0014] Furthermore, the step of batch forming a full-surface beveled slot array on the surface of a substrate using a synchronous area array etching process includes:

[0015] Based on the preset double-step inclined plane contour processing parameters, the etching energy is released in stages to process the groove sidewall layer by layer;

[0016] Real-time acquisition of sidewall morphology parameters of all slots in a single substrate, and synchronous feedback to correct etching output power and compensate for processing deviations;

[0017] After the groove etching is completed, the transition area of ​​the stepped surface of all groove sidewalls is smoothed to make the transition area of ​​the stepped surface continuous, and the shape and specifications of all inclined groove sidewalls are consistent after processing.

[0018] Furthermore, the step of fixing the chips to be packaged in an array arrangement onto the surface of the support fixture includes:

[0019] A global positioning reference mark matching the outline of a single chip and the array spacing is set on the surface of the support fixture;

[0020] The chips to be packaged are sequentially placed into the preset station of the carrier fixture according to the array arrangement order, and the chips are aligned with the reference mark to complete the alignment and positioning.

[0021] All chips to be packaged are fixed to the carrier fixture station using a temporary bonding medium, maintaining a stable posture with the active surface of the chip facing upwards, thus completing the loading and fixing of the array-arranged chips.

[0022] Furthermore, the steps of performing peripheral distributed multi-point tension clamping on the large-area packaging substrate, collecting full-surface shape data after clamping, and correcting substrate warpage deformation include:

[0023] The number of clamping units, the unit spacing, and the initial clamping force are determined based on the overall size and thickness of the substrate. Multiple sets of independent and controllable clamping units are arranged along the four edges of the substrate, and the substrate edges are clamped synchronously by the clamping units to complete multi-point tension clamping.

[0024] Before clamping, the reference surface shape data of the substrate in its free state is collected in advance. During the entire clamping process, the height offset of the substrate relative to the reference surface shape in the clamping state is continuously collected to generate a full-coverage surface shape dataset.

[0025] The surface shape dataset is retrieved to match the tension compensation values ​​of each clamping unit. The clamping force is dynamically and finely adjusted point by point to counteract the uneven deformation of the substrate, resulting in a large-area packaging substrate with completed surface shape correction.

[0026] Furthermore, the step of fully aligning and bonding the corrected large-area packaging substrate with the array of chips to be packaged on the carrier fixture includes:

[0027] The stroke and angle motion parameters of the substrate clamping fixture are retrieved as alignment motion constraints. All clamping fixture linkage control parameters are retrieved simultaneously. Based on a unified motion timing, the coordinated action of multiple clamping units is completed. The full-domain visual coordinate information of the large-area packaging substrate slot array and the carrier fixture chip array is collected simultaneously, and the overall pose compensation between the two arrays is calculated.

[0028] The relative spatial position of the substrate clamping fixture and the carrier fixture is adjusted synchronously according to the pose compensation amount to achieve high-precision full-area alignment of the slot and the chip.

[0029] Multiple sets of downward actuators are driven to output uniform loads synchronously, and the substrate is pushed down in segments along the vertical direction of the substrate. During the descent of the substrate, the gap value between the substrate and the chip is collected in real time, and the descent feed speed is dynamically adjusted according to the gap value until each inclined slot completely covers the outer area of ​​the corresponding single chip. The sidewall of the slot and the active surface of the chip are mutually enclosed to form a complete elementary shallow cavity structure, resulting in a panel composite blank in which the substrate and the chip array are bonded together.

[0030] Furthermore, the step of driving multiple sets of downward actuators to synchronously output uniform loads and continuously push the substrate downwards in segments along the vertical direction of the substrate includes:

[0031] Multiple sets of synchronous pressing actuators are arranged along the entire area of ​​the substrate, and each set of pressing mechanisms outputs equal pressing load synchronously;

[0032] During the pressing operation, the gap data between the substrate and the chip is continuously collected, and the feed stroke of the pressing actuator is adjusted in real time based on the gap data;

[0033] By maintaining a constant bonding pressure and allowing the substrate to stand for a preset time, the relative spatial position of the substrate and the chip array is locked, resulting in a panel composite blank with stable alignment and bonding.

[0034] Furthermore, the step of arranging the substrate pads in layers along the sidewall stepped surfaces of the shallow cavity includes:

[0035] Based on the preset signal transmission performance of chip pins, two types of pad grouping specifications are defined, and the corresponding step elevation ranges of the two types of pads are defined by matching the slot contour structure.

[0036] Match the chip pads corresponding to high transmission rate pins to the low-level substrate pads of adjacent chips, and match the chip pads corresponding to power supply pins and low-speed signal pins to the high-level substrate pads of distant chips.

[0037] The patterning of the substrate pads is completed sequentially along each surface to form a layered interconnect wiring structure that adapts to the different signal transmission requirements.

[0038] Furthermore, according to preset partitioning rules, the large-area packaging substrate after full-area alignment and bonding is divided into multiple parallel processing partitions, and each partition simultaneously performs wire bonding operations according to a preset travel path, including:

[0039] Based on the overall size of the panel composite blank and the number of parallel execution units of the bonding equipment, equal-sized independent processing zones are defined, and the zone boundary coordinates and global travel paths are generated.

[0040] After receiving the device start-up trigger signal, an independent wire bonding execution unit is matched for each processing zone, and each unit retrieves the corresponding zone's dedicated travel path program.

[0041] Multiple bonding execution units simultaneously start the partitioning operation, sequentially completing the layered pad lead interconnection of all the sub-level shallow cavities within the partition along the preset path, thus completing the full-area panel sub-level lead bonding process.

[0042] Furthermore, the step of each zone simultaneously carrying out pilot bonding operations according to a preset travel path also includes:

[0043] The program for the specific travel path of the partition is invoked. The bonding points within the partition are processed sequentially according to the alternating arrangement of rows, and the interval processing time is set between adjacent processing points.

[0044] Retrieve the layered pad layout data to distinguish the substrate pads corresponding to different elevation steps in the shallow cavity of the first step, and complete the layered interconnection by matching the corresponding lead forming shape according to the signal transmission performance.

[0045] The interface and status parameters of each bonding point are collected in real time. The collected parameters are transmitted to the quality judgment unit to generate abnormal point feedback signals. Based on the feedback signals, the defect points are located and the repair welding process is started. After completion, a panel composite blank with bonding integrity meets the standard is obtained.

[0046] The panel-level semiconductor packaging element-level bonding method provided by this invention has the following beneficial effects:

[0047] This invention addresses the structural defects and process limitations of existing panel-level packaging technologies by proposing a novel step-by-step bonding method for panel-level semiconductor packaging. It involves fabricating a structured substrate with an array of beveled slots and stepped, layered pads. The chip and slots enclose a step-by-step shallow cavity three-dimensional interconnect structure, overcoming the wiring limitations of traditional planar bonding. The substrate processing stage employs a combined detection and etching process, effectively ensuring the consistency of the slot structure throughout the board. Combined with peripheral distributed multi-point tension clamping and dynamic tension correction, it precisely eliminates large-area substrate warpage, significantly improving overall alignment and bonding accuracy. Differentiated stepped pads are matched to different functional signals, effectively optimizing high-speed signal transmission paths, reducing signal loss and crosstalk interference, and improving packaging electrical stability. The combination of parallel panel partitioning and staggered bonding processes effectively disperses processing heat accumulation, avoiding secondary substrate deformation. While ensuring batch packaging efficiency, it improves overall bonding process consistency and yield, balancing mass production capability, structural stability, and high-frequency performance of panel-level packaging. Attached Figure Description

[0048] Figure 1 This is a flowchart illustrating a panel-level semiconductor packaging element-level bonding method in one embodiment of the present invention;

[0049] Figure 2 This is a schematic diagram of a double-level inclined shallow cavity elevation structure with first-order bonding in one embodiment of the present invention;

[0050] Figure 3 This is a schematic diagram of the structure of a panel-level semiconductor packaging element-level bonding method in one embodiment of the present invention;

[0051] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0052] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0053] Reference Figure 1 This is a flowchart illustrating a panel-level semiconductor packaging element-level bonding method proposed in this invention, comprising the following steps:

[0054] S1, Prepare a large-area packaging substrate with an array of inclined slots, and arrange substrate pads arranged in layers along the stepped surface on the sidewalls of each slot.

[0055] S2, the chips to be packaged are arranged in an array and fixed on the surface of the carrier fixture, with the active side of each chip facing upwards and the chip pads are arranged.

[0056] S3, perform peripheral distributed multi-point tension clamping on the large-area packaging substrate, collect the full surface shape data of the large-area packaging substrate after clamping, and adjust the tension of each clamping point according to the full surface shape data to correct the warping deformation of the substrate.

[0057] S4. The corrected large-area packaging substrate is fully aligned and bonded to the chip array to be packaged on the carrier fixture. Each inclined slot is correspondingly fastened to the periphery of a single chip. The sidewall of the slot and the active surface of the chip form a shallow cavity of the first level. The chip pad is located at the bottom of the shallow cavity of the first level. The substrate pad is arranged in layers along the sidewall of the shallow cavity of the first level.

[0058] S5 divides the large-area packaging substrate after full-area alignment and bonding into multiple parallel processing zones according to the preset partitioning rules. Each zone simultaneously carries out wire bonding operations according to the preset travel path to complete the wire interconnection between the chip pads in the shallow cavity of each element level and the corresponding layered substrate pads.

[0059] As described in step S1 above, this step is the substrate structuring process of the panel-level hierarchical bonding method of the present invention. Unlike traditional planar slotless packaging substrates, this step specifically prepares a large-area packaging substrate with an array of beveled slots. By constructing an array of beveled slot structures on the substrate surface and arranging the substrate pads layer by layer along the stepped surface on the sidewalls of each slot, the substrate itself possesses vertical layered pad layout characteristics. Through the design of the structured substrate, a structural foundation is provided for the subsequent enclosing of the chip to form a hierarchical shallow cavity structure. Simultaneously, the layered interconnect channels are constructed in advance, which can adapt to the needs of subsequent differentiated signal routing and short-pitch interconnects.

[0060] As described in step S2 above, by fixing all the chips to be packaged in a regular array on the surface of the support fixture and uniformly limiting the arrangement of the chips with their active surfaces facing upwards, the chip pads of each chip maintain a uniform spatial position and exposure state. This step achieves standardized arrangement of the chip array through fixture constraints, matching the sloping slot array specifications of the large-area packaging substrate, avoiding problems such as positional deviations and inconsistent orientations caused by the independent placement of individual chips. This lays a uniform and stable chip array foundation for subsequent precise alignment and batch bonding of the large-area substrate, adapting to the batch process logic of parallel manufacturing at the panel level.

[0061] As described in step S3 above, to address the inherent technical defects in panel-level packaging that are prone to occur in large-size packaging substrates, such as global warpage, local deformation, and uneven stress distribution, a peripheral distributed multi-point tension clamping method is adopted to constrain the large-area packaging substrate as a whole. By collecting the actual full-surface shape data of the substrate under clamping conditions, the tension of each clamping point is adjusted differentially based on the actual surface shape deviation, so as to achieve precise correction of substrate warpage deformation, effectively ensuring the overall flatness and dimensional stability of the large-area substrate, eliminating the hidden dangers of alignment deviation, poor bonding, and insufficient bonding accuracy caused by deformation, and meeting the high-precision process requirements of subsequent global alignment bonding and batch wire bonding.

[0062] As described in step S4 above, the high-precision, large-area packaging substrate with deformation correction is fully aligned and bonded to the standardized chip array. The substrate is then assembled by fastening the beveled slot to the periphery of a single chip, causing the slot sidewalls and the active surface of the chip to enclose each other, forming the core of this invention: the primal shallow cavity structure. The structure formed in this step fixes the chip pads at the bottom of the primal shallow cavity. The substrate pads are arranged in layers along the sidewalls based on the slot's stepped surface, ultimately forming a stable vertically layered spatial layout of the pads. This differs from the traditional two-dimensional interconnect structure of planar bonding, providing core structural support for subsequent layered lead interconnection, optimized signal transmission paths, and avoidance of wiring congestion. Simultaneously, the entire array structure is formed in one step, meeting the requirements of efficient panel-level manufacturing.

[0063] As described in step S5 above, to address the issues of large-area substrate processing range, low single-point processing efficiency, and difficulty in ensuring overall process consistency, the laminated large-area substrate is modularly partitioned using preset partitioning rules, forming multiple parallel processing partitions that can operate independently. Based on the synchronous execution of wire bonding operations along preset paths in each partition, precise interconnection between chip pads and layered substrate pads in each level of shallow cavity is completed in batches. The parallel processing mode significantly improves the overall processing efficiency of panel-level packaging, and standardized path planning ensures the process consistency of all level shallow cavity interconnect structures across the entire area, stably realizing the panel-level level bonding of this invention.

[0064] In one embodiment, step S1, the step of fabricating a large-area packaging substrate with an array of beveled slots, includes:

[0065] The slot contour structure is determined by combining the external dimensions of the chip to be packaged, the mechanical constraints of packaging, and the high-frequency transmission requirements.

[0066] The morphology detection unit is pre-activated to monitor the morphology of the step surface of the slot sidewall of the substrate in real time and synchronously outputs the monitoring signal to the etching control unit. The synchronous array etching process is used to batch form the entire inclined slot array on the surface of the substrate.

[0067] The wiring is patterned stepwise along the corresponding height steps of each slot sidewall, and independent substrate pads are prepared on each step to obtain a large-area packaging substrate with a layered pad inclined slot array.

[0068] Reference Figure 2 This invention provides a schematic diagram of a double-layered inclined shallow cavity elevation structure with first-order bonding in one embodiment. In specific implementations, considering the large-size, array-based processing characteristics of panel-level packaging, precise fabrication of the structured packaging substrate is achieved. The entire process employs a linked detection and processing approach, avoiding the problems of poor consistency and insufficient structural adaptability in traditional panel slotting processes. During the slot outline structure determination stage, the inner perimeter assembly boundary of the slot is limited based on the actual external dimensions of the chip to be packaged. The overall structural strength and shape parameters of the slot are defined by combining the overall structural mechanical tolerance conditions and thermal deformation constraints of the panel-level packaging. Simultaneously, impedance and loss design requirements for high-frequency signal transmission are matched to comprehensively determine the overall slot outline and stepped surface layout structure suitable for batch packaging and high-frequency operating conditions. Before slot forming processing, the onboard morphology detection unit is activated in advance, enabling it to enter a full-domain real-time monitoring state. It performs full-coverage real-time sampling of the substrate's processing area. The monitoring unit continuously generates sidewall stepped surface forming morphology signals and transmits them synchronously to the etching control unit in real time, providing a data basis for real-time control of the etching process. Based on this, a synchronous array etching process is performed. Relying on the whole-board synchronous processing mechanism, the overall etching and forming of all array slots on the surface of a large-area substrate is completed in one go, realizing synchronous processing and forming of all slots and eliminating the forming differences caused by processing in different areas. After the mechanical structure of the slots is formed, a zoned and step-by-step patterned wiring process is adopted for the stepped positions of different heights on the sidewalls of each slot. The substrate surface pattern exposure, area opening, metal layer deposition and pattern curing processes are completed in sequence. Electrically isolated substrate pads are independently prepared on each stepped surface, so that the sidewalls of each slot form a stepped layered pad layout. Finally, a large-area packaging substrate with a regular structure, layered pad arrangement, and adaptability to the step bonding process is obtained.

[0069] In one embodiment, the step of batch forming a full-surface beveled groove array on the surface of a substrate using a synchronous area array etching process includes:

[0070] Based on the preset double-step inclined plane contour processing parameters, the etching energy is released in stages to process the groove sidewall layer by layer;

[0071] Real-time acquisition of sidewall morphology parameters of all slots in a single substrate, and synchronous feedback to correct etching output power and compensate for processing deviations;

[0072] After the groove etching is completed, the transition area of ​​the stepped surface of all groove sidewalls is smoothed to make the transition area of ​​the stepped surface continuous, and the shape and specifications of all inclined groove sidewalls are consistent after processing.

[0073] In practice, this step is a refinement process for the high-precision forming of the double-tiered structure of the beveled slot. It is used to ensure the structural uniformity and step transition regularity of the slots across the entire area of ​​the large-area substrate, adapting to the subsequent chip alignment and bonding requirements. During processing, the equipment system pre-loads the solidified double-tiered beveled contour processing parameters, distinguishes the slope and depth processing standards of different steps, and adopts a progressive etching logic, releasing the corresponding amount of etching energy in stages to sequentially complete the layer-by-layer peeling and forming of the lower and higher steps of the slot. This accurately replicates the double-tiered variable slope sidewall structure, ensuring that the internal step structure of a single slot is regular and controllable. Throughout the etching process, a comprehensive topographic acquisition operation is initiated simultaneously. This continuously collects actual topographic parameters such as sidewall slope, step height, and sidewall flatness of all array slots within a single substrate. The real-time acquired parameters are dynamically compared with preset standard parameters, generating power compensation and control signals that are fed back to the etching power output module in real time. By dynamically correcting the etching output power of each area, local etching deviations occurring during the processing of large-area substrates are compensated, achieving uniform slot forming accuracy across the entire board. After all main slot etching processes are completed, the transition areas of the step connections on all slot sidewalls are uniformly smoothed and regularized. This removes microscopic protrusions, edges, and step structures remaining from the etching process, eliminating structural abrupt changes at step connection points. This creates a continuous and stable transition between adjacent steps, ultimately ensuring uniform specifications for the topography, step structure, and transition forms of all beveled slot sidewalls on the entire substrate. This provides a high-precision structural foundation for subsequent shallow cavity shaping and stable wiring of layered pads.

[0074] In one embodiment, step S2, which involves fixing the chips to be packaged onto the surface of the support fixture in an array arrangement, includes:

[0075] A global positioning reference mark matching the outline of a single chip and the array spacing is set on the surface of the support fixture;

[0076] The chips to be packaged are sequentially placed into the preset station of the carrier fixture according to the array arrangement order, and the chips are aligned with the reference mark to complete the alignment and positioning.

[0077] All chips to be packaged are fixed to the carrier fixture station using a temporary bonding medium, maintaining a stable posture with the active surface of the chip facing upwards, thus completing the loading and fixing of the array-arranged chips.

[0078] In practical implementation, this step is used to complete the standardized and high-precision assembly and fixation of the pre-packaging chip array at the panel level. It solves the technical problems of single-chip positional offset, inconsistent orientation, and poor array matching during large-area batch packaging, ensuring precise matching of the overall chip array parameters with the subsequent substrate slot array parameters, guaranteeing full-area alignment and bonding accuracy. First, based on the external dimensions, pin distribution specifications of the chip to be packaged, and the array layout parameters of the large-area packaging substrate, uniformly deploys full-area positioning reference marks on the surface of the carrier fixture. The single-cell contour and station spacing of each reference mark are perfectly adapted to the shape of the single chip and the overall array layout specifications, establishing a unified reference coordinate system for chip and subsequent substrate alignment, eliminating array assembly reference deviations from the tooling structure level. Subsequently, the automated equipment, according to the preset array row and column order, places the chips to be packaged one by one into the corresponding independent preset stations on the carrier fixture. During chip placement, the reference marks serve as the alignment reference, and the planar offset and rotation angle of the chips are corrected in real time, ensuring that each chip completes precise alignment and positioning within the standard station range, guaranteeing uniform placement, angle, and height of all chips on the entire board. After the chip is aligned and positioned, a temporary bonding medium is applied to the contact interface between the chip and the carrier fixture. The chip is steadily fixed by the controllable bonding and limiting effect of the temporary bonding medium. Throughout the process, the chip is constrained and kept in a uniform assembly posture with the active surface facing upward. This ensures that the chip pads on the active surface of the chip are fully exposed without obstruction or displacement, avoiding assembly abnormalities such as chip slippage, flipping, and misalignment in subsequent continuous processes such as equipment transfer, substrate alignment, and lamination. Finally, the orderly array loading and fixing of the chips across the entire area is completed, forming a chip array carrier structure with uniform posture, precise position, and strong stability. This lays a regular chip array foundation for the subsequent precise snap-fitting of large-area substrates and uniform molding of the multi-level shallow cavity structure.

[0079] In one embodiment, step S3, which involves performing peripheral distributed multi-point tension clamping on the large-area packaging substrate, collecting full-surface shape data after clamping, and correcting substrate warpage deformation, includes:

[0080] The number of clamping units, the unit spacing, and the initial clamping force are determined based on the overall size and thickness of the substrate. Multiple sets of independent and controllable clamping units are arranged along the four edges of the substrate, and the substrate edges are clamped synchronously by the clamping units to complete multi-point tension clamping.

[0081] Before clamping, the reference surface shape data of the substrate in its free state is collected in advance. During the entire clamping process, the height offset of the substrate relative to the reference surface shape in the clamping state is continuously collected to generate a full-coverage surface shape dataset.

[0082] The surface shape dataset is retrieved to match the tension compensation values ​​of each clamping unit. The clamping force is dynamically and finely adjusted point by point to counteract the uneven deformation of the substrate, resulting in a large-area packaging substrate with completed surface shape correction.

[0083] Reference Figure 3 This is a schematic diagram of a panel-level semiconductor packaging element-level bonding method in one embodiment of the present invention. In specific implementation, this step is to adapt to the deformation correction process specific to large-area panel-level packaging, and specifically solve the problems of free-state warping, local concavity and convexity, and uneven stress distribution that are common in large-size ultra-thin packaging substrates. Such deformation will directly lead to subsequent process defects such as substrate and chip array misalignment, slot snapping misalignment, and bonding accuracy failure. It is a core key process to ensure the overall processing accuracy of the panel. First, the clamping scheme is quantitatively matched based on the overall shape and thickness parameters of the large-area packaging substrate. Large-size substrates are matched with more clamping units and uniform spacing, and thin substrates are matched with appropriate initial clamping force to avoid squeezing deformation due to excessive clamping and failure to constrain the substrate posture due to excessive clamping. According to the matching results, multiple sets of independently adjustable clamping units are evenly distributed around the perimeter of the substrate. All clamping units perform clamping actions synchronously, forming distributed multi-point constraints on the substrate edges, completing the overall tension clamping and positioning of the substrate, so that the substrate is in a dynamically adjustable constraint state. Before formal tension correction, the equipment first performs a full-area surface shape scan on the substrate in a free and stretched state without external force constraints. It collects the original flatness reference data of the substrate and establishes a reference surface shape model, which serves as the sole reference standard for subsequent deformation deviation judgment. Throughout the entire process of clamping the substrate with gradually applied force, the surface shape detection equipment continuously scans the entire area of ​​the substrate, collects the height and undulation offset of each area of ​​the substrate relative to the reference surface shape model in real time, summarizes and integrates the deformation data of all points, and generates a full-area surface shape dataset covering the entire area of ​​the substrate, accurately reflecting the warping position, deformation direction, and deformation amplitude of the entire substrate. The system then retrieves the full-area surface shape dataset and independently matches the corresponding tension compensation parameters for each set of clamping units. It distinguishes different deformation states of the substrate, such as convexity, concavity, and local warping, and dynamically fine-tunes the real-time clamping force of each clamping unit point by point. By using differentiated tension compensation to offset the internal stress and deformation error of the substrate itself, the entire substrate is gradually corrected to a flat state. Finally, a high-precision large-area packaging substrate with uniform surface flatness, no local deformation, and stable posture is obtained, which fully meets the high-precision processing requirements of subsequent full-area alignment bonding and array-type inter-level bonding.

[0084] In one embodiment, step S4, which involves fully aligning and bonding the corrected large-area packaging substrate with the array of chips to be packaged on the carrier fixture, includes:

[0085] The stroke and angle motion parameters of the substrate clamping fixture are retrieved as alignment motion constraints. All clamping fixture linkage control parameters are retrieved simultaneously. Based on a unified motion timing, the coordinated action of multiple clamping units is completed. The full-domain visual coordinate information of the large-area packaging substrate slot array and the carrier fixture chip array is collected simultaneously, and the overall pose compensation between the two arrays is calculated.

[0086] The relative spatial position of the substrate clamping fixture and the carrier fixture is adjusted synchronously according to the pose compensation amount to achieve high-precision full-area alignment of the slot and the chip.

[0087] Multiple sets of downward actuators are driven to output uniform loads synchronously, and the substrate is pushed down in segments along the vertical direction of the substrate. During the descent of the substrate, the gap value between the substrate and the chip is collected in real time, and the descent feed speed is dynamically adjusted according to the gap value until each inclined slot completely covers the outer area of ​​the corresponding single chip. The sidewall of the slot and the active surface of the chip are mutually enclosed to form a complete elementary shallow cavity structure, resulting in a panel composite blank in which the substrate and the chip array are bonded together.

[0088] In practical implementation, this step is the core process for forming the shallow cavity structure of the present invention and realizing the integrated assembly of the substrate and chip array. It solves the technical problems of asynchronous multiple fixtures, large alignment deviations, easy chip damage from downward pressure impacts, and poor cavity forming consistency in traditional panel-level bonding processes, ensuring that the structure of all packaging units on the whole board is uniform and the assembly accuracy is controllable. In the alignment preparation stage, the control system first reads the preset motion parameters of the substrate clamping fixture, using the effective stroke and motion angle range of the fixture as hardware motion boundary constraints to prevent alignment interference caused by overtravel or angular movement; at the same time, it retrieves the linkage control parameters of all edge clamping units to unify the motion sequence and response rhythm of the entire clamping fixture, so that multiple independent clamping units maintain a highly coordinated motion state, eliminating the overall alignment deviation caused by local fixture movement lag or offset. Based on this hardware collaboration, the vision acquisition system simultaneously performs a full-domain coordinate scan of the upper substrate slot array and the lower support fixture chip array, acquiring the precise coordinates, angles, and positions of all stations in both arrays. By calculating and comparing the overall array deviation and the deviation of each individual station, the system calculates the overall translational and rotational pose compensation of the substrate relative to the chip array, providing data support for precise alignment. Subsequently, the control system, based on the calculated pose compensation, drives the clamping fixture to fine-tune its spatial position and attitude, achieving precise one-to-one alignment between the large-area substrate slots and the individual chips below, ensuring uniform alignment accuracy across all stations on the entire board. After alignment, multiple sets of pressing actuators are activated, with all pressing points simultaneously outputting uniform and stable pressing loads. A segmented, progressive descent method is used to push the entire substrate vertically downward, avoiding the impact stress generated by a single rapid descent. Throughout the substrate descent process, the gap detection unit continuously collects real-time gap values ​​between the substrate slots and the chips. The system dynamically and adaptively adjusts the pressing feed speed based on gap changes. A conventional feed rate is used to improve efficiency when the gap is large, while the feed rate is reduced as the gap approaches the bonding stage, achieving a flexible bonding process. This continues until each beveled slot completely covers the outer area of ​​the corresponding single chip. The slot sidewall space and the chip's active surface together form a closed and regular stepped shallow cavity structure, ensuring the chip pads are stably positioned at the bottom of the cavity and the layered substrate pads are fixed to the stepped sidewall surface of the cavity. This ultimately completes the integrated bonding of the entire substrate and the chip array, resulting in a structurally regular, precisely aligned, and damage-free panel composite blank.

[0089] In one embodiment, the step of driving multiple sets of downward actuators to synchronously output uniform loads and continuously push the substrate downwards in segments along the vertical direction of the substrate includes:

[0090] Multiple sets of synchronous pressing actuators are arranged along the entire area of ​​the substrate, and each set of pressing mechanisms outputs equal pressing load synchronously;

[0091] During the pressing operation, the gap data between the substrate and the chip is continuously collected, and the feed stroke of the pressing actuator is adjusted in real time based on the gap data;

[0092] By maintaining a constant bonding pressure and allowing the substrate to stand for a preset time, the relative spatial position of the substrate and the chip array is locked, resulting in a panel composite blank with stable alignment and bonding.

[0093] In practical implementation, this step is a refined pressure and positioning process for flexible bonding and steady-state forming of the substrate and chip array. It solves the problems of uneven pressure under single-point pressure on large-area substrates, local gap deviations, and chip damage or bonding misalignment caused by instantaneous pressure impacts, ensuring the consistency of shallow cavity bonding and structural stability of all elements on the entire board. First, for the full coverage of the large-area packaging substrate, multiple sets of pressure actuators are evenly distributed on the substrate surface. The traditional single-point pressure method is replaced by a multi-point distributed pressure structure. The equipment control system uniformly and synchronously regulates the output load of all pressure actuators, so that the pressure load output at each pressure point is equal and the force application sequence is synchronized, ensuring uniform stress on the entire substrate and eliminating the problem of misaligned bonding caused by local warping or excessive force on one side of the large-size substrate. During the continuous pressing operation, the detection unit collects real-time data on the overall gap between the substrate slot and the active surface of the chip, dynamically feeding back the bonding progress and gap deviation at various points on the substrate. The control system uses the real-time gap data as the basis for adjustment, fine-tuning the feed stroke of each pressing actuator in real time. For areas with excessively large gaps, the feed stroke is appropriately increased; for gaps approaching the bonding area, the feed stroke is slowed down, achieving dynamic balance correction of the overall bonding progress and avoiding local over- or under-pressure defects. Once the substrate is pressed to the preset bonding position, all pressing actuators maintain a constant bonding pressure. By allowing the pressure to settle, the minor elastic deformation and residual position deviations generated during the dynamic pressing process are eliminated, ensuring that the enclosure structure of the substrate slot and the chip is fully shaped and stably locked in the relative spatial assembly position of the substrate and the chip array. Finally, a panel composite blank with uniform overall bonding, no assembly offset, and stable structural shape is obtained.

[0094] In one embodiment, the step of arranging substrate pads in layers along the sidewall stepped surfaces of the shallow cavity includes:

[0095] Based on the preset signal transmission performance of chip pins, two types of pad grouping specifications are defined, and the corresponding step elevation ranges of the two types of pads are defined by matching the slot contour structure.

[0096] Match the chip pads corresponding to high transmission rate pins to the low-level substrate pads of adjacent chips, and match the chip pads corresponding to power supply pins and low-speed signal pins to the high-level substrate pads of distant chips.

[0097] The patterning of the substrate pads is completed sequentially along each surface to form a layered interconnect wiring structure that adapts to the different signal transmission requirements.

[0098] In practical implementation, this step is the core structured design process for the layered interconnection of the first-order bonding layer and the optimization of the package electrical performance of this invention. It breaks through the limitations of the traditional planar pad uniform layout and achieves partitioned and layered matching interconnection to address the differences in the transmission characteristics of different types of signals. This solves the technical problems of high crosstalk in high-density bonding wiring, high loss of high-speed signals, and serious interference of power supply traces. First, based on the preset electrical parameters and signal transmission performance requirements of each functional pin of the chip, all chip pads are functionally classified and divided, and standardized grouping specifications for high-speed signal pins, power supply, and low-speed signal pins are established. At the same time, combined with the overall contour of the pre-formed beveled slot, the step height difference, and the cavity space structure, the step height range adapted to different groups of pads is specifically defined to ensure that the pad layout position is completely adapted to the cavity structure space. Based on the grouping specifications and the correspondence between the elevation intervals of the stepped surfaces, a one-to-one matching relationship is established between chip pads and substrate stepped surface pads. High-speed signal pins with higher requirements for transmission delay and signal integrity are mapped to low-level stepped surface substrate pads close to the active surface of the chip. Short-pitch lead structures are used to minimize the transmission path of high-speed signals, reducing transmission loss and signal crosstalk. Power supply pins and low-speed signal pins with lower current carrying capacity and transmission rate are mapped to high-level stepped surface substrate pads far from the chip. The spare space on the high-level stepped surfaces is used to route traces, avoiding close-range interference between power supply traces and high-speed signal traces. Finally, according to the established stepped surface layout scheme, the complete patterning process of pattern exposure, metal deposition, and etching is independently completed in each elevation stepped surface area of ​​the slot. This ensures that substrate pads with different functions are neatly distributed in their corresponding stepped surface positions, forming a differentiated layered interconnection wiring structure with high and low layers, functional partitions, and non-interfering traces. This improves the high-frequency transmission performance and wiring regularity of panel-level packaging from a structural level.

[0099] In one embodiment, step S5, which involves dividing the large-area packaging substrate after full-area alignment and bonding into multiple parallel processing zones according to a preset partitioning rule, and having each zone simultaneously perform wire bonding operations according to a preset travel path, includes:

[0100] Based on the overall size of the panel composite blank and the number of parallel execution units of the bonding equipment, equal-sized independent processing zones are defined, and the zone boundary coordinates and global travel paths are generated.

[0101] After receiving the device start-up trigger signal, an independent wire bonding execution unit is matched for each processing zone, and each unit retrieves the corresponding zone's dedicated travel path program.

[0102] Multiple bonding execution units simultaneously start the partitioning operation, sequentially completing the layered pad lead interconnection of all the sub-level shallow cavities within the partition along the preset path, thus completing the full-area panel sub-level lead bonding process.

[0103] In practical implementation, this step is the core parallel process for efficient and consistent bonding in large-area panel-level packaging. It addresses the technical shortcomings of traditional single-batch bonding, such as low efficiency, large process variations across the entire area, and the risk of secondary substrate deformation due to continuous heat accumulation at a single point. This adapts to the needs of large-scale mass production of panels. Before the bonding operation starts, the control system first collects the overall dimensional parameters of the already bonded panel composite blank. Simultaneously, considering the number of parallel execution units that the bonding equipment can simultaneously schedule, it uses equal partitioning logic to modularly divide the entire blank into several processing partitions with consistent dimensions, independent areas, and regular boundaries. It accurately generates the boundary coordinate parameters of each partition and a standardized travel path suitable for processing without blind spots, ensuring that the processing range of each partition is complete, non-overlapping, and with a balanced processing load. After receiving the machine start-up trigger signal, the equipment system automatically matches a dedicated wire bonding execution unit to each independent processing partition. Each execution unit independently retrieves the pre-stored dedicated travel path program for its corresponding partition, achieving one-to-one binding between the partition and the processing unit, avoiding conflicts in multi-unit operation paths and process interference. After unit matching and program invocation are completed, multiple bonding execution units are powered on synchronously to start the partition bonding operation. Each unit strictly follows the preset path and completes the precise alignment, wire bridging, and bonding curing of the layered pads of each shallow cavity in its own independent partition. The interconnection processing of all high and low level surface pads in the partition is completed in sequence. The entire panel is completed in one go through the synchronous parallel operation of multiple regions, which greatly improves the processing efficiency of large area panel packaging. At the same time, the consistency of the entire bonding process is ensured by the unified partition path planning.

[0104] In one embodiment, the step of each partition synchronously performing wire bonding operations according to a preset travel path further includes:

[0105] The program for the specific travel path of the partition is invoked. The bonding points within the partition are processed sequentially according to the alternating arrangement of rows, and the interval processing time is set between adjacent processing points.

[0106] Retrieve the layered pad layout data to distinguish the substrate pads corresponding to different elevation steps in the shallow cavity of the first step, and complete the layered interconnection by matching the corresponding lead forming shape according to the signal transmission performance.

[0107] The interface and status parameters of each bonding point are collected in real time. The collected parameters are transmitted to the quality judgment unit to generate abnormal point feedback signals. Based on the feedback signals, the defect points are located and the repair welding process is started. After completion, a panel composite blank with bonding integrity meets the standard is obtained.

[0108] In practical implementation, this step is a refined process control and quality closed-loop process for partitioned bonding operations. Based on parallel processing, it further optimizes thermal management, wiring compatibility, and processing yield, solving problems such as heat accumulation deformation from continuous dense bonding, poor compatibility of high- and low-order pad interconnects, and the inability to correct bonding defects in real time. During the partitioned bonding process, each bonding execution unit continuously retrieves the partition-specific travel path program, abandoning the traditional continuous point-to-point adjacent processing mode. It strictly follows the alternating arrangement of points between rows to perform bonding processing in rotation, setting fixed interval processing time periods between adjacent processing points. This staggered, interval-based physical operation method disperses processing heat, weakens the continuous high-temperature accumulation effect in local areas, and suppresses localized thermal deformation of the panel composite blank from the process path level. Meanwhile, the bonding unit retrieves the layered pad layout data prepared in the previous stage in real time, accurately identifies the functional attributes of the substrate pads corresponding to different elevation steps inside the shallow cavity of each element, and adaptively matches the corresponding lead curvature, lead span, and bonding point forming shape for lines with different transmission performance requirements such as high-speed signals, power supply, and low-speed signals. This achieves precise layered and differentiated interconnection of high and low level pads, ensuring that the lead forming of various signals is regular and the transmission adaptability is optimal. Throughout the entire bonding process, the detection module collects key parameters such as interface bonding strength, molding integrity, and alignment status at each bonding point in real time, and uploads all collected operating parameters to the equipment quality judgment unit in real time. The quality judgment unit automatically identifies abnormal defect points such as cold solder joints, desoldering, and lead wire deformation by comparing them with standard process parameter thresholds in real time, and generates accurate feedback signals. The equipment quickly locates the defect coordinates based on the feedback signals and automatically starts the in-situ repair welding process to perform secondary precise bonding correction on abnormal bonding points, completely eliminating bonding defects. Finally, it completes full-domain bonding quality control and obtains a finished panel composite blank with all interconnect points forming neatly, bonding reliably, and meeting integrity standards.

[0109] In summary, this invention involves fabricating a large-area packaging substrate with an array of beveled slots, where the sidewalls of each slot are provided with substrate pads arranged in layers along the stepped surface; fixing the chips to be packaged onto the surface of a support fixture in an array arrangement, with chip pads arranged with the active side of each chip facing upwards; performing peripheral distributed multi-point tension clamping on the large-area packaging substrate, collecting the full surface shape data of the large-area packaging substrate after clamping, adjusting the tension of each clamping point according to the full surface shape data to correct substrate warpage; and performing full-area alignment and bonding between the corrected large-area packaging substrate and the array of chips to be packaged on the support fixture. The process involves attaching the corresponding beveled slots to the periphery of a single chip, with the slot sidewalls and the active surface of the chip forming a shallow cavity. The chip pads are located at the bottom of the shallow cavity, and the substrate pads are arranged in layers along the sidewalls of the shallow cavity. According to a preset partitioning rule, the large-area packaging substrate after full alignment and bonding is divided into multiple parallel processing zones. Each zone simultaneously performs wire bonding operations according to a preset travel path, completing the wire interconnection between the chip pads in each shallow cavity and the corresponding layered substrate pads. This achieves the goal of high-precision, high-consistency, low-loss, and secondary deformation-resistant wire bonding manufacturing for panel-level semiconductor packaging.

[0110] The above description is only a preferred embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A panel-level semiconductor packaging element-level bonding method, characterized in that, Includes the following steps: A large-area packaging substrate with an array of beveled slots is prepared, and substrate pads arranged in layers along the stepped surface are arranged on the sidewalls of each slot. The chips to be packaged are arranged in an array and fixed on the surface of the support fixture, with the active side of each chip facing upwards and the chip pads arranged accordingly. The large-area packaging substrate is subjected to peripheral distributed multi-point tension clamping. The full surface shape data of the large-area packaging substrate after clamping is collected. The tension of each clamping point is adjusted according to the full surface shape data to correct the warping deformation of the substrate. The corrected large-area packaging substrate is fully aligned and bonded to the chip array to be packaged on the carrier fixture. Each inclined slot is correspondingly fastened to the periphery of a single chip. The sidewall of the slot and the active surface of the chip form a primal shallow cavity. The chip pad is located at the bottom of the primal shallow cavity. The substrate pad is arranged in layers along the sidewall of the primal shallow cavity. According to the preset partitioning rules, the large-area packaging substrate after full-area alignment and bonding is divided into multiple parallel processing partitions. Each partition simultaneously carries out wire bonding operations according to the preset travel path to complete the wire interconnection between the chip pads in the shallow cavity of each element level and the corresponding layered substrate pads.

2. The panel-level semiconductor packaging element-level bonding method according to claim 1, characterized in that, The step of preparing a large-area packaging substrate with an array of beveled slots includes: The slot contour structure is determined by combining the external dimensions of the chip to be packaged, the mechanical constraints of packaging, and the high-frequency transmission requirements. The morphology detection unit is pre-activated to monitor the morphology of the step surface of the slot sidewall of the substrate in real time and synchronously outputs the monitoring signal to the etching control unit. The synchronous array etching process is used to batch form the entire inclined slot array on the surface of the substrate. The wiring is patterned stepwise along the corresponding height steps of each slot sidewall, and independent substrate pads are prepared on each step to obtain a large-area packaging substrate with a layered pad inclined slot array.

3. The panel-level semiconductor packaging element-level bonding method according to claim 2, characterized in that, The step of batch forming a full-surface beveled groove array on the surface of a substrate using a synchronous area array etching process includes: Based on the preset double-step inclined plane contour processing parameters, the etching energy is released in stages to process the groove sidewall layer by layer; Real-time acquisition of sidewall morphology parameters of all slots in a single substrate, and synchronous feedback to correct etching output power and compensate for processing deviations; After the groove etching is completed, the transition area of ​​the stepped surface of all groove sidewalls is smoothed to make the transition area of ​​the stepped surface continuous, and the shape and specifications of all inclined groove sidewalls are consistent after processing.

4. The panel-level semiconductor packaging element-level bonding method according to claim 1, characterized in that, The step of fixing the chips to be packaged in an array arrangement on the surface of the support fixture includes: A global positioning reference mark matching the outline of a single chip and the array spacing is set on the surface of the support fixture; The chips to be packaged are sequentially placed into the preset station of the carrier fixture according to the array arrangement order, and the chips are aligned with the reference mark to complete the alignment and positioning. All chips to be packaged are fixed to the carrier fixture station using a temporary bonding medium, maintaining a stable posture with the active surface of the chip facing upwards, thus completing the loading and fixing of the array-arranged chips.

5. The panel-level semiconductor packaging element-level bonding method according to claim 1, characterized in that, The steps of performing peripheral distributed multi-point tension clamping on the large-area packaging substrate, collecting full-surface shape data after clamping, and correcting substrate warpage include: The number of clamping units, the unit spacing, and the initial clamping force are determined based on the overall size and thickness of the substrate. Multiple sets of independent and controllable clamping units are arranged along the four edges of the substrate, and the substrate edges are clamped synchronously by the clamping units to complete multi-point tension clamping. Before clamping, the reference surface shape data of the substrate in its free state is collected in advance. During the entire clamping process, the height offset of the substrate relative to the reference surface shape in the clamping state is continuously collected to generate a full-coverage surface shape dataset. The surface shape dataset is retrieved to match the tension compensation values ​​of each clamping unit. The clamping force is dynamically and finely adjusted point by point to counteract the uneven deformation of the substrate, resulting in a large-area packaging substrate with completed surface shape correction.

6. The panel-level semiconductor packaging element-level bonding method according to claim 1, characterized in that, The step of fully aligning and bonding the corrected large-area packaging substrate with the array of chips to be packaged on the carrier fixture includes: The stroke and angle motion parameters of the substrate clamping fixture are retrieved as alignment motion constraints. All clamping fixture linkage control parameters are retrieved simultaneously. Based on a unified motion timing, the coordinated action of multiple clamping units is completed. The full-domain visual coordinate information of the large-area packaging substrate slot array and the carrier fixture chip array is collected simultaneously, and the overall pose compensation between the two arrays is calculated. The relative spatial position of the substrate clamping fixture and the carrier fixture is adjusted synchronously according to the pose compensation amount to achieve high-precision full-area alignment of the slot and the chip. Multiple sets of downward actuators are driven to output uniform loads synchronously, and the substrate is pushed down in segments along the vertical direction of the substrate. During the descent of the substrate, the gap value between the substrate and the chip is collected in real time, and the descent feed speed is dynamically adjusted according to the gap value until each inclined slot completely covers the outer area of ​​the corresponding single chip. The sidewall of the slot and the active surface of the chip are mutually enclosed to form a complete elementary shallow cavity structure, resulting in a panel composite blank in which the substrate and the chip array are bonded together.

7. The panel-level semiconductor packaging element-level bonding method according to claim 6, characterized in that, The step of driving multiple sets of downward actuators to synchronously output uniform loads and continuously push the substrate downwards in segments along the vertical direction of the substrate includes: Multiple sets of synchronous pressing actuators are arranged along the entire area of ​​the substrate, and each set of pressing mechanisms outputs equal pressing load synchronously; During the pressing operation, the gap data between the substrate and the chip is continuously collected, and the feed stroke of the pressing actuator is adjusted in real time based on the gap data; By maintaining a constant bonding pressure and allowing the substrate to stand for a preset time, the relative spatial position of the substrate and the chip array is locked, resulting in a panel composite blank with stable alignment and bonding.

8. The panel-level semiconductor packaging element-level bonding method according to claim 1, characterized in that, The step of arranging the substrate pads in layers along the sidewall stepped surfaces of the shallow cavity includes: Based on the preset signal transmission performance of chip pins, two types of pad grouping specifications are defined, and the corresponding step elevation ranges of the two types of pads are defined by matching the slot contour structure. Match the chip pads corresponding to high transmission rate pins to the low-level substrate pads of adjacent chips, and match the chip pads corresponding to power supply pins and low-speed signal pins to the high-level substrate pads of distant chips. The patterning of the substrate pads is completed sequentially along each surface to form a layered interconnect wiring structure that adapts to the different signal transmission requirements.

9. The panel-level semiconductor packaging element-level bonding method according to claim 1, characterized in that, The step of dividing the large-area packaging substrate after full-area alignment and bonding into multiple parallel processing zones according to preset partitioning rules, and having each zone synchronously carry out wire bonding operations according to a preset travel path, includes: Based on the overall size of the panel composite blank and the number of parallel execution units of the bonding equipment, equal-sized independent processing zones are defined, and the zone boundary coordinates and global travel paths are generated. After receiving the device start-up trigger signal, an independent wire bonding execution unit is matched for each processing zone, and each unit retrieves the corresponding zone's dedicated travel path program. Multiple bonding execution units simultaneously start the partitioning operation, sequentially completing the layered pad lead interconnection of all the sub-level shallow cavities within the partition along the preset path, thus completing the full-area panel sub-level lead bonding process.

10. The panel-level semiconductor packaging element-level bonding method according to claim 9, characterized in that, The step of each partition synchronously performing wire bonding operations according to a preset travel path also includes: The program for the specific travel path of the partition is invoked. The bonding points within the partition are processed sequentially according to the alternating arrangement of rows, and the interval processing time is set between adjacent processing points. Retrieve the layered pad layout data to distinguish the substrate pads corresponding to different elevation steps in the shallow cavity of the first step, and complete the layered interconnection by matching the corresponding lead forming shape according to the signal transmission performance. The interface and status parameters of each bonding point are collected in real time. The collected parameters are transmitted to the quality judgment unit to generate abnormal point feedback signals. Based on the feedback signals, the defect points are located and the repair welding process is started. After completion, a panel composite blank with bonding integrity meets the standard is obtained.

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