A chip packaging method

Abstract

The chip packaging method provided by the embodiments of the present disclosure can realize precise liquid cooling heat dissipation of the local hotspot area of the chip by pasting the prefabricated integrally formed micro flow channel in the organic intermedium and directly connecting the hotspot area of the second chip with the micro flow channel by using the redistribution layer, greatly shortens the heat dissipation path, makes the heat dissipation more direct and more targeted, improves the heat dissipation level of the chip at the maximum power peak, and avoids the low efficiency problem that the heat needs to pass through the entire chip substrate before being dissipated. The prefabricated integrally formed micro flow channel structure avoids the weak interface problem caused by the layered sealing preparation of the traditional micro flow channel, has high overall structural stability and strong pressure resistance. The entire micro flow channel is built in the organic intermedium, and an external heat sink is not needed, which is conducive to the miniaturization and high-density integration of the package. The method only needs to paste the prefabricated micro flow channel in the single-layer organic intermedium, and does not need the complex alignment process between the multi-layer flow channels, thereby simplifying the process and improving the process yield and reliability.

Description

Technical Field

[0001] This disclosure pertains to the field of semiconductor packaging technology, specifically relating to a chip packaging method. Background Technology

[0002] Artificial intelligence requires massive computing power, which in turn consumes a significant amount of energy. The greater the computing power of a single chip, the higher its energy consumption. Current chip power consumption is already in the 2000W range, and it will be even higher in the future. The greater the power consumption, the greater the heat generated, requiring stronger heat dissipation capabilities. To improve heat dissipation performance, the industry has begun using microfluidic liquid cooling technology, which involves creating microchannels on the back of the chip to rapidly remove heat through liquid flow.

[0003] Current microfluidic designs on the back of chips are helpful in improving heat dissipation, but they still have some shortcomings. The main issue is that high-performance chips are packaged using flip-chip technology, with the circuit layer on the front and facing down. Since the heat source is on the circuit layer, the microfluidic channels need to dissipate heat through the chip itself. The chip's thickness affects heat dissipation, especially since the chip doesn't heat up uniformly and has hot spots. Back-side heat dissipation is more like surface-level heat dissipation for these hot spots, lacking specificity. Furthermore, in future 3D stacked packaging, the heat dissipation path between the back microfluidic channels and the front of the chip involves multiple chips and multiple interfaces, making the heat dissipation path even more complex.

[0004] To address the aforementioned issues, it is necessary to propose a chip packaging method that is both rationally designed and effectively solves these problems. Summary of the Invention

[0005] The present disclosure aims to at least solve one of the technical problems existing in the prior art and provide a chip packaging method.

[0006] This disclosure provides a chip packaging method, the packaging method comprising: Provides prefabricated, one-piece molded microchannels and temporary carrier plates; Multiple conductive pillars are formed on the temporary carrier plate, and multiple first chips and the microchannel are mounted and fixed on the temporary carrier plate. A first molding layer is formed to encapsulate the plurality of conductive pillars, the plurality of first chips, and the microchannels to form an organic intermediary; A redistribution layer is formed on the surface of the organic mediator; Multiple second chips are flip-chip connected to the redistribution layer, wherein the hot spot area of ​​the second chip is connected to the microchannel through the redistribution layer; A second molding layer is formed to encapsulate multiple second chips; The thickness of the second molding layer and the redistribution layer respectively forms a first chamber and a second chamber, wherein the first chamber is connected to the microchannel inlet and the second chamber is connected to the microchannel outlet; An inlet pipe interface and an outlet pipe interface are respectively installed in the first chamber and the second chamber.

[0007] Optionally, the microchannels are fabricated using a 3D printing process.

[0008] Optionally, the microchannel is S-shaped with its ends connected, and the cross-section of the microchannel is square.

[0009] Optionally, after forming the first molding layer, the method further includes: A wiring layer is formed on the side of the first molding layer opposite to the temporary carrier board; Multiple conductive bumps are formed on the wiring layer; Forming a redistribution layer on the surface of the organic medium includes: forming the redistribution layer on the side of the first encapsulation layer opposite to the conductive bumps.

[0010] Optionally, after forming the second molding layer, the method further includes: The components are cut to form multiple independent intermediate packages; The organic intermediate of the plurality of intermediate packages is attached to the substrate via the conductive bumps; Multiple solder balls are formed on the side of the substrate opposite to the organic medium.

[0011] Optionally, the thicknesses of the second molding layer and the redistribution layer are used to form a first chamber and a second chamber, respectively, including: The second molding layer and the redistribution layer at the microchannel inlet and microchannel outlet are etched along the thickness direction to form the first chamber and the second chamber respectively, exposing the top wall of the microchannel; Laser is used to remove the top walls of the microchannel at the inlet and outlet, so that the first chamber and the second chamber are respectively connected to the inlet and outlet of the microchannel.

[0012] Optionally, after installing inlet pipe interfaces and outlet pipe interfaces in the first chamber and the second chamber respectively, the method further includes: A sealant layer is filled between the first chamber and the inlet pipe interface, and between the second chamber and the outlet pipe interface.

[0013] Optionally, multiple second chips are flip-chip connected to the redistribution layer, including: Multiple second chips are flip-chip connected to the redistribution layer via thermal bumps, and the hot spots of the second chips are connected to the microchannels via thermal bumps.

[0014] Optionally, before forming the second molding layer, the method further includes: An underfill layer is formed between the second chip and the redistribution layer to encapsulate the thermal bumps.

[0015] Optionally, the microchannel is based on copper alloy, and the width and height of the hollow space inside the microchannel are both greater than 20 μm.

[0016] The chip packaging method of this disclosure achieves precise liquid cooling of local hot spots in the chip by attaching a pre-fabricated, integrally formed microchannel inside an organic intermediate and directly connecting the hot spots of the second chip to the microchannel using a redistribution layer. This significantly shortens the heat dissipation path, making heat dissipation more direct and targeted, improving the chip's heat dissipation level at maximum power peak, and avoiding the inefficient problem of heat needing to pass through the entire chip substrate to dissipate. At the same time, the use of a pre-fabricated, integrally formed microchannel structure avoids the interface weakness problem caused by traditional microchannel layered sealing preparation, resulting in high overall structural stability and strong pressure resistance. The entire microchannel is built into the organic intermediate, eliminating the need for an external heat sink, which is beneficial for miniaturization and high-density integration of the package. In addition, this method only requires attaching the pre-fabricated microchannel within a single layer of organic intermediate, eliminating the need for complex alignment processes between multiple channels, simplifying the process, and improving process yield and reliability. Attached Figure Description

[0017] Figure 1 This is a schematic flowchart of a chip packaging method according to one embodiment of the present disclosure; Figures 2 to 12 This is a schematic diagram of the process of a chip packaging method according to another embodiment of this disclosure; Figure 13 This is a top view of a microchannel according to another embodiment of this disclosure. Detailed Implementation

[0018] To enable those skilled in the art to better understand the technical solutions of the embodiments of this disclosure, the embodiments of this disclosure will be further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0019] like Figure 1 As shown, this embodiment of the present disclosure provides a chip packaging method S100, the packaging method including: S110 provides prefabricated, one-piece molded microchannels and temporary carrier plates.

[0020] like Figure 2As shown, a prefabricated, integrally formed microchannel 130 and a temporary carrier plate B are provided. A temporary bonding layer is attached to the surface of the temporary carrier plate B.

[0021] In this embodiment, the microchannel 130 can be fabricated using 3D printing. Using 3D printing to fabricate the microchannel 130 results in high forming precision and excellent integration, eliminating the need for subsequent bonding or sealing. This fundamentally eliminates the problems of inadequate sealing or delamination at multi-layer interfaces under pressure, further improving the long-term reliability of the microchannel under high-pressure coolant conditions. The microchannel 130 can also be pre-fabricated using other processes; this embodiment does not impose specific limitations and the choice can be made according to actual needs.

[0022] S120. Multiple conductive pillars are formed on the temporary carrier plate, and multiple first chips and the microchannel are mounted and fixed on the temporary carrier plate.

[0023] like Figure 2 As shown, multiple conductive pillars 112 are formed on the temporary bonding layer of the temporary carrier B using an electroplating process. The conductive pillars 112 can be copper pillars. The conductive pillars 112 enable vertical electrical interconnection between upper and lower layers, reducing the package size.

[0024] like Figure 2 As shown, multiple first chips 111 and pre-fabricated microchannels 130 are mounted and fixed to the temporary bonding layer of the temporary carrier board B.

[0025] S130, A first molding layer is formed to encapsulate the plurality of conductive pillars, the plurality of first chips and the microchannels to form an organic intermediary.

[0026] like Figure 3 As shown, a first molding compound 113 is formed on a temporary carrier board B. The first molding compound 113 encapsulates a plurality of conductive pillars 112, a plurality of the first chips 111, and the microchannels 130 to form an organic intermediate 110. The microchannels 130 are encapsulated within the first molding compound 113. In this step, only the pre-fabricated microchannels need to be mounted inside a single-layer organic intermediate, eliminating the need for complex alignment processes between multiple channels, simplifying the process and improving process yield and reliability.

[0027] For example, after forming the first molding layer 113, the method further includes: like Figure 4As shown, a wiring layer 114 is formed on the side of the first molding layer 111 opposite to the temporary carrier plate B; a plurality of conductive bumps 115 are formed on the wiring layer 114. That is, the organic medium 110 also includes the wiring layer 114 and the conductive bumps 115. Then, the temporary carrier plate B is removed, the organic medium 110 is inverted, and the plurality of conductive bumps 115 are fixed to the temporary glass carrier plate A. Then, other encapsulation structures are formed on the side of the first molding layer 111 opposite to the conductive bumps 115.

[0028] S140, A redistribution layer is formed on the surface of the organic medium.

[0029] like Figure 5 As shown, a redistribution layer 120 is formed on the side of the first molding layer 111 opposite to the conductive bump 115. The redistribution layer 120 increases the interconnect density of the chip.

[0030] In this embodiment, the redistribution layer 120 includes multiple layers of metal and dielectric layers spaced apart. The specific process can be as follows: first, a bottom metal layer is formed on the surface of the organic intermediate 110, wherein the bottom metal layer is connected to the conductive pillars 112 and the microchannels 130; then, a bottom dielectric layer is formed on the bottom metal layer; then, multiple layers of spaced intermediate metal and dielectric layers are formed on the bottom dielectric layer; finally, a top metal layer and a top dielectric layer are formed. It should be noted that the number of metal and dielectric layers in the redistribution layer 120 is not specifically limited and can be selected according to actual needs.

[0031] S150. A plurality of second chips are flip-chip connected to the redistribution layer, wherein the hot spot area of ​​the second chips is connected to the microchannel through the redistribution layer.

[0032] like Figure 6 As shown, multiple second chips 150 are flip-chip mounted to the opening of the uppermost dielectric layer of the redistribution layer 120 via thermal bumps 151, and electrically connected to the uppermost metal layer of the redistribution layer 120. Hot spots of the second chips 150 are connected to the microchannel 130 via thermal bumps 151 and the metal layer of the redistribution layer 120. Figure 6 As shown, an underfill layer is formed between the second chip 150 and the redistribution layer 120 to enclose the thermal bumps. The underfill layer encloses the thermal bumps, providing physical support and protecting the reliability of the bump connection.

[0033] In this step, the hot spots of the second chip are directly connected to the microchannels via thermal bumps and a redistribution layer, creating an ultra-short thermal path from the heat source to the coolant. The thermal bumps themselves are made of a highly thermally conductive metal material, which can rapidly conduct the heat generated in the local hot spots of the chip to the metal layer of the redistribution layer, and then further to the microchannels, where it is directly carried away by the flowing coolant. This makes heat dissipation more direct and targeted, improving the chip's heat dissipation level at maximum power peak.

[0034] S160, A second molding compound is formed to encapsulate the plurality of the second chips.

[0035] like Figure 6 As shown, a second molding compound 160 is formed on the surface of the redistribution layer 120, which encapsulates a plurality of the second chips 150. The second molding compound 160 protects the second chips 150.

[0036] For example, after forming the second molding layer 160, the method further includes: like Figure 7 As shown, the temporary glass substrate A can be removed using a laser debonding method. The completed wafer is then diced to form multiple independent intermediate packages. Figure 8 As shown, the intermediate package is connected to the substrate 170 via multiple conductive bumps 115, and an underfill layer is formed between the conductive bumps 115 and the substrate 170. Multiple solder balls 180 are formed on the side of the substrate 170 opposite to the chip package. Signals from the entire package structure are extracted via the solder balls 180.

[0037] S170. The thickness of the second molding layer and the redistribution layer respectively forms a first chamber and a second chamber, wherein the first chamber is connected to the microchannel inlet and the second chamber is connected to the microchannel outlet.

[0038] like Figure 9 and Figure 10 As shown, the second molding layer 160 and the redistribution layer 120 at the microchannel inlet and microchannel outlet are etched along the thickness direction to form the first chamber 161 and the second chamber 162 respectively, exposing the top wall of the microchannel 130.

[0039] like Figure 12 As shown, a laser is used to remove the top wall of the microchannel at the inlet and outlet of the microchannel, so that the first chamber 161 and the second chamber 162 are respectively connected to the inlet and outlet of the microchannel 130.

[0040] In this step, by first etching the first and second chambers on the second molding layer and the redistribution layer to expose the top wall of the microchannel, and then using a laser to remove the top wall of the microchannel, the connection port between the microchannel and the external coolant circulation system can be accurately opened without damaging the surrounding redistribution and other chip structures. This ensures the accuracy of the connection between the channel system and the external pipeline and the cleanliness of the sealed area.

[0041] S180. Install an inlet pipe interface and an outlet pipe interface in the first chamber and the second chamber, respectively.

[0042] like Figure 11 and Figure 12 As shown, the inlet pipe interface 164 and the outlet pipe interface 165 are respectively installed in the first chamber 161 and the second chamber 162; then, a sealant layer 163 is filled between the first chamber 161 and the inlet pipe interface 164, and between the second chamber 162 and the outlet pipe interface 165. The inlet pipe interface 164 is connected to the inlet pipe, and the outlet pipe interface 165 is connected to the outlet pipe. The coolant is delivered to the inlet pipe interface 164 through the inlet pipe, enters the microchannel 130 through the microchannel inlet, undergoes heat exchange, enters the outlet pipe interface 165 through the microchannel outlet, and flows out through the outlet pipe, completing the heat exchange process.

[0043] By filling the space between the first chamber and the inlet pipe interface, and between the second chamber and the outlet pipe interface, a reliable sealed connection between the microchannel inlet / outlet and the external liquid cooling circulation system is achieved. The sealant filling the chambers completely seals the gaps between the pipe interface and the plastic sealant layer and copper wall, effectively preventing coolant leakage from the interface during high-pressure flow, thus improving the overall fluid sealing safety and long-term stability of the package.

[0044] For example, such as Figure 13 As shown, the microchannel 130 is S-shaped with its ends connected. Figure 3 As shown, the cross-section of the microchannel is square.

[0045] In this embodiment, by setting the microchannels to an S-shape (serpentine) with connected ends and a square cross-section, the flow path length and heat exchange area of ​​the coolant within the limited package plane area are effectively increased. The S-shaped orientation allows the microchannels to repeatedly pass through multiple areas under the chip, extending the contact time between the coolant and the microchannel walls, thereby removing more heat. At the same time, compared to a circular cross-section, the square cross-section channel has a larger specific surface area for the same hydraulic diameter, which is beneficial for the transfer of heat from the channel walls to the coolant. Furthermore, the square channel exhibits uniform stress distribution when subjected to internal fluid pressure, further improving the structural stability and heat dissipation uniformity of the channel.

[0046] For example, in this embodiment, the microchannel 130 is based on copper alloy, and the width and height of the hollow space inside the microchannel 130 are both greater than 20μm.

[0047] In this embodiment, the microchannel uses copper alloy as the base material. Copper alloy has excellent thermal conductivity and mechanical strength, and as the channel wall material, it can quickly conduct the transferred heat to the internal coolant. At the same time, the channel size with an internal space greater than 20μm ensures low flow resistance of the coolant and is compatible with the current mainstream micromachining precision, which is convenient for mass production. In addition, the thick channel wall gives it good pressure resistance, which can adapt to high pressure and high speed liquid cooling conditions and is not easy to deform or break.

[0048] The chip packaging method of this disclosure achieves precise liquid cooling of local hot spots in the chip by attaching a pre-fabricated, integrally formed microchannel inside an organic intermediate and directly connecting the hot spots of the second chip to the microchannel using a redistribution layer. This significantly shortens the heat dissipation path, making heat dissipation more direct and targeted, improving the chip's heat dissipation level at maximum power peak, and avoiding the inefficient problem of heat needing to pass through the entire chip substrate to dissipate. At the same time, the use of a pre-fabricated, integrally formed microchannel structure avoids the interface weakness problem caused by traditional microchannel layered sealing preparation, resulting in high overall structural stability and strong pressure resistance. The entire microchannel is built into the organic intermediate, eliminating the need for an external heat sink, which is beneficial for miniaturization and high-density integration of the package. In addition, this method only requires attaching the pre-fabricated microchannel within a single layer of organic intermediate, eliminating the need for complex alignment processes between multiple channels, simplifying the process, and improving process yield and reliability.

[0049] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the embodiments of this disclosure, and the embodiments of this disclosure are not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the embodiments of this disclosure, and these modifications and improvements are also considered to be within the protection scope of the embodiments of this disclosure.

Claims

1. A chip packaging method, characterized in that, The encapsulation method includes: Provides prefabricated, one-piece molded microchannels and temporary carrier plates; Multiple conductive pillars are formed on the temporary carrier plate, and multiple first chips and the microchannel are mounted and fixed on the temporary carrier plate. A first molding layer is formed to encapsulate the plurality of conductive pillars, the plurality of first chips, and the microchannels to form an organic intermediary; A redistribution layer is formed on the surface of the organic mediator; Multiple second chips are flip-chip connected to the redistribution layer, wherein the hot spot area of ​​the second chip is connected to the microchannel through the redistribution layer; A second molding layer is formed to encapsulate multiple second chips; The thickness of the second molding layer and the redistribution layer respectively forms a first chamber and a second chamber, wherein the first chamber is connected to the microchannel inlet and the second chamber is connected to the microchannel outlet; An inlet pipe interface and an outlet pipe interface are respectively installed in the first chamber and the second chamber.

2. The method according to claim 1, characterized in that, The microchannels are fabricated using 3D printing technology.

3. The method according to claim 1, characterized in that, The microchannels are S-shaped with their ends connected, and the cross-section of the microchannels is square.

4. The method according to claim 1, characterized in that, After forming the first molding layer, the method further includes: A wiring layer is formed on the side of the first molding layer opposite to the temporary carrier board; Multiple conductive bumps are formed on the wiring layer; Forming a redistribution layer on the surface of the organic medium includes: forming the redistribution layer on the side of the first encapsulation layer opposite to the conductive bumps.

5. The method according to claim 1, characterized in that, After forming the second molding layer, the method further includes: The components are cut to form multiple independent intermediate packages; The organic intermediate of the plurality of intermediate packages is attached to the substrate via the conductive bumps; Multiple solder balls are formed on the side of the substrate opposite to the organic medium.

6. The method according to claim 1, characterized in that, The thicknesses of the second molding layer and the redistribution layer respectively form a first chamber and a second chamber, including: The second molding layer and the redistribution layer at the microchannel inlet and microchannel outlet are etched along the thickness direction to form the first chamber and the second chamber respectively, exposing the top wall of the microchannel; Laser is used to remove the top walls of the microchannel at the inlet and outlet, so that the first chamber and the second chamber are respectively connected to the inlet and outlet of the microchannel.

7. The method according to claim 6, characterized in that, After installing inlet pipe interfaces and outlet pipe interfaces in the first chamber and the second chamber respectively, the method further includes: A sealant layer is filled between the first chamber and the inlet pipe interface, and between the second chamber and the outlet pipe interface.

8. The method according to claim 1, characterized in that, Connecting multiple second chips to the redistribution layer via flip-chip bonding includes: Multiple second chips are flip-chip connected to the redistribution layer via thermal bumps, and the hot spots of the second chips are connected to the microchannels via thermal bumps.

9. The method according to claim 8, characterized in that, Before forming the second molding layer, the method further includes: An underfill layer is formed between the second chip and the redistribution layer to encapsulate the thermal bumps.

10. The method according to claim 1, characterized in that, The microchannel is based on copper alloy, and the width and height of the hollow space inside the microchannel are both greater than 20 μm.

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