A method for packaging a cis chip and a packaging structure thereof

Abstract

The application provides a CIS chip packaging method and a packaging structure thereof, which precisely control the cavity height and shape, so that the reliability of the packaged CIS chip is good. A glass weir is made of glass, the cavity height and shape are controlled, the bonding strength is enhanced, and a black glue side wall is formed by coating a layer of black glue around the glass weir. A support column is formed by a low-refractive-index and high-transmittance transparent optical glue in the center of the glass weir. Then, wafer bonding, thinning and through-silicon via processes are sequentially completed. Finally, TSV packaging is completed through RDL, solder resist layer, ball planting and final cutting processes.

Description

Technical Field

[0001] This invention relates to the technical field of semiconductor packaging, specifically to a CIS chip packaging method, and also provides a CIS chip packaging structure. Background Technology

[0002] In CIS (CMOS image sensors), TSV (Through Silicon Via) technology is a key technology for achieving chip miniaturization and high performance, and for transitioning from 2D to 3D stacking. It replaces traditional horizontal wiring with vertical electrical interconnects, which can be understood as "opening up" many vertical channels inside the chip, making signal transmission paths shorter and more efficient. Its application has mainly gone through two stages: 1. Evolution from "Size Reduction" to "Structure Modification": Initial Stage (Replacing Wire Bonding): Primarily used to reduce module size. For example, in the CIS module of a mobile phone camera, replacing traditional wires with TSVs can reduce volume by 55% and area by 36%; Advanced Stage (Supporting 3D Stacking): With the popularization of back-illuminated (BSI) technology, TSVs began to support vertical stacking of pixel layers and logic layers. It places photodiodes on the upper layer and processing circuits on the lower layer, and signals are transmitted directly "up and down" through TSVs, significantly improving speed and light sensitivity. 2. Core Advantages and Value: Extreme miniaturization. Compared to traditional packaging, TSV-based devices can reduce the area by 30%-70%, and the shortened signal path results in lower power consumption, lower latency, and higher bandwidth. This is the foundation for realizing three-layer stacking (such as Sony's solution) and even future AI sensors, enabling the integration of more complex processing / storage functions within a single chip.

[0003] In CIS chips designed with TSV (Through-Shipment Ventilation), the cavity is a deliberately reserved physical space in the 3D stacking packaging process, and is by no means a process defect. Its core function can be summarized in three words: protection, conduction, and stress resistance. CIS relies on the photosensitive area (photodiode) to receive light signals, and this part is extremely fragile. During wafer bonding and TSV drilling, a cavity must be reserved above or around it to prevent filling materials or chemical solutions from directly contacting and contaminating the photosensitive area, essentially putting a "protective shield" on the pixel area. In back-illuminated (BSI) CIS, light enters from the back of the chip. The cavity ensures that there is an air medium channel before the light reaches the photosensitive layer, reducing unnecessary refraction or scattering and ensuring that the light falls precisely on the photodiode.

[0004] However, existing cavities are all fabricated using the TSV process. Since the TSV process involves deep hole etching and metal filling (such as copper), the different thermal expansion coefficients of the materials will generate huge mechanical stress, which will lead to differences in the shape and volume of the cavity. As a result, the existing TSV packaged CIS chips have abnormal reliability due to cavity differences. Summary of the Invention

[0005] To address the above problems, this invention provides a CIS chip packaging method that precisely controls the cavity height and shape, resulting in high reliability of the packaged CIS chip.

[0006] A CIS chip packaging method is characterized by: creating a glass dam in the glass to control the cavity height and shape and enhance bonding strength; simultaneously coating the glass dam with a layer of black adhesive to form black adhesive sidewalls; forming a support pillar in the center of the glass dam through a transparent optical adhesive with low refractive index and high transmittance; then sequentially completing wafer bonding, thinning, and through-silicon via (TSV) processes; finally, completing the TSV packaging process through RDL, solder mask layer, ball placement, and final dicing.

[0007] Its further features are: It includes the following steps: S1, cavities are formed on the glass by deep reactive ion etching; S2, black glue is applied to the glass and exposed to form a light-proof material for the side wall of the cofferdam; S3, an optical adhesive is coated on the glass, and exposure and development form a physical support pillar in the middle of the cavity, while simultaneously forming a glass dam; S4, a layer of bonding adhesive is applied to the upper surface of the glass, and the glass is bonded to the wafer, so that the CIS chip on the wafer is arranged in the glass dam. S5, through grinding, photolithography and dry etching processes, completes wafer thinning and through-silicon via etching; S6, a layer of silicon dioxide is prepared on the silicon surface of the wafer, and a layer of silicon nitride is sputtered to provide insulation, heat insulation and waterproof protection. S7, the bottom of the hole is opened to expose the PAD, and the RDL is connected to the PAD through the process. The solder mask layer is covered on the silicon surface, and the cutting track is pre-cut. S8 opens the surface pads and implants balls through exposure and development; S9, cut along the cutting path to obtain the final product.

[0008] Its further features are: In step S2, the black rubber sidewalls of the cofferdam are roughened by applying Plasma. The rough black vinyl sidewalls are made into arcs or teeth to absorb stray light and reduce glare and ghosting. In step S7, the solder resist layer is applied to the silicon surface by spin coating, spraying adhesive, or printing.

[0009] A CIS chip packaging structure, characterized in that it comprises: Glass substrate; And CIS chips; The glass substrate has a recessed glass dam corresponding to the position of the bottom photosensitive particles of the CIS chip. The sidewalls of the glass dam are provided with black adhesive sidewalls. A support pillar formed by transparent optical adhesive is provided at the center of the glass dam. The height of the support pillar is lower than the lower surface of the photosensitive particles.

[0010] Its further characteristic is: The black rubber sidewalls are made into rough arcs or teeth.

[0011] The beneficial effects of this invention are as follows: 1. By creating a dam on a glass substrate, the height and shape of the cavity can be precisely controlled, enhancing bonding strength and reducing process difficulty; 2. Existing organic material-based dams can lead to delamination after reliability testing, affecting chip performance. Glass dams can avoid delamination anomalies. At the same time, since glass dams replace organic materials, the chip thickness can be thinner, improving performance. 3. The rough black adhesive layer around the glass cofferdam absorbs stray light, reduces glare and ghosting, improves the accuracy of the CIS chip, and can also provide physical support for the glass. 4. The transparent adhesive pillar in the middle of the glass cofferdam serves as a support, which can withstand the outward bulge from the center, reduce the packaging stress, and at the same time, the adhesive pillar does not affect the chip's image performance. 5. The larger the cavity volume, the greater the absolute space for deformation, and the greater the risk of delamination and glass cracking. Adding glue columns inside the glass cofferdam reduces the cavity. At the same time, if water vapor seeps into the sealed cavity, it will vaporize and expand at high temperatures, causing the structure to "burst". A smaller cavity can effectively alleviate this problem and improve the reliability of the product in high temperature and high humidity tests. Attached Figure Description

[0012] Figure 1 This is a simplified schematic diagram of step S1 of the packaging method of the present invention; Figure 2 This is a simplified schematic diagram of step S2 of the packaging method of the present invention; Figure 3 This is a simplified schematic diagram of step S3 of the packaging method of the present invention; Figure 4 This is a simplified schematic diagram of step S4 of the packaging method of the present invention; Figure 5 This is a simplified schematic diagram of step S5 of the packaging method of the present invention; Figure 6 This is a simplified schematic diagram of step S6 of the packaging method of the present invention; Figure 7 This is a simplified schematic diagram of step S7 of the packaging method of the present invention; Figure 8 This is a simplified schematic diagram of step S8 of the packaging method of the present invention; Figure 9 This is a simplified schematic diagram of step S9 of the packaging method of the present invention; Figure 10 This is a cross-sectional schematic diagram of the packaging structure of the present invention. Detailed Implementation

[0013] A CIS chip packaging method, see Figures 1-10 The process involves creating a glass dam to control the cavity height and shape, enhancing bonding strength, and applying black adhesive around the glass dam. A support pillar of moderate thickness is formed in the center of the glass dam using a transparent optical adhesive with low refractive index and high transmittance. Then, wafer bonding, thinning, and through-silicon via (TSV) processes are sequentially completed. Finally, the TSV package is completed through RDL, solder mask, ball-mounting, and final dicing processes.

[0014] The specific steps are as follows: S1, a cavity is formed on glass 10 by deep reactive ion etching; S2, black glue is applied to glass 10 and exposed to form a light-blocking material for the side wall of the dam, and Plasma is applied to roughen the black glue, thus generating black glue side wall 1; S3, apply a layer of optical adhesive to the glass, expose and develop to form a physical support column 2 in the middle of the cavity, and at the same time form a glass dam 11; S4, apply a layer of bonding adhesive 12 to the upper surface of the glass, and bond the glass 10 to the wafer 13, so that the CIS chip of the wafer 13 is arranged in the glass dam. S5, through grinding, photolithography and dry etching processes, completes wafer thinning and through-silicon via etching; S6, a layer of silicon dioxide 14 is prepared on the silicon surface of the wafer, and a layer of silicon nitride 15 is sputtered to provide insulation, heat insulation and waterproof protection. S7, the bottom of the hole is opened to expose the PAD, and the RDL16 is connected to the PAD through the process. The solder mask layer is covered on the silicon surface of the wafer 13 by spin coating, spraying adhesive and printing. At the same time, the dicing channel 201 is pre-cut. S8, the surface pads are opened and balls 202 are implanted through exposure and development; S9, cut along cutting path 201 to obtain the final product.

[0015] In practice, the rough black vinyl sidewall 1 is made into an arc or tooth shape to absorb stray light and reduce glare and ghosting. In step S7, the solder resist layer is applied to the silicon surface 13 by spin coating, spraying adhesive, or printing.

[0016] A CIS chip packaging structure, see Figure 10 It includes a glass substrate 10 and a CIS chip 20; The glass substrate 10 has a recessed glass dam 11 at the position of the bottom photosensitive particle 21 of the CIS chip 20. The sidewall of the glass dam 11 is provided with a black adhesive sidewall 1. A support column 2 formed by transparent optical adhesive is provided at the center of the glass dam 11. The height of the support column 2 is lower than the lower surface of the photosensitive particle 21.

[0017] In practice, the black rubber sidewall 1 is made into a rough arc or tooth shape.

[0018] The beneficial effects of this invention are as follows: 1. By creating a dam on a glass substrate, the height and shape of the cavity can be precisely controlled, enhancing bonding strength and reducing process difficulty; 2. Existing organic material-based dams can lead to delamination after reliability testing, affecting chip performance. Glass dams can avoid delamination anomalies. At the same time, since glass dams replace organic materials, the chip thickness can be thinner, improving performance. 3. The rough black adhesive layer around the glass cofferdam absorbs stray light, reduces glare and ghosting, improves the accuracy of the CIS chip, and can also provide physical support for the glass. 4. The transparent adhesive pillar in the middle of the glass cofferdam serves as a support, which can withstand the outward bulge from the center, reduce the packaging stress, and at the same time, the adhesive pillar does not affect the chip's image performance. 5. The larger the cavity volume, the greater the absolute space for deformation, and the greater the risk of delamination and glass cracking. Adding glue columns inside the glass cofferdam reduces the cavity. At the same time, if water vapor seeps into the sealed cavity, it will vaporize and expand at high temperatures, causing the structure to "burst". A smaller cavity can effectively alleviate this problem and improve the reliability of the product in high temperature and high humidity tests.

[0019] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0020] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A CIS chip packaging method, characterized in that: The process involves creating a glass dam to control the cavity height and shape, enhancing bonding strength, and applying a layer of black adhesive around the glass dam to form black adhesive sidewalls. A support pillar is formed in the center of the glass dam using a transparent optical adhesive with low refractive index and high transmittance. Then, wafer bonding, thinning, and through-silicon via (TSV) processes are sequentially completed. Finally, the TSV package is completed through RDL, solder mask, ball-mounting, and final dicing processes.

2. The CIS chip packaging method according to claim 1, characterized in that... It includes the following steps: S1, cavities are formed on the glass by deep reactive ion etching; S2, black glue is applied to the glass and exposed to form a light-proof material for the side wall of the cofferdam; S3, an optical adhesive is coated on the glass, and exposure and development form a physical support pillar in the middle of the cavity, while simultaneously forming a glass dam; S4, a layer of bonding adhesive is applied to the upper surface of the glass, and the glass is bonded to the wafer, so that the CIS chip on the wafer is arranged in the glass dam. S5, through grinding, photolithography and dry etching processes, completes wafer thinning and through-silicon via etching; S6, a layer of silicon dioxide is prepared on the silicon surface of the wafer, and a layer of silicon nitride is sputtered to provide insulation, heat insulation and waterproof protection. S7, the bottom of the hole is opened to expose the PAD, and the RDL is connected to the PAD through the process. The solder mask layer is covered on the silicon surface, and the cutting track is pre-cut. S8 opens the surface pads and implants balls through exposure and development; S9, cut along the cutting path to obtain the final product.

3. The CIS chip packaging method according to claim 2, characterized in that: In step S2, the black rubber sidewalls of the cofferdam are roughened by applying Plasma.

4. The CIS chip packaging method according to claim 3, characterized in that: The rough black vinyl sidewalls are made into arcs or teeth to absorb stray light and reduce glare and ghosting.

5. A CIS chip packaging method according to claim 2, characterized in that: In step S7, the solder resist layer is applied to the silicon surface by spin coating, spraying adhesive, or printing.

6. A CIS chip packaging structure, which is obtained by the CIS chip packaging method according to any one of claims 1-5, characterized in that: It includes: Glass substrate; And CIS chips; The glass substrate has a recessed glass dam corresponding to the position of the bottom photosensitive particles of the CIS chip. The sidewalls of the glass dam are provided with black adhesive sidewalls. A support pillar formed by transparent optical adhesive is provided at the center of the glass dam. The height of the support pillar is lower than the lower surface of the photosensitive particles.

7. A CIS chip packaging structure according to claim 6, characterized in that... The black rubber sidewalls are made into rough arc or tooth shape.

Images