A heat dissipation enhanced chip backside lead fan-out packaging method

Abstract

The application relates to a heat dissipation enhanced chip back lead-out fan-out packaging method, and belongs to the technical field of semiconductor packaging, which comprises the following steps: forming a temporary bonding layer on a temporary bonding carrier; forming a metal wiring layer and an ultrahigh copper column through a wafer-level wiring process; connecting the back gold surface of a bare chip with bumps to the metal wiring layer through a soldering material; forming a restructured wafer through wafer-level injection molding by using plastic sealing material; thinning the front surface of the restructured wafer to expose the bumps and the ultrahigh copper column; sequentially forming a passivation layer, a metal layer and a pad layer on the front surface; and removing the temporary bonding carrier and dicing after forming the bumps. The ultrahigh copper column is constructed in the plastic sealing material, the double-sided wiring process is combined, the back gold surface of the chip is directly welded to the metal wiring layer on the packaging back surface, and the front surface lead-out packaging of the chip back gold surface is realized. The application effectively shortens the heat dissipation path, significantly improves the heat dissipation performance of the packaging body, and is suitable for the packaging requirements of high-power-density chips.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a chip back-side fan-out packaging method with enhanced heat dissipation. Background Technology

[0002] Fan-out wafer-level packaging (FOWLP / eWLB) embeds the bare die in the molding compound and creates a redistribution layer (RDL) on the front side of the die to achieve I / O fan-out. It has advantages such as short interconnects, high I / O density, and thin package, and has been widely used in mobile and high-performance chips.

[0003] However, traditional fan-out packaging typically only allows for single-layer redistribution on the front side of the chip, which is insufficient to meet the requirements of double-sided interconnection, double-sided heat dissipation, and heterogeneous integration. To achieve double-sided redistribution, existing solutions often require temporary bonding and debonding on both sides of the wafer, or introduce complex processes such as carrier replacement and back-side grinding alignment, resulting in lengthy process flows, high alignment difficulty, and increased manufacturing costs and yield risks. In addition, the bare chip is encapsulated in a low thermal conductivity molding compound, and heat is mainly dissipated through the front bumps during operation, while the back gold surface of the chip is not effectively utilized. This results in a long heat dissipation path and high thermal resistance, making it difficult to meet the heat dissipation requirements of high-power chips; moreover, the back gold surface generally cannot be directly led outward in a fan-out structure.

[0004] Therefore, there is an urgent need to provide a packaging method that can achieve back-side gold lead-out of the chip in fan-out packaging, complete double-sided rewiring with a simple process, and significantly improve heat dissipation capabilities. Summary of the Invention

[0005] This invention addresses the following shortcomings of existing fan-out packaging: it only allows for single-layer redistribution on the front side of the chip, making it difficult to meet double-sided interconnect requirements; achieving double-sided redistribution often requires temporary bonding and debonding on both sides of the wafer, or complex processes such as carrier board replacement, resulting in cumbersome processes, alignment difficulties, and high costs; and the bare chip is covered by a low thermal conductivity molding compound, leaving the back gold surface unused, resulting in a long heat dissipation path and high thermal resistance, making it difficult to adapt to high-power chips. Therefore, this invention aims to provide a heat-enhancing fan-out packaging method with a back-side lead-out, achieving double-sided redistribution with a simplified process and significantly improving heat dissipation capabilities.

[0006] To address the aforementioned technical problems, this invention provides a heat-enhancing chip back-side lead-out fan-out packaging method, comprising: A temporary bonding substrate is provided, and a temporary bonding adhesive is applied to the temporary bonding substrate. After curing, a temporary bonding layer is formed. Using wafer-level wiring technology, a metal wiring layer and ultra-high copper pillars are sequentially formed on a temporary bonding layer. The back gold surface of the bare chip with bumps is connected to the metal wiring layer via soldering material; By employing a wafer-level injection molding process, the bare chip and ultra-high copper pillar are injection molded with molding compound at the wafer level, and a reconstructed wafer is formed after curing. The front side of the reconstructed wafer is thinned using a wafer thinning process until the bumps and ultra-high copper pillars on the bare chip are exposed. Using wafer-level wiring technology, a passivation layer, a metal layer, and a pad layer are sequentially formed on the front side of the reconstructed wafer. By forming bumps on the pad layer, removing the temporary bonding substrate and temporary bonding layer, and dicing to obtain a single package, a double-sided redistribution package on the back gold side of the chip is achieved.

[0007] Preferably, the temporary bonding substrate is made of glass, silicon, metal or ceramic; its thickness is 500μm to 1000μm; the temporary bonding adhesive is a thermoplastic or thermosetting adhesive or a thermoplastic or thermosetting adhesive film, with a thickness of 10μm to 100μm.

[0008] Preferably, the metal wiring layer is made of copper and has a thickness of 0.1μm to 50μm; the height of the ultra-high copper pillar is 50μm to 500μm.

[0009] Preferably, the back gold surface of the bare chip with bumps is connected to the metal wiring layer via a soldering material at a soldering temperature of 150°C to 400°C. The metal wiring layer comprises a single layer or multiple layers of rewiring metal lines, the material of which includes copper, aluminum, or copper-aluminum, and the thickness of a single layer is 1μm to 10μm. The soldering material includes solder, sintered silver, or conductive adhesive. The solder is SnAg, SnCu, AuSn, or SAC series alloy. The thickness of the soldering material is 5μm to 100μm.

[0010] Preferably, the molding compound includes epoxy molding compound or molding compound; the diameter of the reconstructed wafer is 200mm or 300mm, and the thickness is 200μm~800μm.

[0011] Preferably, the height of the ultra-high copper pillar is greater than the thickness of the bare chip; the wafer thinning process employs one or more combinations of mechanical grinding, chemical mechanical polishing, or wet etching.

[0012] Preferably, after thinning the front side of the reconstructed wafer, the remaining thickness of the bumps on the bare chip is 20μm~200μm, the remaining height of the ultra-high copper pillars is 100μm~600μm, and the remaining thickness of the molding compound is 100μm~600μm.

[0013] Preferably, before forming a passivation layer on the front side of the reconstructed wafer, the exposed bumps and ultra-high copper pillars are further subjected to surface cleaning and activation treatment.

[0014] Preferably, the passivation layer is made of polyimide, benzocyclobutene, silicon dioxide, or silicon nitride, and has a thickness of 2 μm to 15 μm; the metal layer is made of copper, aluminum, or copper-aluminum, and has a thickness of 1 μm to 10 μm; the pad layer has a diameter of 20 μm to 100 μm, a height of 30 μm to 150 μm, and a pitch of 40 μm to 200 μm.

[0015] Preferably, the material of the bump includes tin, tin-silver, copper-tin-silver, or nickel-gold; the diameter of the bump is 80μm~300μm, the height is 50μm~250μm, and the pitch is 40μm~200μm.

[0016] Compared with the prior art, the present invention has the following beneficial effects: 1. This invention enables back-side lead-out of the back-gold chip; This invention connects the back-gold surface of the bare chip to the metal wiring layer by soldering material, and after front-side thinning to expose the bumps and ultra-high copper pillars on the bare chip together, a redistribution layer is fabricated, thereby leading the back-gold surface of the chip outward from the front of the package, breaking through the limitation of traditional fan-out packaging that can only interconnect on the front side, and providing a structural basis for back-side I / O, back-side power supply and heterogeneous integration.

[0017] 2. The present invention simplifies the double-sided rewiring process; the present invention only requires one temporary bonding to create rewiring layers on the front and back sides of the reconstructed wafer to achieve double-sided rewiring, eliminating the complex processes of multiple temporary bonding / debonding cycles, substrate replacement, back-side grinding and alignment required by the existing solution. The process flow is shortened, and the alignment difficulty, manufacturing cost and yield risk are reduced.

[0018] 3. The present invention significantly improves heat dissipation capability. In this invention, the back gold surface of the bare chip is connected to metal wiring via soldering material, forming a heat conduction channel from the back of the chip directly to the outside. The front redistribution layer is simultaneously electrically connected to the copper pillars and metal blocks and participates in heat dissipation. The soldering material and the back redistribution layer work together to shorten the heat dissipation path and reduce the thermal resistance of the package, effectively improving the heat dissipation capability of the fan-out package, making it more suitable for high-power chips.

[0019] 4. This invention simultaneously achieves back-gold back-lead-out, double-sided rewiring process simplification and heat dissipation enhancement in fan-out packaging, taking into account interconnect density, process feasibility and thermal management level. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the temporary bonding carrier plate and temporary bonding adhesive provided by the present invention.

[0021] Figure 2 This is a schematic diagram of the wafer-level wiring and electroplated ultra-high copper pillar structure of the present invention.

[0022] Figure 3This is a schematic diagram of the structure for bonding the back gold surface of a bare chip with bumps, as provided by the present invention.

[0023] Figure 4 This is a schematic diagram of the wafer-level injection molding structure using molding compound in this invention.

[0024] Figure 5 This is a schematic diagram of the reconstructed wafer front-side thinning structure of the present invention.

[0025] Figure 6 This is a schematic diagram of the rewiring structure on the front side of the wafer according to the present invention.

[0026] Figure 7 This is a schematic diagram of the structure for reconstructing the bumps on the wafer according to the present invention.

[0027] Figure 8 This is a schematic diagram of the structure of the present invention, which involves removing the temporary bonding carrier and dicing to form a single package.

[0028] Figure 9 This is a schematic flowchart of a heat dissipation-enhanced chip back-side lead-out fan-out packaging method provided by the present invention.

[0029] In the diagram: 101-Temporary bonding substrate, 102-Temporary bonding adhesive, 103-Metallic wiring layer, 104-Ultra-high copper pillar, 105-Bare die, 106-Soldering material, 107-Bump, 108-Molding material, 109-Passivation layer, 110-Metal layer, 111-Pad layer, 112-Passivation layer, 113-Bump. Detailed Implementation

[0030] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0031] like Figures 1 to 9 As shown, this embodiment of the invention specifically provides a heat dissipation-enhanced chip back-lead fan-out packaging method, which includes the following steps: S1. Provide a temporary bonding carrier 101, and coat its surface with temporary bonding adhesive 102, such as Figure 1 As shown.

[0032] In this embodiment, the temporary bonding substrate 101 is a glass substrate with a thickness of approximately 700 μm; the temporary bonding adhesive 102 is a thermosetting adhesive film with a thickness of approximately 50 μm, which is applied smoothly to the surface of the substrate through a coating process to serve as a temporary support layer for subsequent chip and adapter board bonding.

[0033] S2. Using wafer-level wiring technology, a metal wiring layer 103 and an ultra-high copper pillar 104 are formed on the temporary bonding layer. In this embodiment, a seed Ti / Cu layer with a thickness of approximately 0.3 μm is first deposited on the temporary bonding layer. Then, a patterned window for the metal wiring layer is formed by spin-coating photoresist, exposure, and development. Next, copper is filled using an electroplating process to form a metal wiring layer 103, typically 10 μm thick. This metal wiring layer 103 serves not only for signal transmission but, more importantly, as a support surface and heat dissipation channel for subsequent chip back-side gold bonding. After forming the metal wiring layer 103, ultra-high copper pillars 104 are fabricated using the same photolithography and electroplating process. Specifically, deep hole patterns are formed at designated locations on the metal wiring layer 103 using thick photoresist photolithography. The hole diameter is 100 μm, and the depth is set according to the chip thickness, generally 50 μm higher than the bare chip thickness, to ensure reliable exposure of the copper pillars after subsequent thinning. Subsequently, copper is electroplated to fill the hole, forming the ultra-high copper pillars 104. After electroplating, the photoresist is removed, and the exposed seed layer is quickly etched away. The top surface of the ultra-high copper pillars is flat and can serve as a vertical interconnect channel.

[0034] S3. The back gold surface of the bare chip 105 with bumps 107 is connected to the metal wiring layer 103 via soldering material 106. In this embodiment, the bare chip 105 has a gold backing layer on its back side, providing good solderability and thermal conductivity. A soldering material 106 is applied or printed on the metal wiring layer 103 at the location corresponding to chip mounting. The soldering material 106 can be selected from solder paste, conductive adhesive, or sintered silver paste. The bare chip 105 is placed face down on the soldering material 106, and a firm connection is achieved through reflow soldering or thermoforming. Because the gold backing of the bare chip 105 is in direct, large-area contact with the metal wiring layer 103, heat can be efficiently conducted from the back of the chip to the metal wiring layer 103. This step also allows for the initial exposure of the chip's gold backing to the front of the package.

[0035] S4. By using a wafer-level injection molding process, the bare chip 105 and the ultra-high copper pillar 104 are injection molded using molding compound 108, and a reconstructed wafer is formed after curing. In this embodiment, the molding compound 108 is preferably an epoxy molding compound (EMC) with a high thermal conductivity of 23 W / mK to enhance heat dissipation. The injection temperature is typically 150°C, the injection pressure is 10 MPa, and the holding time is 120 seconds. After curing, a reconstructed wafer is formed, with the molding compound 108 completely covering the bare die 108 and the ultra-high copper pillars 104, and filling the gap between the bare die and the ultra-high copper pillars. After injection molding, post-curing is performed at 150°C for 2 hours to improve the crosslinking density and stability of the molding compound 108.

[0036] S5. Thin the front side of the reconstructed wafer using a wafer thinning process until the bumps 107 and ultra-high copper pillars 104 on the bare chip are exposed. In this embodiment, the thinning process first uses a coarse grinding wheel for mechanical grinding to remove most of the molding compound. When the target thickness is approached, a fine grinding wheel is used for precision grinding. Finally, chemical mechanical polishing (CMP) is used to remove the damaged layer. The thinning focus is on just exposing the tops of the bumps 107 and ultra-high copper pillars 104 on the bare die. Since the initial height of the ultra-high copper pillars is higher than the thickness of the bare die, the tops of the copper pillars are basically flush with the tops of the bumps after thinning to ensure the reliability of subsequent electrical connections. The total thickness of the reconstructed wafer after thinning is approximately 250 μm.

[0037] S6. A passivation layer 109, a metal layer 110, and a pad layer 111 are sequentially formed on the front side of the reconstructed wafer using a wafer-level wiring process. In this embodiment, the thinned front side is cleaned and plasma activated to remove residual contaminants and improve interfacial adhesion. Then, a passivation layer of polyimide with a thickness of 10 μm is deposited using a spin-coating process. Windows are created on the passivation layer using photolithography and dry etching to expose the end faces of the bumps 107 and ultra-high copper pillars 104. Next, a wafer-level wiring process is used again to form a metal wiring layer 110 on the passivation layer, redistributing the electrical signals of the bumps 107 and the thermal / electrical pathways of the ultra-high copper pillars 104 to the predetermined pad locations. Then, another passivation layer 112 is deposited on the metal wiring layer, and pad windows are created using photolithography. Finally, a UBM layer is deposited at the pad windows to form the pad layer.

[0038] S7. By forming bumps 113 on the pad layer; removing the temporary bonding substrate 101 and temporary bonding adhesive 102, and dicing to obtain a single package, a double-sided redistribution package of the chip back gold side is achieved. In this embodiment, bumps 113 are formed on the pad layer by ball bonding or electroplating. The bumps can be tin-silver solder balls or copper pillar bumps. The bump diameter is typically 100~400μm. Then, the temporary bonding substrate and temporary bonding adhesive are removed by laser debonding or thermal sliding to expose the underlying metal wiring layer 103. Finally, a diamond cutter is used to cut along the dicing path to obtain a single package.

[0039] In summary, the present invention provides a temporary bonding carrier. A metal wiring layer and ultra-high copper pillars are first fabricated on the temporary bonding carrier. The back gold surface of the bare chip is then connected to the metal wiring layer using soldering material. After wafer-level reconstruction to form a reconstructed wafer, the front side is thinned to expose the copper pillars and metal bumps. A passivation layer, a metal layer, and a pad layer are sequentially formed on the front side. A single-chip package is then obtained through dicing. In this invention, the back gold surface of the chip is directly connected to the bottom metal wiring layer via soldering material, and the bottom metal wiring layer is connected to the top metal wiring layer via ultra-high copper pillars, thereby achieving efficient transfer of electrical signals and heat from the back gold surface of the chip to the front side of the package. Due to the large area of ​​the chip's back gold surface and its direct soldering to a large-area metal wiring layer, the thermal resistance is significantly reduced, and the heat dissipation performance is greatly improved.

[0040] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A chip back-side fan-out packaging method with enhanced heat dissipation, characterized in that, include: A temporary bonding substrate is provided, and a temporary bonding adhesive is applied to the temporary bonding substrate. After curing, a temporary bonding layer is formed. Using wafer-level wiring technology, a metal wiring layer and ultra-high copper pillars are sequentially formed on a temporary bonding layer. The back gold surface of the bare chip with bumps is connected to the metal wiring layer via soldering material; By employing a wafer-level injection molding process, the bare chip and ultra-high copper pillar are injection molded with molding compound at the wafer level, and a reconstructed wafer is formed after curing. The front side of the reconstructed wafer is thinned using a wafer thinning process until the bumps and ultra-high copper pillars on the bare chip are exposed. Using wafer-level wiring technology, a passivation layer, a metal layer, and a pad layer are sequentially formed on the front side of the reconstructed wafer. By forming bumps on the pad layer; The temporary bonding substrate and temporary bonding layer are removed, and a single package is obtained by dicing, so as to realize double-sided redistribution packaging of the back gold surface of the chip.

2. The heat dissipation enhanced chip back-lead fan-out packaging method as described in claim 1, characterized in that, The temporary bonding substrate is made of glass, silicon, metal or ceramic; its thickness is 500μm to 1000μm; the temporary bonding adhesive is a thermoplastic or thermosetting adhesive or a thermoplastic or thermosetting adhesive film, with a thickness of 10μm to 100μm.

3. The heat dissipation enhanced chip back-lead fan-out packaging method as described in claim 1, characterized in that, The metal wiring layer is made of copper and has a thickness of 0.1μm to 50μm; the height of the ultra-high copper pillar is 50μm to 500μm.

4. The heat dissipation enhanced chip back-lead fan-out packaging method as described in claim 1, characterized in that, The back gold surface of the bare chip with bumps is connected to the metal wiring layer via a soldering material at a soldering temperature of 150℃~400℃. The metal wiring layer includes single or multiple layers of rewiring metal lines, and its material includes copper, aluminum, or copper-aluminum, with a single layer thickness of 1μm~10μm. The soldering material includes solder, sintered silver, or conductive adhesive. The solder is SnAg, SnCu, AuSn, or SAC series alloy. The thickness of the soldering material is 5μm~100μm.

5. A chip back-side lead-out fan-out packaging method with enhanced heat dissipation as described in claim 1, characterized in that, The molding compound includes epoxy molding compound or molding compound; the diameter of the reconstructed wafer is 200mm or 300mm, and the thickness is 200μm~800μm.

6. The heat dissipation enhanced chip back-lead fan-out packaging method as described in claim 1, characterized in that, The height of the ultra-high copper pillar is greater than the thickness of the bare chip; the wafer thinning process employs one or more combinations of mechanical grinding, chemical mechanical polishing, or wet etching.

7. A heat-enhancing chip back-lead fan-out packaging method as described in claim 1, characterized in that, After thinning the front side of the reconstructed wafer, the remaining thickness of the bumps on the bare chip is 20μm~200μm, the remaining height of the ultra-high copper pillars is 100μm~600μm, and the remaining thickness of the molding compound is 100μm~600μm.

8. A chip back-side lead-out fan-out packaging method with enhanced heat dissipation as described in claim 1, characterized in that, Before forming a passivation layer on the front side of the reconstructed wafer, the exposed bumps and ultra-high copper pillars are subjected to surface cleaning and activation treatment.

9. A chip back-side lead-out fan-out packaging method with enhanced heat dissipation as described in claim 1, characterized in that, The passivation layer is made of polyimide, benzocyclobutene, silicon dioxide, or silicon nitride, and has a thickness of 2 μm to 15 μm. The metal layer is made of copper, aluminum, or copper-aluminum, and has a thickness of 1 μm to 10 μm. The pad layer has a diameter of 20 μm to 100 μm, a height of 30 μm to 150 μm, and a pitch of 40 μm to 200 μm.

10. A heat-enhancing chip back-lead fan-out packaging method as described in claim 1, characterized in that, The material of the bump includes tin, tin-silver, copper-tin-silver, or nickel-gold; the diameter of the bump is 80μm~300μm, the height is 50μm~250μm, and the pitch is 40μm~200μm.

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