Chip package structure and packaging method thereof, and display device

Abstract

The application provides a chip packaging structure and a packaging method thereof and a display device. The chip packaging structure comprises a substrate, the substrate has a first surface and a second surface arranged oppositely, the first surface is provided with a plurality of first pads, and the second surface is provided with at least one second pad; a bare chip is arranged on the first surface, an adhesive layer is arranged between the bare chip and the first surface, a plurality of chip pads are arranged on the bare chip, and the chip pads and the first pads correspond to each other; a plurality of first leads correspond to the first pads, one end of the first lead is electrically connected with the chip pad, and the other end of the first lead is electrically connected with the first pad; at least one electronic component is electrically connected with at least one first pad through a second lead; and a plastic encapsulating body is arranged on the periphery of the substrate and encapsulates at least the bare chip and the electronic component, wherein the second pad is exposed to the plastic encapsulating body. The technical scheme of the application is beneficial to the thinning of electronic products.

Description

Technical Field

[0001] This application relates to the field of chip packaging technology, specifically to a chip packaging structure and packaging method, and a display device. Background Technology

[0002] Chip packaging refers to the process of mounting semiconductor integrated circuit chips (bare dies) into a specific casing. Chip packaging serves to fix, seal, and protect the chip, as well as enhance its electrothermal performance. However, current chip packaging methods are difficult to adapt to the requirements of thinner and lighter end products. Summary of the Invention

[0003] To address the aforementioned issues, this application provides a chip packaging structure, a packaging method thereof, and a display device.

[0004] In a first aspect, embodiments of this application provide a chip packaging structure, comprising: a substrate having a first surface and a second surface disposed opposite to each other, the first surface having a plurality of first pads, and the second surface having at least one second pad; a bare chip disposed on the first surface, the orthographic projection of the first pads on the substrate surrounding the orthographic projection of the bare chip on the substrate, an adhesive layer being disposed between the bare chip and the first surface, and a plurality of chip pads being disposed on the bare chip, the chip pads corresponding one-to-one with the first pads; a plurality of first leads corresponding to the first pads, one end of the first lead being electrically connected to the chip pad, and the other end of the first lead being electrically connected to the first pad; at least one electronic component, each electronic component being electrically connected to at least one first pad via a second lead; and a molding compound disposed on the periphery of the substrate and at least molding the bare chip and the electronic component, wherein the second pads are exposed in the molding compound.

[0005] In conjunction with the first aspect, at least one electronic component includes at least two electronic components, with an insulating heat dissipation medium disposed between two adjacent electronic components; preferably, one end of the electronic component is connected to a first pad; or, both ends of the electronic component are respectively connected to two first pads; preferably, the electronic component includes at least one of a resistor, a capacitor, and an inductor.

[0006] In conjunction with the first aspect, a plurality of first pads containing the same network signal are electrically connected by a third lead; preferably, a via is provided on the substrate, and one of the plurality of first pads containing the same network signal is connected to a second pad through the via.

[0007] In conjunction with the first aspect, the substrate is provided with vias, and at least a portion of the first pads are electrically connected to the second pads through the vias; preferably, the chip packaging structure further includes a carrier board, and the second pads are soldered to the carrier board; preferably, the carrier board includes a printed circuit board or a flexible printed circuit board.

[0008] In conjunction with the first aspect, the second pad includes a solder ball; preferably, the solder ball is made of at least one of tin, lead, and silver; preferably, the encapsulation body includes an epoxy resin film plastic.

[0009] Secondly, embodiments of this application also provide a packaging method for a chip packaging structure. The chip packaging structure includes a substrate, the substrate having a first surface and a second surface disposed opposite to each other, the first surface having a plurality of first pads, and the second surface having at least one second pad. The packaging method includes: placing a bare chip on the first surface, the orthographic projection of the first pads on the substrate surrounding the orthographic projection of the bare chip on the substrate, the bare chip having a plurality of chip pads, the chip pads corresponding one-to-one with the first pads; bonding one end of a first lead to the chip pads, and bonding the other end of the first lead to the first pads; electrically connecting at least one electronic component to at least one first pad via a second lead; and encapsulating the substrate, the bare chip, and the electronic component with a molding compound to obtain a molding compound, the molding compound covering at least a portion of the bare chip, the electronic component, and the substrate, wherein the second pads are exposed in the molding compound.

[0010] In conjunction with the second aspect, before the step of encapsulating the substrate, bare chip, and electronic components with molding compound to obtain the molding compound, the encapsulation method includes: plasma cleaning of the substrate, bare chip, and electronic components.

[0011] In conjunction with the second aspect, the encapsulation of a substrate, a bare chip, and electronic components using a molding compound to obtain a molding compound includes: heating the molding compound to a softened state; injecting the softened molding compound into a mold cavity containing the substrate; and curing it to obtain the molding compound; the encapsulation method further includes: subjecting the molding compound to high-temperature treatment.

[0012] In conjunction with the second aspect, electrically connecting at least one electronic component to at least one first pad via a second lead includes: bonding the electronic component to at least one first pad via the second lead, wherein the electronic component is not fixed to the substrate.

[0013] Thirdly, embodiments of this application also provide a display device, including the chip packaging structure described above.

[0014] The above technical solution encapsulates electronic components within a chip, with wire bonding between the components and the chip. This solves the problem of signal attenuation and interference caused by long transmission distances between the components and the chip, improving signal stability and quality. Furthermore, when fixing the substrate to the carrier board, there is no need to reserve space for electronic components on the carrier board. This reduces the size of the carrier board, mitigating the problem of an overly large structure and facilitating the thinning and lightening of electronic products. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of a cross-sectional structure of a chip packaging structure in the prior art.

[0016] Figure 2 This is a cross-sectional schematic diagram of a chip packaging structure provided in an embodiment of this application.

[0017] Figure 3 This is a top view of a chip packaging structure provided in an embodiment of this application.

[0018] Figure 4 This is a cross-sectional schematic diagram of a chip packaging structure provided in another embodiment of this application.

[0019] Figure 5 This is a top view of a chip packaging structure provided in another embodiment of this application.

[0020] Figure 6 This is a top view of a chip packaging structure provided in another embodiment of this application.

[0021] Figure 7 This is a top view of a chip packaging structure provided in another embodiment of this application.

[0022] Figure 8 This is a cross-sectional schematic diagram of a chip packaging structure provided in another embodiment of this application.

[0023] Figure 9 This is a schematic flowchart of a chip packaging structure packaging method provided in an embodiment of this application.

[0024] Figure 10 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation

[0025] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0026] Currently, electronic products typically use a combination of printed circuit boards (PCBs) or flexible printed circuit boards (FPCs) + chips + electronic components to achieve normal circuit operation. However, the inventors discovered that this packaging structure makes it difficult to achieve portability in end electronic products, and there are certain problems with electronic signal quality. For example... Figure 1As shown, the chip is electrically connected to the PCB via a substrate, and electronic components are also mounted on the PCB. These electronic components require space on the PCB, which increases the size of the PCB. Furthermore, due to space limitations on the PCB, electronic components are placed at a greater distance. As a result, the signal transmission distance between the chip and the electronic components is relatively long, which affects signal quality.

[0027] To address the aforementioned technical problems, this application provides a chip packaging structure, including: a substrate 10, a bare chip 20, multiple first leads 601, at least one electronic component 50, and a molding compound 40. The substrate 10 has a first surface and a second surface disposed opposite to each other. The first surface is provided with a plurality of first pads 101, and the second surface is provided with at least one second pad 102. A bare chip 20 is disposed on the first surface. The orthographic projection of the first pads 101 on the substrate 10 surrounds the orthographic projection of the bare chip 20 on the substrate 10. An adhesive layer 30 is disposed between the bare chip 20 and the first surface. A plurality of chip pads 201 are disposed on the bare chip 20, and the chip pads 201 correspond one-to-one with the first pads 101. A first lead 601 corresponds to the first pad 101. One end of the first lead 601 is electrically connected to the chip pad 201, and the other end of the first lead 601 is electrically connected to the first pad 101. Each electronic component 50 is electrically connected to at least one first pad 101 through a second lead 602. A molding compound 40 is disposed on the periphery of the substrate 10 and at least molds the bare chip 20 and the electronic component 50, wherein the second pads 102 are exposed to the molding compound 40. In this embodiment, electronic components are encapsulated inside a chip, and the electronic components and the chip are bonded together by wire bonding. This solves the problem of signal attenuation and interference caused by long transmission distances between the electronic components and the chip, which is beneficial for signal stability and improves signal quality. Furthermore, when fixing the substrate to the carrier board, there is no need to reserve space for electronic components on the carrier board. This reduces the size of the carrier board, avoids the problem of an overly large carrier board structure, and facilitates the thinning and lightening of electronic products.

[0028] Figure 2 This is a cross-sectional schematic diagram of a chip packaging structure provided in an embodiment of this application. Figure 3 This is a top view schematic diagram of a chip packaging structure provided in an embodiment of this application. Specifically, Figure 3 yes Figure 2 The diagram shows a cross-sectional view of the chip packaging structure.

[0029] like Figure 2 As shown, the chip packaging structure includes a substrate 10, a bare chip 20, a plurality of first leads 601, at least one electronic component 50, and a molding compound 40.

[0030] In this embodiment, the substrate 10 has a first surface and a second surface disposed opposite to each other. The first surface is provided with a plurality of first pads 101, and the second surface is provided with at least one second pad 102. The second pad 102 is also referred to as an integrated circuit (IC) pad or IC pin, used for electrical connection between the chip 20 and peripheral circuits. Optionally, the second pad 102 includes solder balls. The material of the solder balls includes at least one of tin, lead, and silver; or, the material of the solder balls includes an alloy. In this embodiment, the number of first pads 101 is greater than or equal to the number of second pads 102. Optionally, vias (not shown in the figure) are provided on the substrate 10, and at least a portion of the first pads 101 are electrically connected to the second pads 102 through the vias.

[0031] Optionally, the substrate 10 may include a printed circuit board or a flexible printed circuit board. In this embodiment, the substrate 10 may also include substrates made of other materials. Optionally, the substrate 10 may include organic material substrates, such as Ajinomoto multilayer film; ceramic substrates, such as alumina, aluminum nitride, and silicon nitride; metal substrates, such as copper, aluminum, and copper-molybdenum alloys; composite material substrates, such as aluminum silicon carbide; glass substrates, etc. This embodiment does not limit the material of the substrate 10 and can select it according to actual needs. In some embodiments, a lead frame may be used instead of the substrate 10 to fix the chip 20, and this embodiment does not impose any limitations.

[0032] A bare die 20 (also called a die) is disposed on a first surface, and the orthographic projection of the first pad 101 on the substrate 10 does not overlap with the orthographic projection of the bare die 20 on the substrate 10. Optionally, the orthographic projection of the first pad 101 on the substrate 10 surrounds the orthographic projection of the bare die 20 on the substrate 10. That is, the first pad 101 is disposed around the bare die 20 to facilitate electrical connection between the die 20 and the first pad 101.

[0033] In this embodiment, an adhesive layer 30 is provided between the bare chip 20 and the first surface. That is, the bare chip 20 is fixed to the substrate 10 by the adhesive layer 30. Optionally, if electrical connection is required, the adhesive layer 30 can be made of a conductive material, such as conductive adhesive; if signal isolation is required, the adhesive layer 30 can be made of an insulating material, such as epoxy resin-based material.

[0034] like Figure 3As shown, a plurality of chip pads 201 are disposed on the bare chip 20, and each chip pad 201 corresponds one-to-one with a first pad 101. A first lead 601 also corresponds to a first pad 101 (for example, each first lead 601 corresponds one-to-one with a first pad 101). One end of the first lead 601 is electrically connected to the chip pad 201, and the other end of the first lead 601 is electrically connected to the first pad 101. That is, the chip pad 201 and the corresponding first pad 101 are bonded through the first lead 601, thus allowing signals from the chip 20 to be transmitted to the first pad 101, and then to the second pad 102 via the first pad 101, for signal interaction with external devices. In this embodiment, the first lead 601 includes at least one of gold wire, copper wire, and aluminum wire.

[0035] In this embodiment, each electronic component 50 is electrically connected to at least one first pad 101 via a second lead 602. Optionally, the second lead 602 includes at least one of gold wire, copper wire, and aluminum wire. Optionally, the electronic component 50 includes at least one of a resistor, capacitor, or inductor. Optionally, the electronic component 50 and the chip 20 are connected in a single-pad configuration. For example, if the electronic component 50 is a pull-up or pull-down resistor, one end is electrically connected to the first pad 101, and the other end is connected to a power supply or ground. As another example, if the electronic component 50 is a filter capacitor, one end is electrically connected to the first pad 101, and the other end is grounded. Optionally, the electronic component 50 and the chip 20 can be connected in a dual-pad configuration. For example, if the electronic component 50 is a resistor for impedance matching, the resistor is connected to two first pads 101 respectively. For example, if electronic component 50 is an RC filter capacitor (resistor and capacitor in series structure), one end of the resistor is connected to a first pad 101, and one end of the capacitor is connected to a first pad 101.

[0036] Specifically, in Figure 2 and Figure 3 In this chip package structure, an electronic component 50 is included. This electronic component 50 can be a capacitor or a resistor, and it is connected to the chip 20 via a single pad connection. That is, the electronic component 50 is electrically connected to a first pad 101. Figure 4 This is a cross-sectional schematic diagram of a chip packaging structure provided in another embodiment of this application. Figure 5 This is a top view schematic diagram of a chip packaging structure provided in another embodiment of this application. Wherein, Figure 5 yes Figure 4 A top view of the chip packaging structure. Figure 4 and Figure 5 The chip package structure includes an RC filter capacitor and a resistor. Specifically, as shown below... Figure 5 As shown (for clarity, Figure 4(The leads are not fully shown). One end of the RC filter capacitor is grounded, and the other end is electrically connected to the first pad 101. The resistor of the RC filter capacitor is also electrically connected to the first pad 101. That is, the electronic component 50 and the chip 20 use a dual-pad connection mode for capacitor filtering. The resistors include two resistors connected in series, one of which is electrically connected to one of the first pads 101, and the other is electrically connected to the other first pad 101, thus achieving impedance matching. It should be noted that... Figures 2 to 5 The electronic component 50 in this example is merely an example, and may also include other types of electronic components 50 to achieve different functions. It should be noted that, depending on the function being implemented, the connection mode between the electronic component 50 and the chip 20 may be different. A single-pad connection mode, a dual-pad connection mode, or a multi-pad connection mode may be selected. This application embodiment does not impose any limitations.

[0037] In this embodiment, at least one electronic component 50 includes at least two electronic components 50. An insulating heat dissipation medium 510 is disposed between two adjacent electronic components 50, such as... Figure 4 As shown. By providing an insulating heat dissipation medium 510 between electronic components 50, short circuits between electronic components 50 can be avoided, improving electrical reliability. In this embodiment, multiple electronic components 50 and the insulating heat dissipation medium 510 can be assembled into one unit first, and then each electronic component 50 can be electrically connected to the chip 20. Optionally, the insulating heat dissipation medium 510 can be a material that can provide both insulation and heat dissipation. Optionally, the insulating heat dissipation medium 510 includes alumina, boron nitride, thermally conductive silicone material (e.g., silicone rubber filled with alumina, boron nitride, etc.), thermally conductive potting compound (e.g., epoxy resin filled with alumina or aluminum nitride, etc.), thermally conductive graphite sheet, etc. In some embodiments, after the electronic components 50 are electrically connected to the chip 20, the insulating heat dissipation medium 510 can be used to isolate the electronic components 50 to avoid short circuits.

[0038] like Figures 2 to 5 As shown, a molding compound 40 is disposed on the periphery of the substrate 10 and at least molds the bare chip 20 and electronic components 50. The second pad 102 is exposed to the molding compound 40. This ensures that the second pad 102 can be electrically connected to external devices, thereby enabling signal interaction between the chip 20 and external devices. In this embodiment, the molding compound 40 includes epoxy molding compound (EMC). EMC is a thermosetting chemical material with epoxy resin as the base resin, which provides electrical insulation to prevent short circuits and signal interference in the chip 20; in addition, EMC has high mechanical strength, can withstand vibration and impact, and protects the structural integrity of the chip 20.

[0039] It is understood that in some embodiments, multiple electronic components 50 can be dispersed within the molding compound 40. In this case, the molding compound 40 can be used directly for insulation, eliminating the need for an additional insulating heat dissipation medium 510, thus saving on manufacturing processes and costs. However, in some cases, if multiple components 50 are close together, breakage may easily occur during molding. In such cases, an insulating heat dissipation medium 510 can be used for insulation.

[0040] In some embodiments, the same network signal is typically transmitted to the second pad 102 via its respective first pad 101, which greatly increases the number of second pads 102. The second pads 102 are then connected to their respective peripheral circuits, significantly increasing the complexity of the peripheral circuits. Based on this, embodiments of this application provide an improved solution, specifically as follows: Figure 6 As shown.

[0041] Figure 6 This is a top view schematic diagram of a chip packaging structure provided in an embodiment of this application. For example... Figure 6 As shown, multiple first pads 101 containing the same network signal are electrically connected via a third lead 603 (also called a three-dimensional lead). Optionally, the material of the third lead 603 includes at least one of gold wire, copper wire, and aluminum wire. Optionally, vias are provided on the substrate 10. One of the multiple first pads 101 containing the same network signal is connected to a second pad 102 via a via. In this way, multiple first pads 101 are electrically connected to one second pad 102, which can reduce the number of IC pads, simplify the peripheral circuit, and simplify the structure of the carrier board 70 (for example, changing from a multilayer board to a single-layer board, which is beneficial for achieving a thinner and lighter design of the carrier board 70).

[0042] Figure 7 This is a top view schematic diagram of a chip packaging structure provided in another embodiment of this application. For example... Figure 7As shown, at least one electronic component 50 includes multiple electronic components 50, and an insulating heat dissipation medium 510 is disposed between two adjacent electronic components 50. One end of each electronic component 50 is connected to one of the first pads 101, and the other end is connected to another first pad 101. That is, in this embodiment, the electronic component 50 is connected to the chip 20 (or the first pad 101) via a three-dimensional lead (i.e., a second lead 602) and is encapsulated inside the chip package structure, eliminating the need to be placed on the carrier board 70 and reducing the problem of an oversized motherboard structure. Furthermore, being placed inside the chip package structure results in a shorter signal transmission distance between the chip 20 and the electronic component 50, avoiding signal attenuation and interference caused by excessively long signal transmission distances. Furthermore, in this embodiment, multiple first pads 101 containing the same network signal are electrically connected through a third lead 603, and then connected to a second pad 102 through one of the multiple first pads 101. That is, multiple first pads 101 are connected to one second pad 102, thus reducing the number of second pads 102 and simplifying the peripheral circuit and the size of the carrier board 70.

[0043] Figure 8 This is a cross-sectional schematic diagram of a chip packaging structure provided in another embodiment of this application. For example... Figure 8 As shown, the chip packaging structure also includes a carrier board 70, to which the second pad 102 is soldered. Optionally, the carrier board 70 includes a printed circuit board or a flexible printed circuit board. Figure 8 As can be seen, since the electronic component 50 is packaged inside the chip package structure, it does not occupy the volume of the carrier board 70. This reduces the size of the carrier board 70, which is beneficial for achieving a thinner and lighter design of the carrier board 70, and thus enabling a thinner and lighter design of electronic products. In addition, multiple first pads 101 with the same network signal are connected to a second pad 102. This reduces the number of second pads 102, simplifies the peripheral circuitry, simplifies the structure of the carrier board 70, and also helps to achieve a thinner and lighter carrier board 70.

[0044] This application also provides a chip packaging method for preparing the aforementioned chip packaging structure. The packaging method includes: placing a bare chip on a first surface, with the orthographic projection of a first pad on a substrate surrounding the orthographic projection of the bare chip on the substrate; a plurality of chip pads being disposed on the bare chip, each corresponding to a first pad; bonding one end of a first lead to a chip pad and the other end of the first lead to a first pad; electrically connecting at least one electronic component to at least one first pad via a second lead; and encapsulating the substrate, the bare chip, and the electronic component using a molding compound to obtain a molding compound that covers at least a portion of the bare chip, the electronic component, and the substrate, wherein the second pad is exposed within the molding compound. In this application embodiment, this packaging method can encapsulate electronic components within the chip packaging structure and directly bond the electronic components to the chip via wire bonding. This solves the problem of signal attenuation and interference caused by excessively long signal transmission distances outside the chip; furthermore, it reduces the required substrate volume, facilitating the thinning and lightening of electronic products.

[0045] Figure 9 This is a schematic flowchart of a chip packaging method provided in an embodiment of this application. Figure 9 As shown, the method includes the following steps.

[0046] Step S910: Place the bare chip on the first surface.

[0047] In the embodiments of this application, such as Figures 2 to 8 As shown, the chip packaging structure includes a substrate 10, which has a first surface and a second surface disposed opposite to each other. The first surface is provided with a plurality of first pads 101, and the second surface is provided with at least one second pad 102. The orthographic projection of the first pads 101 on the substrate 10 surrounds the orthographic projection of the bare chip 20 on the substrate 10. The bare chip 20 is provided with a plurality of chip pads 201, and the chip pads 201 correspond one-to-one with the first pads 101.

[0048] In this embodiment, placing the bare die on the first surface includes: applying an adhesive layer to the location where the bare die is to be placed (the location on the substrate where the bare die is designed); and placing the bare die on the adhesive layer. This achieves the fixation of the bare die on the first surface.

[0049] Step S920: Bond one end of the first lead to the chip pad and the other end of the first lead to the first pad.

[0050] In this embodiment of the application, the first lead includes at least one of gold wire, copper wire, and aluminum wire.

[0051] Wire bonding is a process that connects the bonding pads of a bare die to the first pad of a substrate using metal leads. Wire bonding enables effective electrical connection and signal transmission between the chip and external circuits. Optionally, plasma cleaning of the substrate and the bare die is required before wire bonding. This removes contaminants from the surfaces of the substrate and the bare die, improving bond strength and reducing the risk of bond separation. Optionally, the plasma used in plasma cleaning may include argon ions, electrons, or active substrates. Plasma cleaning generates plasma in a vacuum state using a high-frequency alternating electric field. The chemical reactions and physical bombardment of the active plasma convert impurities on the chip and substrate surfaces into ions or gaseous substances, which are then expelled from the cavity, achieving surface cleaning.

[0052] During wire bonding, the method includes: bonding one end of a first lead to a chip pad to form a first solder joint; pulling the lead to a first pad on the substrate according to a machine-defined arc algorithm; and bonding the other end of the first lead to the first pad to form a second solder joint, thereby achieving an electrical connection between the chip and the substrate. In this embodiment, the above steps are repeated until all chip pads and first pads are wire bonded. It should be noted that which first pad a chip pad is bonded to can be pre-set by a machine algorithm.

[0053] In the embodiments of this application, the wire bonding welding method includes at least one of thermocompression welding, ultrasonic welding, and thermo-ultrasonic welding.

[0054] In step S930, at least one electronic component is electrically connected to at least one first pad 101 via a second lead.

[0055] In the embodiments of this application, such as Figures 2 to 8 As shown, one end of the second lead 602 is electrically connected to the electronic component 50, and the other end of the second lead 602 is electrically connected to the first pad 101. The second lead 602 includes at least one of gold wire, copper wire, and aluminum wire.

[0056] In this embodiment, the electronic component is bonded to at least one first pad via a second lead. Optionally, one end of the electronic component is bonded to one of the first pads via a second lead. Alternatively, both ends of the electronic component are bonded to different first pads via second leads. This embodiment is not limited and can be selected according to the function of different electronic components.

[0057] In this embodiment, the electronic components are not fixed to the substrate. In the prior art, electronic components are typically fixed to a carrier board. Due to space limitations on the carrier board, the electronic components and the chip are usually far apart, resulting in a long signal transmission distance and potential signal attenuation or interference. Therefore, in this embodiment, the electronic components are placed within the chip packaging structure. Since the substrate is used to fix the chip and no space is reserved for fixing the electronic components, designing a fixing position for the electronic components on the substrate would increase the substrate area, which is also detrimental to the thinning and lightening of electronic products. In this embodiment, the electronic components and the chip are electrically connected via a second lead (i.e., a three-dimensional lead). During subsequent molding, the electronic components are fixed within the molding compound. This utilizes the space within the molding compound to place the electronic components without increasing the volume of the chip packaging structure. Furthermore, the electrical connection between the chip and the electronic components via leads shortens the signal transmission distance between them, avoiding signal attenuation or interference caused by excessive transmission distance.

[0058] Optionally, the packaging method further includes electrically connecting multiple first pads having the same network signal via a third lead. Then, the multiple first pads can be connected to a second pad through one of the first pads, eliminating the need for each first pad to be connected to a second pad. This reduces the number of second pads, simplifies the complexity of the external circuitry, and facilitates a thinner and lighter substrate design. Optionally, the third lead includes at least one of gold wire, copper wire, and aluminum wire.

[0059] Step S940: The substrate, bare chip and electronic components are encapsulated using a molding compound to obtain a molding compound.

[0060] In the embodiments of this application, such as Figures 2 to 8 As shown, the molding compound 40 covers at least a portion of the bare chip 20, electronic components 50, and substrate 10, wherein the second pad 102 is exposed to the molding compound 40.

[0061] In this embodiment, before encapsulating the substrate, bare die, and electronic components with molding compound to obtain the encapsulated body, the encapsulation method further includes plasma cleaning of the substrate, bare die, and electronic components. The principle of plasma cleaning before encapsulation is similar to that before wire bonding. By using the chemical reaction and physical bombardment of plasma, contaminants on the surface of the substrate, bare die, and electronic components are converted into ions or gaseous substances and discharged, achieving the purpose of surface cleaning. Furthermore, plasma cleaning can activate the substrate surface, increase the bonding force between the molding compound and the substrate, improve the encapsulation effect, and thus enhance product reliability.

[0062] Optionally, a molding compound is encapsulated using a molding compound material to obtain a molded body. This includes: heating the molding compound material to a softened state; injecting the softened molding compound material into a mold cavity containing the substrate; and curing to obtain the molded body. In this embodiment, the molding compound material includes EMC, which can soften at temperatures above 70°C. Softening refers to the molding compound material melting into a liquid state to achieve good fluidity. Methods for injecting the liquid molding compound material into the mold cavity include transfer molding and multi-injection head technology; this application does not impose limitations, as long as injection molding can be achieved. After injection molding, the epoxy resin in the EMC material cross-links and cures under the action of a hardener and coupling agent to form the molded body (i.e., the outer shell). The cross-linking and curing time is set according to the thickness and structure of the product.

[0063] In some embodiments, the cross-linked and cured encapsulated body has not yet fully reacted. Therefore, it needs to be baked at high temperature to ensure complete reaction, stabilize the epoxy resin molecular structure, improve the hardness and material stability of the encapsulated body, and eliminate internal stress. Optionally, the encapsulation method further includes: subjecting the encapsulated body to high-temperature treatment. The conditions for high-temperature treatment include: a temperature greater than or equal to 150°C and less than or equal to 17°C, and a baking time greater than or equal to 2 hours and less than or equal to 10 hours. It is understood that the conditions for high-temperature treatment can be determined according to the actual product and are not limited here.

[0064] Thirdly, embodiments of this application provide a display device including the chip packaging structure described above. The display device includes a display panel. The chip packaging structure in the above embodiments can be directly mounted on the display panel of the display device (Chip on Panel, COP), or mounted on the display panel of the display device via a flexible printed circuit board (Chip on FPC, COF). Embodiments of this application do not impose any limitations on this.

[0065] Figure 10 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Figure 10 As shown, display device 1000 is a product with image display function. For example, display device 1000 can be used to display static images, such as pictures or photographs. Display device 1000 can also be used to display moving images, such as videos.

[0066] Display device 1000 can be a laptop, mobile phone, handheld or portable computer, camera, camcorder, in-vehicle smart central control screen, calculator, smartwatch, GPS navigator, electronic photo, electronic billboard or sign, projector, etc.

[0067] The display device 1000 includes the chip packaging structure and display panel provided in any of the above embodiments. The display panel may be an organic light-emitting diode display panel or a quantum dot electroluminescent display panel.

[0068] In addition, the display device 1000 can also perform functions such as taking photos, recording videos, fingerprint recognition, and facial recognition. Accordingly, the display device 1000 also includes at least one functional module for implementing the above functions, such as an under-display camera or an under-display fingerprint recognition sensor.

[0069] The basic principles of this application have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this application are merely examples and not limitations, and should not be considered as essential features of each embodiment of this application. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the application to the necessity of employing the aforementioned specific details for implementation.

[0070] The block diagrams of devices, apparatuses, devices, and systems involved in this application are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as “comprising,” “including,” “having,” etc., are open-ended terms meaning “including but not limited to,” and are used interchangeably with them. The terms “or” and “and” as used herein refer to the terms “and / or,” and are used interchangeably with them unless the context clearly indicates otherwise. The term “such as” as used herein refers to the phrase “such as but not limited to,” and is used interchangeably with it.

[0071] It should also be noted that in the apparatus, equipment, and methods of this application, the components or steps can be disassembled and / or recombined. These disassemblies and / or recombinations should be considered as equivalent solutions of this application.

[0072] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this application. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other aspects without departing from the scope of this application. Therefore, this application is not intended to be limited to the aspects shown herein, but rather to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0073] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this application to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations thereof.

[0074] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A chip packaging structure, characterized in that, include: A substrate having a first surface and a second surface disposed opposite to each other, the first surface having a plurality of first pads and the second surface having at least one second pad; A bare chip is disposed on the first surface. The orthographic projection of the first pad on the substrate surrounds the orthographic projection of the bare chip on the substrate. An adhesive layer is disposed between the bare chip and the first surface. A plurality of chip pads are disposed on the bare chip, and the chip pads correspond one-to-one with the first pad. Multiple first leads are provided, corresponding to the first pads. One end of each first lead is electrically connected to the chip pad, and the other end of each first lead is electrically connected to the first pad. At least one electronic component, each of which is electrically connected to at least one of the first pads via a second lead; A molding compound is disposed on the periphery of the substrate and at least molds the bare chip and the electronic components, wherein the second pad is exposed to the molding compound.

2. The chip packaging structure according to claim 1, characterized in that, The at least one electronic component includes at least two electronic components, and an insulating heat dissipation medium is disposed between two adjacent electronic components. Preferably, one end of the electronic component is connected to the first pad; or, both ends of the electronic component are respectively connected to the two first pads. Preferably, the electronic component includes at least one of a resistor, a capacitor, and an inductor.

3. The chip packaging structure according to claim 1, characterized in that, Multiple first pads containing the same network signal are electrically connected via a third lead; Preferably, the substrate is provided with vias, and one of the plurality of first pads containing the same network signal is connected to the second pad through the vias.

4. The chip packaging structure according to claim 1, characterized in that, The substrate is provided with vias, and at least a portion of the first pad is electrically connected to the second pad through the vias; Preferably, the chip packaging structure further includes a carrier board, to which the second pad is soldered; Preferably, the carrier board includes a printed circuit board or a flexible printed circuit board.

5. The chip packaging structure according to claim 1, characterized in that, The second pad includes solder balls; Preferably, the material of the solder ball includes at least one of tin, lead, and silver; Preferably, the encapsulating body comprises an epoxy resin film plastic.

6. A packaging method for a chip packaging structure, characterized in that, The chip packaging structure includes a substrate having a first surface and a second surface disposed opposite to each other. The first surface has a plurality of first pads, and the second surface has at least one second pad. The packaging method includes: A bare chip is placed on the first surface, and the orthogonal projection of the first pad on the substrate surrounds the orthogonal projection of the bare chip on the substrate. A plurality of chip pads are provided on the bare chip, and the chip pads correspond one-to-one with the first pad. One end of the first lead is bonded to the chip pad, and the other end of the first lead is bonded to the first pad. At least one electronic component is electrically connected to at least one first pad via a second lead; The substrate, the bare chip, and the electronic components are encapsulated using a molding compound to obtain a molding compound that covers at least a portion of the bare chip, the electronic components, and the substrate, wherein the second pad is exposed in the molding compound.

7. The packaging method for the chip packaging structure according to claim 6, characterized in that, Before the step of encapsulating the substrate, the bare chip, and the electronic components with a molding compound to obtain a molding compound, the encapsulation method includes: performing plasma cleaning on the substrate, the bare chip, and the electronic components.

8. The packaging method for the chip packaging structure according to claim 6, characterized in that, The method of encapsulating the substrate, the bare chip, and the electronic components with a molding compound to obtain a molding compound includes: heating the molding compound to a softened state; injecting the softened molding compound into a mold cavity containing the substrate; and curing to obtain the molding compound. The encapsulation method further includes: subjecting the encapsulated body to high-temperature treatment.

9. The packaging method for the chip packaging structure according to claim 6, characterized in that, The step of electrically connecting at least one electronic component to at least one first pad via a second lead includes: The electronic component is bonded to at least one first pad via a second lead, wherein the electronic component is not fixed to the substrate.

10. A display device, characterized in that, Includes the chip packaging structure described in any one of claims 1 to 5.

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