Semiconductor package cavity for electrical isolation and thermal dissipation

Abstract

A semiconductor package cavity for electrical isolation and thermal dissipation is disclosed. In an example, a semiconductor package (100) includes a die attach pad (102) and a semiconductor member (106) having a bottom surface attached to the die attach pad, a top surface (112) opposite the bottom surface, and a cavity (114). The semiconductor package also includes an insulating layer (116) in the cavity and on at least a portion of the top surface, and a semiconductor die (122) inside the cavity and attached to the insulating layer by a die attach material (128).

Description

Technical Field

[0001] This application relates to a semiconductor package cavity for electrical isolation and heat dissipation. Background Technology

[0002] A semiconductor wafer is a circular piece of semiconductor material (such as silicon) used to manufacture semiconductor chips. Generally, complex manufacturing processes are used to form many integrated circuits on a single wafer. Forming such integrated circuits on a wafer is called fabrication. After wafer fabrication, the wafer is diced into multiple pieces called semiconductor dies, each of which contains one or more of the integrated circuits. Dicing or sawing the wafer into individual dies is called splitting. The individual dies can then be attached to a substrate or die attachment pads. The resulting structure is then covered with molding compound to produce a package. Summary of the Invention

[0003] In one example, a semiconductor package includes: a die attachment pad; and a semiconductor component having a bottom surface attached to the die attachment pad, a top surface opposite the bottom surface, and a cavity. The semiconductor package further includes: an insulating layer within the cavity and on at least a portion of the top surface; and a semiconductor die inside the cavity and attached to the insulating layer by a die attachment material.

[0004] In one example, a method for manufacturing a semiconductor package includes: etching a semiconductor wafer to form a cavity; depositing an insulating layer on the semiconductor wafer; sawing the semiconductor wafer to produce a semiconductor component including the cavity; attaching the semiconductor component to metal die attachment pads using a first die attachment material; attaching a semiconductor die to the semiconductor component inside the cavity using a second die attachment material; attaching bonding wires to the device side of the semiconductor die and to conductive terminals; and covering the metal die attachment pads, the conductive terminals, the semiconductor component, the first die attachment material and the second die attachment material, the insulating layer, the semiconductor die, and the bonding wires with molding compound. Attached Figure Description

[0005] Figure 1A , 1B 1C and 1D are cross-sectional views, top-down views, sectional views, and perspective views of semiconductor packages containing cavities for electrical isolation and heat dissipation, according to various examples.

[0006] Figure 2A , 2B 2C and 2D are cross-sectional views, top-down views, sectional views, and perspective views of semiconductor packages containing cavities for electrical isolation and heat dissipation, according to various examples.

[0007] Figure 3A , 3B 3C and 3D are cross-sectional views, top-down views, sectional views, and perspective views of semiconductor packages containing cavities for electrical isolation and heat dissipation, based on various examples.

[0008] Figure 4 This is a flowchart illustrating various examples of methods for manufacturing semiconductor packages containing cavities for electrical isolation and heat dissipation.

[0009] Figure 5A , 5B 5C, 5D, 5E, 5F, 5G, and 5H are process flows for manufacturing semiconductor packages containing cavities for electrical isolation and heat dissipation, as depicted according to various examples.

[0010] Figure 6 It is a block diagram of an electronic device comprising a semiconductor package having cavities for electrical isolation and heat dissipation, according to various examples. Detailed Implementation

[0011] In some applications, semiconductor dies should be electrically isolated from the die attachment pads to which they are attached. Electrically insulating die attachment materials can be used to attach the semiconductor die to the die attachment pads and provide the aforementioned isolation. However, in some cases, mechanical sawing is used to cut the semiconductor die, which causes semiconductor debris to accumulate at the periphery of the semiconductor die (a phenomenon known as "edge chipping"). This semiconductor debris can collapse from the periphery of the semiconductor die to the underlying die attachment pads, thereby short-circuiting the semiconductor die to the die attachment pads and effectively bypassing the die attachment material. When this short circuit occurs, the electrical isolation previously provided by the die attachment material is lost. To mitigate the risk of such short circuits caused by edge chipping, other semiconductor wafer cutting techniques (e.g., plasma, laser) may be useful, as these techniques tend to avoid generating semiconductor debris. However, regardless of the type of cutting technique used, die attachment materials have low thermal conductivity. Therefore, even if the risk of electrical short circuits is reduced or eliminated, poor thermal conductivity remains a technical challenge.

[0012] This specification presents various examples of semiconductor packages including cavities for electrical isolation and heat dissipation. More specifically, the semiconductor package includes an active semiconductor die containing an integrated circuit capable of performing various operations, and the semiconductor package further includes passive semiconductor components that omit such circuitry. The passive semiconductor component includes a cavity coated with an insulating layer (e.g., electrically insulating but thermally conductive), and the active semiconductor die is disposed within the cavity and attached to the insulating layer by a highly conductive and thermally conductive die attach material. The passive semiconductor component is attached to a die attach pad by another example of a conductive and thermally conductive die attach material. Each of the layers between the active semiconductor die and the die attach pad is thermally conductive, thereby facilitating heat dissipation through the bottom surface of the semiconductor package. Furthermore, the cavity in the passive semiconductor component contains a non-adhesive die attach material, preventing the non-adhesive die attach material from leaking downwards and unintentionally forming an electrical short circuit with the structure beneath the insulating layer. In this way, electrical isolation is achieved. Furthermore, the presence of cavities in passive semiconductor components reduces the thickness of the semiconductor package compared to the thickness that would result from omitting the cavities. This reduction in package thickness is achieved because the active semiconductor die is placed in a lower horizontal plane than would otherwise be (i.e., within the cavity). The semiconductor packages described herein can have thicknesses ranging from 0.5 mm to 1.0 mm.

[0013] Figures 1A to 1D These are cross-sectional views, top-bottom views, sectional views, and perspective views of semiconductor packages containing cavities for electrical isolation and heat dissipation, based on various examples. Specifically, Figures 1A to 1DA semiconductor package 100 (e.g., a quad flat no-lead (QFN) package) is shown, comprising a die attachment pad 102, conductive terminals 104, and a passive semiconductor (e.g., silicon) component 106 attached to the die attachment pad 102 via a die attachment material 108. The passive semiconductor component 106 has a bottom surface 110 and a top surface 112 that contact the die attachment material 108. A cavity 114 is formed in the passive semiconductor component 106, and more specifically, in the top surface 112, meaning that the cavity 114 begins at the top surface 112 and extends toward the bottom surface 110 through some, but not all, of the thickness of the passive semiconductor component 106. The top surface 112 surrounds the cavity 114. An insulating layer 116 contacts the top surface 112 and multiple surfaces of the cavity 114. In some examples, the insulating layer 116 contacts all surfaces of the top surface 112 and all surfaces of the cavity 114. The surface of cavity 114 includes a bottom surface 118 extending parallel to the bottom surface 110, and four lateral surfaces 120 extending perpendicular to the bottom surface 110. An active semiconductor (e.g., silicon) die 122 includes a device side 124 in which an integrated circuit is formed, and a non-device side 126 opposite to the device side 124. The active semiconductor die 122 is disposed within cavity 114, and more specifically, the active semiconductor die 122 is attached to an insulating layer 116 contacting the bottom surface 118 and / or the lateral surfaces 120 of cavity 114 using die attachment material 128. Bonding wires 130 attach the device side 124 to conductive terminals 104. Molding compound 132 covers various structures of semiconductor package 100.

[0014] Although the passive semiconductor component 106 is described herein as including semiconductor materials, other materials may be used. For example, glass, silicon carbide, and aluminum nitride may be used in the passive semiconductor component 106.

[0015] The die attach materials 108 and 128 are highly thermally conductive. In the example, die attach materials 108 and / or 128 comprise a polymeric material (e.g., a thermosetting polymer matrix, such as ATROX® 800HT7A), and one or both of die attach materials 108 and 128 have a thermal conductivity of at least 75 watts per meter Kelvin (W / mK). Such materials can be applied, for example, using a time-pressure distribution technique, and have a thickness in the range of 10 micrometers to 100 micrometers, where thicknesses below this range are disadvantageous because thinner die attach materials will have higher stress and thus cause delamination, and thicknesses above this range are disadvantageous because uneven sintering can occur within the material and lead to delamination and cracking. In the example, die attach materials 108 and / or 128 comprise a polymeric material (e.g., a thermosetting polymer matrix, such as ATROX® 800HT2VX), and one or both of die attach materials 108 and 128 have a thermal conductivity of at least 175 W / mK. Such materials can be applied, for example, using screen printing or stencil printing techniques, and have a thickness in the range of 10 micrometers to 100 micrometers. Thicknesses below this range are disadvantageous because thinner materials are at risk of delamination due to higher stress, and thicknesses above this range are disadvantageous because uneven sintering can occur within the material, leading to delamination and cracking.

[0016] The insulating layer 116 may include a passivation outer coating comprising an inorganic dielectric material (e.g., silicon nitride, silicon dioxide, or oxide oxynitride, which can be deposited using techniques such as plasma-enhanced chemical vapor deposition (PECVD), low-pressure CVD, or atomic layer deposition) or a polymer outer coating (e.g., polyimide, benzocyclobutene, or other epoxy-based materials, which can be deposited using techniques such as spraying). The insulating layer 116 has a thickness ranging from 1 micrometer to 20 micrometers, where thicknesses below this range are disadvantageous because they are too thin to provide adequate insulation, and thicknesses above this range are disadvantageous due to a significant negative impact on thermal properties, particularly for coatings with lower thermal conductivity. The insulating layer 116 has a thickness of at least 1 × 10⁻⁶. 12 The resistivity is measured in ohmmeters, where values ​​below this range are undesirable because they result in unacceptable levels of current leakage.

[0017] Cavity 114 contains die attachment material 128 and prevents die attachment material 128 from leaking downwards toward other conductive structures (e.g., passive semiconductor component 106, die attachment material 108, die attachment pad 102, conductive terminal 104) above the edge of top surface 112. Cavity 114 may have a volume to accommodate die attachment material 128 and a portion of active semiconductor die 122 below a horizontal plane defined by a top surface 134 of a portion of the contact top surface 112 of insulating layer 116. For example, a larger volume of cavity 114 may be chosen in response to a heavier and / or larger active semiconductor die 122, because such a semiconductor die is more likely to cause die attachment material 128 to flow out of cavity 114. Similarly, a larger volume of die attachment material 128 can be selected for the cavity 114 in response to a larger volume of die attachment material 128, because this larger volume of die attachment material 128 is more likely to cause the die attachment material 128 to flow out of the cavity 114. Likewise, a larger volume of the cavity 114 can be selected in response to a lower viscosity of die attachment material 128, because lower viscosity may make it easier for the die attachment material 128 to flow out of the cavity 114. Furthermore, the horizontal region of the top surface 112 can be selected based on one or more of the aforementioned factors (e.g., the volume or weight of the active semiconductor die 122, the volume of the die attachment material 128, the viscosity of the die attachment material 128) and the volume of the cavity 114. This is because the top surface 112 serves as a backup safety measure to prevent the die attachment material 128 from reaching and leaking above the outer edge of the top surface 112 in the event that the die attachment material 128 flows out of the cavity 114. The larger the horizontal area of ​​the top surface 112, the more difficult it is for the die attachment material 128 to reach the outer edge of the top surface 112 and leak over said outer edge. Therefore, the depth of the cavity 114 should be at least 50% of the thickness of the semiconductor die 122, where a depth smaller than this range significantly increases the risk of die attachment material overflowing onto the top surface 112 and / or exceeding the outer edge of the top surface 112, thereby causing reliability challenges (e.g., electrical short circuits). Furthermore, to further mitigate the risk of the die attachment material 128 reaching and leaking above the outer edge of the top surface 112, the viscosity of the die attachment material 128 is selected to be in the range of 5,000 mPa⁻² to 50,000 mPa⁻². Viscosities below this range are disadvantageous because the risk of leakage above the outer edge of the top surface 112 is too high under conventional manufacturing conditions, and viscosities above this range are disadvantageous because the die attachment material 128 will not flow sufficiently to provide a uniform planar adhesive, which the active semiconductor die 122 can utilize to attach to the insulating layer 116. Due to one or more of the foregoing measures, a vertical gap separates the topmost portion of the die attachment material 128 from the horizontal plane defined by the top surface 134.

[0018] In some examples, cavity 114 may contain multiple active semiconductor dies. Figures 2A to 2D These are cross-sectional views, top-bottom views, sectional views, and perspective views of semiconductor packages containing cavities for electrical isolation and heat dissipation, based on various examples. More specifically, Figures 2A to 2D Display and Figures 1A to 1D The semiconductor package 100 is the same as the semiconductor package 200 (and therefore the above is for...). Figures 1A to 1D The provided description also applies Figures 2A to 2D ,achieve Figures 2A to 2D and Figures 1A to 1D The difference lies in the degree of matching, where the cavity 114 in semiconductor package 200 contains multiple active semiconductor dies 222a and 222b. Although the cavity 114 in semiconductor package 200 is shown as containing two active semiconductor dies 222a and 222b, in some examples, the cavity 114 may contain three or more active semiconductor dies. Die attachment material 128 attaches the active semiconductor dies 222a and 222b to a portion of the bottom surface 118 of the contact cavity 114 of the insulating layer 116. The cavity 114 in semiconductor package 200 is larger than the cavity 114 in semiconductor package 100 to accommodate multiple semiconductor dies 222a and 222b and additional volume of die attachment material 128 for attaching the multiple semiconductor dies 222a and 222b to the passive semiconductor member 106. Each of the active semiconductor dies 222a and 222b has a device side in which an integrated circuit is formed, and the device side faces away from the passive semiconductor component 106. A bonding wire 230a is attached to the device side of the active semiconductor die 222a and a first conductive terminal 104. A bonding wire 230b is attached to the device side of the active semiconductor die 222b and a second conductive terminal 104.

[0019] In some examples, a semiconductor package may contain multiple active semiconductor dies, each of which is in a separate cavity. Figures 3A to 3D These are cross-sectional views, top-bottom views, sectional views, and perspective views of semiconductor packages containing cavities for electrical isolation and heat dissipation, based on various examples. More specifically, Figures 3A to 3D Display and Figures 1A to 1D The semiconductor package 100 is the same as the semiconductor package 300 (and therefore the above is for...). Figures 1A to 1D The provided description also applies Figures 3A to 3D ,achieve Figures 3A to 3D and Figures 1A to 1DThe degree of matching differs in that the semiconductor package 300 includes multiple cavities 314a and 314b in the passive semiconductor component 106, and different active semiconductor dies 322a and 322b are respectively placed inside each of the cavities 314a and 314b. The above refers to... Figures 1A to 1D The description provided for cavity 114 also applies to each of cavities 314a and 314b. The description provided above for each of the active semiconductor dies 122 also applies to each of active semiconductor dies 322a and 322b. Insulating layer 116 covers multiple (e.g., all) surfaces of each of cavities 314a and 314b, such as the base plate and sidewalls of cavities 314a and 314b. Die attachment material 328a attaches semiconductor die 322a to insulating layer 116 in cavity 314a, and die attachment material 328b attaches active semiconductor die 322b to insulating layer 116 in cavity 314b. The topmost portion of die attachment material 328a is separated from the horizontal plane defined by top surface 134 by a vertical gap. This vertical gap has the same characteristics as described above. Figures 1A to 1D The vertical gap described has the same physical characteristics, so it will not be repeated here. Similarly, the topmost portion of the bare die attachment material 328b is separated from the horizontal plane defined by the top surface 134 by the vertical gap. This vertical gap has the same physical characteristics as the one described above. Figures 1A to 1D The physical characteristics of the vertical gaps described are the same, so they will not be repeated here. Each of the active semiconductor dies 322a and 322b has a device side in which an integrated circuit is formed and the device side faces away from the passive semiconductor member 106. Bonding wire 330a attaches the device side of the active semiconductor die 322a to a first conductive terminal 104, and bonding wire 330b attaches the device side of the active semiconductor die 322b to a second conductive terminal 104.

[0020] Figure 4 This is a flowchart of a method 400 for manufacturing a semiconductor package containing cavities for electrical isolation and heat dissipation, according to various examples. Figures 5A to 5H This describes the fabrication process of a semiconductor package containing cavities for electrical isolation and heat dissipation, based on various examples. Therefore, they are now described in parallel. Figure 4 And 5A to 5H.

[0021] In the example, method 400 includes etching a semiconductor wafer having first and second opposing surfaces to form a cavity (402). Figure 5A This is a cross-sectional view of a semiconductor wafer 500 having opposing surfaces 502 and 504. The semiconductor wafer 500 is passive, meaning that no circuit system is formed in the semiconductor wafer 500. Figure 5B yes Figure 5AThe cross-sectional view of semiconductor wafer 500 differs in that cavities 506 and 508 have been etched into surface 502 of semiconductor wafer 500. Any suitable technique can be used to form cavities 506 and 508, such as deep reactive ion etching (DRIE), wet chemical etching, laser ablation, focused ion beam (FIB) milling, etc. Semiconductor wafer 500 represents a device used to form passive semiconductor component 106. Figures 1A to 1D Semiconductor materials (2A to 2D and 3A to 3D). The semiconductor wafer 500 may have physical characteristics attributed herein to the passive semiconductor component 106.

[0022] Method 400 includes applying an insulating layer to the cavity and a first surface (404) of the semiconductor wafer. Figure 5C yes Figure 5B The cross-sectional view of the structure differs in that insulating layer 510 is applied to surface 502 and to some or all surfaces of cavities 506, 508. Insulating layer 510 represents insulating layer 116. Figures 1A to 1D (2A to 2D and 3A to 3D), and may have physical characteristics attributed herein to insulating layer 116. Various techniques may be used to apply insulating layer 510 to various surfaces 502 and cavities 506 and 508, such as PECVD, low-pressure CVD, spraying, etc.

[0023] Method 400 involves sawing a semiconductor wafer to produce a semiconductor component containing a cavity (406). Any suitable technique may be useful, such as a mechanical saw or a laser saw. Figure 5D yes Figure 5C The cross-sectional view of the structure differs in that the number 512 indicates that the semiconductor wafer 500 has been sawn to produce multiple separate passive semiconductor components 514 and 516. Passive semiconductor components 514 and 516 represent passive semiconductor component 106 ( Figures 1A to 1D (2A to 2D and 3A to 3D). Each of the passive semiconductor components 514 and 516 has a different insulating layer 510 due to sawing.

[0024] Method 400 includes attaching a second surface to a metal die attachment pad (408) using a first die attachment material. Figure 5E yes Figure 5D The passive semiconductor component 514 is shown in a cross-sectional view, except that die attachment material 518 attaches the passive semiconductor component 514 to die attachment pad 520. Die attachment material 518 represents die attachment material 108, and die attachment pad 520 represents die attachment pad 102. Figures 1A to 1D(2A to 2D and 3A to 3D). Any suitable technique can be used to apply the bare film attachment material 518, such as time-pressure distribution technique, stencil printing or screen printing, etc.

[0025] Method 400 includes attaching a semiconductor die to a semiconductor component (410) inside a cavity using a second die attachment material. In the example, all the second die attachment material remains in contact with the insulating layer during and after attaching the semiconductor die to the semiconductor component (410). Figure 5F yes Figure 5E The cross-sectional view of the structure differs in that the active semiconductor die 522 is attached to the insulating layer 510 inside the cavity 506 using die attachment material 524. The die attachment material 524 can be applied by any suitable technique, such as time-pressure dispensing or screen printing or stencil printing. Die attachment material 524 represents die attachment material 128, and therefore the description provided herein for die attachment material 128 also applies to die attachment material 524. As shown, all die attachment material 524 remains in contact with the insulating layer 510 during and after the active semiconductor die 522 is attached to the insulating layer 510. In some examples, the die attachment material 524 is completely retained within the cavity 506 during and after the active semiconductor die 522 is attached to the insulating layer 510. In other examples, the die attachment material 524 flows out of the cavity 506 during and / or after the active semiconductor die 522 is attached to the insulating layer 510, but in such examples, the die attachment material 524 does not reach the outer edge of the top surface of the passive semiconductor member 514 (i.e., the periphery of the top surface of the insulating layer 510). As described above, the die attachment material 524 is prevented from reaching this periphery by one or more of the following: the volume of the cavity 506, the volume of the die attachment material 524, the weight and / or volume of the active semiconductor die 522, the viscosity of the die attachment material 524, and / or the area of ​​the top surface of the passive semiconductor member 514 (i.e., the area of ​​the portion of the insulating layer 510 in contact with surface 502).

[0026] Method 400 includes attaching bonding wires to the device side of a semiconductor die in which a circuit system is formed and attaching them to conductive terminals (412). Figure 5G yes Figure 5F The cross-sectional view of the structure differs in that the bonding wire 526 is attached to the device side of the active semiconductor die 522 and to the conductive terminal 528.

[0027] Method 400 includes covering a metal die attachment pad, a conductive terminal, a semiconductor component, first and second die attachment materials, an insulating layer, a semiconductor die, and a bonding wire (414) with a molding compound. Figure 5H yes Figure 5GA cross-sectional view of the structure, the difference being that molding compound 530 covers and contacts all remaining components of the completed semiconductor package 532, as shown.

[0028] Figure 6 This is a block diagram of an electronic device comprising a semiconductor package with cavities for electrical isolation and heat dissipation, based on various examples. More specifically, Figure 6 An electronic device 600 is shown, comprising a printed circuit board (PCB) 602 to which a semiconductor package 604 is attached. Semiconductor package 604 refers to various semiconductor packages described herein, such as semiconductor packages 100, 200, 300, and 532. Semiconductor package 604 can be used in applications such as high-speed multiplexer / demultiplexer switches, voltage level shifters and bidirectional bus transceivers, current shunt monitors, power switches, current sensors, etc. The scope of this disclosure is not limited to these or any other applications.

[0029] In this specification, the term "attachment" may cover a connection, communication, or signal path that achieves a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first example, device A is attached to device B via a direct connection; or (b) in a second example, device A is attached to device B via an intermediate component C, provided that the intermediate component C does not alter the functional relationship between device A and device B such that device B is controlled by device A via the control signal generated by device A.

[0030] As used herein, the terms “conductive terminal,” “node,” “interconnect,” “pin,” and “lead” are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to refer to interconnects or ends thereof between device elements, circuit elements, integrated circuits, devices, or semiconductor assemblies.

Claims

1. A semiconductor package comprising: bare die attachment pads; A semiconductor component having a bottom surface attached to the die attachment pad, a top surface opposite the bottom surface, and a cavity; An insulating layer, which is in the cavity and on at least a portion of the top surface; as well as A semiconductor die, which is located inside the cavity and attached to the insulating layer by a die attachment material.

2. The semiconductor package of claim 1, further comprising a vertical gap between the topmost portion of the die attachment material and a horizontal plane defined by a top surface of a portion of the top surface of the insulating layer that contacts the semiconductor member.

3. The semiconductor package according to claim 1, wherein the insulating layer comprises an inorganic dielectric material.

4. The semiconductor package of claim 1, wherein the insulating layer has a thickness in the range of 1 micrometer to 20 micrometers.

5. The semiconductor package of claim 1, wherein the die attachment material has a thermal conductivity of at least 75 watts per meter (W / mK).

6. The semiconductor package of claim 1, wherein the volume of the cavity is greater than the combination of the volume of the die attachment material and the volume of a portion of the semiconductor die, the portion of the semiconductor die being below a horizontal plane defined by a top surface of a portion of the top surface of the insulating layer that contacts the semiconductor member.

7. The semiconductor package of claim 1, wherein the die attachment material is a first die attachment material, and the semiconductor package further includes a second die attachment material between the die attachment pad and the semiconductor component.

8. A semiconductor package comprising: Metal bare die attachment pads; A first bare die attachment material contacts the metal bare die attachment pad; A semiconductor component having a first surface in contact with the first die attachment material, a second surface opposite to the first surface, and a cavity including a cavity wall and a cavity base plate; An insulating layer that contacts the second surface, the cavity wall, and the cavity bottom plate; A second die attachment material contacts the insulating layer on the cavity wall and the cavity floor, wherein the top surface of the second die attachment material is located below a horizontal plane defined by the top surface of the insulating layer that contacts a portion of the second surface; A semiconductor die having a device side and a non-device side opposite to the device side, the non-device side contacting a second die attachment material; Bonding wires are attached to the device side of the semiconductor die and to conductive terminals; as well as Molding compound that contacts the metal die attachment pads, the first die attachment material and the second die attachment material, the semiconductor component, the insulating layer, the semiconductor die, the bonding wire and the conductive terminal.

9. The semiconductor package of claim 8, further comprising: A second cavity, located within the semiconductor component, comprising a second cavity wall and a second cavity base plate, wherein the insulating layer contacts the second cavity base plate and the second cavity wall; and A second semiconductor die is attached to the insulating layer on the second cavity wall and the second cavity base plate by a third die attachment material, the topmost portion of which is located below the horizontal plane.

10. The semiconductor package of claim 8, wherein the second surface surrounds the cavity.

11. The semiconductor package of claim 8, wherein the volume of the cavity is greater than the combination of the volume of the second die attachment material and the volume of a portion of the semiconductor die below the horizontal plane.

12. The semiconductor package of claim 8, wherein the insulating layer comprises an inorganic dielectric material selected from the group consisting of silicon nitride, silicon dioxide, and oxides oxynitride.

13. The semiconductor package of claim 8, wherein the insulating layer has a thickness in the range of 1 micrometer to 20 micrometers.

14. The semiconductor package of claim 8, wherein the second die attachment material has a thermal conductivity of at least 75 watts per meter (W / mK).

15. The semiconductor package of claim 8, further comprising a second semiconductor die in the cavity and in contact with the second die attachment material, the second semiconductor die having a second device side attached to a second conductive terminal via a second bonding wire.

16. A method for manufacturing a semiconductor package, comprising: Etching semiconductor wafers to form cavities; An insulating layer is deposited on the semiconductor wafer; The semiconductor wafer is sawn to produce a semiconductor component containing the cavity; The semiconductor component is attached to the metal die attachment pad using a first die attachment material; The semiconductor die is attached to the semiconductor component inside the cavity using a second die attachment material; The bonding wire is attached to the device side of the semiconductor die and to the conductive terminal. as well as The molding compound covers the metal die attachment pads, the conductive terminals, the semiconductor components, the first die attachment material and the second die attachment material, the insulating layer, the semiconductor die, and the bonding wires.

17. The method of claim 16, wherein depositing the insulating layer comprises using plasma-enhanced chemical vapor deposition (PECVD) or spraying techniques.

18. The method of claim 16, wherein the insulating layer has a thickness in the range of 1 micrometer to 20 micrometers.

19. The method of claim 16, wherein the depth of the cavity is at least 50% of the thickness of the semiconductor die.

20. The method of claim 16, wherein during the attachment of the semiconductor die to the semiconductor component, the second die attachment material fills the cavity and flows onto a portion of the top surface of the insulating layer that contacts the semiconductor component, without flowing through the periphery of the top surface.

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