A double-sided heat dissipating semiconductor package device and a method for manufacturing the same

Abstract

The application relates to the technical field of semiconductor packaging, and discloses a double-sided heat dissipation semiconductor packaging device and a preparation method thereof. The device comprises a lead frame, a semiconductor chip, a metal clamping sheet and a plastic sealing body. The lead frame comprises a lead frame body and a pin. The semiconductor chip is arranged on the lead frame. The metal clamping sheet comprises a metal clamping sheet body and a connecting arm formed by extending from the metal clamping sheet body. The metal clamping sheet body covers the semiconductor chip, and the connecting arm is connected with the pin at an end away from the metal clamping sheet body. The plastic sealing body wraps the lead frame, the semiconductor chip and the metal clamping sheet. The thickness ratio of the metal clamping sheet body to the lead frame body ranges from 1.15:1 to 1.35:1. The application has the effect of avoiding warping deformation of the packaging device.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and proposes a double-sided heat dissipation semiconductor packaging device and its fabrication method. Background Technology

[0002] In the field of semiconductor packaging, with the continuous improvement of the performance of electronic devices and the development trend of miniaturization and integration, the power density of semiconductor chips is increasing day by day, and heat dissipation has become a key factor restricting their performance and reliability.

[0003] In the past, various methods have been used in the industry to solve the heat dissipation problem of semiconductor chips. One common approach is to use metal clips on the top surface of the chip and a metal frame on the bottom surface for heat dissipation. However, these existing heat dissipation methods have significant drawbacks when dealing with the thermal processes of semiconductor packaging. Due to the mismatch in the coefficients of thermal expansion of different materials, combined stresses are generated during the packaging thermal process, leading to warping and deformation of the packaged device. This warping and deformation not only affects the appearance and dimensional accuracy of the packaged device, but may also cause loosening or damage to the connection between the chip and other components, seriously affecting the performance and reliability of the semiconductor package.

[0004] The aforementioned technologies suffer from the defect of mismatched thermal expansion coefficients of different materials, leading to warping and deformation of the packaged devices. Summary of the Invention

[0005] In order to avoid warping and deformation of the packaged device, this application provides a double-sided heat dissipation semiconductor packaged device and its fabrication method.

[0006] On the one hand, the double-sided heat dissipation semiconductor packaging device provided in this application adopts the following technical solution: A double-sided heat-dissipating semiconductor package device, comprising: A lead frame, comprising a lead frame body and multiple pins; A semiconductor chip is disposed on the lead frame; A metal clip includes a metal clip body and a connecting arm extending from the metal clip body, the metal clip body covering the semiconductor chip, and one end of the connecting arm away from the metal clip body being connected to the pin. A molding compound encapsulates the lead frame, the semiconductor chip, and the metal clip; wherein the ratio of the thickness of the metal clip body to the thickness of the lead frame body is in the range of 1.15:1 to 1.35:1.

[0007] By adopting the above technical solution, during the reflow soldering and high-temperature operation of semiconductor packaging, the significant differences in the coefficients of thermal expansion (CTE) of the molding compound, lead frame, metal clip, and semiconductor chip, coupled with the connecting arm extending from one end of the metal clip, lead to an asymmetry between the mechanical constraint force inside the package and the shrinkage volume of the molding compound. This asymmetry easily generates combined thermal stress, causing warpage deformation of the packaged device. This application limits the thickness ratio of the metal clip body to the lead frame body to 1.15:1-1.35:1. This specific thickness asymmetry design effectively compensates for the structural asymmetry caused by the connecting arm, ensuring that the neutral strain surface of the entire packaged device during thermodynamic deformation is precisely translated and maintained at the center layer of the semiconductor chip. This mechanical balance design effectively counteracts the combined thermal bending moment generated during the packaging thermal process, minimizing the warpage risk of the packaged device and significantly improving the coplanarity qualification rate of the leads. Furthermore, the elimination of warpage greatly reduces the risk of stress peeling of the internal interface of the packaged device and the risk of stress cracking of the semiconductor chip, thereby significantly extending the service life of the packaged device under harsh high and low temperature cycling environments. At the same time, the use of large-area metal clips instead of traditional metal wire bonding provides a conduction path with extremely low thermal resistance for the upper surface of the chip. Combined with the bottom lead frame, this achieves a highly efficient and reliable double-sided heat dissipation structure.

[0008] Optionally, the thickness of the lead frame body is in the range of 200-600um; the thickness of the semiconductor chip is in the range of 50-200um; and the thickness of the metal clip body is in the range of 250-800um.

[0009] By adopting the above technical solution, the dimensions are quantified, with the lead frame body thickness ranging from 200-600µm, the semiconductor chip thickness ranging from 50-200µm, and the metal clip body thickness ranging from 250-800µm. This ensures that the ratio of the metal clip body thickness to the lead frame body thickness is achieved within the range of 1.15:1-1.35:1, while also ensuring that the overall thickness of the packaged device meets the requirements of modern thinner and lighter electronic products. Furthermore, the 250-800µm metal clip is sufficient to withstand the current surges of common power devices.

[0010] Optionally, the connecting arm extends from the metal clip body toward the pin by bending, and one end of the connecting arm away from the metal clip body lies flat and overlaps the pin.

[0011] By adopting the above technical solution, the bending structure gives the connecting arm a certain degree of elasticity. During packaging and temperature cycling, the connecting arm can act as a buffer spring, absorbing the thermomechanical stress between the semiconductor chip, metal clip, and molding compound. The flat overlap maximizes the contact area between the connecting arm and the pin, avoiding localized overheating and excessive resistance caused by point contact, thus improving soldering yield and connection strength.

[0012] Optionally, the molding compound has a first heat dissipation window for exposing the lead frame body, a second heat dissipation window for exposing the metal clip, and a plurality of pin through holes for exposing the pins.

[0013] By employing the above technical solution, the first and second heat dissipation windows eliminate the obstruction of heat dissipation by the molding compound. This allows external heat sinks or cold plates to directly contact the metal inside the package, greatly reducing thermal resistance. This semi-exposed structure is generally more advantageous for controlling the overall package thickness than a fully encapsulated structure.

[0014] Optionally, the surface of the lead frame body located within the first heat dissipation window constitutes a first heat dissipation surface, and the surface of the metal clip located within the second heat dissipation window constitutes a second heat dissipation surface.

[0015] By adopting the above technical solution, the existence of the heat dissipation contact surface is clearly defined, facilitating subsequent processes (such as electroplating and soldering heat sinks onto the heat dissipation surface). This structural design allows the device to be mounted using a top-mount heat dissipation process, increasing the flexibility of application scenarios.

[0016] Optionally, a solder layer is provided between the lead frame body and the semiconductor chip, between the semiconductor chip and the metal clip, and between the pin and the connecting arm.

[0017] By employing the above technical solutions, solder layers (such as solder paste and solder pads) exhibit higher thermal and electrical conductivity compared to conductive adhesives, making them suitable for the stringent requirements of power semiconductors. The intermetallic compound formed by the solder provides a robust mechanical bond, ensuring that the structure does not loosen under thermal cycling shock.

[0018] On the other hand, this application provides a method for fabricating a double-sided heat-dissipating semiconductor packaged device using the following technical solution: A method for fabricating a double-sided heat-dissipating semiconductor packaged device, comprising: S2. Apply a solder layer to the lead frame body and multiple pins; S3. Place the semiconductor chip on the lead frame body; S4. Apply a solder layer onto the semiconductor chip; S5. Place a metal clip body on the semiconductor chip, and have the connecting arm overlap the pin; S6. Bake and solder the lead frame body, the semiconductor chip and the metal clip body; S7. The lead frame body, the semiconductor chip, the metal clip body, and the connecting arm are encapsulated to form a plastic encapsulation body that encapsulates the lead frame body, the semiconductor chip, the metal clip body, and the connecting arm, thereby forming a packaged device; wherein the thickness ratio of the metal clip body to the lead frame body is in the range of 1.15:1 to 1.35:1.

[0019] By adopting the above technical solution, a standard process of first mounting, then baking, and finally molding is employed, which is highly compatible with existing surface mount equipment. Clearly separating the tasks of soldering and molding ensures that the semiconductor chip has achieved reliable electrical connection before being encapsulated in the molding compound, facilitating the monitoring of soldering quality.

[0020] Optionally, in step S7, the packaging device has a first heat dissipation window for exposing the lead frame body and a second heat dissipation window for exposing the metal clip body.

[0021] By adopting the above technical solution, heat dissipation through holes are formed simultaneously during the molding process, avoiding the risk of chip damage during subsequent mechanical processing and ensuring the cleanliness and positional accuracy of the heat dissipation interface.

[0022] Optionally, the method may also include the following steps before step S2: S1. The wafer is diced to form a plurality of semiconductor chips.

[0023] By adopting the above technical solutions, the process chain is extended upstream, the source and processing of semiconductor chips are clarified, and the protection scope of the manufacturing method is made more complete.

[0024] Optionally, the process may further include the following after step S7: S8. Tin plating is performed on the lead frame body, the pins and the metal clip body that expose the plastic encapsulation. S9. Perform lead trimming on the multiple packaged devices; S10. Test the packaged device; S11. Package the encapsulated device.

[0025] By adopting the above technical solutions, tin plating prevents lead oxidation and ensures high soldering yield during PCB mounting. Lead shaving separates the lead frame strips into independent units; testing removes defective products, ensuring shipment quality; and packaging facilitates transportation and automated pick-and-place machine processing. These steps transform semi-finished products into commercially viable final products.

[0026] In summary, this application includes at least one of the following beneficial technical effects: 1. During the reflow soldering and high-temperature operation of semiconductor packaging, the significant differences in the coefficients of thermal expansion (CTE) of the molding compound, lead frame, metal clips, and semiconductor chip, coupled with the connecting arm extending from one end of the metal clip, lead to an asymmetry between the mechanical constraint force inside the package and the shrinkage volume of the molding compound. This asymmetry easily generates combined thermal stress, causing warpage deformation of the packaged device. This application limits the thickness ratio of the metal clip body to the lead frame body to 1.15:1-1.35:1. This specific thickness asymmetry design effectively compensates for the structural asymmetry caused by the connecting arm, ensuring that the neutral strain surface of the entire packaged device during thermodynamic deformation is precisely translated and maintained at the center layer of the semiconductor chip. This mechanical balance design effectively counteracts the combined thermal bending moment generated during the packaging thermal process, minimizing the risk of warpage and significantly improving the coplanarity yield of the leads. In addition, the elimination of warpage greatly reduces the risk of stress peeling of the internal interface of the packaged device and the risk of stress cracking of the semiconductor chip, thereby significantly extending the service life of the packaged device in harsh high and low temperature cycling environments; at the same time, the use of large-area metal clips to replace traditional metal wire bonding provides a conduction path with extremely low thermal resistance for the upper surface of the chip, and together with the bottom lead frame, a highly efficient and reliable double-sided heat dissipation structure is achieved. 2. By quantifying the dimensions, the thickness of the leadframe body ranges from 200-600µm, the semiconductor chip thickness ranges from 50-200µm, and the metal clip body thickness ranges from 250-800µm. This ensures that the ratio of the metal clip body thickness to the leadframe body thickness is achieved within the range of 1.15:1-1.35:1, while also ensuring that the overall thickness of the packaged device meets the requirements of modern thinner and lighter electronic products. At the same time, the 250-800µm metal clip is sufficient to withstand the current surges of common power devices. 3. The bent structure gives the connector arm a certain degree of elasticity, allowing it to act as a buffer spring during packaging and temperature cycling, absorbing the thermomechanical stress between the semiconductor chip, metal clips, and molding compound. The flat overlap maximizes the contact area between the connector arm and the pins, avoiding localized overheating and excessive resistance caused by point contact, thus improving soldering yield and connection strength. 4. It adopts a standard process of first mounting, then baking, and finally molding, which is highly compatible with existing surface mount equipment. The clear division of labor between soldering and molding ensures that the semiconductor chip has achieved reliable electrical connection before being encapsulated, facilitating the monitoring of soldering quality. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the structure of a double-sided heat dissipation semiconductor packaging device from a first angle according to an embodiment of this application; Figure 2 This is a schematic diagram of the structure of a double-sided heat dissipation semiconductor packaging device from a second angle according to an embodiment of this application; Figure 3 This is a cross-sectional view of a double-sided heat dissipation semiconductor packaging device according to an embodiment of this application; Figure 4 This is a flowchart of a method for fabricating a double-sided heat-dissipating semiconductor packaged device according to an embodiment of this application.

[0028] Explanation of reference numerals in the attached figures: 10, lead frame; 11, lead frame body; 12, pin; 13, first heat dissipation surface; 20, semiconductor chip; 30, metal clip; 31, metal clip body; 32, connecting arm; 33, second heat dissipation surface; 40, molding compound; 41, first heat dissipation window; 42, second heat dissipation window; 43, pin through-hole; 50, solder layer. Detailed Implementation

[0029] The following combination Figures 1-4 This application will be described in further detail.

[0030] This application discloses a double-sided heat dissipation semiconductor packaging device.

[0031] Figure 1 This is a schematic diagram of the structure of a double-sided heat dissipation semiconductor packaging device from a first angle according to an embodiment of this application. Figure 2 This is a schematic diagram of the structure of a double-sided heat dissipation semiconductor packaging device from a second angle according to an embodiment of this application. Figure 3 This is a cross-sectional view of a double-sided heat-dissipating semiconductor packaged device according to an embodiment of this application. (Refer to...) Figure 1 , Figure 2 and Figure 3 The double-sided heat-dissipating semiconductor package includes a lead frame 10, a semiconductor chip 20, a metal clip 30, and a molding compound 40. The semiconductor chip 20 is disposed on the lead frame 10, the metal clip 30 is disposed on the semiconductor chip 20, and the molding compound 40 encapsulates the lead frame 10, the semiconductor chip 20, and the metal clip 30 to form a package.

[0032] The lead frame 10 includes a lead frame body 11 and a plurality of pins 12. The lead frame body 11 is located below the semiconductor chip 20 and is used to support the semiconductor chip 20. The metal clip 30 includes a metal clip body 31 and a connecting arm 32 extending from the metal clip body 31. The metal clip body 31 is located above the semiconductor chip 20. The connecting arm 32 bends and extends from the metal clip body 31 toward the pins 12, and one end of the connecting arm away from the metal clip body 31 lies flat and overlaps the pins 12.

[0033] Solder layers 50 are provided between the lead frame body 11 and the semiconductor chip 20, between the semiconductor chip 20 and the metal clip body 31, and between the connecting arm 32 and the pin 12.

[0034] The molding compound 40 has a first heat dissipation window 41 for exposing the lead frame body 11, a second heat dissipation window 42 for exposing the metal clip body 31, and a pin through-hole 43 for exposing the pins 12. The surface of the lead frame body 11 located within the first heat dissipation window 41 forms a first heat dissipation surface 13, and the surface of the metal clip 30 located within the second heat dissipation window 42 forms a second heat dissipation surface 33.

[0035] The thickness ratio of the metal clip body 31 to the lead frame body 11 ranges from 1.15:1 to 1.35:1, preferably 5:4. The thickness of the lead frame body 11 can range from 200 to 600 μm, preferably 400 μm; the thickness of the metal clip body 31 can range from 250 to 800 μm, preferably 500 μm; the thickness of the solder layer 50 can range from 20 to 80 μm, preferably 40 μm; and the thickness of the semiconductor chip 20 can range from 50 to 200 μm, preferably 100 μm.

[0036] Theoretical analysis of the composite stress balance of the packaged device: During the packaging process, the semiconductor chip 20 (with a coefficient of thermal expansion CTE of approximately 3ppm / ℃) is soldered between the lead frame 10 and the metal clips 30 (both made of copper, with a CTE of approximately 17ppm / ℃), and is encapsulated by the molding compound 40 (with a CTE of approximately 10-15ppm / ℃).

[0037] Due to the shrinkage of the molding compound 40 during cooling after high-temperature curing, and the significant CTE mismatch between the copper and silicon materials, shear stress will be generated at the interface of the semiconductor chip 20. According to the multilayer structure thermal stress model, the overall bending moment M of the packaged device can be approximately expressed as: Where E is the elastic modulus, α is the coefficient of thermal expansion CTE, ΔT is the temperature difference, A is the cross-sectional area, and z is the distance from the neutral axis.

[0038] In the double-sided heat-dissipating semiconductor package of this application, since the metal clip 30 includes the downwardly extending connecting arm 32 structure and its top is exposed, the mechanical constraint force exerted by the metal clip 30 on the molding compound 40 is not completely symmetrical with the bottom-laid lead frame 10. Through extensive mechanical calculations and simulations, it was found that when the thickness of the metal clip 30 is slightly greater than the thickness of the lead frame 10, and the ratio is maintained in the range of 1.15:1-1.35:1, it can compensate for the structural asymmetry caused by the connecting arm 32, so that the neutral strain plane of the entire package falls exactly on the central layer of the semiconductor chip 20, thereby achieving stress cancellation.

[0039] Comparison of simulation data (ANSYS finite element analysis) This application utilizes finite element analysis software, setting the molding and curing temperature to 175℃ and cooling to room temperature (25℃), to simulate warpage displacement for different thickness ratios. The results are shown in the table below: Control group A1 400 320 0.80:1 bend upwards 38.5 Severe warping Control group A2 400 400 1.00:1 bend upwards 22.3 Significant warping Control group A3 400 440 1.10:1 bend upwards 14.2 Exceeding tolerance Scope of this application 1 400 460 1.15:1 Slight increase 8.2 qualified Scope 2 of this application 400 500 1.25:1 Near level 4.8 Excellent Scope of this application 3 400 540 1.35:1 Slight decrease -7.5 qualified Control group B1 400 580 1.45:1 Bend downwards -18.6 Exceeding tolerance Control group B2 400 640 1.60:1 Bend downwards -32.4 Severe warping Experimental conclusion: Traditional techniques suggest that a symmetrical (1:1) thickness ratio between the metal clip body 31 and the lead frame body 11 minimizes stress. However, simulation data shows that even with a 1:1 thickness ratio (Comparison Group A2), the packaged device still exhibits a significant upward warping of 22.3 μm. This is because the connecting arm 32 extending from the metal clip body 31 disrupts the internal geometric symmetry of the molding compound 40, and the anchoring effect of the connecting arm 32 results in a greater contraction constraint force above the semiconductor chip 20 than below.

[0040] When the thickness ratio of the metal clip body 31 to the lead frame body 11 is increased to within the range of 1.15:1-1.35:1, the thickened metal clip body 31 effectively compensates for the structural stress deviation caused by the connecting arm 32 by increasing the mechanical rigidity of the upper structure. When the ratio of the metal clip body 31 to the lead frame body 11 is 1.25:1 (i.e., 5:4), the thermal bending moment of the packaged device reaches dynamic equilibrium, and the neutral strain plane coincides exactly with the center plane of the semiconductor chip 20, reducing the warpage displacement to 4.8 μm. This value is far below the industry tolerance standard (typically 50 μm), greatly improving the pin coplanarity.

[0041] Experimental verification and yield improvement: Shadow Moire testing was performed on 1000 packaged devices prepared with a thickness ratio of 5:4 between the metal clip body 31 and the lead frame body 11. The data showed that the pin coplanarity pass rate of the packaged devices increased from 85% to 99.2%. After 1000 cycles of TCT (high and low temperature cycling test, -55℃ to 150℃), ultrasonic scanning microscopy revealed no delamination at the interface between the semiconductor chip 20 and the solder layer 50 due to stress concentration. Because warpage was controlled, the contact thermal resistance between the first heat dissipation surface 13 and the second heat dissipation surface 33 and the external heat sink was reduced by 15%, ensuring efficient double-sided heat dissipation performance.

[0042] The implementation principle of a double-sided heat-dissipating semiconductor packaging device according to an embodiment of this application is as follows: During the reflow soldering and high-temperature operation of semiconductor packaging, due to the significant differences in the coefficients of thermal expansion (CTE) of the molding compound 40, the lead frame 10, the metal clip 30, and the semiconductor chip 20, and the fact that the metal clip 30 has a connecting arm 32 extending from one end, the mechanical constraint force inside the packaging device and the shrinkage volume of the molding compound exhibit an asymmetry, which easily generates compound thermal stress and causes the packaging device to warp and deform. This application limits the thickness ratio of the metal clip body 31 to the lead frame body 11 to a range of 1.15:1-1.35:1. This specific thickness asymmetry design can effectively compensate for the structural asymmetry caused by the connecting arm 32, so that the neutral strain surface of the entire packaging device in thermodynamic deformation is precisely translated and maintained in the central layer of the semiconductor chip 20. This mechanical balance design effectively offsets the compound thermal bending moment generated in the packaging thermal process, minimizes the warpage risk of the packaging device, and significantly improves the coplanarity qualification rate of the pins. Furthermore, the elimination of warpage significantly reduces the risk of stress peeling at the internal interface of the packaged device and the risk of stress cracking of the semiconductor chip 20, thereby significantly extending the service life of the packaged device under harsh high and low temperature cycling environments. Simultaneously, the use of large-area metal clips 30 instead of traditional metal wire bonding provides an extremely low thermal resistance conduction path for the chip's upper surface, which, together with the bottom lead frame 10, achieves a highly efficient and reliable double-sided heat dissipation structure.

[0043] This application also discloses a method for fabricating a double-sided heat-dissipating semiconductor packaged device.

[0044] Figure 4 This is a flowchart illustrating a method for fabricating a double-sided heat-dissipating semiconductor packaged device according to an embodiment of this application. (Refer to...) Figure 4 The method for fabricating the double-sided heat-dissipating semiconductor packaged device includes: S1. The wafer is diced to form a plurality of semiconductor chips 20.

[0045] S2. Apply solder layer 50 to lead frame body 11 and multiple pins 12.

[0046] S3. Place the semiconductor chip 20 on the lead frame body 11.

[0047] S4. Apply a solder layer 50 to the semiconductor chip 20.

[0048] S5. A metal clip body 31 is placed on the semiconductor chip 20, and the connecting arm 32 is attached to the pin 12.

[0049] S6. The lead frame body 11, the semiconductor chip 20 and the metal clip body 31 are baked and soldered.

[0050] S7. The lead frame body 11, the semiconductor chip 20, the metal clip body 31 and the connecting arm 32 are encapsulated to form a plastic encapsulation body 40 that encapsulates the lead frame body 11, the semiconductor chip 20, the metal clip body 31 and the connecting arm 32, thereby forming a packaged device.

[0051] S8. Tin plating is performed on the lead frame body 11, the pins 12 and the metal clip body 31 that expose the plastic encapsulation 40.

[0052] S9. Perform lead trimming on the multiple packaged devices.

[0053] S10. Test the packaged device.

[0054] S11. Package the encapsulated device.

[0055] The steps described above are explained in detail below.

[0056] In step S1, the wafer is diced to form multiple semiconductor chips 20. Specifically, the manufactured wafer is attached to a blue film (UV film), and then a high-speed rotating diamond blade (mechanical cutting) or laser cutting equipment is used to dice the entire wafer into individual semiconductor chips 20 along the scribe lines. Mechanical cutting is low-cost and a mature process, while laser cutting has a small heat-affected zone, is less prone to edge chipping, and can ensure the structural integrity of the edges of high-power chips.

[0057] In step S2, a solder layer 50 is applied to the lead frame body 11 and the plurality of pins 12. A stencil can be used to align the lead frame body 11 and the pins 12, and a squeegee is used to evenly apply conductive / thermal conductive solder paste (such as high-temperature lead-free solder paste SAC alloy or high-lead solder) onto the lead frame body 11 and the pins 12. Compared to dispensing, the solder paste application process provides extremely high solder thickness consistency (typically controlled within tens of micrometers), effectively reducing solder voids and providing a very low thermal resistance interface for large-area heat dissipation at the bottom.

[0058] In step S3, the semiconductor chip 20 is placed on the lead frame body 11. The pre-cut semiconductor chip 20 can be picked up from the blue film using the nozzle of a pick-and-place machine. Then, after precise alignment using a vision recognition system, the back side (typically the drain) of the semiconductor chip 20 is placed on the lead frame body 11. Visual alignment ensures the correct positioning of the semiconductor chip 20, preventing short circuits or poor contact during subsequent placement of the metal clip body 31 due to misalignment, and ensuring the reliability of the back side electrical connection and heat conduction path.

[0059] In step S4, a solder layer 50 is applied to the semiconductor chip 20. Specifically, a high-precision stencil and scraper are used to apply solder paste to the source and gate metallized areas on the front side of the semiconductor chip 20, preparing for the placement of the metal clip body 31 on top. Precise control of the solder paste amount prevents solder paste overflow during reflow soldering, which could cause a short circuit (bridging) between the source and gate, while also ensuring the formation of a large-area heat dissipation interface on top.

[0060] In step S5, a metal clip body 31 is placed on the semiconductor chip 20, and the connecting arm 32 overlaps the pin 12. High-precision metal strip mounting equipment can be used to precisely place the pre-stamped metal clip body 31 onto the solder paste on the front side of the semiconductor chip 20. One end of the metal clip body 31 contacts the source electrode of the semiconductor chip 20, and the connecting arm 32 overlaps the pin 12. Using thick copper clips instead of traditional aluminum or gold wire bonding greatly increases the cross-sectional area and reduces parasitic inductance. Simultaneously, the flat and thick metal clip body 31 creates a top heat conduction channel, laying the physical foundation for double-sided heat dissipation.

[0061] In step S6, the lead frame body 11, the semiconductor chip 20, and the metal clip body 31 are baked and soldered. The assembled frame can be placed into a multi-zone reflow oven. Following a set temperature profile (preheating, holding, reflow, cooling), the solder paste melts simultaneously to form an intermetallic compound (IMC), completing the soldering. A single reflow completes the soldering of both the top and bottom surfaces, avoiding stress damage to the semiconductor chip 20 caused by repeated heating. The optimized temperature profile effectively removes flux gas from the solder, reduces voids, and ensures extremely smooth bidirectional heat conduction paths.

[0062] In step S7, the lead frame body 11, the semiconductor chip 20, the metal clip body 31, and the connecting arm 32 are encapsulated to form a molded body 40 that encapsulates the lead frame body 11, the semiconductor chip 20, the metal clip body 31, and the connecting arm 32, thereby forming a packaged device. The thickness ratio of the metal clip body 31 to the lead frame body 11 ranges from 1.15:1 to 1.35:1. A transfer molding process can be used, in which epoxy resin molding compound (EMC) is injected into a mold cavity under high temperature and pressure to encapsulate the lead frame body 11, the semiconductor chip 20, the metal clip body 31, and the connecting arm 32. For a double-sided heat dissipation design, the top of the mold will be in close contact with the top surface of the metal clip body 31, or a thinning process can be used after molding to expose the top of the metal clip body 31 outside the molded body 40. The molding compound 40 provides mechanical protection and isolates external moisture. Exposing the top of the metal clip body 31 breaks through the bottleneck of the extremely low thermal conductivity (approximately 0.8-3 W / m·K) of traditional encapsulation molding materials, allowing heat to be directly conducted from the top of the metal clip body 31 to the external heat sink, achieving true double-sided heat dissipation.

[0063] In step S8, the lead frame body 11, the pins 12, and the metal clip body 31 exposed by the molded enclosure 40 are tin-plated. Specifically, a layer of pure tin or a tin alloy can be plated onto the surfaces of the lead frame body 11, the pins 12, and the metal clip body 31 exposed by the molded enclosure 40 using an electrochemical method in an electroplating bath, ensuring excellent solderability of the packaged device during final assembly (mounting onto the PCB board).

[0064] In step S9, the connecting ribs of the multiple packaged devices are cut. This can be done using a punching die or a sawing tool to cut the connecting ribs of the multiple packaged devices, separating the array of multiple packaged devices into individual packaged devices.

[0065] In step S10, the packaged device is tested. This can be achieved using automated testing equipment and a robotic arm to perform comprehensive electrical parameter tests (such as withstand voltage BVDSS, leakage current IDSS, on-resistance RDS(on), threshold voltage VTH, etc.) and thermal resistance tests on the packaged device. Defective products, such as those with poor soldering or damaged chips, are rejected to ensure that all packaged devices leaving the factory meet design specifications, especially the thermal reliability requirements under high current conditions.

[0066] In step S11, the packaged device is packaged. This involves placing the tested and qualified device into a tape reel, sealing it with heat-sealing tape, then placing it into an anti-static and moisture-proof aluminum foil bag and vacuum-sealing it. This facilitates automated SMT assembly production, and the vacuum sealing also provides anti-static and moisture-proof protection (MSL level control), ensuring the packaged device's quality is not compromised during transportation and storage.

[0067] The implementation principle of the method for fabricating a double-sided heat-dissipating semiconductor packaged device according to an embodiment of this application is as follows: A standard process of first mounting, then baking, and finally molding is adopted, which is highly compatible with existing surface mount equipment. The clear division of labor between soldering and molding ensures that the semiconductor chip 20 has achieved reliable electrical connection before being encapsulated by the molding compound 40, facilitating monitoring of soldering quality.

[0068] The above are all preferred embodiments of this application, and are not intended to limit the scope of protection of this application. Therefore, all equivalent changes made in accordance with the structure, shape and principle of this application should be covered within the scope of protection of this application.

Claims

1. A double-sided heat-dissipating semiconductor packaged device, characterized in that, include: The lead frame (10) includes a lead frame body (11) and multiple pins (12). A semiconductor chip (20) is disposed on the lead frame (10); The metal clip (30) includes a metal clip body (31) and a connecting arm (32) extending from the metal clip body (31), the metal clip body (31) covering the semiconductor chip (20), and the end of the connecting arm (32) away from the metal clip body (31) being connected to the pin (12). A molding compound (40) encapsulates the lead frame (10), the semiconductor chip (20), and the metal clip (30); wherein the ratio of the thickness of the metal clip body (31) to the thickness of the lead frame body (11) is 1.15:1 to 1.35:

1.

2. The double-sided heat-dissipating semiconductor packaged device according to claim 1, characterized in that, The thickness of the lead frame body (11) ranges from 200 to 600 μm; the thickness of the semiconductor chip (20) ranges from 50 to 200 μm; and the thickness of the metal clip body (31) ranges from 250 to 800 μm.

3. The double-sided heat-dissipating semiconductor packaged device according to claim 1, characterized in that, The connecting arm (32) extends from the metal clip body (31) toward the pin (12) and the end of the connecting arm (32) away from the metal clip body (31) is laid flat on the pin (12).

4. The double-sided heat-dissipating semiconductor packaged device according to claim 1, characterized in that, The encapsulation body (40) is provided with a first heat dissipation window (41) for exposing the lead frame body (11), a second heat dissipation window (42) for exposing the metal clip (30) and a plurality of pin through holes (43) for exposing the pins (12).

5. The double-sided heat-dissipating semiconductor packaged device according to claim 4, characterized in that, The surface of the lead frame body (11) located within the first heat dissipation window (41) constitutes the first heat dissipation surface (13), and the surface of the metal clip (30) located within the second heat dissipation window (42) constitutes the second heat dissipation surface (33).

6. The double-sided heat-dissipating semiconductor packaged device according to claim 1, characterized in that, A solder layer (50) is provided between the lead frame body (11) and the semiconductor chip (20), between the semiconductor chip (20) and the metal clip (30), and between the pin (12) and the connecting arm (32).

7. A method for fabricating a double-sided heat-dissipating semiconductor packaged device, characterized in that, include: S2. Apply solder layer (50) to lead frame body (11) and multiple pins (12). S3. Place the semiconductor chip (20) on the lead frame body (11); S4. Apply a solder layer (50) to the semiconductor chip (20); S5. A metal clip body (31) is placed on the semiconductor chip (20), and a connecting arm (32) is attached to the pin (12); S6. The lead frame body (11), the semiconductor chip (20) and the metal clip body (31) are baked and soldered. S7. The lead frame body (11), the semiconductor chip (20), the metal clip body (31) and the connecting arm (32) are encapsulated to form a plastic encapsulation body (40) that encapsulates the lead frame body (11), the semiconductor chip (20), the metal clip body (31) and the connecting arm (32) to form a packaged device; wherein the thickness ratio of the metal clip body (31) to the lead frame body (11) is in the range of 1.15:1-1.35:

1.

8. The method for fabricating a double-sided heat-dissipating semiconductor packaged device according to claim 7, characterized in that, In step S7, the packaging device has a first heat dissipation window (41) for exposing the lead frame body (11) and a second heat dissipation window (42) for exposing the metal clip body (31).

9. The method for fabricating a double-sided heat-dissipating semiconductor packaged device according to claim 7, characterized in that, The steps preceding step S2 also include: S1. The wafer is diced to form a plurality of semiconductor chips (20).

10. The method for fabricating a double-sided heat-dissipating semiconductor packaged device according to claim 7, characterized in that, The process after step S7 also includes: S8. Tin plating is performed on the lead frame body (11), the pin (12) and the metal clip body (31) that expose the plastic encapsulation body (40). S9. Perform lead trimming on the multiple packaged devices; S10. Test the packaged device; S11. Package the encapsulated device.

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