A SiC MOSFET solid-state relay package structure and manufacturing method

Abstract

The application provides a SiC MOSFET solid-state relay packaging structure and a manufacturing method, relates to the technical field of power semiconductor packaging, and comprises a PCB substrate, a bearing plate, a SiC MOSFET chip and a driving circuit. The PCB substrate is provided with an embedding cavity, a main circuit connection assembly and a gate control circuit. The bearing plate is arranged on the heat dissipation side of the PCB substrate and covers the embedding cavity. The chip is embedded in the embedding cavity. The drain electrode is electrically and thermally connected with the bearing plate and is connected with the main circuit connection assembly through a drain electrode interconnecting piece. The source electrode and the gate electrode are respectively led out to the circuit side of the PCB substrate through a source electrode interconnecting piece and a gate electrode interconnecting piece. The manufacturing method comprises PCB substrate preparation, chip sintering, bearing plate assembly, chip electrode interconnection and driving circuit installation. The application can shorten the power circuit and the heat dissipation path, improve the packaging integration and the working reliability.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor packaging technology, and in particular to a SiC MOSFET solid-state relay packaging structure and manufacturing method. Background Technology

[0002] As new energy vehicles and energy storage systems develop towards higher voltage, higher power density, and miniaturization, the Battery Disconnect Unit (BDU), as a switching and protection device between the power battery and the external high-voltage load, places higher demands on the electrical performance, heat dissipation capacity, and operational reliability of its switching devices. Traditional BDUs mainly use mechanical relays or contactors to control the switching of the main circuit. Solid-state relays based on SiC MOSFETs, with their advantages of fast switching speed, no contact wear, no arcing, and long service life, are gradually being applied to the high-voltage main circuits of vehicles and energy storage systems.

[0003] Existing BDU-based SiC MOSFET solid-state relays are typically packaged as independent power modules, and then assembled separately with drive and detection circuits, main circuit copper busbars, and heat dissipation components. Due to limitations in packaging and component layout, the connection path between the power device and the main circuit is long and involves numerous interfaces, easily leading to significant parasitic inductance and resistance. This can cause voltage overshoot, switching losses, and electromagnetic interference during high-speed switching. The heat generated by the power device must be transferred outwards through multiple package interfaces, increasing thermal resistance and causing interface fatigue under temperature cycling and vibration conditions. Furthermore, the dispersed power modules, control circuits, and connecting components occupy considerable installation space, resulting in numerous assembly steps and connection points, making it difficult to balance power circuit performance, heat dissipation capacity, and long-term operational reliability within a limited space. Summary of the Invention

[0004] To solve the above-mentioned technical problems, the present invention adopts the following technical solution: This invention provides a SiC MOSFET solid-state relay package structure, characterized in that it comprises: The PCB substrate has a circuit side and a heat dissipation side, and is provided with an embedding cavity, a main circuit connection assembly and a gate control line. The main circuit connection assembly includes a drain power terminal and a source power terminal that are insulated from each other. The drain power terminal and the source power terminal are electrically connected to the copper busbars on both sides of the BDU main circuit, respectively. A carrier plate is disposed on the heat dissipation side of the PCB substrate and covers the mounting cavity. The carrier plate includes a chip-side conductive layer, an insulating and thermally conductive layer and a heat dissipation-side conductive layer stacked sequentially. A SiC MOSFET chip is embedded in the aforementioned mounting cavity. The drain of the SiC MOSFET chip is electrically and thermally connected to the chip-side conductive layer, while the source and gate face the circuit side of the aforementioned PCB substrate. The drain interconnect extends from the chip-side conductive layer to the circuit side of the PCB substrate and connects the chip-side conductive layer to the drain power terminal. Source interconnects connect the aforementioned source to the source power terminal; Gate interconnects connect the aforementioned gate to the gate control circuitry; The driving circuit is disposed on the circuit side of the PCB substrate and is electrically connected to the gate through the gate control line.

[0005] Further improvements include an over-temperature detection unit, an over-current detection unit, a current sampling unit, and a pre-charge control circuit. The over-temperature detection unit and the over-current detection unit are respectively connected to the drive circuit, the current sampling unit is connected to the BMS interface, and the pre-charge control circuit is connected to the drive circuit. The over-current detection unit, the current sampling unit, and the pre-charge control circuit are disposed on the PCB substrate.

[0006] As a further improvement, the above-mentioned over-temperature detection unit includes an NTC thermistor, which is disposed on the chip-side conductive layer and adjacent to the SiC MOSFET chip; the above-mentioned over-current detection unit includes a shunt resistor connected in series with the main power path.

[0007] As a further improvement, the aforementioned precharge control circuit outputs a PWM signal to the drive circuit based on the difference between the battery-side voltage and the load-side voltage, and when the difference is less than a set threshold, the drive circuit controls the SiC MOSFET chip to be fully turned on.

[0008] As a further improvement, the aforementioned carrier plate is an AMB substrate, the aforementioned chip-side conductive layer and heat dissipation-side conductive layer are both copper layers, the aforementioned insulating and thermally conductive layer is a silicon nitride ceramic layer or an aluminum nitride ceramic layer, and the aforementioned drain electrode is connected to the aforementioned chip-side conductive layer through a silver sintering layer.

[0009] As a further improvement, the heat sink is disposed on the side of the carrier plate opposite to the SiC MOSFET chip, and the conductive layer on the heat sink side is thermally connected to the heat sink through a thermally conductive interface layer. The heat sink is a BDU housing or a heat sink.

[0010] As a further improvement, a buffer gap is provided between the sidewall of the aforementioned mounting cavity and the side of the SiC MOSFET chip, and the buffer gap is filled with a low-stress thermally conductive material; an insulating coating covers the front and side surfaces of the aforementioned SiC MOSFET chip, the exposed surfaces of the drain interconnect, source interconnect and gate interconnect, and the side edges of the carrier plate.

[0011] Another aspect of the present invention provides a method for manufacturing a SiC MOSFET solid-state relay package structure, comprising the following steps: S1: Prepare a PCB substrate and form an embedding cavity, a main circuit connection assembly and a gate control line on the PCB substrate. The main circuit connection assembly includes a drain power terminal and a source power terminal that are insulated from each other. S2: Prepare a carrier plate including a chip-side conductive layer, an insulating and thermally conductive layer and a heat dissipation-side conductive layer, and sinter the drain of the SiC MOSFET chip onto the chip-side conductive layer; S3: Fix the carrier plate to the heat dissipation side of the PCB substrate and cover the mounting cavity, so that the SiC MOSFET chip is embedded in the mounting cavity with the source and gate facing the circuit side of the PCB substrate. S4: The chip-side conductive layer and the drain power terminal are connected by a drain interconnect extending from the chip-side conductive layer to the circuit side of the PCB substrate, the source and the source power terminal are connected by a source interconnect, and the gate and the gate control line are connected by a gate interconnect. S5: The driving circuit is installed on the circuit side of the PCB substrate and electrically connected to the gate through the gate control line.

[0012] As a further improvement, in step S2, nano-silver paste is placed between the conductive layer and the drain electrode on the chip side, and sintered at a temperature of 200°C to 250°C and a pressure of 5MPa to 20MPa for 10 to 30 minutes to form a silver sintered layer, and the silver sintered layer is subjected to ultrasonic scanning detection.

[0013] As a further improvement, in step S2, after forming the silver sintered layer, one end of the copper strip is bonded to the conductive layer on the chip side, and the other end of the copper strip is reserved; in step S4, the other end of the copper strip is soldered or pressed to the drain power terminal to form the drain interconnect.

[0014] Compared with the prior art, the beneficial effects of the present invention are: Firstly, this invention features an embedding cavity on the PCB substrate, into which the SiC MOSFET chip is embedded along with the carrier plate. The drain on the back of the chip is connected to the drain power terminal via a conductive layer on the chip side and a drain interconnect, while the source on the front is connected to the source power terminal via a source interconnect. The gate is connected to the drive circuit via a gate interconnect and a gate control line. Thus, the SiC MOSFET chip, main circuit connection components, and drive circuit can be integrated onto the same PCB substrate, shortening the power connection path between the chip and the BDU main circuit, reducing external copper busbars, connectors, and transition interfaces. This helps reduce parasitic inductance and resistance in the power circuit, suppresses voltage overshoot and electromagnetic interference during high-speed switching, and reduces the space occupied by the solid-state relay inside the BDU, simplifying the assembly process.

[0015] Secondly, this invention forms a heat conduction path on the back of the chip to transfer heat to the heat sink via a carrier plate. Using an AMB substrate, a silver sintered layer, and a thermally conductive interface layer helps reduce the thermal resistance between the chip and the BDU housing or heat sink. The low-stress thermally conductive material within the mounting cavity buffers the stress caused by the difference in thermal expansion between the chip and the PCB substrate, while the insulating coating improves the electrical insulation and environmental protection capabilities of the exposed surfaces of the chip and interconnects. Over-temperature detection, over-current detection, current sampling, and pre-charge control functions, in conjunction with the drive circuit, can control the SiC MOSFET chip to turn off in case of abnormal temperature or overcurrent in the main circuit, and control its pulse conduction before the main circuit is turned on, thereby improving the protection capability of the solid-state relay and the operational reliability of the BDU main circuit.

[0016] Third, the manufacturing method of this invention first sintersects the SiC MOSFET chip onto a carrier plate, and then embeds the chip along with the carrier plate into a PCB substrate, completing the interconnection of the drain, source, and gate. This facilitates separate control of the chip sintering quality and embedding position. When using copper strip, one end of the copper strip is first bonded to the conductive layer on the chip side, and then the other end of the copper strip is connected after embedding. This helps reduce the assembly difficulty of the drain interconnection and improves the connection stability. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained from these drawings without creative effort.

[0018] Figure 1 This is a cross-sectional view of the packaging structure of the present invention; Figure 2 This is a flowchart of the manufacturing method of the present invention.

[0019] Figure label: 1-PCB substrate; 11-Embedding cavity; 12-Main circuit connection assembly; 13-Gate control circuit; 14-Drive circuit; 15-Overcurrent detection unit; 16-Overtemperature detection unit; 17-Current sampling unit; 18-Precharge control circuit; 2-Carrier board; 21-Chip-side conductive layer; 22-Insulating and thermally conductive layer; 23-Heat dissipation-side conductive layer; 24-NTC thermistor; 3-SiC MOSFET chip; 4-Drain interconnect; 5-Source interconnect; 6-Gate interconnect; 7-Silver sintered layer; 8-Heat dissipation component; 81-Thermal conductive interface layer; 9-Low-stress thermally conductive materials. Detailed Implementation

[0020] The present invention will be further described below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments are used to illustrate the technical content of the present invention, and the materials, dimensions, quantity, and process parameters of the components can be adjusted according to the rated voltage, rated current, installation space, and heat dissipation conditions. Figure 1 This is a cross-sectional schematic diagram of the package structure. The number of SiC MOSFET chip 3 and circuit elements in the diagram is only used to indicate the corresponding positions and does not constitute a quantity limit.

[0021] This embodiment provides a SiC MOSFET solid-state relay package structure, including a PCB substrate 1, a carrier plate 2, a SiC MOSFET chip 3, a drain interconnect 4, a source interconnect 5, a gate interconnect 6, and a driving circuit 14. The PCB substrate 1 has a circuit side and a heat dissipation side arranged opposite to each other. The lower side of the PCB substrate 1 is provided with an embedding cavity 11, a main circuit connection assembly 12, and a gate control line 13. The main circuit connection assembly 12 includes a drain power terminal and a source power terminal that are insulated from each other, and the drain power terminal and the source power terminal are electrically connected to the copper busbars on both sides of the BDU main circuit, respectively. The carrier plate 2 is disposed on the heat dissipation side of the PCB substrate 1 and covers the embedding cavity 11, and the SiC MOSFET chip 3 is embedded in the embedding cavity 11.

[0022] Specifically, the PCB substrate 1 can be made of FR-4 multilayer board, and the board thickness can be set from 1.6mm to 3.2mm depending on the number of wiring layers and mechanical strength requirements. The circuit side is the side where the drive circuit 14 and other control components are installed, and the heat dissipation side is the side close to the BDU housing or heat sink. The mounting cavity 11 is formed by partial layer openings in the PCB substrate 1. The planar dimensions of the mounting cavity 11 are larger than the external dimensions of the SiC MOSFET chip 3, allowing the chip to enter the mounting cavity 11, and leaving assembly tolerances and thermal expansion displacement space between the chip side and the cavity wall. The specific location of the mounting cavity 11 is determined according to the arrangement of the BDU main circuit copper busbar, drive circuit 14, and heat dissipation area, so that the power connection path and control connection path remain compact.

[0023] In the above embodiment, the main circuit connection assembly 12 can be formed from a thick copper layer on the circuit side of the PCB substrate 1. The drain power terminal and the source power terminal are electrically insulated from each other and extend to the location where they are connected to the BDU main circuit copper busbar. The drain power terminal and the source power terminal can be made of thick copper pads, integrated copper busbar electrodes, or metal terminals connected to the PCB copper layer. When using integrated copper busbar electrodes, the copper busbar electrodes can be connected to the BDU main circuit copper busbar by soldering, crimping, or other low-resistance connection methods. The copper thickness of the main circuit connection assembly 12 is not less than 2 oz, preferably 3 oz to 6 oz, to improve the high current carrying capacity and reduce conductivity loss.

[0024] In one optional embodiment, the drain power terminal and the source power terminal form adjacent conductive regions on the outer layer of the PCB substrate 1, with the main current inflow path and outflow path as close as possible. The two conductive regions can also be arranged in an alternating pattern, with a spacing of 0.5 mm to 2 mm. When the current directions in adjacent conductive regions are opposite, the magnetic fields generated by the two current paths can partially cancel each other out, thereby reducing the equivalent area and parasitic inductance of the power circuit. A reference conductive plane can be provided on the inner layer of the PCB substrate 1, and sufficient insulation distance can be maintained between it and the high-voltage conductive region according to the withstand voltage requirements. This arrangement is one specific implementation of the main circuit connection assembly 12, which can also adopt other shapes that meet current carrying and insulation requirements depending on the direction of the copper busbar inside the BDU.

[0025] like Figure 1 As shown, the carrier plate 2 includes a chip-side conductive layer 21, an insulating and thermally conductive layer 22, and a heat dissipation-side conductive layer 23 stacked sequentially. The chip-side conductive layer 21 faces the mounting cavity 11 and is used to support the SiC MOSFET chip 3 and conduct drain current and chip heat. The insulating and thermally conductive layer 22 is located between the two conductive layers and is used to isolate the high voltage potential on the chip side from the heat dissipation-side components, while transferring the heat generated by the chip to the heat dissipation side. The heat dissipation-side conductive layer 23 is used to diffuse the heat transferred through the insulating and thermally conductive layer 22 and is in contact with the thermally conductive interface layer 81.

[0026] In one specific embodiment, the carrier board 2 uses an AMB substrate. Both the chip-side conductive layer 21 and the heat dissipation-side conductive layer 23 are copper layers with a thickness of 0.4 mm. The insulating and thermally conductive layer 22 is a 0.5 mm thick silicon nitride ceramic layer or aluminum nitride ceramic layer. The thermal conductivity of the silicon nitride AMB substrate can reach 60 W / (m·K) or higher, and the thermal conductivity of the aluminum nitride AMB substrate can reach 170 W / (m·K) or higher. The breakdown field strength of the ceramic layer can reach 20 kV / mm or higher. The above materials and dimensions can balance thermal conductivity, mechanical strength, and high-voltage insulation. The carrier board 2 can also use other power substrates with conductive layers and insulating and thermally conductive layers 22, depending on the power rating.

[0027] The carrier plate 2 is closely attached to the heat dissipation side surface of the PCB substrate 1, or partially embedded in the interlayer region of the PCB substrate 1 near the heat dissipation side. After the carrier plate 2 covers the mounting cavity 11, the chip-side conductive layer 21 closes one end of the mounting cavity 11 from the heat dissipation side, the SiC MOSFET chip 3 is located inside the mounting cavity 11, and the heat dissipation-side conductive layer 23 faces the BDU housing or heat sink. The edge area of ​​the carrier plate 2 can be fixed to the PCB substrate 1 by reflow soldering, conductive adhesive bonding, or mechanical pressing. The fixing area and the chip mounting area are spaced apart to reduce the transmission of assembly stress to the chip and the silver sintered layer 7.

[0028] In the above embodiment, the drain of the SiC MOSFET chip 3 is located on the back side of the chip, while the source and gate are located on the front side. The back side of the chip faces the chip-side conductive layer 21, and the drain forms an electrical and thermal connection with the chip-side conductive layer 21; the front side of the chip faces the circuit side of the PCB substrate 1, allowing the source and gate to be led out to the circuit side within the mounting cavity 11. The number of chips can be determined according to the rated current, on-resistance, and redundancy requirements of the BDU main circuit, using one chip or multiple chips operating in parallel. When multiple chips are used, each chip is arranged with its back drain facing the carrier plate 2 and its front source and gate facing the circuit side.

[0029] In one specific embodiment, the SiC MOSFET chip 3 is a bare chip with a withstand voltage rating of 1200V and a chip size of 5mm by 5mm. A single chip can be selected based on a continuous current capability of 120A or higher. The chip can adopt a planar gate or trench gate configuration; the actual specifications are determined based on the BDU's operating voltage, current, and switching frequency. The drain metallization layer on the back of the chip is cleaned before mounting to remove oxides and surface contaminants, improving the bonding quality between the drain and the chip-side conductive layer 21.

[0030] In the above embodiment, the drain is connected to the chip-side conductive layer 21 via a silver sintered layer 7. The silver sintered layer 7 is located between the drain metallization layer and the chip-side conductive layer 21 on the back of the chip, and its connection area matches the back area of ​​the chip. The silver sintered layer 7 simultaneously serves the functions of current conduction, heat transfer, and chip fixation, which can reduce the contact resistance and thermal resistance at the drain connection location. The nano-silver sintered material has a high melting point and thermal conductivity, and can maintain a relatively stable connection state under temperature cycling and power cycling conditions.

[0031] Drain interconnect 4 extends from the chip-side conductive layer 21 to the circuit side of the PCB substrate 1, connecting the chip-side conductive layer 21 and the drain power terminal. Drain current enters the silver sintered layer 7 and the chip-side conductive layer 21 from the back drain of the chip, and then reaches the drain power terminal via drain interconnect 4. The connection point between drain interconnect 4 and the chip-side conductive layer 21 is located outside the projection range of the SiC MOSFET chip 3, allowing drain interconnect 4 to extend from the chip side through the mounting cavity 11 to the circuit side. This connection brings the back drain to the circuit side of the PCB substrate 1, facilitating the connection between the drain power terminal and the BDU main circuit copper busbar, and shortening the distance between the chip and the main circuit connection assembly 12.

[0032] The drain interconnect 4 can be made of copper strip, copper wire, metal bump, or copper pillar. When using copper strip, one end of the copper strip is connected to the chip-side conductive layer 21 by ultrasonic bonding or thermo-ultrasonic bonding, and the other end is connected to the drain power terminal by soldering or crimping. The copper strip can be made of oxygen-free copper, with a width of 2 mm and a thickness of 0.2 mm. When using copper wire, the diameter of the copper wire can be 15 mil. The cross-sectional area and conductivity of the copper wire help reduce the resistance of the drain lead-out path. When using metal bump or copper pillar, the metal bump or copper pillar is located between the chip-side conductive layer 21 and the drain power terminal, and the connection can be formed by thermo-press bonding or reflow soldering during the assembly of the carrier board 2 and the PCB substrate 1.

[0033] like Figure 1 As shown, source interconnect 5 connects the source and source power terminals on the front side of the chip, and gate interconnect 6 connects the gate and gate control line 13 on the front side of the chip. Source interconnect 5 carries the main current and can be made of copper strip, copper wire, metal bump, or copper pillar depending on the current magnitude. The connection cross-sectional area can be increased, or multiple parallel connection positions can be set. Gate interconnect 6 transmits the gate drive signal and can be made of copper wire, copper strip, metal bump, or copper pillar. Source interconnect 5 and gate interconnect 6 are respectively placed on independent pads on the circuit side of the PCB substrate 1 or the periphery of the mounting cavity 11. The two pads are electrically isolated and then connected to the main circuit connection assembly 12 and the gate control line 13, respectively.

[0034] The gate control line 13 can be disposed on the outer or inner layer of the PCB substrate 1 and connects the drive circuit 14 to the gate interconnect 6. An insulating distance is maintained between the gate control line 13 and the high-voltage power conductive area, and the line length is shortened according to the relative position of the drive circuit 14 and the chip. The drive circuit 14 can also be provided with an independent source reference connection to reduce the impact of the voltage drop generated by the main current on the source power path on the gate drive voltage. The source reference connection can be established by connecting the chip source to the reference terminal of the drive circuit 14 via the PCB copper layer.

[0035] The drive circuit 14 is located on the circuit side of the PCB substrate 1 and is electrically connected to the gate of the SiC MOSFET chip 3 via the gate control line 13. The drive circuit 14 can use a magnetically isolated or capacitively isolated gate drive chip, with an isolation withstand voltage of over 2500Vrms. The control side of the drive circuit 14 receives PWM switching commands from the BMS or vehicle controller, and the power side outputs positive and negative bias drive voltages to the gate. The turn-on voltage can be set to +18V to +20V, and the turn-off voltage can be set to -4V to -5V to meet the turn-on and turn-off requirements of the SiC MOSFET chip 3.

[0036] This embodiment also includes an over-temperature detection unit 16, an over-current detection unit 15, a current sampling unit 17, and a pre-charge control circuit 18. The over-temperature detection unit 16 and the over-current detection unit 15 are respectively connected to the drive circuit 14, and output a fault signal to the drive circuit 14 when an abnormal state is detected. The current sampling unit 17 is connected to the BMS interface and transmits the main circuit current detection result to the BMS. The pre-charge control circuit 18 is connected to the drive circuit 14 and adjusts the conduction state of the SiC MOSFET chip 3 according to the voltage state on the battery side and the load side. The over-current detection unit 15, the current sampling unit 17, and the pre-charge control circuit 18 are mounted on the PCB substrate 1 and are arranged together with the drive circuit 14 and the main circuit connection assembly 12.

[0037] The over-temperature detection unit 16 includes an NTC thermistor 24. The NTC thermistor 24 is disposed on the chip-side conductive layer 21 and adjacent to the SiC MOSFET chip 3, making the detection location close to the main heat-generating area of ​​the chip. The NTC thermistor 24 is connected to the drive circuit 14 via PCB traces. When the temperature reaches the warning threshold, a temperature warning message can be output to the BMS; when the temperature reaches the protection threshold, the drive circuit 14 reduces the gate voltage or turns off the SiC MOSFET chip 3. In one specific embodiment, the warning threshold is set to 80°C and the protection threshold is set to 90°C; the specific values ​​can be adjusted according to the chip junction temperature limit, thermal resistance, and safety margin.

[0038] The overcurrent detection unit 15 includes a shunt resistor connected in series in the main power path. The shunt resistor can be set in the negative path of the BDU main circuit. The voltage across the shunt resistor changes with the main circuit current. The overcurrent detection unit 15 collects this voltage and compares it with a set threshold. When the main circuit current exceeds the peak threshold or the sustained overcurrent threshold, the overcurrent detection unit 15 outputs a fault signal to the drive circuit 14, and the drive circuit 14 turns off the SiC MOSFET chip 3. In one specific embodiment, the peak overcurrent threshold can be set to 800A, the sustained overcurrent threshold can be set to 400Arms, and the turn-off time is set to the microsecond level according to the chip's short-circuit withstand capability.

[0039] The current sampling unit 17 can employ a Hall effect current sensor, or a precision shunt resistor and instrumentation amplifier. The current sampling unit 17 converts the main circuit current into an analog or digital signal that the BMS can acquire. In one specific embodiment, a main circuit current of 0A to 300A corresponds to an analog output of 0V to 3.3V. The current sampling lines are arranged separately from the gate drive lines and high-voltage power lines to reduce the impact of switching transients on the sampling results.

[0040] The pre-charge control circuit 18 acquires the battery-side voltage and the load-side voltage, and outputs a PWM signal to the drive circuit 14 based on the difference between the two. In the initial stage of BDU main circuit connection, the pre-charge control circuit 18 controls the SiC MOSFET chip 3 to gradually turn on in a pulsed manner, performing current-limited charging on the load-side DC bus capacitor. The duty cycle of the PWM signal can gradually increase as the load-side voltage rises, keeping the pre-charge current within a set range. In one specific embodiment, the pre-charge current is limited to 10A to 30A. When the difference between the load-side voltage and the battery-side voltage is less than a set threshold, the pre-charge control circuit 18 controls the SiC MOSFET chip 3 to fully turn on through the drive circuit 14. The set threshold can be 5% of the battery-side voltage. This control method can reduce the use of independent pre-charge contactors, pre-charge resistors, and matching copper busbars.

[0041] The heat sink 8 is disposed on the side of the carrier plate 2 opposite to the SiC MOSFET chip 3. The heat sink-side conductive layer 23 is thermally connected to the heat sink 8 through a thermally conductive interface layer 81. The heat sink 8 is a BDU housing, or a heat sink disposed inside or outside the BDU. The thermally conductive interface layer 81 can be made of thermally conductive silicone grease, phase change material, or thermally conductive pad. The thermally conductive interface layer 81 fills the tiny gap between the heat sink-side conductive layer 23 and the heat sink 8 to reduce contact thermal resistance. In one specific embodiment, the thermal resistance of the thermally conductive interface layer 81 is less than 0.1℃ / W.

[0042] The main heat generated by the SiC MOSFET chip 3 is sequentially transferred to the heat sink 8 via the back drain, silver sintered layer 7, chip-side conductive layer 21, insulating and thermally conductive layer 22, heat dissipation-side conductive layer 23, and thermally conductive interface layer 81. The carrier plate 2 is directly disposed on the back of the chip, allowing heat to be transferred to the heat dissipation side along the chip thickness direction. Heat from the front of the chip can also diffuse to the circuit side via the source interconnect 5, gate interconnect 6, and the copper layer of the PCB substrate 1. The drain interconnect 4 can also transfer some of the heat from the chip-side conductive layer 21 to the PCB substrate 1.

[0043] A buffer gap is provided between the sidewall of the mounting cavity 11 and the side of the SiC MOSFET chip 3, and the buffer gap is filled with a low-stress thermally conductive material 9. In one specific embodiment, the width of the buffer gap is 0.1 mm to 0.3 mm, and the low-stress thermally conductive material 9 is a thermally conductive gel with a thermal conductivity of not less than 3 W / (m·K). After the thermally conductive gel is filled, it can transfer heat from the side of the chip to the PCB substrate 1, while allowing the chip and the PCB substrate 1 to produce a small relative displacement when the temperature changes. The coefficient of thermal expansion of SiC material is about 4 ppm / K, and the coefficient of thermal expansion of FR-4 material is about 14 ppm / K to 17 ppm / K. The low-stress thermally conductive material 9 can reduce the concentrated stress formed at the edge of the chip due to the difference in thermal expansion.

[0044] An insulating coating covers the front and sides of the SiC MOSFET chip 3, the exposed surfaces of the drain interconnect 4, source interconnect 5, and gate interconnect 6, as well as the side edges of the carrier plate 2. The insulating coating can be made of polyimide varnish, epoxy ceramic composite insulating varnish, or silicone-based insulating material, with a coating thickness ranging from 0.05 mm to 0.2 mm. The cured breakdown field strength can reach over 2.5 kV / mm. The insulating coating forms a continuous insulating film on exposed high-voltage parts, reducing surface leakage caused by moisture, salt spray, and contaminants, while also providing environmental protection for the interconnects. Power terminals, control interfaces, and areas requiring soldering or crimping are left exposed during coating to maintain subsequent electrical connections.

[0045] For an 800V DC platform, the creepage distance and clearance of the high-voltage power area and low-voltage control area of ​​the PCB substrate 1 are set according to the operating voltage, pollution level, and material group. The high-voltage power terminal can be arranged on the outer layer of the PCB substrate 1, and a slot or insulating baffle is provided between the high-voltage area and the control area. In one specific embodiment, the minimum creepage distance is not less than 8mm, the minimum clearance is not less than 5.5mm, and the slot width is not less than 2mm. The ceramic insulating layer in the carrier plate 2 forms solid insulation between the chip-side conductive layer 21 and the heat dissipation-side conductive layer 23, and the insulating coating further improves the surface insulation capability of the chip front and the area around the interconnects.

[0046] This embodiment also provides a method for manufacturing a SiC MOSFET solid-state relay package structure, such as... Figure 2 As shown, the manufacturing method includes steps S1 to S5, and can continue with insulation coating, gap filling, inspection and BDU assembly.

[0047] In step S1, a PCB substrate 1 is prepared, and an embedding cavity 11, a main circuit connection assembly 12 and a gate control line 13 are formed on the PCB substrate 1. The main circuit connection assembly 12 includes a drain power terminal and a source power terminal that are insulated from each other.

[0048] Specifically, a multilayer FR-4 substrate with a thickness of 1.6mm to 3.2mm is selected, and the mounting cavity 11 is formed by mechanical milling or laser cutting according to the chip position. The size of the mounting cavity 11 is 0.1mm to 0.3mm larger on each side than the SiC MOSFET chip 3. The circuit side of the PCB substrate 1 is reserved with a thick copper area for the main circuit, mounting pads for the drive circuit 14, BMS interface pads, source connection pads, gate connection pads, and positioning holes. The copper thickness of the thick copper area for the main circuit is not less than 2oz, preferably 3oz to 6oz. After processing, the PCB substrate 1 is deburred, chemically cleaned, and dried to remove processing residues from the cavity walls and pad surfaces.

[0049] In step S2, a carrier plate 2 comprising a chip-side conductive layer 21, an insulating and thermally conductive layer 22, and a heat dissipation-side conductive layer 23 is prepared, and the drain of the SiC MOSFET chip 3 is sintered onto the chip-side conductive layer 21.

[0050] In one specific embodiment, the carrier plate 2 uses a silicon nitride AMB substrate or an aluminum nitride AMB substrate. The thickness of the copper layer on the chip side and the copper layer on the heat dissipation side are both 0.4 mm, and the ceramic layer thickness is 0.5 mm. Before sintering, the copper layer on the chip side is polished, ultrasonically cleaned, and micro-etched to ensure that the surface roughness Ra is no greater than 1 μm. The SiC MOSFET chip 3 is a 1200V bare chip with a size of 5 mm × 5 mm. The drain metallization layer on the back of the chip is cleaned with plasma to remove oxides and organic contaminants.

[0051] A nano-silver paste with a particle size of 1μm to 3μm and a silver content of not less than 90% is deposited between the conductive layer 21 on the chip side and the drain electrode. The nano-silver paste can be formed by screen printing, with a printing thickness of 50μm to 100μm. The SiC MOSFET chip 3 is placed on the nano-silver paste, with the drain electrode on the back of the chip facing the conductive layer 21 on the chip side, and then pressure sintering is performed. The sintering temperature is 200℃ to 250℃, the sintering pressure is 5MPa to 20MPa, and the holding time is 10min to 30min. In one specific process, the sintering temperature is 250℃, the sintering pressure is 10MPa, and the holding time is 15min.

[0052] After sintering, the silver sintered layer 7 is subjected to ultrasonic scanning to check for voids and delamination. The void ratio of the silver sintered layer 7 can be controlled within 10%. When the test results meet the requirements, a continuous electrical and thermal connection is formed between the drain on the back of the chip and the conductive layer 21 on the chip side. Substituting carrier boards 2 that fail the test can be reworked or rejected before entering the PCB assembly process, reducing the number of chips with sintering defects entering subsequent assembly processes.

[0053] After forming the silver sintered layer 7, one end of the copper strip is bonded to the chip-side conductive layer 21, leaving the other end of the copper strip unbonded. The bonding position between the copper strip and the chip-side conductive layer 21 is set outside the projection range of the SiC MOSFET chip 3, allowing the copper strip to bend from the chip side and extend to the circuit side of the PCB substrate 1. The copper strip can be an oxygen-free copper strip with a width of 2 mm and a thickness of 0.2 mm. The thermo-ultrasonic bonding temperature can be 150℃ to 200℃, the ultrasonic power can be 5W to 15W, and the bonding time can be 20ms to 50ms. The length of the unbonded end of the copper strip is determined according to the depth of the mounting cavity 11 and the position of the drain power terminal.

[0054] In step S3, the carrier plate 2 is fixed on the heat dissipation side of the PCB substrate 1 and covers the mounting cavity 11, so that the SiC MOSFET chip 3 is embedded in the mounting cavity 11 with the source and gate facing the circuit side of the PCB substrate 1.

[0055] During assembly, the SiC MOSFET chip 3 on the carrier plate 2 is aligned with the mounting cavity 11 on the PCB substrate 1, allowing the chip to enter the mounting cavity 11 without touching the cavity wall. The edge fixing area of ​​the carrier plate 2 contacts the heat dissipation side of the PCB substrate 1 and forms a fixed connection through reflow soldering or conductive adhesive bonding. When copper strip is used as the drain interconnect 4, the reserved end of the copper strip enters the mounting position with the carrier plate 2 and extends towards the circuit side of the PCB substrate 1. When metal bumps or copper pillars are used, thermoforming or reflow soldering of the metal bumps or copper pillars to the pads of the PCB substrate 1 can be completed in this step.

[0056] In step S4, the chip-side conductive layer 21 and the drain power terminal are connected by the drain interconnect 4 extending from the chip-side conductive layer 21 to the circuit side of the PCB substrate 1, the source and the source power terminal are connected by the source interconnect 5, and the gate and the gate control line 13 are connected by the gate interconnect 6.

[0057] When using copper strip, the other end of the copper strip is soldered or crimped to the drain power terminal. After the two ends of the copper strip are connected, a drain lead-out path is formed from the conductive layer 21 on the chip side to the drain power terminal. When using copper wire, the two ends of the copper wire can be connected by ultrasonic bonding or thermo-ultrasonic bonding. When using metal bumps or copper pillars, the metal bumps or copper pillars are bonded to the conductive layer 21 on the chip side and the drain power terminal respectively by thermo-press bonding or reflow soldering. After interconnection, check the appearance, contact resistance, and mechanical bonding status of the connection positions.

[0058] Source interconnect 5 connects the source pad on the front side of the chip to the source power terminal, and gate interconnect 6 connects the gate pad on the front side of the chip to the gate control line 13. The cross-sectional area of ​​source interconnect 5 is determined according to the main circuit current, and the length of gate interconnect 6 is determined according to the drive circuit layout. The source and gate can first be connected to the independent pads on the periphery of the mounting cavity 11, and then connected to the source power terminal and drive circuit 14 respectively through the thick copper layer and control copper layer of PCB substrate 1. After completing the source and gate interconnection, the insulation status between the source and gate, and between the gate and drain power terminals is checked.

[0059] In step S5, the driving circuit 14 is installed on the circuit side of the PCB substrate 1 and electrically connected to the gate through the gate control line 13.

[0060] The drive circuit 14, overcurrent detection unit 15, current sampling unit 17, and precharge control circuit 18 can be mounted on the preset pad area on the circuit side of the PCB substrate 1 using an SMT reflow soldering process. An NTC thermistor 24 is mounted on the chip-side conductive layer 21 adjacent to the SiC MOSFET chip 3. The reflow soldering peak temperature can be between 245°C and 255°C, and the duration of the peak temperature range can be between 60 and 90 seconds. After mounting, check the connection status between the drive circuit 14 and the gate control line 13, the detection unit and the drive circuit 14, and the current sampling unit 17 and the BMS interface.

[0061] After the drive and protection circuits are mounted, an insulating coating can be formed using selective spraying or dip coating processes. The insulating material can be polyimide insulating coating or epoxy ceramic composite insulating varnish, with a coating thickness of 0.1 mm. Avoid coating the drain power terminal, source power terminal, BMS interface, and other external connection areas. After coating, pre-bake at 80°C for 30 minutes, then cure at 150°C for 2 hours to form a continuous insulating film on the front and sides of the chip, the exposed surfaces of interconnects, and the two edges of the carrier board.

[0062] After the insulating coating has cured, low-stress thermally conductive gel is filled into the buffer gap between the sidewall of the mounting cavity 11 and the chip side using a syringe dispensing method. The thermal conductivity of the thermally conductive gel is not less than 3 W / (m·K), and the filling height is flush with or slightly lower than the front side of the chip. After filling, it can be cured at 80℃ for 1 hour. During the filling process, the dispensing pressure and amount of gel are controlled to reduce air bubbles and local voids, so that the thermally conductive gel continuously coats the chip side.

[0063] A thermally conductive interface material is provided on the heat dissipation-side conductive layer 23 of the support plate 2, and the heat dissipation-side conductive layer 23 is attached to the BDU shell or heat sink. The thermally conductive interface material can be thermally conductive silicone grease, phase change material, or thermally conductive pad. The assembly pressure is determined based on the compression amount of the thermally conductive interface material and the mechanical strength of the support plate 2, so that the thermally conductive interface material can fill the micro-gaps of the contact surface, while avoiding excessive mechanical stress on the support plate 2 and the silver sintered layer 7.

[0064] After packaging, the solid-state relay undergoes electrical, thermal, insulation, and reliability testing. Static parameter testing includes gate threshold voltage, on-resistance, leakage current, gate leakage current, and body diode voltage drop. Dynamic parameter testing includes turn-on time, turn-off time, switching energy, reverse recovery charge, reverse recovery energy, spike voltage, and power loop parasitic inductance. Thermal performance testing measures steady-state temperature rise at a rated current of 400 Arms. Insulation withstand voltage testing uses a 2500V AC voltage held for 1 minute, without breakdown or flashover occurring during the test.

[0065] Reliability testing can include thermal cycling tests within the range of -40°C to 125°C, high-temperature and high-humidity tests at 85°C and 85% relative humidity, and random vibration tests within the range of 10Hz to 2000Hz. The number of thermal cycles can be 1000, the high-temperature and high-humidity test duration can be 1000 hours, and the random vibration acceleration can be 5 grms, lasting 8 hours in each direction. The testing items and judgment criteria can be adjusted according to the application standards of the vehicle or energy storage system.

[0066] After passing inspection, the solid-state relay package structure is installed inside the BDU. The positioning holes on the PCB substrate 1 are aligned with the positioning pins inside the BDU housing, and the PCB substrate 1 is then secured with screws or clips. The drain power terminal and source power terminal are connected to the copper busbars on both sides of the BDU main circuit via soldering or crimping, respectively. The BMS interface is connected to the external BMS via a ribbon cable or board-to-board connector. The heat dissipation-side conductive layer 23 is attached to the BDU housing or heat sink via the thermal interface layer 81, allowing electrical, control, and heat dissipation connections to be completed inside the BDU.

[0067] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the invention by those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the invention should be included within the scope of protection of the invention.

Claims

1. A SiC MOSFET solid-state relay package structure, characterized in that, include: The PCB substrate has a circuit side and a heat dissipation side, and is provided with an embedding cavity, a main circuit connection assembly and a gate control line. The main circuit connection assembly includes a drain power terminal and a source power terminal that are insulated from each other. The drain power terminal and the source power terminal are electrically connected to the copper busbars on both sides of the BDU main circuit, respectively. A carrier plate is disposed on the heat dissipation side of the PCB substrate and covers the mounting cavity. The carrier plate includes a chip-side conductive layer, an insulating and thermally conductive layer and a heat dissipation-side conductive layer stacked sequentially. A SiC MOSFET chip is embedded in the mounting cavity. The drain of the SiC MOSFET chip is electrically and thermally connected to the chip-side conductive layer, and the source and gate face the circuit side of the PCB substrate. The drain interconnect extends from the chip-side conductive layer to the circuit side of the PCB substrate and connects the chip-side conductive layer to the drain power terminal. Source interconnects connect the source to the source power terminal; Gate interconnects connect the gate to the gate control circuitry; The driving circuit is disposed on the circuit side of the PCB substrate and is electrically connected to the gate through the gate control line.

2. The SiC MOSFET solid-state relay package structure as described in claim 1, characterized in that, It also includes an over-temperature detection unit, an over-current detection unit, a current sampling unit, and a pre-charge control circuit. The over-temperature detection unit and the over-current detection unit are respectively connected to the drive circuit, the current sampling unit is connected to the BMS interface, and the pre-charge control circuit is connected to the drive circuit. The over-current detection unit, the current sampling unit, and the pre-charge control circuit are disposed on the PCB substrate.

3. The SiC MOSFET solid-state relay package structure as described in claim 2, characterized in that, The over-temperature detection unit includes an NTC thermistor, which is disposed on the chip-side conductive layer and adjacent to the SiC MOSFET chip; the over-current detection unit includes a shunt resistor connected in series with the main power path.

4. The SiC MOSFET solid-state relay package structure as described in claim 2, characterized in that, The precharge control circuit outputs a PWM signal to the drive circuit based on the difference between the battery side voltage and the load side voltage, and when the difference is less than a set threshold, the drive circuit controls the SiC MOSFET chip to be fully turned on.

5. The SiC MOSFET solid-state relay package structure as described in claim 1, characterized in that, The carrier plate is an AMB substrate, the chip-side conductive layer and the heat dissipation-side conductive layer are both copper layers, the insulating and thermally conductive layer is a silicon nitride ceramic layer or an aluminum nitride ceramic layer, and the drain electrode is connected to the chip-side conductive layer through a silver sintered layer.

6. The SiC MOSFET solid-state relay package structure as described in claim 5, characterized in that, The heat sink is located on the side of the carrier plate away from the SiC MOSFET chip. The conductive layer on the heat sink side is thermally connected to the heat sink through a thermally conductive interface layer. The heat sink is a BDU housing or a heat sink.

7. The SiC MOSFET solid-state relay package structure as described in claim 5, characterized in that, A buffer gap is provided between the sidewall of the mounting cavity and the side of the SiC MOSFET chip, and the buffer gap is filled with a low-stress thermally conductive material. An insulating coating covers the front and sides of the SiC MOSFET chip, the exposed surfaces of the drain interconnect, source interconnect and gate interconnect, as well as the side edges of the carrier plate.

8. A method for manufacturing a SiC MOSFET solid-state relay package structure, characterized in that, Includes the following steps: S1: Prepare a PCB substrate, and form an embedding cavity, a main circuit connection assembly and a gate control line on the PCB substrate. The main circuit connection assembly includes a drain power terminal and a source power terminal that are insulated from each other. S2: Prepare a carrier plate including a chip-side conductive layer, an insulating and thermally conductive layer and a heat dissipation-side conductive layer, and sinter the drain of the SiC MOSFET chip onto the chip-side conductive layer; S3: Fix the carrier plate to the heat dissipation side of the PCB substrate and cover the mounting cavity, so that the SiC MOSFET chip is embedded in the mounting cavity with the source and gate facing the circuit side of the PCB substrate; S4: The chip-side conductive layer and the drain power terminal are connected by a drain interconnect extending from the chip-side conductive layer to the circuit side of the PCB substrate; the source and the source power terminal are connected by a source interconnect; and the gate and the gate control line are connected by a gate interconnect. S5: Install the driving circuit on the circuit side of the PCB substrate and connect it to the gate through the gate control line.

9. The method for manufacturing the SiC MOSFET solid-state relay package structure as described in claim 8, characterized in that, In step S2, nano-silver paste is placed between the conductive layer and the drain electrode on the chip side, and sintered at a temperature of 200°C to 250°C and a pressure of 5MPa to 20MPa for 10 to 30 minutes to form a silver sintered layer, and the silver sintered layer is subjected to ultrasonic scanning detection.

10. The method for manufacturing the SiC MOSFET solid-state relay package structure as described in claim 9, characterized in that, In step S2, after the silver sintered layer is formed, one end of the copper strip is bonded to the conductive layer on the chip side, and the other end of the copper strip is reserved. In step S4, the other end of the copper strip is welded or crimped to the drain power terminal to form the drain interconnect.

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