Array substrate, display panel and display device

Abstract

An array substrate, a display panel and a display device. The array substrate comprises a substrate, a plurality of pixel units, a plurality of signal line groups, a plurality of data sub-lines and a plurality of data buses. Each pixel unit comprises a plurality of sub-pixels, the plurality of sub-pixels of the plurality of pixel units are arranged in an array, and are arranged as rows along a first direction and as columns along a second direction. Each signal line group comprises M scanning signal lines which are distributed at intervals along the second direction. M is a natural number greater than 2. The plurality of data sub-lines are arranged at intervals along the first direction, one data sub-line is electrically connected to one column of sub-pixels. One data bus is electrically connected to three data sub-lines. Between two adjacent rows of sub-pixels, one signal line group is included, one sub-pixel is electrically connected to one scanning signal line, one row of sub-pixels is electrically connected to N scanning signal lines, and three sub-pixels in one row of sub-pixels which are electrically connected to the same data bus are respectively electrically connected to different scanning signal lines. N is a natural number greater than 2.

Description

Array substrate, display panel and display device Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Technology

[0002] With the continuous development of display technology, display devices have been widely used. Common display devices include liquid crystal displays (LCDs) and organic light-emitting diode displays (OLEDs). Thanks to the simpler pixel circuit structure of liquid crystal displays (which can contain fewer thin-film transistors and capacitors) and lower manufacturing costs, liquid crystal displays have advantages in ultra-high pixel density (e.g., greater than or equal to 1000 PPI), high refresh rates, and ultra-narrow bezels, and have seen significant development.

[0003] In display panels with high pixel density and high refresh rate, the number of data lines is usually large. Conventional technologies typically use multiple source driver ICs for driving, but source driver ICs are expensive. How to reduce the manufacturing cost of display panels has become an urgent technical problem to be solved. Summary of the Invention

[0004] On one hand, an array substrate is provided. The array substrate has a display area and a fan-out area adjacent to the display area. The array substrate includes a substrate, multiple pixel units, multiple signal line groups, multiple data sub-lines, and multiple data buses. The multiple pixel units are disposed within the display area, each pixel unit including multiple sub-pixels. The multiple sub-pixels of the multiple pixel units are arranged in an array, forming rows along a first direction and columns along a second direction. The first direction intersects the second direction. Each of the multiple signal line groups includes M scan signal lines spaced apart along the second direction. Wherein, M is a natural number greater than 2. The multiple data sub-lines are spaced apart along the first direction, penetrate the display area along the second direction, and extend to the fan-out area. One data sub-line is electrically connected to one column of sub-pixels. The multiple data buses are disposed in the fan-out area, and one data bus is electrically connected to N data sub-lines. Wherein, N is a natural number greater than 2. Each row of sub-pixels includes a signal line group, each sub-pixel is electrically connected to one scan signal line, each row of sub-pixels is electrically connected to three scan signal lines, and three sub-pixels in a row that are electrically connected to the same data bus are respectively electrically connected to different scan signal lines.

[0005] In some embodiments, M is an odd number, and the values ​​of M and N may be equal or unequal.

[0006] In some embodiments, the values ​​of M and N are both multiples of 3.

[0007] In some embodiments, the array substrate further includes a plurality of touch traces, which are spaced apart along the first direction. The sub-pixel includes a pixel electrode, and the orthographic projection of the touch traces onto the substrate partially overlaps with the orthographic projection of the pixel electrode onto the substrate. The portion of the touch traces that overlap with the pixel electrode is located at the center of the pixel electrode along the first direction.

[0008] In some embodiments, the array substrate further includes a plurality of touch traces, which are spaced apart along the first direction. Each sub-pixel includes a pixel electrode, and the touch traces are disposed adjacent to the data sub-lines. The orthographic projection of the touch traces onto the substrate does not coincide with the orthographic projection of the pixel electrodes onto the substrate.

[0009] In some embodiments, three data sub-lines are included between two adjacent touch traces along the first direction, and each pair of adjacent touch traces forms a group, wherein the two touch traces in a group are configured to transmit the same drive signal.

[0010] In some embodiments, six data sub-lines are included between two adjacent touch traces along the first direction, and the two adjacent touch traces are electrically insulated from each other.

[0011] In some embodiments, the pixel unit includes three sub-pixels arranged adjacent to each other along the first direction, and the three sub-pixels of the pixel unit are respectively configured to emit red, green, and blue light. Sub-pixels in the same column are configured to emit light of the same color.

[0012] In some embodiments, the sub-pixel further includes a thin-film transistor and a pixel electrode. The gate of the thin-film transistor is electrically connected to the scan signal line, and one of its source and drain is electrically connected to the data sub-line, while the other is electrically connected to the pixel electrode. A row of sub-pixels is electrically connected to three scan signal lines of the same signal line group. The row of sub-pixels electrically connected to the signal line group is the target row sub-pixel. Along the direction away from the target row sub-pixel, the three scan signal lines of the signal line group are, in sequence, a first scan signal line, a second scan signal line, and a third scan signal line. The thin-film transistor of the sub-pixel electrically connected to the first scan signal line is located on the side of the first scan signal line closer to the target row sub-pixel. The thin-film transistor of the sub-pixel electrically connected to the second scan signal line is located between the first scan signal line and the second scan signal line. The thin-film transistor of the sub-pixel electrically connected to the third scan signal line is located between the second scan signal line and the third scan signal line.

[0013] In some embodiments, the first scan signal line includes a first groove formed by bending away from the target row sub-pixel, and a thin-film transistor electrically connected to the first scan signal line is located within the first groove. The second scan signal line includes a second groove formed by bending away from the target row sub-pixel, and both the thin-film transistor electrically connected to the second scan signal line and the first groove are located within the second groove. The third scan signal line extends along the first direction, and the thin-film transistor electrically connected to the third scan signal line is offset from the second groove and located between the second scan signal line and the third scan signal line.

[0014] In some embodiments, the first scan signal line includes a first extension segment and a second extension segment alternately connected along the first direction. The first extension segment includes a first sub-portion extending along the first direction and two second sub-portions respectively connected to both ends of the first sub-portion. The second sub-portions extend along the second direction, and one end of the second sub-portion away from the first sub-portion is connected to the second extension segment. The first extension segment forms the first groove. The second extension segment, relative to the first sub-portion, extends away from the target row sub-pixel along the second direction.

[0015] In some embodiments, the second scan signal line includes a third extension segment and a fourth extension segment alternately connected along the first direction. The third extension segment includes a third sub-section extending along the first direction and two fourth sub-sections respectively connected to both ends of the third sub-section. The fourth sub-sections extend along the second direction, and one end of the fourth sub-section away from the third sub-section is connected to the fourth extension segment; the third extension segment forms the second groove. The fourth extension segment is farther away from the target row sub-pixel along the second direction than the third sub-section.

[0016] In some embodiments, along the second direction, a portion of the third sub-section is disposed opposite to the first sub-section, and a portion is disposed opposite to the second extension. The spacing between the third sub-section and the first sub-section is smaller than the spacing between the third sub-section and the second extension. The thin-film transistor electrically connected to the second scan signal line is located between the third sub-section and the second extension.

[0017] In some embodiments, the spacing between the third scan signal line and the third sub-section is smaller than the spacing between the third scan signal line and the fourth extension. The thin-film transistor electrically connected to the third scan signal line is located between the third scan signal line and the fourth extension.

[0018] In some embodiments, the orthographic projection of the pixel electrode of the sub-pixel electrically connected to the second scan signal line onto the substrate at least partially coincides with the orthographic projection of the first scan signal line onto the substrate. Similarly, the orthographic projection of the pixel electrode of the sub-pixel electrically connected to the third scan signal line onto the substrate at least partially coincides with the orthographic projections of both the first and second scan signal lines onto the substrate.

[0019] In some embodiments, a row of sub-pixels is electrically connected to three scan signal lines belonging to two signal line groups, respectively.

[0020] In some embodiments, along the scanning direction of the plurality of scan signal lines, the three scan signal lines of the signal line group are sequentially a first scan signal line, a second scan signal line, and a third scan signal line. In the two signal line groups located on either side of a row of sub-pixels along the second direction, the one transmitting the scan signal first is the first signal line group, and the other is the second signal line group. The row of sub-pixels is electrically connected to the third scan signal line of the first signal line group and the first and second scan signal lines of the second signal line group.

[0021] In some embodiments, two adjacent pixel units along the first direction form a group, and a group of pixel units is electrically connected to the same scan signal line. Two adjacent groups of pixel units along the first direction are electrically connected to different scan signal lines, and two adjacent pixel units electrically connected to the same scan signal line include two groups of pixel units.

[0022] In some embodiments, three sub-pixels of a pixel unit are electrically connected to the same scan signal line. Within the same row of sub-pixels, adjacent pixel units are electrically connected to different scan signal lines, and adjacent pixel units electrically connected to the same scan signal line include two pixel units between them. A column of sub-pixels is electrically connected to a scan signal line at the same position in one of a plurality of signal line groups.

[0023] In some embodiments, two adjacent pixel units along the first direction form a group, and the sub-pixels of a group of pixel units are electrically connected to the same scan signal line. Within the same row of sub-pixels, two adjacent groups of pixel units are electrically connected to different scan signal lines. The connection order of the three groups of pixel units belonging to two adjacent rows and electrically connected to the six adjacent data buses is reversed.

[0024] In some embodiments, two adjacent sub-pixels along the first direction form a group, and a group of sub-pixels is electrically connected to the same scan signal line. Within the same row of sub-pixels, two adjacent groups of sub-pixels are electrically connected to different scan signal lines, and the spacing between two adjacent pixel units electrically connected to different scan signal lines is unequal. A column of sub-pixels is electrically connected to a scan signal line at the same position in one of the plurality of signal line groups.

[0025] In some embodiments, 18 data sub-lines electrically connected to and arranged adjacent to the six adjacent data buses are numbered sequentially along the first direction. Data sub-lines 1, 4, and 10 are electrically connected to one data bus. Data sub-lines 2, 5, and 8 are electrically connected to one data bus. Data sub-lines 3, 6, and 12 are electrically connected to one data bus. Data sub-lines 7, 13, and 16 are electrically connected to one data bus. Data sub-lines 9, 15, and 18 are electrically connected to one data bus. Data sub-lines 11, 14, and 17 are electrically connected to one data bus.

[0026] In some embodiments, the three data buses electrically connected to the data sub-lines 1, 3, and 11 are configured to transmit data signals of the same polarity within a frame. The three data buses electrically connected to the data sub-lines 2, 7, and 9 are configured to transmit data signals of the same polarity within a frame. The data bus electrically connected to the data sub-line 1 and the data bus electrically connected to the data sub-line 2 are configured to transmit data signals of opposite polarity within a frame.

[0027] In some embodiments, five data sub-lines are included between two adjacent data sub-lines electrically connected to the same data bus, and the two adjacent data buses are configured to transmit data signals of opposite polarity within a frame.

[0028] In some embodiments, three sub-pixels of a pixel unit are electrically connected to the same scan signal line, and adjacent pixel units in the same row are electrically connected to different scan signal lines. The three scan signal lines electrically connected to the sub-pixels in the same row are a fourth scan signal line, a fifth scan signal line, and a sixth scan signal line. Three pixel units are between two adjacent pixel units electrically connected to the fourth scan signal line, two pixel units are between two adjacent pixel units electrically connected to the fifth scan signal line, and one pixel unit is between two adjacent pixel units electrically connected to the sixth scan signal line.

[0029] In some embodiments, two data sub-lines are included between two adjacent data sub-lines that are electrically connected to the same data bus.

[0030] In some embodiments, nine data buses that are electrically connected to and arranged adjacent to the nine adjacent data sub-lines form a group, three of the data buses in a group are configured to transmit data signals of the same polarity within a frame, and two adjacent groups of data buses are configured to transmit data signals of opposite polarity within a frame.

[0031] In some embodiments, three columns of sub-pixels electrically connected to the same data bus are configured to emit light of the same color.

[0032] In some embodiments, the three data sub-lines electrically connected to the same data bus are respectively electrically connected to three adjacent columns of sub-pixels. Within the same row of sub-pixels, two adjacent sub-pixels are electrically connected to different scan signal lines. A column of sub-pixels is electrically connected to a scan signal line at the same position in one of a plurality of signal line groups.

[0033] In some embodiments, adjacent data buses are configured to transmit data signals of opposite polarity within a frame.

[0034] In some embodiments, the pixel unit includes three sub-pixels arranged adjacent to each other along the second direction, and the three sub-pixels of the pixel unit are respectively configured to emit red, green, and blue light. The sub-pixels in the same row are configured to emit light of the same color.

[0035] In some embodiments, two or six adjacent sub-pixels along the first direction form a group, and a group of sub-pixels is electrically connected to the same scan signal line. Within the same row of sub-pixels, two adjacent groups of sub-pixels along the first direction are electrically connected to different scan signal lines. A column of sub-pixels is electrically connected to a scan signal line at the same position in one of the plurality of signal line groups.

[0036] In some embodiments, five data sub-lines are included between two adjacent data sub-lines electrically connected to the same data bus. Two adjacent data buses are configured to transmit data signals of opposite polarity within a frame.

[0037] In other aspects, a display panel is provided. The display panel includes an array substrate as described in any of the above embodiments, a color filter substrate, and a liquid crystal layer. The color filter substrate is disposed opposite to the array substrate. The liquid crystal layer is disposed between the array substrate and the color filter substrate.

[0038] In other aspects, a display device is provided, comprising the aforementioned display panel and a backlight module. The backlight module is disposed on the backlight side of the display panel. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0040] Figure 1 is a structural diagram of a display device according to some embodiments;

[0041] Figure 2 is a structural diagram of a display device according to some embodiments;

[0042] Figure 3 is a schematic diagram of a display area of ​​a display device according to some embodiments;

[0043] Figure 4 is a planar structural diagram of an array substrate according to some embodiments;

[0044] Figure 5 is a diagram showing a connection method of sub-pixels with scan signal lines and data lines according to some embodiments;

[0045] Figure 6 is a planar structure diagram of a single sub-pixel according to some embodiments;

[0046] Figure 7 is a diagram showing an arrangement of touch traces and data sub-lines in an array substrate according to some embodiments;

[0047] Figure 8 is a diagram showing another arrangement of touch traces and data sub-lines in an array substrate according to some embodiments;

[0048] Figure 9 is a diagram showing another arrangement of touch traces and data sub-lines in an array substrate according to some embodiments;

[0049] Figure 10 is another arrangement diagram of touch traces and data sub-lines in an array substrate according to some embodiments;

[0050] Figure 11 is a connection structure diagram between pixel electrodes and scan signal lines according to some embodiments;

[0051] Figure 12 is a schematic diagram of the structure of three scan signal lines of a signal line group according to some embodiments;

[0052] Figure 13 is a diagram of another connection method between sub-pixels and scan signal lines and data lines according to some embodiments;

[0053] Figure 14 is a diagram showing another connection method between sub-pixels and scan signal lines and data lines according to some embodiments;

[0054] Figure 15 is a diagram showing another connection method between sub-pixels and scan signal lines and data lines according to some embodiments;

[0055] Figure 16 is a diagram showing another connection method between sub-pixels and scan signal lines and data lines according to some embodiments;

[0056] Figure 17 is a diagram showing another connection method between sub-pixels and scan signal lines and data lines according to some embodiments;

[0057] Figure 18 is a diagram showing another connection method between sub-pixels and scan signal lines and data lines according to some embodiments;

[0058] Figure 19 is a diagram showing another connection method between sub-pixels and scan signal lines and data lines according to some embodiments;

[0059] Figure 20 is a diagram showing another connection method between sub-pixels and scan signal lines and data lines according to some embodiments;

[0060] Figure 21 is a diagram showing another connection method between sub-pixels and scan signal lines and data lines according to some embodiments. Detailed Implementation

[0061] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0062] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0063] In this disclosure, terms such as “down,” “below,” “above,” and “up” are used to explain the relationships between components shown in the accompanying drawings. The terms may be relative concepts and described based on the directions shown in the drawings, or based on the sequence of process steps, but are not limited thereto.

[0064] The term "relative" means that the first element can be directly or indirectly relative to the second element. In the case where the third element is between the first and second elements, although they are still relative to each other, the first and second elements can be understood as being indirectly relative to each other.

[0065] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0066] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. The term "connected" should be interpreted broadly; for example, a "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection via an intermediate medium. The term "coupled," for example, indicates that two or more components have direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0067] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0068] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0069] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0070] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0071] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0072] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0073] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0074] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0075] Referring to FIG1, an embodiment of the present disclosure provides a display device, the display device 1000 being a product having image display functionality. Exemplarily, the display device 1000 can be any device that displays either moving (e.g., video) or fixed (e.g., still image) content, and whether it is text or an image.

[0076] For example, the display device 1000 can be any product or component with display function, such as a television, laptop computer, tablet computer, personal digital assistant (PDA), mobile phone, watch, clock, calculator, GPS receiver / navigator, camera, display of camera view (e.g., display of rearview camera in a vehicle), wearable device, augmented reality (AR) device, virtual reality (VR) device, mixed reality (MR) device, in-vehicle display, flying display, etc.

[0077] In a specific example, the aforementioned display device can be an in-vehicle display, which includes, but is not limited to, instrument panels and central control screens. Compared to other types of display devices, in-vehicle displays typically have higher requirements for the viewing angle, brightness, and reliability of the display panel.

[0078] In some embodiments, from the perspective of the light emission type of the display device 1000, the display device 1000 can be a liquid crystal display (LCD). From the perspective of the shape of the display device 1000, the display device 1000 can be a flat panel display device or a curved panel display device, etc. From the perspective of the shape of the display device 1000, the display device 1000 can be rectangular or circular, etc. The following uses a rectangular and flat liquid crystal display device as an example to illustrate some embodiments of this disclosure. However, the embodiments of this disclosure are not limited to this, and any other display device can be considered as long as the same technical concept is applied.

[0079] Referring to Figure 2, in some embodiments, when the display device 1000 is a liquid crystal display device, the display device 1000 may include a display panel 1100, a backlight module 1200 disposed on the backlight side of the display panel 1100, and an upper polarizer (not shown in the figure) disposed on the light-emitting side of the display panel 1100. The backlight module 1200 is used to provide a light source for the display panel 1100. The display device 1000 may also include a driving circuit board (not shown in the figure). The driving circuit board may include, for example, a timing controller (TCON), a power management chip (DC / DC), and an adjustable resistor voltage divider circuit (generating Vcom), etc. Of course, the driving circuit board may also include other circuit structures, which will not be listed here. The driving circuit board is electrically connected to the display panel 1100 and the backlight module 1200, and is used to transmit control signals to the display panel 1100 and the backlight module 1200 to drive the backlight module 1200 to emit light and drive the display panel 1100 to display images. In addition, the display device 1000 may also include, but is not limited to, a touch structure, an under-display camera, and an under-display fingerprint sensor, enabling the display device 1000 to perform various functions such as touch, photography, video recording, or fingerprint recognition, which will not be listed here.

[0080] For example, the backlight module 1200 can be a direct-lit backlight module or an edge-lit backlight module. In a specific example of a direct-lit backlight module, the backlight module 1200 may include a light-emitting substrate. The light-emitting substrate may include a driving backplate and multiple light-emitting chips (mini-LED chips / micro-LED chips) disposed on the driving backplate. The multiple light-emitting chips may include blue LED chips for emitting blue light, red LED chips for emitting red light, and green LED chips for reflecting green light. A driving circuit and a reflective layer (such as white ink) may be disposed on the driving backplate. The light-emitting chips are electrically connected to the driving circuit, which is configured to drive the light-emitting chips to emit light. The reflective layer can reflect light reflected from the display panel onto the driving backplate back to the display panel, which helps to improve the light extraction efficiency of the light-emitting surface of the display panel (the side away from the backlight module).

[0081] The backlight module 1200 may further include a plurality of optical films disposed between the light-emitting substrate and the display panel. The optical films can homogenize the light emitted from the light-emitting substrate, enabling the backlight module 1200 to provide a uniform surface light source for the display panel 1100, thereby improving the brightness uniformity of the display panel in different areas. For example, the plurality of optical films may include a scattering film, a prism film, and a diffusing film disposed sequentially along a direction close to the display panel.

[0082] The display device may also include a polarizer disposed between the backlight module and the display panel. The polarizer projects polarized light emitted from the backlight module 1200 in a single polarization direction onto the display panel. It can be attached to the side of the display panel closest to the backlight module. The polarizer can be, for example, an absorptive iodine-based polarizer, an advanced polarizer film (APF), or a metal wire grid polarizer (WGP) disposed on the backlight side of the display panel. For example, the material of the metal display polarizer WGP can be aluminum (Al), the wire grid period can be 90nm–200nm, the wire grid height can be 120nm–200nm, and the wire grid width duty can be 30%–70%.

[0083] When the display device 1000 is an in-vehicle display, the upper polarizer of the display device 1000 is usually designed with a lateral (along the extension direction of the scanning signal line 24 / first direction X) compensation film to compensate for the contrast ratio (CR) of the display device 1000 at a wide viewing angle.

[0084] Referring again to Figure 2, when the display panel 1100 is a liquid crystal display panel, the display panel 1100 may include an array substrate 100 and a color filter substrate 200 disposed opposite each other, and a liquid crystal layer 300 disposed between the array substrate 100 and the color filter substrate 200. The color filter substrate 200 may also be referred to as an opposing substrate or an encapsulation substrate. Of course, the structure of the display panel 1100 is not limited to this; the display panel 1100 may also include other structures, as long as the same technical concept is adopted. For example, the display panel 1100 may also include a first alignment film (not shown in the figure) disposed on the side of the array substrate 100 near the liquid crystal layer 300, and a second alignment film (not shown in the figure) disposed on the side of the color filter substrate 200 near the liquid crystal layer 300, etc.

[0085] Referring to Figure 3, the display panel 1100 may include multiple pixel units P, which are arranged in an array. A pixel unit P refers to the smallest repeating unit in the display panel capable of achieving color display; a pixel unit P can also be called a pixel. A pixel unit P typically includes at least two sub-pixels PX for emitting light of different colors; the sub-pixels PX are the smallest light-emitting units in the display panel.

[0086] For example, as shown in FIG3, a pixel unit P may include a first sub-pixel PX1 for emitting red light, a second sub-pixel PX2 for emitting green light, and a third sub-pixel PX3 for emitting blue light. Of course, in some other embodiments, the pixel unit P may include four sub-pixels (not shown in the figure) for emitting red light, blue light, yellow light, and green light; or, in other embodiments, the pixel unit P may include four sub-pixels PX (not shown in the figure) for emitting red light, blue light, green light, and white light. Naturally, the embodiments of this disclosure are not limited to these, and the composition of the pixel unit P will not be listed individually here. As shown in FIG3, the embodiments of this application will be illustratively described below using the example of a pixel unit P including three sub-pixels PX, and the three sub-pixels PX including a first sub-pixel PX1 for emitting red light, a second sub-pixel PX2 for emitting green light, and a third sub-pixel PX3 for emitting blue light.

[0087] The sub-pixel PX may include circuit structures (including but not limited to thin-film transistors, pixel electrodes, and common electrodes) on the array substrate 100, a color filter layer on the color filter substrate 200, and liquid crystal molecules located between the pixel circuit and the color filter layer. The circuit structures can be used to form an electric field that drives the liquid crystal molecules in the liquid crystal layer to deflect. The deflection angle of the liquid crystal molecules, combined with a polarizer, can adjust the grayscale displayed by the sub-pixel. The color filter layer filters light so that each sub-pixel can emit light of a single color (such as red, green, or blue). Different sub-pixels PX can display the same or different colors and grayscale levels to achieve the purpose of image display.

[0088] In the embodiments of this disclosure, the same description as for pixel units (sub-pixels) is used when describing the array substrate. This can refer to the circuit structure of the pixel unit (sub-pixel) located in the array substrate, and it can be combined with the color filter substrate to form a complete pixel unit (sub-pixel). When describing the sub-pixel of the array substrate as being configured to emit light of a color, it refers to the color that the light passing through the sub-pixel ultimately presents on the light-emitting side of the display panel. The formation of this color can depend on the color filter layer on the color filter substrate.

[0089] Referring to Figure 4, in some embodiments, the array substrate 100 may have a display area A1 and a peripheral area A2 surrounding the display area A1. The display area A1 may include, but is not limited to, multiple pixel circuits, pixel electrodes, and a common electrode, and the peripheral area A2 may include, but is not limited to, a gate driver on array (GOA) 110, control signal lines (such as clock signal lines, VSS / VDD signal lines, etc.) 120, and a source driver IC 130. The peripheral area A2 may include a fan-out area A3 adjacent to one side of the display area A1, for example, the fan-out area A3 is adjacent to the lower edge of the display area A1.

[0090] Referring to Figure 5, the array substrate 100 also includes a substrate and multiple pixel units P, multiple signal line groups 20, multiple data sub-lines 31 and multiple data buses 32.

[0091] Multiple pixel units P are disposed within the display area A1. Each pixel unit P includes multiple sub-pixels PX. The multiple (all) sub-pixels PX of the multiple pixel units P are arranged in an array, that is, all the sub-pixels PX included in the array substrate 100 are arranged in an array. The sub-pixels PX are arranged in rows along a first direction X and in columns along a second direction Y. The first direction X and the second direction Y intersect; for example, the first direction X and the second direction Y can be perpendicular to each other.

[0092] A signal line group 20 is included between two adjacent rows of sub-pixels PX. Each of the multiple signal line groups 20 includes M scan signal lines 24 (also referred to as gate lines) spaced apart along a second direction Y. The multiple signal line groups 20 can be spaced apart along the second direction Y, and the M scan signal lines 24 of each signal line group 20 extend generally along a first direction X. Wherein, M is a natural number greater than 2. For example, the value of M can be 3, 4, or 5, that is, a signal line group 20 includes at least 3 scan signal lines 24. All embodiments of this disclosure below are described exemplified by the example of M being 3, that is, a signal line group 20 including 3 scan signal lines. The embodiments of this disclosure are not limited, and the number of scan signal lines 24 included in the signal line group 20 can be selected according to actual needs.

[0093] Multiple data sub-lines 31 are arranged at intervals along the first direction X, pass through the display area A1 along the second direction Y, and extend to the fan-out area A3. Multiple signal line groups 20 and multiple data sub-lines 31 intersect to form a grid structure. One grid (the area enclosed between two adjacent signal line groups 20 and two adjacent data sub-lines 31) defines a pixel area 101, and one pixel area 101 is used to form a sub-pixel PX.

[0094] A data sub-line 31 is electrically connected to a column of sub-pixels PX. Multiple data buses 32 are disposed in the fan-out area A3, and each data bus 32 is electrically connected to N data sub-lines 31. Here, N is a natural number greater than 2. For example, the value of N can be 3, 4, or 5, meaning that one data bus 32 can be electrically connected to at least 3 data sub-lines 31. All embodiments of this disclosure below are described exemplified by the example of N being 3, i.e., one data bus 32 being electrically connected to 3 data sub-lines 31. The embodiments of this disclosure are not limited to these examples, and the number of scan signal lines 24 included in the signal line group 20 can be selected according to actual needs.

[0095] In some embodiments, the value of M is an odd number; for example, the value of M can be 3 or 5. Furthermore, the value of M and the value of N can be equal; for example, the values ​​of M and N can both be 3 or 5. Alternatively, the values ​​of M and N can be unequal; for example, the value of M can be 3 and the value of N can be 6; or the value of M can be 5, in which case the value of N can be 10. When the values ​​of M and N are unequal, for example, when the value of N is a multiple of the value of M, a multiplexing circuit (MUX) can be provided in the peripheral area so that the N data sub-lines 31 electrically connected to a data bus 32 can be used only to transmit data signals to one sub-pixel within a certain time period.

[0096] In some embodiments, the values ​​of M and N are both multiples of 3. For example, the values ​​of M and N are equal, and both M and N are 3. The embodiments of this disclosure will be described exemplarily below using the example of equal values ​​of M and N, and both M and N being 3.

[0097] In some embodiments, when both M and N are 3, one sub-pixel PX is electrically connected to one scan signal line 24, and a row of sub-pixels PX is electrically connected to three scan signal lines 24. In other words, three scan signal lines 24 are electrically connected to different sub-pixels PX located in the same row. Three sub-pixels PX in a row that are electrically connected to the same data bus 32 are each electrically connected to different scan signal lines 24. Thus, one data bus 32 can transmit data signals to three columns of sub-pixels PX through three data sub-lines 31 and three scan signal lines 24, which helps reduce the number of data buses 32, i.e., reduces the number of data signal channels in the source driver chip, thereby reducing the number of source driver chips and manufacturing costs.

[0098] Referring, as exemplarily to FIG6, a sub-pixel PX includes a thin-film transistor (TFT) T1 and a pixel electrode 40. The gate of the TFT T1 is electrically connected to a scan signal line 24, one of its source and drain is electrically connected to a data sub-line 31, and the other of its source and drain is electrically connected to the pixel electrode 40. The TFT T1 can be turned on and off under the control of the scan signal line 24. When the TFT T1 is turned on under the control of the scan signal line 24, it can transmit the data signal transmitted by the data sub-line 31 to the pixel electrode 40. In embodiments of this disclosure, when describing the pixel unit P (or sub-pixel PX) as electrically connected to the data sub-line 31 or the scan signal line 24, it means that the TFT T1 included in the pixel unit P (or sub-pixel PX) is electrically connected to the data sub-line 31 or the scan signal line 24.

[0099] As shown in Figure 5, three data sub-lines 31, electrically connected to the same data bus 32, are respectively connected to three different sub-pixels PX in the same row. The thin-film transistors T1 of these three different sub-pixels PX are respectively connected to three different scan signal lines 24. Thus, when the three scan signal lines 24 transmit scan signals at different time periods, the three thin-film transistors T1 of the three sub-pixels PX can be controlled to be turned on at different time periods, so that the data signals transmitted on the data bus 32 are transmitted to the pixel electrodes 40 of the three sub-pixels PX at different time periods. This reduces the number of data buses 32, thereby reducing the number of data signal channels in the source driver chip, achieving the goal of reducing the number of source driver chips and manufacturing costs.

[0100] It should be understood that in Figure 5 and other figures of this application, the number “21” marked on the pixel electrode 40 refers to the sub-pixel PX where the pixel electrode 40 is located, which is electrically connected to the first scan signal line 21. Similarly, the numbers “22” and “23” marked on the pixel electrode 40 refer to the sub-pixel PX where the pixel electrode 40 is located, which is electrically connected to the second scan signal line 22 and the third scan signal line 23.

[0101] In some embodiments, the active layer material of the thin-film transistor T1 can be any one or more of metal oxide, amorphous silicon (a-Si), polycrystalline silicon (p-Si), and low-temperature polycrystalline silicon (LTPS), wherein the active layer material is preferably metal oxide.

[0102] In some embodiments, the active layer material of the thin-film transistor T1 may include: metal oxide materials and / or metal oxide nitride materials. The metal oxide materials include, but are not limited to: indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium tin zinc oxide (ITZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), zinc tin oxide (ZTO), indium-free metal oxides (In-free OS), rare earth-doped oxides (Ln-OS), zinc oxide (ZnO), gallium oxide (GaO), indium oxide (InO), HfInZnO (HIZO), ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, and Cd-Sn-O. The metal oxide nitride materials include, but are not limited to, zinc oxynitride, indium oxynitride, gallium oxynitride, tin oxynitride, cadmium oxynitride, aluminum oxynitride, germanium oxynitride, titanium oxynitride, silicon oxynitride, or combinations thereof. The active layer material can be amorphous, partially crystalline, single-crystal or polycrystalline, and can also be a single-layer or multi-layer structure.

[0103] Oxide thin-film transistors have the characteristic of low leakage current, which helps to reduce the leakage current of thin-film transistor T1, thereby simplifying the circuit structure of pixel circuit, improving the aperture ratio of array substrate 100, and improving the light transmittance of array substrate 100.

[0104] In some embodiments, as shown in FIG5, the pixel unit P includes three sub-pixels PX arranged adjacently along the first direction X. The three sub-pixels PX include a first sub-pixel PX1 for emitting red light, a second sub-pixel PX2 for emitting green light, and a third sub-pixel PX3 for emitting blue light. Furthermore, sub-pixels PX in the same column are configured to emit light of the same color; for example, all sub-pixels PX in the same column are configured to emit red light, green light, or blue light. The upper polarizer of the display device 1000 typically employs a lateral (along the extension direction of the scan signal line 24 / first direction X) compensation film design to compensate for the contrast ratio (CR) of the display device at large viewing angles. Compared to arranging the three sub-pixels PX of the pixel unit P along the second direction Y, in the embodiments of this disclosure, the three sub-pixels PX included in the pixel unit P are arranged along the extension direction of the scan signal line 24 (first direction X), which is beneficial to improving the effect of the upper polarizer on the contrast ratio of the display device at large viewing angles, i.e., it is beneficial to further improve the contrast ratio of the display device at large viewing angles.

[0105] Referring to Figures 7 and 8, in some embodiments, the array substrate 100 further includes a plurality of touch traces 33. The plurality of touch traces 33 are arranged at intervals along a first direction X, and all of the touch traces 33 extend along a second direction Y. Exemplarily, the touch traces 33 may be made of the same material and fabricated in the same layer as the data sub-lines 31.

[0106] As shown in Figures 7 and 8, the orthographic projection of the touch trace 33 on the substrate partially coincides with the orthographic projection of the pixel electrode 40 on the substrate, and the portion where the orthographic projections of the touch trace 33 and the pixel electrode 40 coincide is located at the middle of the pixel electrode 40 along the first direction X. In other words, in the embodiments of this disclosure, the touch trace 33 is disposed within the opening region of the sub-pixel PX. This eliminates the need for a black matrix on the color filter substrate to block the touch trace 33, which helps to reduce the size of the black matrix and thereby improves the aperture ratio (AR) and light extraction efficiency of the display panel 1100.

[0107] The middle part of the pixel electrode 40 along the first direction X refers to any region other than the two side boundaries of the pixel electrode 40 along the first direction X, including but not limited to the geometric center of the pixel electrode 40 along the first direction X. For example, as shown in Figures 7 and 8, the orthogonal projection of the touch trace 33 onto the substrate can be located slightly to the left of the orthogonal projection of the pixel electrode 40 onto the substrate, and can penetrate multiple pixel electrodes 40 of a row of sub-pixels PX along the second direction Y.

[0108] Referring to Figures 9 and 10, in some other embodiments, the touch trace 33 may also be disposed adjacent to the data sub-line 31, and the orthographic projection of the touch trace 33 on the substrate does not coincide with the orthographic projection of the pixel electrode 40 on the substrate. That is to say, the touch trace 33 may also be disposed outside the opening area of ​​the sub-pixel PX. In this way, the orthographic projection of the black matrix on the color filter substrate onto the array substrate 100 may also cover the touch trace 33.

[0109] Referring to Figures 7 and 9, in some embodiments, three data sub-lines 31 are included between two adjacent touch traces 33 along the first direction X, that is, one touch trace 33 is provided for each column of pixel units P. Each pair of adjacent touch traces 33 forms a group, and the two touch traces 33 in a group are configured to transmit the same driving signal. Exemplarily, the array substrate 100 may also include touch electrodes (not shown in the figures), and the two touch traces 33 in a group are electrically connected to the same column of touch electrodes.

[0110] Referring to Figures 8 and 10, in some embodiments, six data sub-lines 31 are included between two adjacent touch traces 33 along the first direction X, that is, one touch trace 33 is provided for every two columns of pixel units P. Adjacent touch traces 33 are electrically insulated from each other. Exemplarily, the array substrate 100 may also include touch electrodes (not shown in the figures), with each adjacent touch trace 33 connected to a different touch electrode.

[0111] A row of sub-pixels PX can be electrically connected to three scan signal lines 24 of the same signal line group 20, and sub-pixels PX in different rows can be electrically connected to scan signal lines 24 of different signal line groups 20 (as shown in Figure 3). Alternatively, a row of sub-pixels PX can be electrically connected to three scan signal lines 24 belonging to two different signal line groups 20, and at least two scan signal lines of a signal line group 20 can be electrically connected to sub-pixels PX in different rows; for example, a row of sub-pixels PX can be electrically connected to one scan signal line 24 of a signal line group 20 located on one side (e.g., the upper side) of that row of sub-pixels PX, and electrically connected to two scan signal lines 24 of a signal line group 20 located on the other side (e.g., the lower side) of that row of sub-pixels PX (as shown in Figure 5).

[0112] Referring to Figures 6 to 11, in some embodiments, a row of sub-pixels PX is electrically connected to three scan signal lines 24 of the same signal line group 20. As shown in Figure 11, the row of sub-pixels PX electrically connected to the signal line group 20 is the target row sub-pixel PX'. Along the direction away from the target row sub-pixel PX', the three scan signal lines 24 of the signal line group 20 are, in sequence, the first scan signal line 21, the second scan signal line 22, and the third scan signal line 23.

[0113] For example, as shown in FIG11, the target row sub-pixel PX' is electrically connected to three scan signal lines 24 of a signal line group 20 located below the target row sub-pixel PX'. At this time, the direction away from the target row sub-pixel PX' is the direction from top to bottom along the second direction Y.

[0114] The thin-film transistor T1 (hereinafter referred to as the first transistor T11) of the sub-pixel PX electrically connected to the first scan signal line 21 is located on the side (upper side) of the first scan signal line 21 closer to the target sub-pixel PX'. The thin-film transistor T1 (hereinafter referred to as the second transistor T12) of the sub-pixel PX electrically connected to the second scan signal line 22 is located between the first scan signal line 21 and the second scan signal line 22. The thin-film transistor T1 (hereinafter referred to as the third transistor T13) of the sub-pixel PX electrically connected to the third scan signal line 23 is located between the second scan signal line 22 and the third scan signal line 23. In this way, interference between the three scan signal lines 24 can be avoided, that is, the three scan signal lines 24 will not cross, and the parasitic capacitance between the scan signal lines 24 and the thin-film transistor T1 can be greatly reduced, for example, the parasitic capacitance between the pixel electrode 40 and the scan signal line 24 can be reduced, and the load on the scan signal line 24 can be reduced.

[0115] Referring again to Figures 11 and 12, in some embodiments, the first scan signal line 21 includes a first groove 211 formed by bending away from the target row sub-pixel PX' (bending downwards), and a thin-film transistor T1 (first transistor T11) electrically connected to the first scan signal line 21 is located within the first groove 211. The second scan signal line 22 includes a second groove 221 formed by bending away from the target row sub-pixel PX' (bending downwards), and a thin-film transistor T1 (second transistor T12) electrically connected to the second scan signal line 22 and the first groove 211 are both located within the second groove 221. The third scan signal line 23 extends along the first direction X. Thus, the three scan signal lines 24 of a signal line group 20 and all the thin-film transistors T1 of a row sub-pixel PX have approximately the same size along the second direction Y at any position in the first direction X, that is, the signal line group 20 and the thin-film transistors T1 occupy approximately the same space along the second direction Y. Thus, the edges of the pixel electrodes 40 that are electrically connected to different scanning signal lines 24 near the signal line group 20 can be flush or approximately flush, which helps to improve the structural uniformity of the pixel electrodes 40 in different sub-pixels PX and makes the aperture ratios of different sub-pixels PX equal or approximately equal.

[0116] As shown in Figures 11 and 12, in some embodiments, the first scan signal line 21 includes a first extension segment 212 and a second extension segment 213 alternately connected along a first direction X. The first extension segment 212 includes a first sub-portion 214 extending along the first direction X, and two second sub-portions 215 connected to both ends of the first sub-portion 214. The second sub-portions 215 extend along a second direction Y, and the end of the second sub-portion 215 away from the first sub-portion 214 is connected to the second extension segment 213. The first extension segment 212 forms a first groove 211. The second extension segment 213 is farther away from the target row sub-pixel PX' along the second direction Y than the first sub-portion 214. This greatly simplifies the structure of the first scan signal line 21 and reduces the fabrication difficulty of the first scan signal line 21.

[0117] Referring again to Figures 11 and 12, in some embodiments, the second scan signal line 22 includes a third extension segment 222 and a fourth extension segment 223 alternately connected along a first direction X. The third extension segment 222 includes a third sub-section 224 extending along the first direction X, and two fourth sub-sections 225 connected to both ends of the third sub-section 224. The fourth sub-sections 225 extend along a second direction Y, and one end of the fourth sub-section 225 away from the third sub-section 224 is connected to the fourth extension segment 223. The third extension segment 222 forms a second groove 221. The fourth extension segment 223 is farther away from the target row sub-pixel PX' along the second direction Y compared to the third sub-section 224. This greatly simplifies the structure of the second scan signal line 22 and reduces the difficulty of fabricating the second scan signal line 22.

[0118] For example, as shown in Figures 11 and 12, the dimension of the first extension segment 212 along the first direction X is smaller than the dimension of the second extension segment 213 along the first direction X. The dimension of the third extension segment 222 along the first direction X is larger than the dimension of the fourth extension segment 223 along the first direction X. The dimension of the third extension segment 222 along the first direction X is larger than the dimension of the first extension segment 212 along the first direction X. This facilitates the placement of the first groove 211 within the second groove 221.

[0119] Referring again to Figures 11 and 12, along the second direction Y, a portion of the third sub-section 224 is disposed opposite to the first sub-section 214, and a portion is disposed opposite to the second extension 213. The gap D1 between the third sub-section 224 and the first sub-section 214 is smaller than the gap D2 between the third sub-section 224 and the second extension 213. A first gap is formed between the third sub-section 224 and the second extension 213, and the thin-film transistor T1 (second transistor T12), which is electrically connected to the second scan signal line 22, is located within the first gap between the third sub-section 224 and the second extension 213.

[0120] The gap D3 between the third scan signal line 23 and the third sub-section 224 is smaller than the gap D4 between the third scan signal line 23 and the fourth extension 223. A second gap is formed between the third scan signal line 23 and the fourth extension 223, and the thin-film transistor T1 (third transistor T13) electrically connected to the third scan signal line 23 is located within the second gap between the third scan signal line 23 and the fourth extension 223.

[0121] Referring to FIG11, in some embodiments, the orthographic projection of the pixel electrode 40 of the sub-pixel PX electrically connected to the second scan signal line 22 onto the substrate at least partially overlaps with the orthographic projection of the first scan signal line 21 onto the substrate.

[0122] For example, as shown in FIG11, the orthographic projection of the pixel electrode 40 of the sub-pixel PX electrically connected to the second scan signal line 22 on the substrate can also coincide with the orthographic projection of the second scan signal line 22 on the substrate.

[0123] Referring to FIG11, in some embodiments, the orthographic projection of the pixel electrode 40 of the sub-pixel PX electrically connected to the third scan signal line 23 onto the substrate at least partially overlaps with the orthographic projections of the first scan signal line 21 and the second scan signal line 22 onto the substrate.

[0124] For example, as shown in FIG11, the orthographic projection of the pixel electrode 40 of the sub-pixel PX electrically connected to the third scan signal line 23 onto the substrate can also coincide with the orthographic projection of the third scan signal line 23 onto the substrate.

[0125] Referring to Figure 5, in some embodiments, a row of sub-pixels PX is electrically connected to three scan signal lines 24 belonging to two signal line groups 20, respectively. This reduces the number of scan signal lines 24 that the pixel electrode 40, electrically connected to the third scan signal line 23, traverses along the second direction Y, thereby reducing the overlapping area of ​​the pixel electrode 40 and the scan signal lines 24 on the substrate, lowering the parasitic capacitance generated by the pixel electrode 40, and reducing the load on the scan signal lines 24.

[0126] As shown in Figure 5, in some embodiments, along the scanning direction of multiple scanning signal lines 24 (from top to bottom in Figure 12), the three scanning signal lines 24 of the signal line group 20 are sequentially the first scanning signal line 21, the second scanning signal line 22, and the third scanning signal line 23. In the two signal line groups 20 located on either side of a row of sub-pixels PX along the second direction Y, the one that transmits the scanning signal first is the first signal line group 201, and the other is the second signal line group 202. The signal line group 20 located between the two rows of sub-pixels PX serves as the first signal line group 201 and the second signal line group 202 for the two rows of sub-pixels PX, respectively. A row of sub-pixels PX is electrically connected to the third scanning signal line 23 of the first signal line group 201 and the first scanning signal line 21 and the second scanning signal line 22 of the second signal line group 202.

[0127] The scan signal line 24 can be electrically connected to the gate driving circuit of the peripheral region. The gate driving circuit includes multiple shift registers cascaded together. The multiple shift registers sequentially transmit scan signals to the multiple scan signal lines 24 included in the multiple signal line groups 20. The scanning direction of the multiple scan signal lines 24 described in the embodiments of this disclosure refers to the direction in which the gate driving circuit transmits scan signals to the multiple scan signal lines, that is, the cascading direction of the multiple shift registers.

[0128] Referring to Figures 5 and 13, in some embodiments, two adjacent pixel units P along the first direction X form a group, and a group of pixel units P1 is electrically connected to the same scan signal line 24. Two adjacent groups of pixel units P1 along the first direction X are electrically connected to different scan signal lines 24. There are two groups of pixel units P1 between two adjacent pixel units P1 electrically connected to the same scan signal line 24, that is, every two columns of pixel units P are connected to different scan signal lines 24.

[0129] In the embodiments shown in Figures 5 and 13, the row of sub-pixels P shown in Figure 12 is electrically connected to three scan signal lines 24 belonging to two signal line groups 20 respectively; the row of sub-pixels P shown in Figure 13 is electrically connected to three scan signal lines 24 of the same signal line group 20. The following description uses the example of "a row of sub-pixels P being electrically connected to three scan signal lines 24 belonging to two signal line groups 20" to illustrate the embodiments of this disclosure. It is foreseeable that the embodiments of this disclosure are not limited to this, and the connection method shown in Figure 13 can also be considered.

[0130] As shown in Figures 5 and 13, each column of sub-pixels PX is electrically connected to a scan signal line 24 located at the same position in multiple signal line groups 20. For example, as shown in Figure 5, along the left-to-right direction, the sub-pixels PX in columns 1 to 6 are all electrically connected to the third scan signal line 23 of the first signal line group 201 (the signal line group 20 located above the sub-pixels PX); the sub-pixels PX in columns 7 to 12 are all electrically connected to the first scan signal line 21 of the second signal line group 202 (the signal line group 20 located below the sub-pixels PX); and the sub-pixels PX in columns 13 to 18 are all electrically connected to the second scan signal line 22 of the second signal line group 202. For example, as shown in FIG13, along the direction from left to right, the sub-pixels PX in columns 1 to 6 are all electrically connected to the third scan signal line 23; the sub-pixels PX in columns 7 to 12 are all electrically connected to the first scan signal line 21; and the sub-pixels PX in columns 13 to 18 are all electrically connected to the second scan signal line 22.

[0131] As shown in Figures 5 and 13, in some embodiments, six adjacent data buses 32 and 18 adjacent data sub-lines 31 electrically connected to the aforementioned six adjacent data buses 32 constitute a minimum repetition period for the arrangement of the data sub-lines 31 and data buses 32. Within the same minimum repetition period, five data sub-lines 31 are included between two adjacent data sub-lines 31 electrically connected to the same data bus 32. Adjacent data buses 32 are configured to transmit data signals of opposite polarity within one frame. Thus, within the same frame, the data signals of two adjacent columns of sub-pixels PX have opposite polarities. For the same data bus 32, it can be configured to transmit data signals of opposite polarities within two adjacent frames. This ensures that the data signals of the same column of sub-pixels PX have opposite polarities within two adjacent frames, which is beneficial for improving the display effect of the display panel.

[0132] The polarity of a data signal refers to whether the voltage of the data signal is positive or negative. For example, if two data signals have the same polarity, then the voltage of both data signals is either positive or negative. If two data signals have opposite polarities, then the voltage of one data signal is positive and the voltage of the other data signal is negative.

[0133] Three data sub-lines 31, electrically connected to the same data bus 32, are configured to transmit data signals sequentially to three different sub-pixels P in the same row during a first time period, a second time period, and a third time period. The inventors discovered that during the first time period, the voltage of the data bus 32 and the data sub-lines 31 changes from 0V to the voltage V of the first data signal. data1 The voltage change of data sub-line 31 is V. data1 During the second time period, the voltage of data bus 32 and data sub-line 31 changes from V... data1 The voltage V of the second data signal changes.data2 The voltage change of data sub-line 31 is (V data2 -V data1 During the third time period, the voltage of data bus 32 and data sub-line 31 changes from V... data2 The voltage V of the third data signal changes. data3 The voltage change of data sub-line 31 is (V data3 -V data2 The voltage changes on the data bus 32 and data sub-line 31 during the first time period show a clear difference from those during the second and third time periods. This difference is referred to as the pre-stored difference in the data signal. This pre-stored difference in the data signal leads to voltage differences in the data signals of different columns of sub-pixels PX on the display panel, which may cause vertical lines to appear on the display panel during display. Furthermore, the more adjacent sub-pixels PX electrically connected to the same scan signal line 24, the more easily the vertical lines on the display panel are observed by the human eye.

[0134] Referring to Figure 14, in some embodiments, three sub-pixels PX of a pixel unit P are electrically connected to the same scan signal line 24. Within the same row of sub-pixels PX, adjacent pixel units P are electrically connected to different scan signal lines 24, and there are two pixel units P between two adjacent pixel units P electrically connected to the same scan signal line 24. That is, each pixel unit P is connected to one scan signal line 24, and adjacent pixel units P are connected to different scan signal lines 24. This reduces the number of adjacent sub-pixels PX electrically connected to the same scan signal line 24, thus reducing the likelihood of vertical lines being observed by the human eye.

[0135] As shown in Figure 14, a column of sub-pixels PX is electrically connected to a scan signal line 24 located at the same position in multiple signal line groups 20. For example, within a minimum repetition period of the data bus 32 and data sub-lines 31, along the left-to-right direction, the pixel units P in the 1st and 4th columns are all electrically connected to the third scan signal line 23 of the first signal line group 201 (the signal line group 20 located above pixel unit P); the pixel units P in the 2nd and 5th columns are all electrically connected to the first scan signal line 21 of the second signal line group 202 (the signal line group 20 located below pixel unit P); and the pixel units P in the 3rd and 6th columns are all electrically connected to the second scan signal line 22 of the second signal line group 202.

[0136] As shown in Figure 14, in some embodiments, five data sub-lines 31 are included between two adjacent data sub-lines 31 electrically connected to the same data bus 32, and the two adjacent data buses 32 are configured to transmit data signals of opposite polarity within a frame. Thus, within the same frame, the data signals of two adjacent columns of sub-pixels PX have opposite polarities. For the same data bus 32, it can be configured to transmit data signals of opposite polarities within two adjacent frames. This ensures that the data signals of the same column of sub-pixels PX have opposite polarities within two adjacent frames, which is beneficial for improving the display effect of the display panel.

[0137] Referring to Figure 15, in some embodiments, two adjacent pixel units P along the first direction X form a group. The sub-pixels PX of a group of pixel units P2 are electrically connected to the same scan signal line 24. In the same row of sub-pixels PX, two adjacent groups of pixel units P2 are electrically connected to different scan signal lines 24. That is, every two pixel units P are electrically connected to one scan signal line. The connection order of the three groups of pixel units P2 belonging to two adjacent rows and electrically connected to the six adjacent data buses 32 is reversed with the three scan signal lines 24. In this way, two columns of pixel units P with pre-stored differences can be interrupted every other row, thereby canceling the effect of vertical lines and reducing the possibility of the human eye observing vertical lines.

[0138] For example, as shown in Figure 15, the 18 data sub-lines 31 electrically connected to and arranged adjacent to the six adjacent data buses 32 constitute a minimum repetition period of the arrangement of the data sub-lines 31 and the data buses 32. Within the same minimum repetition period, each row of sub-pixels PX includes three sets of pixel units P2, which are the "three sets of pixel units P2 electrically connected to the six adjacent data buses 32". The connection order of the three sets of pixel units P2 belonging to two adjacent rows of sub-pixels PX is reversed from left to right compared to the connection order of the three scan signal lines 24. For example, in Figure 15, the three rows of sub-pixels PX, from top to bottom, are the first row of sub-pixels PX, the second row of sub-pixels PX, and the third row of sub-pixels PX. The three groups of pixel units P2 in the first row of sub-pixels PX are electrically connected to the third scan signal line 23, the second scan signal line 22, and the first scan signal line 21 from left to right. Similarly, the three groups of pixel units P2 in the second row of sub-pixels PX2 are electrically connected to the first scan signal line 21, the second scan signal line 22, and the third scan signal line 23 from left to right. Of course, the connection order between the three groups of pixel units P2 electrically connected to the six adjacent data buses 32 and the three scan signal lines 24 is not limited to that shown in Figure 15; other connection orders can also be used, which will not be listed here.

[0139] As shown in Figure 15, in some embodiments, there are five data sub-lines 31 between two adjacent data sub-lines 31 electrically connected to the same data bus 32, and the two adjacent data buses 32 are configured to transmit data signals of opposite polarity within a frame. Thus, within the same frame, the data signals of two adjacent columns of sub-pixels PX have opposite polarities. For the same data bus 32, it can be configured to transmit data signals of opposite polarities within two adjacent frames. This ensures that the data signals of the same column of sub-pixels PX have opposite polarities within two adjacent frames, which is beneficial for improving the display effect of the display panel.

[0140] Referring to Figures 16 and 17, in some embodiments, two adjacent sub-pixels PX along the first direction X are grouped together, and a group of sub-pixels PX is labeled "PX4". A group of sub-pixels PX4 is electrically connected to the same scan signal line 24. Within the same row of sub-pixels PX, two adjacent groups of sub-pixels PX4 are electrically connected to different scan signal lines 24, and the intervals between adjacent groups of sub-pixels PX4 electrically connected to different scan signal lines 24 are unequal. This not only reduces the number of adjacent sub-pixels PX electrically connected to the same scan signal line 24, but also avoids the appearance of regular vertical lines on the display panel (such as vertical lines appearing between every three / six columns of sub-pixels PX and head-shaking lines), thereby reducing the risk of the human eye observing vertical lines.

[0141] For example, as shown in Figures 16 and 17, among the 18 columns of sub-pixels P that are electrically connected to and adjacent to the six adjacent data buses 32, nine groups of sub-pixels PX4 located in the same row along the first direction X from left to right are sequentially electrically connected to the third scan signal line 23 of the first signal line group 201 (the signal line group 20 located above the sub-pixel PX), the first scan signal line 21 of the second signal line group 202 (the signal line group 20 located below the sub-pixel PX), the second scan signal line 22 of the second signal line group 202, the first scan signal line 21 of the second signal line group 202, the second scan signal line 22 of the second signal line group 202, the third scan signal line 23 of the first signal line group 201, the second scan signal line 22 of the second signal line group 202, the third scan signal line 23 of the first signal line group 201, and the first scan signal line 21 of the second signal line group 202.

[0142] Referring again to Figures 16 and 17, a column of sub-pixels PX1 are electrically connected to a scan signal line 24 in the same position in multiple signal line groups 20. For example, the sub-pixels PX in columns 1, 2, 11, 12, 15, and 16 from left to right are all electrically connected to the third scan signal line 23 of the first signal line group 201 (the signal line group 20 located above the sub-pixel PX); the sub-pixels PX in columns 3, 4, 7, 8, 17, and 18 from left to right are all electrically connected to the first scan signal line 21 of the second signal line group 202 (the signal line group 20 located below the sub-pixel PX); and the sub-pixels PX in columns 5, 6, 9, 10, 13, and 14 from left to right are all electrically connected to the second scan signal line 22 of the second signal line group 202 (the signal line group 20 located below the sub-pixel PX).

[0143] As shown in Figure 16, in some embodiments, among the 18 adjacent data sub-lines 31 electrically connected to the six adjacent data buses 32, five data sub-lines 31 are included between two adjacent data sub-lines 31 electrically connected to the same data bus 32. Furthermore, five data sub-lines 31 are included between two adjacent data sub-lines 31 electrically connected to the same data bus 32, and adjacent data buses 32 are configured to transmit data signals of opposite polarity within a frame. Thus, within the same frame, the data signals of two adjacent columns of sub-pixels PX have opposite polarities. Moreover, the data signals of the same column of sub-pixels PX have opposite polarities in two adjacent frames, which is beneficial for improving the display effect of the display panel.

[0144] As shown in Figure 17, in some embodiments, the 18 data sub-lines 31, which are electrically connected to and adjacent to the six adjacent data buses 32, are numbered sequentially along the first direction X. For example, they are numbered sequentially from left to right along the first direction X as data sub-line 1, data sub-line 2, ..., data sub-line 17 and data sub-line 18. Specifically, data sub-lines 1, 4, and 10 are electrically connected to one data bus 32. Data sub-lines 2, 5, and 8 are electrically connected to one data bus 32. Data sub-lines 31 3, 6, and 12 are electrically connected to one data bus 32. Data sub-lines 7, 13, and 16 are electrically connected to one data bus 32. Data sub-lines 9, 15, and 18 are electrically connected to one data bus 32. Data sub-lines 11, 14, and 17 are electrically connected to one data bus 32.

[0145] As shown in Figure 17, in some embodiments, when the data bus 32 of the array substrate 100 is electrically connected to the data sub-line 31 in the manner shown in Figure 17, the three data buses electrically connected to the 1st, 3rd, and 11th data sub-lines are configured to transmit data signals of the same polarity within one frame. The three data buses electrically connected to the 2nd, 7th, and 9th data sub-lines are configured to transmit data signals of the same polarity within one frame. The data bus electrically connected to the 1st data sub-line and the data bus electrically connected to the 2nd data sub-line are configured to transmit data signals of opposite polarity within one frame. In this way, within the same frame, the data signals of adjacent columns of sub-pixels PX have opposite polarities, and the data signals of the same column of sub-pixels PX have opposite polarities in adjacent frames, which is beneficial to improving the display effect of the display panel.

[0146] Referring to Figure 18, in some embodiments, the three sub-pixels PX of a pixel unit P are electrically connected to the same scan signal line 24. In the same row of sub-pixels PX, two adjacent pixel units P are electrically connected to different scan signal lines 24. The three scan signal lines 24 electrically connected to the sub-pixels PX in the same row are the fourth scan signal line 241, the fifth scan signal line 242, and the sixth scan signal line 243.

[0147] There are three pixel units P between two adjacent pixel units P electrically connected to the fourth scan signal line 241, two pixel units P between two adjacent pixel units P electrically connected to the fifth scan signal line 242, and one pixel unit P between two adjacent pixel units P electrically connected to the sixth scan signal line 243. In other words, the spacing between two adjacent pixel units P electrically connected to different scan signal lines 24 is unequal. This macroscopically disrupts the possible locations of vertical lines, thereby reducing the risk of the human eye observing vertical lines.

[0148] For example, the fourth scan signal line 241, the fifth scan signal line 242, and the sixth scan signal line 243 can correspond to one of the first scan signal line 21, the second scan signal line 22, and the third scan signal line 23, respectively. Figure 18 only illustrates one correspondence by example. In Figure 18, the fourth scan signal line 241 corresponds to the third scan signal line 23, that is, the fourth scan signal line 241 and the third scan signal line 23 are the same scan signal line; the fifth scan signal line 242 corresponds to the first scan signal line 21, that is, the fifth scan signal line 242 and the first scan signal line 21 are the same scan signal line; and the sixth scan signal line 243 corresponds to the second scan signal line 22, that is, the sixth scan signal line 243 and the second scan signal line 22 are the same scan signal line. The correspondence between the fourth scan signal line 241, the fifth scan signal line 242, and the sixth scan signal line 243 and the first scan signal line 21, the second scan signal line 22, and the third scan signal line 23 is not unique, and the embodiments disclosed herein will not list them one by one.

[0149] As shown in Figure 18, a column of sub-pixels PX is electrically connected to a scan signal line 24 in the same position in multiple signal line groups 20. For example, as shown in Figure 18, along the left-to-right direction, the six columns of sub-pixels PX containing the 1st and 5th pixel units P are all electrically connected to the third scan signal line 23 of the first signal line group 201 (the signal line group 20 located above the sub-pixels PX); the six columns of sub-pixels PX containing the 2nd and 4th pixel units P are all electrically connected to the second scan signal line 22 of the second signal line group 202 (the signal line group 20 located below the sub-pixels PX); and the six columns of sub-pixels PX containing the 3rd and 6th pixel units P are all electrically connected to the first scan signal line 21 of the second signal line group 202.

[0150] Referring again to FIG18, in some embodiments, when the scan signal line 24 is electrically connected to the sub-pixel P in the manner shown in FIG18, there are two data sub-lines 31 between two adjacent data sub-lines 31 electrically connected to the same data bus 32.

[0151] As shown in Figure 18, in some embodiments, three data buses 32 that are electrically connected to and arranged adjacent to the nine adjacent data sub-lines 31 form a group. The three data buses 32 in a group are configured to transmit data signals with the same polarity within a frame, and two adjacent groups of data buses 32 are configured to transmit data signals with opposite polarities within a frame.

[0152] For example, in Figure 18, the three data buses 32 on the left form one group, and the three data buses 32 on the right form another group. The three data buses 32 on the left are configured to transmit data signals of the same polarity within the same frame period, the three data buses 32 on the right are configured to transmit data signals of the same polarity within the same frame period, and the three data buses 32 on the left and the three data buses 32 on the right are configured to transmit data signals of opposite polarity within the same frame period.

[0153] Referring to Figure 18, in some embodiments, where two adjacent data sub-lines 31 electrically connected by the same data bus 32 include two data sub-lines 31, the adjacent two data buses 32 can also be configured to transmit data signals with opposite polarities. This can greatly reduce the phenomenon of polarity concentration in the pixel electrodes 40 of adjacent sub-pixels PX, which is beneficial to improving the display effect of the display panel.

[0154] Referring to Figures 13 to 18, in some embodiments, three columns of sub-pixels PX electrically connected to the same data bus 32 are configured to emit light of the same color.

[0155] Referring to Figure 19, in some embodiments, three data sub-lines 31 electrically connected to the same data bus 32 are respectively electrically connected to three adjacent columns of sub-pixels PX. For example, the three data sub-lines 31 electrically connected to the same data bus 32 are respectively electrically connected to the three columns of sub-pixels PX contained in a column of pixel unit P. In this case, the three columns of sub-pixels PX electrically connected to the same data bus 32 are configured to emit light of different colors. In the same row of sub-pixels PX, two adjacent sub-pixels PX are electrically connected to different scan signal lines 24. In this way, the number of adjacent sub-pixels PX electrically connected to the same scan signal line 24 can be further reduced, greatly reducing the risk of the human eye observing vertical lines.

[0156] For example, as shown in FIG19, multiple sub-pixels PX in each column are electrically connected to a scan signal line 24 in the same position in multiple signal line groups 20. For example, in Figure 19, the sub-pixels PX in columns 1, 4, 7, 10, 13, and 16 from left to right are all electrically connected to the third scan signal line 23 of the first signal line group 201 (the signal line group 20 located above the sub-pixel PX); the sub-pixels PX in columns 2, 5, 8, 11, 14, and 17 from left to right are all electrically connected to the first scan signal line 21 of the second signal line group 202 (the signal line group 20 located below the sub-pixel PX); and the sub-pixels PX in columns 3, 6, 9, 12, 15, and 18 from left to right are all electrically connected to the second scan signal line 22 of the second signal line group 202 (the signal line group 20 located below the sub-pixel PX).

[0157] When the data bus 32 is electrically connected to the data sub-line 31 as shown in FIG. 19, adjacent data buses 32 are configured to transmit data signals of opposite polarity within a frame. This can greatly reduce the phenomenon of polarity concentration in the pixel electrodes 40, which is beneficial to improving the display effect of the display panel. In addition, for the same data bus 32, the data signals transmitted in two adjacent frames can be configured to have opposite polarities. In this way, the data signals of the same column of sub-pixels PX have opposite polarities in two adjacent frames, which is beneficial to improving the display effect of the display panel.

[0158] Referring to Figures 20 and 21, the pixel unit P may further include three sub-pixels PX arranged adjacently along the second direction Y. The three sub-pixels PX of the pixel unit P may include a first sub-pixel PX1 for emitting red light, a second sub-pixel PX2 for emitting green light, and a third sub-pixel PX3 for emitting blue light. Sub-pixels PX in the same row are configured to emit light of the same color. That is, the pixel unit P is arranged along the extension direction of the data sub-line 31. In this way, the connection method between the signal line group 20 and the sub-pixel P can be called a 9-gate architecture, that is, one row of pixel unit P can be electrically connected to 9 scan signal lines 24. This helps to further reduce the number of data buses 32, thereby reducing the number of data signal channels of the source driver chip, achieving the goal of reducing the number of source driver chips and manufacturing costs.

[0159] For example, taking a 3-row × 18-column pixel unit (108 sub-pixels PX) as an example, with the 3-gate architecture shown in Figures 13-19, three signal line groups 20 are required, totaling 9 scan signal lines 24, and 18 data sub-lines. With the 9-gate architecture shown in Figure 20, nine signal line groups 20 are required, totaling 27 scan signal lines 24, and 6 data buses 32. This significantly reduces the number of data buses 32, thereby reducing the number of data signal channels in the source driver chip and lowering the manufacturing cost of the display panel.

[0160] As shown in Figures 20 and 21, a column of sub-pixels PX is electrically connected to a scan signal line 24 located at the same position in multiple signal line groups 20. For example, as shown in Figure 20, along the left-to-right direction, sub-pixels PX in any row of columns 1 to 6 are electrically connected to the third scan signal line 23 of the first signal line group 201 (the signal line group 20 located above the sub-pixel PX); sub-pixels PX in any row of columns 7 to 12 are electrically connected to the first scan signal line 21 of the second signal line group 202 (the signal line group 20 located above the sub-pixel PX); and sub-pixels PX in any row of columns 13 to 18 are electrically connected to the second scan signal line 22 of the second signal line group 202. Alternatively, as exemplarily shown in FIG21, along the left-to-right direction, the different row sub-pixels PX of columns 1, 2, 11, 12, 15, and 16 are all electrically connected to the third scan signal line 23 of the first signal line group 201; the different row sub-pixels PX of columns 3, 4, 7, 8, 17, and 18 are all electrically connected to the first scan signal line 21 of the second signal line group 202; and the different row sub-pixels PX of columns 5, 6, 9, 10, 13, and 14 are all electrically connected to the second scan signal line 22 of the second signal line group 202.

[0161] In some embodiments, two or six adjacent sub-pixels PX along the first direction X form a group, and a group of sub-pixels PX is electrically connected to the same scan signal line 24. Within the same row of sub-pixels PX, two adjacent groups of sub-pixels PX along the first direction X are electrically connected to different scan signal lines 24.

[0162] For example, as shown in FIG20, six adjacent sub-pixels PX along the first direction X form a group, and a group of sub-pixels PX is electrically connected to the same scan signal line 24; in the same row of sub-pixels PX, two adjacent groups of sub-pixels PX along the first direction X are electrically connected to different scan signal lines 24.

[0163] For example, as shown in FIG21, two adjacent sub-pixels PX along the first direction X form a group, and a group of sub-pixels PX is electrically connected to the same scan signal line 24; in the same row of sub-pixels PX, two adjacent groups of sub-pixels PX along the first direction X are electrically connected to different scan signal lines 24.

[0164] Referring again to Figures 20 and 21, in some embodiments, six adjacent data buses 32, and 18 adjacent data sub-lines 31 electrically connected to the aforementioned six adjacent data buses 32, constitute a minimum repetition period for the arrangement of the data sub-lines 31 and data buses 32. Within the same minimum repetition period, five data sub-lines 31 are included between two adjacent data sub-lines 31 electrically connected to the same data bus 32, and two adjacent data buses 32 are configured to transmit data signals of opposite polarity within one frame. Thus, within the same frame, the data signals of two adjacent columns of sub-pixels PX have opposite polarities. For the same data bus 32, it can be configured to transmit data signals of opposite polarities within two adjacent frames. This ensures that the data signals of the same column of sub-pixels PX have opposite polarities within two adjacent frames, which is beneficial for improving the display effect of the display panel.

[0165] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. An array substrate having a display area and a fan-out area adjacent to the display area, the array substrate comprising a substrate, and: Multiple pixel units are disposed within the display area, each pixel unit including multiple sub-pixels, the multiple sub-pixels of the multiple pixel units are arranged in an array, and are arranged in rows along a first direction and in columns along a second direction; the first direction and the second direction intersect. Multiple signal line groups, each signal line group comprising M scan signal lines spaced apart along the second direction, wherein, M is a natural number greater than 2; Multiple data sub-lines are arranged at intervals along the first direction, pass through the display area along the second direction, and extend to the fan-out area; one of the data sub-lines is electrically connected to a column of the sub-pixels; Multiple data buses are provided in the fan-out area, and one data bus is electrically connected to N data sub-lines, where N is a natural number greater than 2; Among them, there is a signal line group between two adjacent rows of sub-pixels, one sub-pixel is electrically connected to one scan signal line, one row of sub-pixels is electrically connected to M scan signal lines, and three sub-pixels in one row that are electrically connected to the same data bus are electrically connected to different scan signal lines respectively.

2. The array substrate according to claim 1, wherein, M is an odd number, and the values ​​of M and N may be equal or unequal.

3. The array substrate according to claim 2, wherein, The values ​​of M and N are both multiples of 3.

4. The array substrate according to any one of claims 1 to 3, further comprising: Multiple touch lines are arranged at intervals along the first direction; The sub-pixel includes a pixel electrode. The orthographic projection of the touch trace on the substrate coincides with the orthographic projection of the pixel electrode on the substrate. The portion of the touch trace that coincides with the pixel electrode is located at the middle of the pixel electrode along the first direction.

5. The array substrate according to any one of claims 1 to 3, further comprising: Multiple touch lines are arranged at intervals along the first direction; The sub-pixel includes a pixel electrode, the touch trace is disposed adjacent to the data sub-line, and the orthographic projection of the touch trace on the substrate does not coincide with the orthographic projection of the pixel electrode on the substrate.

6. The array substrate according to claim 4 or 5, wherein, Three data sub-lines are included between two adjacent touch traces along the first direction, and each pair of adjacent touch traces forms a group, with the two touch traces in a group configured to transmit the same drive signal.

7. The array substrate according to claim 4 or 5, wherein, The two adjacent touch traces along the first direction include six data sub-lines, and the two adjacent touch traces are electrically insulated from each other.

8. The array substrate according to any one of claims 1 to 7, wherein, The pixel unit includes three sub-pixels arranged adjacent to each other along the first direction, and the three sub-pixels of the pixel unit are respectively configured to emit red, green and blue light; The sub-pixels in the same column are configured to emit light of the same color.

9. The array substrate according to claim 8, wherein, The sub-pixel further includes a thin-film transistor and a pixel electrode. The gate of the thin-film transistor is electrically connected to the scan signal line, and one of its source and drain is electrically connected to the data sub-line, while the other is electrically connected to the pixel electrode. A row of sub-pixels is electrically connected to three scan signal lines of the same signal line group; a row of sub-pixels electrically connected to the signal line group is a target row sub-pixel, and along the direction away from the target row sub-pixel, the three scan signal lines of the signal line group are, in order, a first scan signal line, a second scan signal line, and a third scan signal line; The thin-film transistor of the sub-pixel electrically connected to the first scan signal line is located on the side of the first scan signal line closer to the target row sub-pixel; The thin-film transistor of the sub-pixel electrically connected to the second scan signal line is located between the first scan signal line and the second scan signal line; The thin-film transistor of the sub-pixel, which is electrically connected to the third scan signal line, is located between the second scan signal line and the third scan signal line.

10. The array substrate according to claim 9, wherein, The first scan signal line includes a first groove formed by bending in a direction away from the target row sub-pixel, and a thin-film transistor electrically connected to the first scan signal line is located in the first groove; The second scan signal line includes a second groove formed by bending in a direction away from the target row sub-pixel, and the thin film transistor electrically connected to the second scan signal line and the first groove are both located in the second groove; The third scan signal line extends along the first direction, and the thin-film transistor electrically connected to the third scan signal line is offset from the second groove and located between the second scan signal line and the third scan signal line.

11. The array substrate according to claim 10, wherein, The first scan signal line includes a first extension segment and a second extension segment that are alternately connected along the first direction; The first extension includes a first sub-part extending along the first direction, and two second sub-parts respectively connected to both ends of the first sub-part. The second sub-parts extend along the second direction, and the end of the second sub-part away from the first sub-part is connected to the second extension; the first extension forms the first groove. The second extension segment is farther away from the target row sub-pixel along the second direction compared to the first sub-part.

12. The array substrate according to claim 11, wherein, The second scan signal line includes a third extension segment and a fourth extension segment that are alternately connected along the first direction; The third extension includes a third sub-part extending along the first direction, and two fourth sub-parts respectively connected to both ends of the third sub-part. The fourth sub-parts extend along the second direction, and one end of the fourth sub-parts away from the third sub-part is connected to the fourth extension; the third extension forms the second groove. The fourth extension segment is farther away from the target row sub-pixel along the second direction compared to the third sub-part.

13. The array substrate according to claim 12, wherein, Along the second direction, a portion of the third sub-part is disposed opposite to the first sub-part, and a portion is disposed opposite to the second extension segment; the interval between the third sub-part and the first sub-part is smaller than the interval between the third sub-part and the second extension segment. The thin-film transistor electrically connected to the second scan signal line is located between the third sub-section and the second extension.

14. The array substrate according to claim 12 or 13, wherein, The interval between the third scan signal line and the third sub-section is smaller than the interval between the third scan signal line and the fourth extension segment; The thin-film transistor electrically connected to the third scan signal line is located between the third scan signal line and the fourth extension.

15. The array substrate according to claim 14, wherein, The orthographic projection of the pixel electrode of the sub-pixel electrically connected to the second scan signal line onto the substrate at least partially overlaps with the orthographic projection of the first scan signal line onto the substrate; The orthographic projection of the pixel electrode of the sub-pixel electrically connected to the third scan signal line onto the substrate at least partially coincides with the orthographic projections of the first scan signal line and the second scan signal line onto the substrate.

16. The array substrate according to claim 8, wherein, Each row of sub-pixels is electrically connected to three scan signal lines belonging to two of the signal line groups, respectively.

17. The array substrate according to claim 16, wherein, Along the scanning direction of the plurality of scanning signal lines, the three scanning signal lines of the signal line group are, in sequence, a first scanning signal line, a second scanning signal line, and a third scanning signal line; In the two signal line groups located on both sides of the sub-pixel in a row along the second direction, the one that transmits the scan signal first is the first signal line group, and the other is the second signal line group; The sub-pixel in one row is electrically connected to the third scan signal line of the first signal line group and the first scan signal line and the second scan signal line of the second signal line group.

18. The array substrate according to any one of claims 8 to 17, wherein, Two adjacent pixel units along the first direction form a group, and a group of pixel units is electrically connected to the same scan signal line; Two adjacent groups of pixel units along the first direction are electrically connected to different scan signal lines, and two adjacent pixel units electrically connected to the same scan signal line include two groups of pixel units.

19. The array substrate according to any one of claims 8 to 17, wherein, The three sub-pixels of one pixel unit are electrically connected to the same scan signal line; In the same row of sub-pixels, two adjacent pixel units are electrically connected to different scan signal lines, and two adjacent pixel units electrically connected to the same scan signal line include two pixel units between them. Each of the sub-pixels is electrically connected to a scan signal line at the same position in one of the multiple signal line groups.

20. The array substrate according to any one of claims 8 to 17, wherein, Two adjacent pixel units along the first direction form a group, and the sub-pixels of a group of pixel units are electrically connected to the same scan signal line; Within the sub-pixels in the same row, two adjacent groups of pixel units are electrically connected to different scan signal lines; The connection order of the three groups of pixel units, which belong to two adjacent rows and are electrically connected to the six adjacent data buses, is reversed with that of the three scan signal lines.

21. The array substrate according to any one of claims 8 to 17, wherein, Two adjacent sub-pixels along the first direction form a group, and a group of sub-pixels is electrically connected to the same scan signal line; In the same row of sub-pixels, two adjacent groups of sub-pixels are electrically connected to different scan signal lines, and the interval between two adjacent pixel units electrically connected to different scan signal lines is not equal; Each of the sub-pixels is electrically connected to a scan signal line at the same position in one of the multiple signal line groups.

22. The array substrate according to claim 21, wherein, Eighteen data sub-lines, which are electrically connected to and adjacent to the six adjacent data buses, are numbered sequentially along the first direction. The data sub-lines described in Articles 1, 4, and 10 are electrically connected to one of the data buses; The data sub-lines described in Articles 2, 5, and 8 are electrically connected to one of the data buses; The data sub-lines described in Articles 3, 6, and 12 are electrically connected to one of the data buses; The data sub-lines described in Articles 7, 13, and 16 are electrically connected to one of the data buses; The data sub-lines described in Articles 9, 15, and 18 are electrically connected to one of the data buses; The data sub-lines described in Articles 11, 14 and 17 are electrically connected to one of the data buses.

23. The array substrate according to claim 22, wherein, The three data buses electrically connected to the data sub-lines described in Clauses 1, 3, and 11 are configured to transmit data signals of the same polarity within a frame; The three data buses electrically connected to the data sub-lines described in Articles 2, 7, and 9 are configured to transmit data signals of the same polarity within a frame; The data bus electrically connected to the first data sub-line and the data bus electrically connected to the second data sub-line are configured to transmit data signals of opposite polarity within a frame.

24. The array substrate according to any one of claims 18 to 21, wherein, Five data sub-lines are included between two adjacent data sub-lines electrically connected to the same data bus, and the two adjacent data buses are configured to transmit data signals of opposite polarity within a frame.

25. The array substrate according to any one of claims 8 to 17, wherein, The three sub-pixels of a pixel unit are electrically connected to the same scan signal line, and in the same row of sub-pixels, two adjacent pixel units are electrically connected to different scan signal lines; The three scan signal lines electrically connected to the sub-pixels in the same row are the fourth scan signal line, the fifth scan signal line, and the sixth scan signal line, respectively. The two adjacent pixel units electrically connected to the fourth scan signal line include three pixel units, the two adjacent pixel units electrically connected to the fifth scan signal line include two pixel units, and the two adjacent pixel units electrically connected to the sixth scan signal line include one pixel unit.

26. The array substrate according to claim 25, wherein, Two adjacent data sub-lines electrically connected to the same data bus include two data sub-lines.

27. The array substrate according to claim 26, wherein, Three data buses that are electrically connected to and arranged adjacent to the nine adjacent data sub-lines form a group. The three data buses in a group are configured to transmit data signals of the same polarity within a frame, and two adjacent groups of data buses are configured to transmit data signals of opposite polarity within a frame.

28. The array substrate according to any one of claims 18 to 27, wherein, The three columns of sub-pixels, electrically connected to the same data bus, are configured to emit light of the same color.

29. The array substrate according to any one of claims 8 to 17, wherein, The three data sub-lines electrically connected to the same data bus are respectively electrically connected to the three adjacent columns of sub-pixels; Within the same row of sub-pixels, two adjacent sub-pixels are electrically connected to different scan signal lines; Each of the sub-pixels is electrically connected to a scan signal line at the same position in one of the multiple signal line groups.

30. The array substrate according to any one of claims 18 to 26 and 29, wherein, The adjacent data buses are configured to transmit data signals of opposite polarity within a frame.

31. The array substrate according to any one of claims 1 to 7, wherein, The pixel unit includes three sub-pixels arranged adjacent to each other along the second direction, and the three sub-pixels of the pixel unit are respectively configured to emit red, green and blue light; The subpixels in the same row are configured to emit light of the same color.

32. The array substrate according to claim 31, wherein, Two or six adjacent sub-pixels along the first direction form a group, and a group of sub-pixels is electrically connected to the same scan signal line; In the same row of sub-pixels, two adjacent groups of sub-pixels along the first direction are electrically connected to different scan signal lines; a column of sub-pixels is electrically connected to a scan signal line in the same position among multiple signal line groups.

33. The array substrate according to claim 32, wherein, Five data sub-lines are included between two adjacent data sub-lines electrically connected to the same data bus; The two adjacent data buses are configured to transmit data signals of opposite polarity within a frame.

34. A display device, comprising: The array substrate as described in any one of claims 1 to 33; A color filter substrate is disposed opposite to the array substrate; A liquid crystal layer is disposed between the array substrate and the color filter substrate.

Images