Vector cryptographic processing

Abstract

Apparatuses, methods, and computer program products are disclosed. Decoded instructions control execution of data processing, and a plurality of vector registers store data vectors, each data vector comprising a plurality of data elements. A vector cryptographic processing instruction specifies a destination vector register, a source vector register, a cryptographic key vector register, and a key index value. The instruction controls execution of a set of operations comprising: reading an array of data values from the source vector register and reading a cryptographic key from a sub-portion of the cryptographic key vector register indicated by the key index value; using the cryptographic key to perform cryptographic processing on the array of data values to generate a transformed array of data values; and writing the transformed array of data values to the destination vector register.

Description

[0001] This disclosure relates to data processing. Specifically, this disclosure relates to vector cryptography processing.

[0002] The data processing apparatus can be configured to perform data processing on data stored in various data formats. For example, a single data value stored in a scalar register (i.e., an individual data value) can be the object of data processing, or a group of data values ​​stored in a vector register (i.e., multiple data values) can be the object of data processing. Data processing may include cryptographic operations.

[0003] In one example implementation described herein, there is an apparatus comprising:

[0004] A processing circuit that performs data processing;

[0005] An instruction decoding circuit is used to decode instructions to control the processing circuit to perform the data processing; and

[0006] Multiple vector registers are used to store data vectors, each data vector comprising multiple data elements.

[0007] The instruction decoding circuit responds to vector cryptography processing instructions specifying the destination vector register, source vector register, cryptographic key vector register, and key index value to control the processing circuit to perform a set of operations, which include:

[0008] Read an array of data values ​​from the source vector register, and read the cryptographic key from the sub-part of the cryptographic key vector register indicated by the key index value;

[0009] Use the cryptographic key to perform cryptographic processing on the array of data values ​​to generate a transformed array of data values; and

[0010] Write the transformed array of data values ​​into the destination vector register.

[0011] In one example implementation described herein, there is a method that includes:

[0012] The control processing circuit performs data processing;

[0013] Decode the instruction to control the processing circuit to perform the data processing; and

[0014] The data vectors are stored in multiple vector registers, and each data vector includes multiple data elements.

[0015] Decoding the instructions includes controlling the processing circuit to perform a set of operations in response to decoding vector cryptography processing instructions specifying the destination vector register, source vector register, cryptographic key vector register, and key index value. These operations include:

[0016] Read an array of data values ​​from the source vector register, and read the cryptographic key from the sub-part of the cryptographic key vector register indicated by the key index value;

[0017] Use the cryptographic key to perform cryptographic processing on the array of data values ​​to generate a transformed array of data values; and

[0018] Write the transformed array of data values ​​into the destination vector register.

[0019] In one example embodiment described herein, there is a computer program for controlling a host data processing device to provide an instruction execution environment, the computer program comprising:

[0020] The processing logic is configured to perform data processing;

[0021] Instruction decoding program logic, configured to decode instructions to control the processing program logic to perform the data processing; and

[0022] Multiple vector data structures are used to store data vectors, each data vector consisting of multiple data elements.

[0023] The instruction decoding program logic responds to vector cryptography processing instructions specifying the destination vector data structure, source vector data structure, cryptographic key vector data structure, and key index value to control the processing program logic to perform a set of operations, which include:

[0024] Read an array of data values ​​from the source vector data structure, and read the cryptographic key from the sub-section of the cryptographic key vector data structure indicated by the key index value;

[0025] Use the cryptographic key to perform cryptographic processing on the array of data values ​​to generate a transformed array of data values; and

[0026] Write the transformed array of data values ​​into the destination vector data structure.

[0027] The present invention will be further described by way of example only, with reference to embodiments of the invention illustrated in the accompanying drawings, wherein:

[0028] Figure 1 The apparatus embodying the present technology is illustrated schematically according to some examples;

[0029] Figure 2 The execution of vector cryptographic processing instructions is illustrated schematically according to some examples;

[0030] Figure 3 The execution of vector cryptographic processing instructions is illustrated schematically based on some examples;

[0031] Figure 4A and Figure 4B The illustrations illustrate the use of different round keys for each round of a vector cryptographic processing algorithm, based on some examples;

[0032] Figure 5A , Figure 5B and Figure 5C Different segment lengths within a given vector length are illustrated schematically, based on some examples;

[0033] Figure 6A The parallel processing of two segments is illustrated schematically according to some examples;

[0034] Figure 6B The illustration demonstrates the parallel processing of multiple arrays based on some example data values;

[0035] Figure 7 This is a flowchart illustrating a sequence of steps performed when executing vector cryptographic processing instructions, based on some examples; and

[0036] Figure 8 The simulator implementation is illustrated schematically based on some examples.

[0037] Before discussing the implementation scheme with reference to the accompanying drawings, the following description of the implementation scheme is provided.

[0038] According to an example configuration, an apparatus is provided that includes:

[0039] A processing circuit that performs data processing;

[0040] An instruction decoding circuit is used to decode instructions to control the processing circuit to perform data processing; and

[0041] Multiple vector registers are used to store data vectors, each data vector comprising multiple data elements.

[0042] The instruction decoding circuit responds to vector cryptography processing instructions specifying the destination vector register, source vector register, cryptographic key vector register, and key index value to control the processing circuit to perform a set of operations, which include:

[0043] Read an array of data values ​​from the source vector register and read the cryptographic key from the sub-part of the cryptographic key vector register indicated by the key index value;

[0044] Use a cryptographic key to perform cryptographic processing on an array of data values ​​to generate a transformed array of data values; and

[0045] Write the transformed array of data values ​​into the destination vector register.

[0046] In data processing apparatuses performing vector cryptographic processing, multiple different cryptographic keys are typically required for processing. For example, the cryptographic algorithm being implemented may have round functions that iterate multiple times within the algorithm, with a different round key used in each iteration. A set of round keys (sometimes called a set of subkeys) used for these rounds can be pre-derived from the master cryptographic key depending on the specific cryptographic algorithm being implemented. The storage requirements for a set of subkeys are not insignificant, especially when these subkeys will be stored in registers local to the processing circuitry performing the data processing operations. For example, the specification for the Advanced Encryption Standard (AES) for encryption / decryption requires 11, 13, or 15 round keys, depending on the key size, which is 128 bits, 192 bits, or 256 bits. Therefore, for data processing apparatuses implementing such cryptographic algorithms, there is a considerable demand for available registers, not only to store these round keys but also to store the data blocks being encrypted / decrypted, the resulting values, and other auxiliary values. One possible approach to this problem is to limit the number of rounds in the cryptographic algorithm (i.e., where multiple rounds are executed per clock cycle). Another possible approach is to load each round key immediately before using it. However, the former method does not fully utilize devices capable of performing independent operations / instructions in parallel, and the latter method introduces loading latency.

[0047] In this context, the present technology provides a vector register-based method in which a cryptographic key vector register stores multiple keys, and a specific key is selected from a sub-part of the cryptographic key vector register indicated by a key index value (as required by the current stage of cryptographic processing). A dedicated vector cryptographic processing instruction is provided, specifying a destination vector register, a source vector register, a cryptographic key vector register, and a key index value. The processing circuitry of the device is then controlled to perform a set of operations, wherein an array of data values ​​is read from the source vector register, and a cryptographic key is read from the sub-part of the cryptographic key vector register indicated by the key index value. Cryptographic processing is then performed on the array of data values ​​using the cryptographic key to generate a transformed array of data values, which is written to the destination vector register. Thus, multiple cryptographic keys are stored in the cryptographic key vector register and selected sequentially as needed by the key index value. The key index value can be specified by the vector cryptographic processing instruction in various ways, but in some examples, the key index value is an immediate value provided by the vector cryptographic processing instruction.

[0048] Multiple cryptographic keys stored in a cryptographic key vector register, from which the current cryptographic key is selected by a key index value, can be provided in a range of contexts and used in various ways. However, in some examples, the cryptographic processing is at least part of the processing of one round of an iterative cryptographic algorithm, and the cryptographic key is a round key generated for one round of the iterative cryptographic algorithm. Therefore, in some examples, the cryptographic key vector register holds multiple cryptographic keys in multiple sub-parts, and each of the multiple sub-parts holds a different round key for a different round of the iterative cryptographic algorithm.

[0049] This technique is not limited to any specific length of the vector register (i.e., the length of the set of data values ​​stored in the vector register). Therefore, the methods disclosed herein can be applied to vector registers of various lengths. However, within a vector register of a given length, in some examples, the processing circuitry is configured to process the source vector register as a set of segments, wherein the instruction decoding circuitry is configured to control the processing circuitry to read an array of data values ​​from that segment of the source vector register for each segment, and to read the cryptographic key from a sub-part of the corresponding segment of the cryptographic key vector register. This supports a method independent of vector length, whereby the key index value indicates a sub-part of a segment in the cryptographic key vector register, and therefore, the vector length is irrelevant and can, for example, be the same as or greater than the segment length when using the key index value to indicate a sub-part of a segment.

[0050] Processing vectors in a segmented manner also has the following consequences: the segments are largely independent of each other (except that they are typically loaded and stored together), and this provides additional opportunities to enhance the processing efficiency of the device. In some examples, the processing circuitry is configured to process a set of segments in parallel. Furthermore, processing vectors in a segmented manner limits the width of the portion of the vector that a given key needs to be routed across, thus avoiding overly complex wiring requirements when the key needs to be passed from one side of a wide vector to the other.

[0051] Similarly, in some examples, the bit length of each segment in a set of segments is greater than the bit length of the array of data values, such that the segments comprise multiple arrays, and the processing circuitry is configured to process multiple arrays in parallel. This further supports efficient execution of the device.

[0052] In some examples, the sub-part of the cryptographic key vector register from which the cryptographic key is read is a sub-part of a segment within a set of segments.

[0053] In some examples, a set of cryptographic keys stored in the corresponding sub-sections of a segment of the cryptographic key vector register is repeated across all segments of the cryptographic key vector register. This further supports parallel processing of multiple arrays, thus allowing, for example, in a given round of an encryption algorithm, the same round key used for that round to be applied to multiple arrays of data values ​​from the corresponding segments.

[0054] In some examples, the destination vector register is the same vector register as the source vector register, and writing the transformed array of data values ​​to the destination vector register destructively overwrites the source vector register. This allows for efficient use of the device's registers when executing iterative cryptographic algorithms, since each round of the iterative cryptographic algorithm does not require a usable destination vector register to write the results of that round.

[0055] In some examples, the vector cryptographic processing instructions are encryption vector processing instructions, the cryptographic key is an encryption key, and the cryptographic processing performed on the array of data values ​​is an encryption operation. In other examples, the vector cryptographic processing instructions are decryption vector processing instructions, the cryptographic key is a decryption key, and the cryptographic processing performed on the array of data values ​​is a decryption operation.

[0056] In some examples, the cryptographic processing performed on arrays of data values ​​also includes column mixing operations. For instance, according to the specification of the Advanced Encryption Standard (AES) for encryption / decryption, column mixing operations form part of a processing wheel. Therefore, in some examples, vector cryptographic processing instructions may be arranged to perform some or all of the operations required to implement a processing wheel when performing cryptographic processing.

[0057] Therefore, in some examples, the cryptographic processing performed on arrays of data values ​​is based on the Advanced Encryption Standard (AES).

[0058] In some examples, the cryptographic processing performed on an array of data values ​​is part of an encryption algorithm that includes authentication. For instance, the AES algorithm can be extended to implement AES Galois Counter Mode (AES-GCM).

[0059] In some examples, vector cryptography processing instructions specify a set of destination vector registers and a set of source vector registers, and one set of operations is performed on each source vector in the set of source vector registers, including writing a corresponding transformed array of data values ​​to the corresponding destination vector register. Therefore, the execution of the device's cryptographic processing is enhanced while maintaining high code density, i.e., instead of requiring multiple vector cryptography processing instructions to perform multiple sets of cryptographic operations, all these operations are initiated by a single vector cryptography processing instruction.

[0060] In some examples, the vector cryptography processing instruction specifies a first destination vector register in a set of destination vector registers, while the other destination vector registers in the set are implicit. This further supports high code density because only the first destination vector register needs to be explicitly specified in the vector cryptography processing instruction. Similarly, in some examples, the vector cryptography processing instruction specifies a first source vector register in a set of source vector registers, while the other source vector registers in the set are implicit.

[0061] Based on an example configuration, a method is provided that includes:

[0062] The control processing circuit performs data processing;

[0063] Decode the instructions to control the processing circuitry to perform data processing; and

[0064] The data vectors are stored in multiple vector registers, and each data vector includes multiple data elements.

[0065] Decoding the instructions includes controlling the processing circuitry to perform a set of operations in response to decoding vector cryptography processing instructions specifying the destination vector register, source vector register, cryptographic key vector register, and key index value. These operations include:

[0066] Read an array of data values ​​from the source vector register and read the cryptographic key from the sub-part of the cryptographic key vector register indicated by the key index value;

[0067] Use a cryptographic key to perform cryptographic processing on an array of data values ​​to generate a transformed array of data values; and

[0068] Write the transformed array of data values ​​into the destination vector register.

[0069] According to an example configuration, a computer program is provided for controlling a host data processing device to provide an instruction execution environment, the computer program comprising:

[0070] The processing logic is configured to perform data processing;

[0071] Instruction decoding program logic, configured to decode instructions to control the processing program logic to perform data processing; and

[0072] Multiple vector data structures are used to store data vectors, each data vector consisting of multiple data elements.

[0073] The instruction decoding program logic responds to vector cryptography processing instructions specifying the destination vector data structure, source vector data structure, cryptographic key vector data structure, and key index value to control the processing program logic to execute a set of operations, which include:

[0074] Read an array of data values ​​from the source vector data structure, and read the cryptographic key from the sub-section of the cryptographic key vector data structure indicated by the key index value;

[0075] Use a cryptographic key to perform cryptographic processing on an array of data values ​​to generate a transformed array of data values; and

[0076] Write the transformed array of data values ​​into the destination vector data structure.

[0077] Specific implementation schemes will now be described with reference to the accompanying drawings.

[0078] Figure 1 An example of a data processing apparatus 100 according to one embodiment is illustrated. Apparatus 100 has a pipeline structure, which in... Figure 1The diagram illustrates a high-level hierarchy through a linking sequence of instruction fetch circuit 101, decoding circuit 102, transmit circuit 103, and processing circuit 104. Instructions fetched from the memory system by the action of instruction fetch circuit 101 are decoded by decoding circuit 102 to generate control signals for the entire pipeline structure, and particularly for processing circuit 104. Processing circuit 104 includes different execution units provided to perform different types of data processing tasks, illustrated in the diagram by cryptographic unit 105, ALUs 106 and 107, and floating-point (FP) unit 108. The apparatus also includes a load / store unit 109 that executes load instructions and store instructions to bring data values ​​from the memory system into registers local to processing circuit 104 and store data values ​​from registers into the memory system, respectively. A set of vector registers 110 is explicitly shown in the diagram. Processing circuit 104 also accesses a set of scalar registers not shown in the diagram. The storage system is represented in the accompanying drawings by an instruction cache (L1$) 111, a L1 cache (L1$) 112, a L2 cache (L2$) 113, and a memory 114. Data values ​​retrieved from memory 114 are loaded into registers (e.g., vector register 110) of the processing circuitry 109 for data processing operations, and modified data values ​​are stored in memory 114. Temporary copies of reused data values ​​may be stored in caches 111, 112, and 113 to mitigate the latency associated with retrieving data values ​​from memory 114. One particular type of instruction processed by device 100 is a vector cryptographic processing instruction, executed by cryptographic unit 105, which accesses a vector of data values ​​stored in vector register 110. Further details of these instructions are given with reference to the following drawings, which are the subject of this disclosure.

[0079] Figure 2 The execution of vector cryptography processing instructions according to some examples is illustrated schematically. Vector cryptography processing instruction 200 has the following format: Command [Destination], [Source], [Key], [Index] Wherein, [Destination], [Source], and [Key] specify the destination vector register, source vector register, and cryptographic key vector register, respectively. Additionally, [Index] may specify the register storing the key index value, but in many examples, [Index] is an immediate value specified in the instruction encoding. Executing the vector cryptography processing instruction causes an array 202 of data values ​​to be read from the source vector register 201. The array 202 of data values ​​is typically retrieved from the source vector register 201 as a contiguous set of data values ​​(e.g., bytes), where the illustrated 4x4 array format is implicit. Executing the vector cryptography processing instruction also causes the cryptographic key vector register 203 to be accessed, from which the cryptographic key (K1 in the illustrated example) is selected from a sub-part of the vector register, where this sub-part is indicated by the key index value [Index]. The cryptographic key is then used to perform a cryptographic operation 204 on the array 202 of data values ​​to generate a transformed array 205 of data values. The transformed array 205 of data values ​​is written to the destination vector register 206. Note that although the source vector register 201 and the destination vector register 206 are in... Figure 2 While these vector registers are illustrated as distinct from each other, in some examples, they can be the same vector register, such that writing the transformed array 205 of data values ​​to the (source / destination) vector register destructively overwrites the original array 202 of data values ​​therein. In such cases, [destination] and [source] are the same in the instruction encoding, or alternatively, the encoding of the instruction that only allows this loop operation can also be provided as: instruction [source / destination], [key], [index]. Vector cryptography processing instructions can also specify a set of destination vector registers and a set of source vector registers, such that cryptographic operations are performed against each source vector in the set of source vector registers, and the corresponding transformed array of data values ​​is written to the corresponding destination vector register. In such cases, vector cryptography processing instructions can have the following form: Instructions [a set of destination registers], [a set of source registers], [key], [index]

[0080] However, it is not necessary to explicitly specify either or both of a set of destination registers and a set of source registers. For example, the apparatus may be configured to perform cryptographic operations on a predetermined number of vectors obtained from a predetermined number of source registers, and the results may be written to a predetermined number of destination registers. In such cases, vector cryptographic processing instructions may specify only the first source vector register and / or destination vector register, and the other source vector registers and / or destination vector registers are implicit. In such cases, vector cryptographic processing instructions may have the following form: Instructions [First Destination Register], [First Source Register], [Key], [Index]

[0081] Figure 3The illustration schematically demonstrates the execution of vector cryptographic processing instructions based on some examples, which is consistent with... Figure 2 Similar to the example shown. Vector cryptography processing instruction 300 has the same format: instruction[destination], [source], [key], [index]. Executing the vector cryptography processing instruction causes an array 302 of data values ​​to be read from the source vector register 301; however, in this example, the source vector register 301 is processed as a group of four segments. In the example shown, the array 302 of data values ​​is read from the leftmost segment of the source vector register 301. Figure 2 In this case, executing the vector cryptography processing instruction also accesses the cryptographic key vector register 303, from which a cryptographic key (K1 in the illustrated example) is selected from a sub-part of the vector register, indicated by the key index value [index]. Then, the cryptographic key is used to perform cryptographic operation 304 on the array of data values ​​302 to generate a transformed array of data values ​​305, which is written to the corresponding segment of the destination vector register 206. (As in...) Figure 2 In this case, the source vector register 301 and the destination vector register 306 can be the same vector register. Processing the source vector register and the destination vector register in a segmented manner means, on the one hand, that segments of a predetermined length can be used regardless of the vector length (i.e., configured to be "vector length independent"), and on the other hand, that segments can be processed in parallel if supported, thereby increasing the throughput of the device.

[0082] Figure 4A and Figure 4B The illustrations schematically demonstrate the use of different round keys for each round of a vector cryptographic processing algorithm, based on several examples. Selecting a cryptographic key from the sub-section of the cryptographic key vector register, indicated by the key index value, supports various configurations for using cryptographic keys. However, in cases such as... Figure 4A and Figure 4B In some of the examples shown, multiple keys stored in multiple sub-parts of the cryptographic key vector register correspond to different round keys used in each round of the vector cryptography processing algorithm. Therefore, Figure 4A and Figure 4B The diagram shows four round keys RK0 to RK3 stored in the cryptographic key vector register 400. In round 0 of the algorithm, round key RK0 is selected and used in the cryptographic operations performed on the four separate arrays A0 to A3 of data values ​​obtained from the source vector register 401. Subsequently, in round 1 of the algorithm, round key RK1 is selected and used in the cryptographic operations performed on the four separate arrays A0 to A3 of data values ​​obtained from the source vector register 401.

[0083] Figure 5A , Figure 5Band Figure 5C The diagram illustrates different segment lengths within a given vector length, based on some examples. Figure 5A In the example, the segment length is half the vector length. Therefore, two segments within the vector length are processed independently of each other. Furthermore, in this example, the segment length is four times the key length. Only matching is given. Figure 5A A set of example bit sizes is configured such that, for a 128-bit key, the segment length is 512 bits, and the vector length is 1024 bits. The arrays of data values ​​obtained from source vector register 501 are also each 128 bits (16 bytes). Therefore, the index is a 2-bit value, allowing selection of one of four keys within a segment of the cryptographic key register 500. Figure 5B In the example, the segment length is the same as the vector length. Furthermore, in this example, the segment length is twice the key length. Only matching is given. Figure 5A A set of example bit sizes is configured such that, for a 128-bit key, the segment length and vector length are both 256 bits. The arrays of data values ​​obtained from the source vector register 503 are also each 128 bits (16 bytes). Therefore, the index is a 1-bit value, allowing selection of one of two keys within a segment of the cryptographic key register 502. Figure 5C In the example, the segment length is one-quarter of the vector length. Therefore, the four segments within the vector length are processed independently of each other. Furthermore, in this example, the segment length is twice the key length. Only matching is given. Figure 5C The configured example bit size is 256 bits for a 128-bit key and 1024 bits for the vector length. The arrays of data values ​​retrieved from source vector register 505 are also 128 bits (16 bytes) each. Therefore, the index is a 1-bit value, allowing selection of one of two keys within a segment of the cryptographic key register 504. Figure 5A , Figure 5B and Figure 5C The examples illustrate that the vector cryptography processing instructions disclosed herein are independent of vector length, and therefore can be written into program code applicable to any vector length greater than a minimum. A set of optional key pair segment length constraints also constrains the size of the index value, meaning that only a finite number of encoded bits are needed to provide the value as an immediate value.

[0084] Figure 6AThe parallel processing of two segments according to some examples is illustrated schematically. The contents of the two segments of the source vector register 600 (i.e., arrays of data values) are retrieved in parallel to be processed in parallel in parallel cryptographic operations 601, 602 by selecting (not shown) the corresponding key (e.g., round key) by applying the index value indicated by the vector cryptographic processing instructions. The results of parallel cryptographic operations 601, 602 (i.e., transformed arrays of data values) are written to the corresponding segments of the destination vector register 603. Figure 6A The contents of the two segments of the source vector register 600 can be a single array of data values ​​in each segment, or they can be a set of arrays of data values ​​in each segment. The latter case is shown in... Figure 6B The diagram illustrates the parallel processing of multiple arrays of data values ​​based on some examples. An array of data values ​​is retrieved from both segments of the source vector register 605 and the corresponding key RK (not shown) is selected by applying the index value indicated by the vector cryptography processing instructions. i (The round key used in the i-th round), these multiple arrays (A0 to A7) of data values ​​are processed in parallel by cryptographic operation 606. The result of parallel cryptographic operation 606 (i.e., the transformed array of data values) is written to destination vector register 607.

[0085] Figure 7 This is a flowchart illustrating a sequence of steps performed when executing a vector cryptographic processing instruction, according to some examples. The process begins at step 700, where the vector cryptographic processing instruction is decoded. In response, at step 701, an array of data values ​​is read from the source vector register specified by the vector cryptographic processing instruction. Furthermore, at step 702, a cryptographic key is read from a sub-part of the cryptographic key vector register specified by the vector cryptographic processing instruction, where the sub-part is indicated by a key index value specified by the vector cryptographic processing instruction. Then, at step 703, cryptographic processing is performed on the array of data values ​​using the cryptographic key to generate a transformed array of data values. Finally, at step 704, the transformed array of data values ​​is written to the destination vector register specified by the vector cryptographic processing instruction.

[0086] Figure 8Schematic illustrations of emulator implementations according to some examples are provided. While the embodiments described earlier implement the invention in terms of means and methods for operating specific processing hardware supporting the technology of interest, it is also possible to provide an instruction execution environment implemented using a computer program according to the embodiments described herein. Such computer programs are often referred to as emulators because they provide a software-based implementation of a hardware architecture. Types of emulator computer programs include emulators, virtual machines, models, and binary translators (including dynamic binary translators). Typically, emulator implementations can run on a host processor 830 that optionally runs a host operating system 820 and supports an emulator program 810. In some arrangements, multiple layers of emulation may exist between the hardware and the provided instruction execution environments and / or multiple different instruction execution environments provided on the same host processor. Historically, powerful processors have been required to provide emulator implementations that execute at reasonable speeds, but such approaches may be reasonable in certain situations, such as when it is desirable to run native code from another processor for compatibility or reuse reasons. For example, emulator implementations may provide instruction execution environments with additional functionality not supported by the host processor hardware, or provide instruction execution environments typically associated with different hardware architectures. An overview of simulation is given in “Some Efficient Architecture Simulation Techniques”, Robert Bedichek, Winter USENIX Conference, 1990, pp. 53–63.

[0087] Where embodiments have been previously described with reference to a particular hardware architecture or feature, equivalent functionality can be provided in a simulated embodiment through a suitable software architecture or feature. For example, a particular circuit may be implemented as computer program logic in a simulated embodiment. Similarly, memory hardware (such as registers or caches) may be implemented as software data structures in a simulated embodiment. One or more of the hardware elements mentioned in the previously described embodiments are present in a configuration on host hardware (e.g., host processor 830), and some simulated embodiments may use the host hardware where appropriate.

[0088] The simulator program 810 may be stored on a computer-readable storage medium (which may be a non-transitory medium) and provides a program interface (instruction execution environment) to the target code 800 (which may include applications, operating systems, and hypervisors), the program interface being identical to the interface of the hardware architecture modeled by the simulator program 810. Figure 8As the example illustrates, the simulator program 810 thus includes (among many other components) instruction decoding program logic 812, processing program logic 814, and vector data structure logic 816, enabling it to emulate the apparatus described herein. Therefore, the program instructions of the object code 800 can be executed from within the instruction execution environment using the simulator program 810, allowing a host computer 830, which does not actually possess the hardware features of the apparatus discussed above, to emulate these features.

[0089] In summary, an apparatus, method, and computer program product are disclosed. Decoded instructions control the execution of data processing, and multiple vector registers store data vectors, each data vector comprising multiple data elements. Vector cryptographic processing instructions specify a destination vector register, a source vector register, a cryptographic key vector register, and a key index value. The instructions control the execution of a set of operations, including: reading an array of data values ​​from the source vector register and reading a cryptographic key from a sub-part of the cryptographic key vector register indicated by the key index value; performing cryptographic processing on the array of data values ​​using the cryptographic key to generate a transformed array of data values; and writing the transformed array of data values ​​into the destination vector register.

[0090] In this application, the term "configured as" is used to mean that the elements of the device are configured to perform the defined operations. In this context, "configuration" means the configuration or manner of interconnection of hardware or software. For example, the device may have dedicated hardware that provides the defined operations, or a processor or other processing device may be programmed to perform functions. "Configured as" does not mean that the elements of the device need to be changed in any way to provide the defined operations.

[0091] While exemplary embodiments of the invention have been described in detail herein with reference to the accompanying drawings, it should be understood that the invention is not limited to those precise embodiments, and that various changes, additions, and modifications can be made therein by those skilled in the art without departing from the scope of the invention as defined by the appended claims. For example, features of the dependent claims can be combined with features of the independent claims in various ways without departing from the scope of the invention.

Claims

1. An apparatus, the apparatus comprising: Processing circuitry, the processing circuitry being used to perform data processing; An instruction decoding circuit is used to decode instructions to control the processing circuit to perform the data processing; and Multiple vector registers, each used to store data vectors, wherein each data vector includes multiple data elements. The instruction decoding circuit, in response to a vector cryptography processing instruction specifying a destination vector register, a source vector register, a cryptographic key vector register, and a key index value, controls the processing circuit to perform a set of operations, the set of operations including: An array of data values ​​is read from the source vector register, and the cryptographic key is read from the sub-part of the cryptographic key vector register indicated by the key index value; The cryptographic key is used to perform cryptographic processing on the array of data values ​​to generate a transformed array of data values; and Write the transformed array of data values ​​into the destination vector register.

2. The apparatus of claim 1, wherein the cryptographic processing is at least part of a round of processing of an iterative cryptographic algorithm, and the cryptographic key is a round key generated for the round of the iterative cryptographic algorithm.

3. The apparatus of claim 2, wherein the cryptographic key vector register stores a plurality of cryptographic keys in a plurality of sub-parts, and each of the plurality of sub-parts stores a different round key for a different round of the iterative cryptographic algorithm.

4. The apparatus according to any one of claims 1 to 3, wherein the processing circuitry is configured to process the source vector register as a set of segments, wherein the instruction decoding circuitry is configured to control the processing circuitry to read the array of data values ​​from the segment of the source vector register for each segment, and to read the cryptographic key from the sub-part of the corresponding segment of the cryptographic key vector register.

5. The apparatus of claim 4, wherein the processing circuitry is configured to process the group of segments in parallel.

6. The apparatus of claim 4 or claim 5, wherein the bit length of each segment in the set of segments is greater than the bit length of the array of data values, such that the segments comprise a plurality of arrays, and the processing circuitry is configured to process the plurality of arrays in parallel.

7. The apparatus according to any one of claims 4 to 6, wherein the sub-part of the cryptographic key vector register from which the cryptographic key is read is a sub-part of a segment in the set of segments.

8. The apparatus according to claims 4 to 7, wherein a set of cryptographic keys stored in the corresponding sub-parts of the segments of the cryptographic key vector register is repeated in all segments of the cryptographic key vector register.

9. The apparatus according to any of the preceding claims, wherein the destination vector register is the same vector register as the source vector register, and the transformation array of data values ​​is written to the destination vector register to destructively overwrite the source vector register.

10. The apparatus according to any one of claims 1 to 9, wherein the vector cryptographic processing instruction is an encryption vector processing instruction, the cryptographic key is an encryption key, and the cryptographic processing performed on the array of data values ​​is an encryption operation.

11. The apparatus according to any one of claims 1 to 9, wherein the vector cryptographic processing instruction is a decryption vector processing instruction, the cryptographic key is a decryption key, and the cryptographic processing performed on the array of data values ​​is a decryption operation.

12. The apparatus according to any one of claims 1 to 9, wherein the cryptographic processing performed on the array of data values ​​further includes a column mixing operation.

13. The apparatus according to any of the preceding claims, wherein the cryptographic processing performed on the array of data values ​​is based on the Advanced Encryption Standard (AES).

14. The apparatus according to any of the preceding claims, wherein the cryptographic processing performed on the array of data values ​​is part of an encryption algorithm that includes authentication.

15. The apparatus according to any preceding claim, wherein the vector cryptography processing instructions specify a set of destination vector registers and a set of source vector registers, and wherein the set of operations is performed for each source vector in the set of source vector registers, and includes writing a corresponding transformation array of data values ​​into a corresponding destination vector register.

16. The apparatus of claim 15, wherein the vector cryptography processing instruction specifies a first destination vector register in the set of destination vector registers, and the other destination vector registers in the set of destination vector registers are implicit.

17. The apparatus of any one of claims 15 and 16, wherein the vector cryptography processing instructions specify a first source vector register in the set of source vector registers, and the other source vector registers in the set of source vector registers are implicit.

18. A method, the method comprising: The control processing circuit performs data processing; The instructions are decoded to control the processing circuitry to perform the data processing; as well as The data vectors are stored in multiple vector registers, and each data vector includes multiple data elements. Decoding the instructions includes controlling the processing circuit to perform a set of operations in response to decoding a vector cryptography processing instruction specifying a destination vector register, a source vector register, a cryptographic key vector register, and a key index value. These operations include: An array of data values ​​is read from the source vector register, and the cryptographic key is read from the sub-part of the cryptographic key vector register indicated by the key index value; The cryptographic key is used to perform cryptographic processing on the array of data values ​​to generate a transformed array of data values; and Write the transformed array of data values ​​into the destination vector register.

19. A non-transitory computer-readable medium storing a computer program for controlling a host data processing device to provide an instruction execution environment, the computer program comprising: Processing logic, configured to perform data processing; Instruction decoding program logic, configured to decode instructions to control the processing program logic to perform the data processing; and Multiple vector data structures are used to store data vectors, each data vector including multiple data elements. The instruction decoding program logic responds to vector cryptography processing instructions specifying a destination vector data structure, a source vector data structure, a cryptographic key vector data structure, and a key index value to control the processing program logic to perform a set of operations, the set of operations including: Read an array of data values ​​from the source vector data structure, and read the cryptographic key from the sub-section of the cryptographic key vector data structure indicated by the key index value; The cryptographic key is used to perform cryptographic processing on the array of data values ​​to generate a transformed array of data values; and Write the transformed array of data values ​​into the destination vector data structure.

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