System and method for coherent data transfer with synchronization in a multi-core processor

Abstract

A method and system for a digital signal processor (DSP) to transfer data between a first central processing unit (CPU) core (a producer core) and a second CPU core (a consumer core). The first CPU core and the second CPU core are aligned in time such that one or more cycles of the first CPU core are associated with one or more cycles of the second CPU core. The first CPU core and the second CPU core are configured to access a shared memory through which data can be written and / or read by the first CPU core and the second CPU core.

Description

[0001] Priority declarations / cross-references

[0002] This application claims priority to U.S. nonprovisional patent application No. 18 / 582,166, filed February 20, 2024, entitled “Systems and methods for coherent data transfer with synchronization in a multi-core processor”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Some embodiments of this disclosure relate to control systems. More specifically, some embodiments of this disclosure relate to data transfer between a production central processing unit (CPU) or core and a consuming CPU in a manner that mitigates data conflicts during data transfer operations. Background Technology

[0004] Existing control systems are used to activate various devices, such as motors controlling the position of articulated enclosures (e.g., doors or fairings of vehicles like aircraft). For example, a control system can be implemented by transferring instructions between a CPU that generates instructions and a CPU that controls the devices. However, signal transmission can be interfered with if multiple CPUs attempt to write to shared memory. Therefore, a system capable of mitigating signal interference is needed.

[0005] By comparing such systems with the present disclosure as described in conjunction with the accompanying drawings in the remainder of this application, the further limitations and disadvantages of conventional and traditional methods will become apparent to those skilled in the art. Summary of the Invention

[0006] Systems and / or methods are provided for transferring data between cores of an exemplary digital signal processor (DSP). More specifically, the disclosed examples relate to a DSP configured to utilize shared memory to synchronize data transfers between cores.

[0007] These and various other advantages, aspects and novel features of this disclosure, as well as details of exemplary embodiments thereof, will be more fully understood from the following description and accompanying drawings. Attached Figure Description

[0008] Figure 1 An exemplary flow diagram of a digital signal processor (DSP) employing multiple central processing units (CPUs) according to an exemplary embodiment of the present disclosure is shown.

[0009] Figure 2An exemplary flow diagram of a DSP employing multiple CPUs and shared memory, according to an exemplary embodiment of the present disclosure, is shown.

[0010] Figure 3 An exemplary method of data transmission operation according to an exemplary embodiment of the present disclosure is shown.

[0011] The accompanying drawings are not necessarily drawn to scale. Where appropriate, similar or identical reference numerals are used to refer to similar or identical components. Detailed Implementation

[0012] An exemplary system and method for a digital signal processor (DSP) to transfer data between a first central processing unit (CPU) core (producing core) and a second CPU core (consuming core) are disclosed. The first CPU core and the second CPU core are time-aligned such that the period of one or more frames of the first CPU core is associated with one or more periods of the second CPU core. The first CPU core and the second CPU core are configured to access shared memory through which they can write and / or read data.

[0013] For example, coherent data transfer with synchronization provides a lightweight solution for delivering data between first and second CPU cores using shared memory. Therefore, this process prevents data from being manipulated (e.g., overwritten, modified, etc.) while being transferred and / or consumed simultaneously. Memory access conflicts between producing and / or consuming processors (e.g., central processing units (CPUs)) are avoided due to access restrictions on each processor. Data receipt (ACK) and / or negative receipt (NACK) can be detected in response to the communication protocol. Furthermore, the process specifies that each CPU core is configured to verify that each other processor remains synchronized with other processors.

[0014] Multi-core solutions typically require communication between individual processing cores. The disclosed systems and methods are for inter-process communication (IPC), where two or more CPUs are configured to communicate with each other through synchronous operation. Communication between CPUs can be implemented via one or more shared memory devices, which may internally include partitioned regions.

[0015] In some publicly available examples, the processor includes at least one production CPU and one consumption CPU. The production CPU receives commands and generates instructions via data signals, which are written to shared memory for the consumption CPU to read. The shared memory location acts as a buffer where the instructions written by the production CPU are stored, and the consumption CPU accesses and reads data from this buffer.

[0016] In an exemplary multi-core processor employing two cores (e.g., a first CPU (CPU1) and a second CPU (CPU2)), each core may have different responsibilities and / or functions on a digital signal processor (DSP). For example, the first CPU may be configured to perform one or more of serial communication, fault detection, and / or event logging. In this example, the second CPU may be configured to execute all external commands (e.g., motor control functions, system activation, etc.).

[0017] Because of their different roles, a first CPU can run at a first frame rate, and a second CPU can run at a second frame rate. The first frame rate (e.g., 5 kHz) is slower than the faster first frame rate (e.g., 20 kHz), resulting in a 4:1 frame rate ratio. While some examples provide specific frame rates or frame rate ratios, the frame rate and the resulting ratio can vary depending on the specific application, desired response time, number of CPU cores used, or other factors. For example, a 2:1 ratio (e.g., 5 kHz to 10 kHz) might be used for time-insensitive operations, while an 8:1 ratio (e.g., 5 kHz to 40 kHz) might be used for faster-responding operations. Faster rates may require more power and / or computing resources, so different frame rates can be selected for different applications based on their specific requirements.

[0018] In an exemplary data operation, a first, production CPU transmits motor commands and motor control parameters (e.g., from a user interface, electronic control, computing platform, etc.) to a second, consumption CPU. The second CPU then transmits feedback data to the first CPU for system performance evaluation.

[0019] To ensure correct operation, processor-to-processor communication relies on data coherence. For example, if a second CPU begins processing or executing a new command (e.g., motor control loop parameters) before the first CPU has finished modifying it, the motor may be commutated in an unintended, incorrect, and / or harmful manner. Similarly, when evaluating motor performance (e.g., based on feedback provided by the second CPU), the first CPU must access coherent data from the second CPU. If the data is incoherent, the first CPU may arrive at incorrect conclusions—for example, returning a wrong conclusion that a fully operable system is not functioning correctly, or incorrectly concluding that a faulty system is operating normally.

[0020] Advantageously, the disclosed multi-core system employing coherent data transmission with a synchronization solution allows for rapid data transfer and consumption without memory address conflicts between communicating cores.

[0021] This is achieved while maintaining data coherence even though each core operates at a different frame rate. In some examples, data from a first producing CPU is provided to a first shared memory. Once a write operation is complete, an indication is given to a second consuming CPU (e.g., via a flag or other signal), which then reads the data. In some examples, certain memory locations allow only certain CPUs to perform write access (e.g., the first, producing CPU, which may have both read and write access rights), while certain other CPUs (e.g., the second consuming CPU, which may have both read and write access rights) are only granted read access rights (e.g., at all times, at specific times, and / or in response to permission indications).

[0022] Furthermore, feedback from the second CPU is only provided to the first CPU after the indication feedback signal has been fully received from the shared memory. Access is enabled by a flag or other indicator from the opposite CPU, which provides an address on the shared memory for writing data / instructions, thereby allowing the receiving CPU to point to the data / instructions being written.

[0023] The disclosed systems and methods offer numerous advantages over conventional systems. For example, the disclosed systems and methods avoid data conflicts by writing flags to addresses in shared memory, both indicating to the opposing CPU core that data is available and ensuring that the address is not in use. In some examples, the cycles of the primary and / or secondary frames producing the CPU core can be aligned with one or more consuming frames consuming the CPU core. In some disclosed examples, both flags and timing are used to provide redundancy techniques to ensure that data conflicts are mitigated.

[0024] In some examples, flags can be provided between opposing CPU cores to inform another CPU core of data availability and / or address without aligning the cycles of the communicating CPU cores. For example, activating or setting a flag can indicate the presence (and / or consumption of) new data in a certain portion of shared memory by a given CPU. Furthermore, confirmation of read and / or write operations (e.g., performed by the opposing CPU) can trigger the activation of flags (e.g., "raising" the flag by a write operation and "lowering" the flag after a read operation).

[0025] In some examples, CPU cores can align without additional flags. For instance, when a frame begins and / or ends, the corresponding CPU core can query shared memory and may not require affirmative confirmation of the flags to continue read and / or write operations.

[0026] To optimize the use of shared memory (e.g., shared memory with multiple IPC registers and / or shared regions) and ensure responsive communication between CPU cores, the use of flags and other communications (e.g., ACK, NACK) between CPU cores and the timing / cycle alignment of each CPU core will be described in conjunction with the accompanying figures.

[0027] As used herein, “and / or” means any one or more items in a list joined together by “and / or”. For example, “x and / or y” means any element in the three-element set {(x), (y), (x, y)}. Similarly, “x, y and / or z” means any element in the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}. As used herein, the term “module” refers to a function that can be implemented in hardware, software, firmware, or any combination thereof. As used herein, the term “exemplary” means used as a non-limiting example, instance, or illustration.

[0028] As used herein, the terms “first” and “second” can be used to enumerate different components or elements of the same type and do not necessarily imply any particular order. For example, while a first moment may occur earlier than a second moment within a time period, the terms “first moment” and “second moment” do not imply any particular order in which the first moment or the second moment occurs relative to each other within that time period.

[0029] As used herein, “circuit” or “circuit system” includes any analog and / or digital components, power and / or control elements (such as microprocessors, digital signal processors (DSPs), software, etc.), discrete and / or integrated components, or parts and / or combinations thereof.

[0030] As used herein, the terms “control circuit,” “control circuit system,” and / or “controller” can include digital and / or analog circuitry, discrete and / or integrated circuits, processors, microprocessors, digital signal processors (DSPs), and / or other logic circuitry, and / or associated software, hardware, and / or firmware. The control circuitry or control circuit system may be located on one or more circuit boards forming part or all of the controller.

[0031] As used herein, the term "memory" includes volatile and non-volatile memory devices and / or other storage devices.

[0032] As used herein, the term "multi-core processor" includes a microprocessor arranged on a single integrated circuit (IC) having two or more independent processing units (e.g., cores or CPU cores), each of which is configured to write, read, and / or execute instructions from the other processing units.

[0033] As used in this article, the term “digital signal processor (DSP)” includes microprocessor chips with a dedicated architecture designed specifically for optimal digital signal processing.

[0034] As used in this article, the term "data coherence" provides consistency across shared resource data, as well as logical connectivity and integrity within a single dataset and across datasets.

[0035] Figure 1 An exemplary DSP is shown that provides a unique set of registers for inter-process communication (IPC). Among other features, these registers provide means for each CPU core to implement one or more of the following: 1) pass the address of a shared memory containing new data to another CPU; 2) notify another CPU that new data exists in the shared memory; and / or 3) acknowledge the presence and / or transfer of data from each CPU.

[0036] The disclosed DSP has random access memory (RAM) that can be divided into various physical and / or logical portions. During data transfer operations, address conflicts are mitigated by configuring each CPU core to access a shared memory region that is different from the region accessible by another CPU core (e.g., at a given time, at a given address, etc.).

[0037] therefore, Figure 1 An exemplary flow diagram of a multi-core processor 10 configured for communication between a first CPU 100 and a second CPU 102 is shown. One or more shared memory devices 14 and 16 are provided, which are accessible to one or both of the first CPU 110 and the second CPU 102.

[0038] To ensure successful data transfer between the first CPU and the second CPU and avoid data conflicts, the first CPU and the second CPU are configured to agree on the structure of the data to be transferred. Furthermore, the first CPU and the second CPU are initialized such that the buffer or memory (e.g., shared memory 14, 16) being read by the consuming CPU (e.g., second CPU 102) is not the same buffer being written to by the producing CPU (e.g., first CPU 100). Therefore, the producing CPU can write to the buffer at a first moment, while the consuming CPU reads at a second moment, with the timing based on the transmission and reception of flags from the opposite CPU indicating that the write / read operation has been completed. In some examples, the producing CPU writes to the first buffer, and the consuming CPU reads from the second buffer; this can occur simultaneously and / or in response to a flag.

[0039] Based on this shared picture, the production CPU will know the type and / or size of the data being transmitted, while the consuming CPU will know the type and / or size of the data being received.

[0040] Although in some examples the first CPU 100 is described as performing the function of a production CPU and the second CPU 102 is described as performing the function of a consumption CPU, either CPU and / or other CPUs and / or cores can be configured to run as a production CPU and / or a consumption CPU, depending on the specific application or desired outcome.

[0041] As shown in the figure, each CPU is configured to write data to and / or read data from shared memories 14, 16 and / or another CPU. For example, the first CPU 100 writes data (e.g., a set) to the first shared memory 14, which provides status information (e.g., status STS) to the second CPU 102, indicating that the data write operation has been completed. Once read, the second CPU 102 then writes an acknowledgment (e.g., an ACK) to the first shared memory 14. In some examples, the second CPU writes the acknowledgment to clear a presence flag generated at the shared memory along with the status indication of the opposing CPU. In some additional or alternative examples, the write acknowledgment triggers a flag transfer to the first CPU 100 (e.g., a flag) and / or to the shared memory with feedback.

[0042] Once the information is read and acknowledged, the second CPU 102 can be configured to execute the instructions written by the first CPU 100. Upon completion, the second CPU 102 is similarly configured to write data (e.g., a set) to the second shared memory 16, providing status information (e.g., status STS) to the first CPU 100 indicating that the instruction has been successfully executed (or a failure has occurred). The first CPU 100 then reads the status information and writes an acknowledgment (e.g., an ACK) to the second shared memory 16. In some examples, the first CPU writes the acknowledgment to clear a presence flag generated at the shared memory along with the status indication of the counterpart CPU. In some additional or alternative examples, the write acknowledgment triggers a flag transfer to the second CPU 102 (e.g., a flag). This process will be described in reference to... Figure 2 and Figure 3 To provide a more detailed description.

[0043] Figure 2 Example systems (such as) are shown Figure 1 Detailed graphical representation of the multi-core processor 10 provided in the documentation. Figure 2As shown, the disclosed system employs a first shared memory 104 and a second shared memory 106, each for one communication direction. In the example shown, the production CPU 102 points to the first shared memory 104 when writing new data (e.g., for transfer to another CPU, such as the first CPU 100), because the first consuming CPU 100 is configured to read data thereon during data transfer operations.

[0044] Similarly, when the first CPU 100 writes new data (e.g., for transfer to another CPU, such as the second CPU 102), it points to the second shared memory 106, while the second CPU 102 is configured to read data transferred from the first CPU 100.

[0045] like Figure 2 As shown, each shared memory includes a separate region, such that one CPU can access a given region of the shared memory while another CPU can access another region of the shared memory (and / or opposing CPUs can access a common region at different times). Here, the first shared memory 104 includes a first region 108 and a second region 110, and the second shared memory 106 includes a third region 112 and a fourth region 114.

[0046] In some examples, the second CPU is configured to write to the first region 108 from write frames W Frame0 through W Frame3 and W Frame8 through W Frame11. The first region 108 is read by read frames Read Frame 1 and Read Frame n of the first CPU. The second CPU is also configured to write to the second region 110 from write frames W Frame4 through W Frame7, which is read by read frames Read Frame 0 and Read Frame 2 of the first CPU.

[0047] In some examples, the first CPU is configured to write to the third region 112 from write frames 0 and 2, and to read from the second CPU using read frames R Frame 4 through R Frame 7 and R Frame n through R Frame (n+3). The first CPU is also configured to write to the second region 110 from write frames 4 through 7, and to read from the second CPU using read frames R Frame 0 through R Frame 3 and R Frame 8 through R Frame 11.

[0048] This arrangement allows communication between cores while avoiding memory address conflicts and always maintaining data consistency. This is guaranteed because the first and second CPUs are configured to read from and / or write to separate regions (e.g., regions 108-114) of the first shared memory 104 and the second shared memory 106.

[0049] The following reference Figure 2 The system shown provides an exemplary data transfer operation. In some examples, prior to the data transfer operation, frames 120a-120n of the first CPU 100 are aligned with frames 122a-122n of the second CPU 102. For example, each frame 120 of the first CPU 100 is aligned with multiple corresponding frames of the second CPU 102. Since frames 120a-120n operate at a slower rate (e.g., 5 kHz) than frames 122a-122n (e.g., 20 kHz), a 4:1 frame ratio is achieved. Once aligned, the production CPU (e.g., the first CPU 100) verifies that the desired buffer location for new data (e.g., an IPC register within one or more of regions 108-114) is not being used by the consuming CPU (e.g., the second CPU 102) or other CPU cores. This can be achieved by checking a “new data” flag at the selected buffer location. When the production CPU receives a response that the buffer location (e.g., an IPC register) has been cleared by the consuming CPU, the production CPU can initiate a data write operation as disclosed herein.

[0050] When the data write from the production CPU to shared memory is complete, the production CPU then initiates a "new data" flag in its IPC register, associated with the newly written buffer / region, to notify the consuming CPU that new data is available. The consuming CPU can then continue accessing the new data without conflicting with the production CPU. When the production CPU has additional new data to transfer to the consuming CPU, it will access another buffer to write the new data.

[0051] Similarly, if the production CPU has not set the "new data" flag for the expected buffer before the start of each cycle, this indicates an error condition, because the consuming CPU expects the flag to be present at the start of each cycle.

[0052] Figure 3 This is a logical representation of a data transfer operation 300 between a first CPU 100 (e.g., a production CPU) and a second CPU 102 (e.g., a consumption CPU). According to this disclosure, the method can represent logic or instructions executable by a DSP or other processing system.

[0053] At block 302, a first CPU 100 (e.g., a production CPU) is aligned with a second CPU 102 (e.g., a consumption CPU). This alignment may include associating the start and end times of the first CPU's production minor frames 120a-n with one or more frames 122a-n of the second CPU. In some examples, the second CPU comprises four frames for each production minor frame, such that the ratio between the first CPU's production minor frames and the second CPU's four frames is 1:4. For a 200 µs cycle (e.g., a production minor frame runs for 200 µs), the length of each consumption minor frame will be 50 µs. In this example, a write operation from the first CPU can transfer data to shared memory during one complete production minor frame, while the second CPU can receive data from shared memory during a second complete production minor frame.

[0054] In some examples, the number of shared memory IPC frames is related to the number of minor frames consumed. Furthermore, a production major frame may include multiple production minor frames (e.g., five (5) per second).

[0055] At block 304, the first CPU 100 (e.g., a production CPU) writes new data to shared memory. For example, the first CPU may handle initial data transfer operations, such as during system startup. At block 306, a flag is set by the first CPU. In this example, the flag may include the address of the location where the new data is stored in shared memory, timing information, or other relevant information. At block 308, the second CPU 102 queries the shared memory to retrieve the flag from the first CPU 100. If no flag is present in the shared memory and / or no new data is carried at the start of each minor frame, the method returns to block 304 and continues querying the shared memory.

[0056] In some examples, because the first CPU 100 operates at a slower rate, the second CPU 200 may not expect a flag (or other indication) from the first CPU 100 in each cycle. Therefore, the system can be programmed to expect an error at each instance where a flag is not received in a minor frame of the first CPU 100. However, the system can be programmed to allow one or more read operations of a read frame from the second CPU 200 to return without a flag (or other indication). In some examples provided in this disclosure, the second CPU 200 operates at four times the frequency of the first CPU 100, so the system can accept three operations by the second CPU 200 without reading a flag (or other indication).

[0057] However, if a flag is present, the second CPU reads new data from the desired memory location at block 310. When the data is no longer needed within each 200 µs time slot, in block 312, the second CPU may send an acknowledgment (e.g., an ACK signal) to the first CPU, clearing the "new data" flag in the IPC register associated with the first buffer / region indicating that new data has been received. Here, the acknowledgment is transmitted to shared memory to mark the end of the first production minor frame. In an alternative example, as shown in block 314, the second CPU generates a flag and writes it to shared memory. This action prepares for receiving additional new data in a second buffer, which will be ready at the start of the subsequent cycle (e.g., at the 200 µs time slot).

[0058] In block 316, at the start of the next (e.g., the second) production minor frame 120, the first CPU queries the shared memory to check for the presence of a flag. In response to the presence of the flag from the second CPU, in block 318, the first CPU changes its pointer to the memory address provided by the flag to read information from the flag. For example, the second CPU can submit confirmation that an instruction has been received and / or executed while simultaneously writing the flag to a different address on the same shared memory (e.g., shared memory 106) and / or shared memory regions (e.g., regions 112 and 114) as the first CPU. Therefore, the pointer will identify an address on another shared memory (e.g., shared memory 104) and / or shared memory regions (e.g., regions 108 and 110).

[0059] Once the first CPU reads the flag in block 318, the next / second production minor frame 120 can continue with a new cycle, essentially as described with respect to blocks 302 through 320. This can occur if block 304 is being executed as part of a continuous / cyclic operation, rather than an initial data transfer operation.

[0060] In one example, the flag is not identified at box 316, and the first CPU generates a fault signal at box 320. In some examples, the fault (and / or fault signal) causes the system to halt further operation. This may include preventing additional read / write operations between CPUs, and / or preventing the transfer of data to or from the CPU and / or the execution of instructions. Handling the fault and / or resetting the flag may require corrective actions from the control system and / or the user.

[0061] In additional or alternative examples, a fault (and / or fault signal) is registered, generating alarms and / or communications to related systems, but operation continues. For example, even if the expected flag is absent and a fault is registered, read and / or write operations on one or both of the first and second CPUs may continue. This could include receiving new data, writing new data to shared memory and / or reading new data from shared memory, and / or executing any instructions (e.g., instructions received at the consuming CPU).

[0062] Furthermore, at block 322, the second CPU can execute instructions corresponding to the new data received in block 310. For example, the instructions may include commands to operate or move actuators, motors, and / or other controls of systems (e.g., systems associated with a vehicle, such as an aircraft).

[0063] Although shown as occurring after a commit confirmation (in box 314, etc.) and / or commit another flag, the second CPU can execute instructions at any time after the read operation, including before generating and / or writing confirmations or flags.

[0064] However, if the flag does not exist and the shared memory (e.g., a region of the shared memory) is not in use, the method proceeds to block 310, where in block 312 the first CPU 100 points to an accessible buffer and writes new data for transfer to the shared memory.

[0065] Referring to several accompanying figures, multiple advantages are achieved through the innovative system and method disclosed herein.

[0066] While this disclosure has been described with reference to certain embodiments, those skilled in the art will understand that various changes and substitutions can be made without departing from the scope of this disclosure. Furthermore, many modifications can be made to adapt particular situations or materials to the teachings of this disclosure without departing from the scope of this disclosure. Therefore, it is intended that this disclosure be limited to the specific embodiments disclosed, but rather that it encompass all embodiments falling within the scope of the appended claims.

Claims

1. A digital signal processor (DSP) for an electronic controller, comprising: First Central Processing Unit (CPU) core; A second central processing unit core whose cycle is aligned with that of the first central processing unit core; as well as The shared memory is accessible to both the first central processing unit core and the second central processing unit core, wherein the first central processing unit core is configured as follows: Write data to the first portion of the shared memory; and Write a first flag to the shared memory; The second central processing unit is configured as follows: The first flag is queried in the first part of the shared memory; and In response to confirmation that the first flag exists in the shared memory, the data is read from the first portion of the shared memory.

2. The system according to claim 1, wherein, The first central processing unit core includes a main frame having two or more minor frames.

3. The system according to claim 2, wherein, The second central processing unit core includes multiple consumption frames.

4. The system according to claim 3, wherein, The first central processing unit core queries the shared memory at the beginning or end of one of the two or more minor frames.

5. The system according to claim 4, wherein, The secondary frames operate at a first frequency, and the plurality of consumed frames operate at a second frequency greater than the first frequency.

6. The system according to claim 5, wherein, The second frequency is four times greater than the first frequency.

7. The system according to claim 1, wherein, In response to confirmation that the first flag does not exist in the shared memory, the second central processing unit core registers a fault.

8. The system according to claim 1, wherein, The second central processing unit is configured to write a second flag to a second portion of the shared memory after reading the data from a first portion of the shared memory, wherein the second central processing unit registers a fault in response to confirmation that the second flag does not exist in the shared memory.

9. The system according to claim 1, wherein, The first central processing unit core is configured to query the second flag in the second part of the shared memory, and in response to confirming that the second flag does not exist in the shared memory, the first central processing unit core registers a fault.

10. The system according to claim 1, wherein, The first flag provides the address of the data on the shared memory.

11. The system according to claim 10, wherein, The shared memory includes one or more regions, the one or more regions including one or more inter-processor communication (IPC) registers, and the address on the shared memory identifies one of the one or more IPC registers storing the data.

12. A method for digital signal processing in electronic control, comprising: Timing alignment of the first central processing unit core and the second central processing unit core; Data is written from the first central processing unit core to the shared memory; Write a first flag to the shared memory; The second central processing unit core queries the first flag in the shared memory; Confirm that the first flag exists in the shared memory; as well as Read the data from the shared memory.

13. The method according to claim 12, wherein, Each of the first central processing unit core and the second central processing unit core includes one or more write frames and one or more read frames.

14. The method according to claim 12, wherein, Timing alignment includes aligning the minor frames of the first central processing unit core to the multiple consumable frames of the second central processing unit core.

15. The method according to claim 14, wherein, The secondary frames operate at a frequency of 20 kHz, and the plurality of consumption frames operate at a frequency of 5 kHz.

16. The method of claim 12, further comprising writing a second flag to the shared memory by the second central processing unit after completing reading the data from the shared memory.

17. The method of claim 12, further comprising activating a controller of a vehicle by a second central processing unit according to the data from the shared memory, the vehicle comprising one of an aircraft, a wheeled vehicle, a marine vehicle, and a rail vehicle.

18. The method according to claim 17, wherein, The motor controller is configured to activate one of the following: a torque motor, a solenoid, and an actuator.

19. A method for digital signal processing in electronic control, comprising: Data is written from the first central processing unit core to the shared memory; A first flag is transferred from the first central processing unit core to the second central processing unit core, the first flag including an address in the shared memory where the data is stored; The first flag is received at the second central processing unit core; The second central processing unit core accesses the data at the address in the shared memory; as well as The data is read by the second central processing unit core.

20. The method of claim 19, further comprising transmitting a second flag acknowledging receipt of the data from the shared memory by the second central processing unit to the first central processing unit core.

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