Arithmetic device and tensor update method

Abstract

The operation device of the present application is configured to have a contraction unit (1) that expresses an L (L is an integer of 2 or more) order tensor as a product of a plurality of tensors, i.e., small tensors, having a number of elements less than the number of elements of the L order tensor, and performs contraction processing on the plurality of small tensors to introduce factor information existing between the plurality of small tensors.

Description

Technical Field

[0001] This disclosure relates to computing devices and tensor update methods. Background Technology

[0002] There exists a computational device that represents a tensor of order L (L being an integer greater than 2) as a product of multiple tensors (hereinafter referred to as "small tensors") having fewer elements than a tensor of order L, and performs a factorization process on the tensor group containing multiple small tensors.

[0003] As such a computing device, for example, Non-Patent Document 1 discloses a computing device that performs the following shrinkage process: after moving all factor information existing other than between the two small tensors contained in the tensor group to between the two small tensors, the factor information existing between the two small tensors is introduced into the two small tensors.

[0004] Non-patent literature 1: U. Schollwock, “The density-matrix renormalization group in the age of atrix product states”, submitted to arXiv on August 20, 2010: 1008.3477v2

[0005] The computing device disclosed in Non-Patent Document 1 has the following problem: before performing the shrinking process, a large amount of computing time is required to move all factor information that exists between the two small tensors contained in the tensor group to between the two small tensors. Summary of the Invention

[0006] This disclosure was made to solve the aforementioned problems, and its purpose is to obtain a computing device that can shorten the computing processing time compared with the computing device disclosed in Non-Patent Document 1.

[0007] The computing device disclosed herein includes a shrinking unit that represents a tensor of order L (L is an integer greater than 2) as a product of multiple tensors, i.e., smaller tensors, having fewer elements than a tensor of order L, and performs shrinking processing on the multiple smaller tensors by introducing factor information existing between the multiple smaller tensors.

[0008] According to this disclosure, the processing time can be shortened compared to the computing device disclosed in Non-Patent Document 1. Attached Figure Description

[0009] Figure 1 This is a structural diagram showing the computing device involved in Embodiment 1.

[0010] Figure 2 This is a hardware structure diagram showing the hardware of the computing device involved in Embodiment 1.

[0011] Figure 3 It is a hardware structure diagram of a computer when the computing device is implemented by software or firmware.

[0012] Figure 4 This is a flowchart representing the tensor update method as a processing step of the computing device.

[0013] Figure 5A It represents matrix a j,k And matrix a i,k An illustration of a second-order tensor. Figure 5B It represents tensor a i,j,k An illustration of a third-order tensor. Figure 5C It represents the tensor M i,j σi,σi+1 An illustration of a 4th-order tensor.

[0014] Figure 6 This is an illustration showing that an L-order tensor is represented as the product of multiple smaller tensors.

[0015] Figure 7 This is an illustrative diagram illustrating an example of reducing the number of elements in a tensor by increasing its order.

[0016] Figure 8 This is an illustration of the existing contraction process disclosed in Non-Patent Document 1.

[0017] Figure 9 It means Figure 1 The diagram illustrates the shrinking, decomposition, and approximation processes in the shown computing device.

[0018] Figure 10 This is a structural diagram showing the interior of the contracted section 1.

[0019] Figure 11 This is a flowchart illustrating the processing steps of the contraction section 1.

[0020] Figure 12 This is a structural diagram showing the computing device involved in Embodiment 2.

[0021] Figure 13 This is a hardware structure diagram showing the hardware of the computing device involved in Embodiment 2.

[0022] Figure 14 This is a flowchart illustrating the tensor update method, which is a processing step of the computing device involved in Embodiment 2.

[0023] Figure 15 It means Figure 12The diagram illustrates the shrinking, decomposition, approximation, and reconfiguration processes in the shown computing device.

[0024] Figure 16 This is an explanatory diagram illustrating a specific example of the reconfiguration process performed by the reconfiguration unit 4.

[0025] Figure 17 This is an illustrative diagram representing an example of multiple factor information existing between multiple small tensors.

[0026] Figure 18 This is an explanatory diagram showing the factor information after the shift.

[0027] Figure 19 This is a flowchart illustrating the shrinking process of the shrinking unit 1 in the computing device according to Embodiment 4.

[0028] Figure 20A This is an explanatory diagram showing a structural example of the switching object. Figure 20B This is an illustrative diagram showing an example of a user interface used for settings.

[0029] Figure 21 is an illustrative diagram representing an example of multiple shrunk object tensors that are shrunk in parallel.

[0030] Figure 22A This is an illustrative diagram illustrating an example where the product of small tensors has a one-dimensional shape. Figure 22B This is an illustrative diagram illustrating an example where the product of small tensors has a two-dimensional, two-row shape. Figure 22C This is an illustrative diagram illustrating an example where the product of small tensors has a two-dimensional, two-column shape. Figure 22D This is an illustrative diagram representing a larger example of two-dimensional rows or two-dimensional columns. Detailed Implementation

[0031] The following description, for the purpose of explaining this disclosure in more detail, refers to the accompanying drawings to illustrate the manner in which this disclosure is carried out.

[0032] Implementation method 1.

[0033] Figure 1 This is a structural diagram showing the computing device involved in Embodiment 1.

[0034] Figure 2 This is a hardware structure diagram showing the hardware of the computing device involved in Embodiment 1.

[0035] Figure 1 The arithmetic unit shown includes a reduction section 1, a decomposition section 2, and an approximation section 3.

[0036] For example, the contraction part 1 is composed of Figure 2 The shown shrinkage circuit 11 is implemented.

[0037] The contraction part 1 represents a tensor of order L (where L is an integer greater than 2) as a product of multiple tensors with fewer elements than a tensor of order L, i.e., smaller tensors.

[0038] The shrinking section 1 performs shrinking processing on multiple small tensors by introducing factor information that exists between the multiple small tensors.

[0039] As factor information, it can be expressed as a factor matrix in matrix form, or as numerical values ​​or sequences of values ​​after omitting near-zero components of the matrix. Factor information is obtained when transforming each L-order tensor, for example, into a basis transformation matrix, and may contain information representing quantum states. Among multiple factors, those closer to the operator's tensor have a greater impact on computational accuracy.

[0040] The merging unit 1 outputs the merging result obtained from the merging process to the decomposition unit 2.

[0041] Here, the shrinking unit 1 performs shrinking processing on multiple small tensors by introducing factor information existing between the multiple small tensors. However, this is just an example; the shrinking unit 1 can also perform shrinking processing on multiple small tensors by introducing factor information existing between the multiple small tensors and by applying operators to the multiple small tensors.

[0042] In the following description, it is assumed that the contraction part 1 performs contraction processing that introduces factor information and operators.

[0043] Decomposition part 2, for example, is composed of Figure 2 The decomposition circuit 12 shown is implemented.

[0044] The decomposition unit 2 obtains the shrinkage result obtained from the shrinkage processing of the shrinkage unit 1.

[0045] The decomposition unit 2 decomposes the shrinkage result and outputs the tensor group containing multiple small tensors and factor information to the approximation unit 3.

[0046] Approximate part 3, for example, is from Figure 2 The approximate circuit 13 shown is implemented.

[0047] The approximation part 3 obtains a tensor set containing multiple small tensors and factor information from the decomposition part 2.

[0048] Approximation section 3 performs approximate processing on the factor information contained in the tensor set.

[0049] exist Figure 1 In this context, it is assumed that the contraction section 1, the decomposition section 2, and the approximation section 3, which are components of the arithmetic unit, are respectively composed of... Figure 2 The dedicated hardware implementation is shown. That is, it is assumed that the arithmetic unit is implemented by the shrinking circuit 11, the decomposition circuit 12, and the approximation circuit 13.

[0050] The shrinking circuit 11, the decomposition circuit 12, and the approximation circuit 13 are each, for example, equivalent to a single circuit, a composite circuit, a programmable processor, a parallel programmable processor, an ASIC (Application Specific Integrated Circuit), an FPGA (Field-Programmable Gate Array), or a combination thereof.

[0051] The components of a computing device are not limited to being implemented by dedicated hardware; a computing device can also be implemented by software, firmware, or a combination of software and firmware.

[0052] Software or firmware is stored as a program in the computer's memory. A computer refers to the hardware that executes programs, such as CPU (Central Processing Unit), GPU (Graphics Processing Unit), central processing unit, processing unit, arithmetic unit, microprocessor, microcomputer, processor, or DSP (Digital Signal Processor).

[0053] Figure 3 It is a hardware structure diagram of a computer when the computing device is implemented by software or firmware.

[0054] When the computing device is implemented by software or firmware, the program for causing the computer to execute each processing step in the condensation section 1, the decomposition section 2, and the approximation section 3 is stored in the memory 21. Then, the computer's processor 22 executes the program stored in the memory 21.

[0055] In addition, Figure 2 The image shows an example where the various components of a computing device are implemented using dedicated hardware. Figure 3 The image shows an example of a computing device implemented by software or firmware. However, this is just one example; some components of a computing device can also be implemented by dedicated hardware, while the remaining components can be implemented by software or firmware.

[0056] Next, for Figure 1 The operation of the shown arithmetic device will be explained.

[0057] Figure 4 This is a flowchart representing the tensor update method as a processing step of the computing device.

[0058] exist Figure 5A In the diagram, the L-order tensor is a 2-order tensor, and matrix a is represented as a 2-order tensor.j,k And matrix a i,k Matrix a j,k The number of elements is D j D k Matrix a i,k The number of elements is D i D k .

[0059] exist Figure 5B In the diagram, the L-order tensor is a 3rd-order tensor, and tensor a is shown as a 3rd-order tensor. i,j,k Tensor a i,j,k The number of elements is D i D j D k .

[0060] exist Figure 5C In the diagram, the L-order tensor is a 4-order tensor, and tensor M is shown as a 4-order tensor. i,j σi,σi+1 .

[0061] Figure 10 This is a structural diagram showing the interior of the contracted section 1.

[0062] like Figure 10 As shown, the merging unit 1 includes a tensor acquisition unit 31, a tensor representation unit 32, and a merging processing unit 33.

[0063] Figure 11 This is a flowchart illustrating the processing steps of the contraction section 1.

[0064] Tensor acquisition part 31 of the contraction part 1 Figure 6 As shown in the figure above, it has M subscripts σ. m The L-order tensor Φ of (m = 1, ..., M) Figure 11 Step ST11). M is an integer greater than 2. Tensor Φ, for example, in subscript σ m When the degrees of freedom are 2, it has 2 M The number of elements grows exponentially.

[0065] like Figure 6 As shown in the figure below, the tensor representation unit 32 of the contraction part 1 represents the L-order tensor Φ as multiple smaller tensors T with fewer elements than the tensor Φ itself. i product ( Figure 11 Step ST12). i = 1, ..., I. I is an integer greater than 2.

[0066] Figure 6 The small tensor T shown in the figure below i A fixed number of elements. The number of these elements is less than 2. M .

[0067] Figure 6 This is an illustration showing that an L-order tensor is represented as the product of multiple smaller tensors.

[0068] The techniques disclosed herein can be applied by transforming a first-order tensor into a second-order or higher tensor.

[0069] Figure 7 This is an illustrative diagram illustrating an example of reducing the number of elements in a tensor by increasing its order.

[0070] exist Figure 7 In the example, when D is the number of elements i The value is 10000, representing the number of elements, D. a D b The value is 100, representing the number of elements, D. c When the value is 5, the rightmost tensor in the graph is represented as the product of two smaller tensors, and the number of elements in the rightmost tensor becomes 1000, which is a reduction compared to the number of elements in the leftmost tensor.

[0071] exist Figure 7 In this example, the number of elements in a tensor is reduced by increasing its order. However, this is just one example; the number of elements can also be reduced by decreasing the tensor's order. Reducing the tensor's order to decrease its element count is a well-known technique, so a detailed explanation is omitted.

[0072] exist Figure 7 The example shows how an L-order tensor can be represented as the product of two smaller tensors. However, this is just one example; an L-order tensor can also be represented as the product of three or more smaller tensors.

[0073] The shrinking processing unit 33 of the shrinking unit 1 performs shrinking processing on multiple small tensors by introducing factor information existing between the multiple small tensors and by performing shrinking processing on the multiple small tensors. Figure 4 Step ST1 Figure 11 Step ST13).

[0074] The merging processing unit 33 outputs the merging result obtained from the merging processing to the decomposition unit 2.

[0075] Figure 8 This is an illustration of the existing contraction process disclosed in Non-Patent Document 1.

[0076] In the existing shrinking process, the leftmost factor information is moved one position to the right, thereby moving the leftmost factor information between the two smaller tensors.

[0077] Furthermore, in existing shrinking processes, all factor information is moved between the two smaller tensors by shifting all factor information to the right of the two smaller tensors. For example, the rightmost factor information is moved five positions to the left to be placed between the two smaller tensors.

[0078] The process of shifting factor information is a well-known technique, so a detailed explanation is omitted.

[0079] Existing merging processes require computational processing time to move this factor information.

[0080] exist Figure 8 In the example, after these factor information are moved, the two small tensors are condensed to incorporate all factor information and operators.

[0081] Figure 9 It means Figure 1 The diagram illustrates the shrinking, decomposition, and approximation processes in the shown computing device.

[0082] exist Figure 1 In the shown computing device, the shrinking processing unit 33 of the shrinking unit 1 does not perform the factor information movement as in conventional shrinking processing.

[0083] Originally, for factor information other than that existing between two small tensors, the further away from the two small tensors, the smaller its impact on computational accuracy. In other words, if factor information existing between two small tensors is selectively introduced, computation can be performed efficiently.

[0084] Therefore, in the shrinking process performed by the shrinking processing unit 33, factor information existing between multiple small tensors is selectively introduced into the two small tensors.

[0085] If Figure 9 Let a be the leftmost small tensor contained in the tensor set of the condensed object shown. ' i,k' σ'l Let b be the smaller tensor on the right side of the tensor group of the shrunken object. ' k'，j σ'1+1 Let the factor information existing between the two small tensors be s. ' k' Set the operator to M σ'l,σ'1+1 σl,σ1+1 The result M obtained by the shrinking process is... i,j σl,σ1+1 As shown in equation (1) below. L is a variable representing the dimension.

[0086]

[0087] Here, an example is shown where the operation applied to a tensor, i.e., the operator, is represented as a 4th-order tensor, and the operation applied to it is represented by a product-sum operation. However, this is just one example; for instance, the order of the operator may be different from 4th. Furthermore, the operation applied to it is sometimes represented by a linear equation.

[0088] Decomposition unit 2 obtains the merging result M obtained from the merging process in merging unit 1. i,j σl,σ1+1 Here, the contraction process is represented by a product sum operation. However, this is just one example, such as the preference for satisfying the commutative semi-ring axiom, and is not limited to the product sum operation.

[0089] The decomposition section 2 performs a condensation of the result M. i,j σl,σ1+1 Decomposition process ( Figure 4 Step ST2).

[0090] As a result of the contraction M i,j σl,σl+1 Decomposition processes include singular value decomposition, QR decomposition, or QLP decomposition.

[0091] Through decomposition, a tensor set containing two smaller tensors and factor information is obtained.

[0092] A tensor set containing two small tensors and factor information is represented as shown in equation (2) below.

[0093] Decomposition unit 2 outputs a tensor set containing information about two small tensors and factors to approximation unit 3.

[0094]

[0095] In equation (2), a i,k σl It is the small tensor on the left, b k,j σl+1 It is the small tensor on the right, s k It is factor information that exists between two small tensors.

[0096] The approximation part 3 obtains a tensor set containing information about two small tensors and factors from the decomposition part 2.

[0097] Approximation section 3 performs approximate processing on the factor information contained in the tensor set. Figure 4 Step ST3).

[0098] As an approximation of factor information, there is a process for removing singular values ​​close to 0 from the singular values ​​of the factor matrix representing factor information.

[0099] The number of singular values ​​in the factor matrix representing the factor information contained in the tensor group is D. ' When this happens, singular values ​​close to 0 are removed, thus setting the number of singular values ​​in the factor matrix to D (D < D< D0). ' When ), the tensor set after approximation is represented as shown in equation (3) below.

[0100]

[0101] In Embodiment 1 described above, the computing device is configured to include a shrinking unit 1. This shrinking unit 1 represents a tensor of order L (L is an integer of 2 or more) as a product of multiple tensors, i.e., smaller tensors, having fewer elements than a tensor of order L. It then performs shrinking processing on these smaller tensors, introducing factor information present between them. Therefore, compared to the computing device disclosed in Non-Patent Document 1, the computing device can shorten the computation time.

[0102] Furthermore, in Embodiment 1, the computing device is configured to include an approximation unit 3, which performs approximation processing on the factor information contained in the tensor set output from the decomposition unit 2. Therefore, the computing device can miniaturize the size of the factor information contained in the tensor set.

[0103] Implementation method 2.

[0104] In Embodiment 2, a computing device is described, which includes a reconfiguration unit 4. The reconfiguration unit 4 reconfigures the factor information, i.e., the adjacent factor information, which is the factor information that exists in the factor information other than the factor information between the multiple small tensors, for the tensor group after approximation processing by the approximation unit 3.

[0105] Figure 12 This is a structural diagram showing the computing device involved in Embodiment 2. Figure 12 In, with Figure 1 The same reference numerals indicate the same or equivalent parts, therefore detailed descriptions are omitted.

[0106] Figure 13 This is a hardware structure diagram showing the hardware of the computing device involved in Embodiment 2. Figure 13 In, with Figure 2 The same reference numerals indicate the same or equivalent parts, therefore detailed descriptions are omitted.

[0107] Figure 12 The arithmetic unit shown includes a condensation unit 1, a decomposition unit 2, an approximation unit 3, and a reconfiguration unit 4.

[0108] Reconfiguration Unit 4, for example, by Figure 13 The reconfiguration circuit 14 shown is implemented.

[0109] The reconfiguration unit 4 obtains the approximate tensor set from the approximation unit 3.

[0110] The reconfiguration unit 4 reconfigures the factor information that is adjacent to each small tensor in the factor information that exists in the factor information other than the factor information between multiple small tensors, i.e., the adjacent factor information.

[0111] exist Figure 12 In this context, it is assumed that the condensation section 1, decomposition section 2, approximation section 3, and reconfiguration section 4, which are components of the arithmetic unit, are respectively composed of... Figure 13 The dedicated hardware implementation is shown. That is, it is assumed that the arithmetic unit is implemented by the shrinking circuit 11, the decomposition circuit 12, the approximation circuit 13, and the reconfiguration circuit 14.

[0112] The shrinking circuit 11, the decomposition circuit 12, the approximation circuit 13, and the reconfiguration circuit 14 are each, for example, equivalent to a single circuit, a composite circuit, a programmable processor, a parallel programmable processor, an ASIC, an FPGA, or a combination thereof.

[0113] The components of a computing device are not limited to being implemented by dedicated hardware; a computing device can also be implemented by software, firmware, or a combination of software and firmware.

[0114] When the computing device is implemented by software or firmware, the program for causing the computer to execute each processing step in the merging unit 1, decomposition unit 2, approximation unit 3, and reconfiguration unit 4 is stored in... Figure 3 The memory 21 is shown. Then, Figure 3 The processor 22 shown executes the program stored in the memory 21.

[0115] In addition, Figure 13 The image shows an example where the various components of a computing device are implemented using dedicated hardware. Figure 3 The image shows an example of a computing device implemented by software or firmware. However, this is just one example; some components of a computing device can also be implemented by dedicated hardware, while the remaining components can be implemented by software or firmware.

[0116] Next, for Figure 12 The operation of the shown arithmetic unit will be explained. This includes, except for the reconfiguration unit 4, and... Figure 1 Since the arithmetic unit shown is the same, only the operation of the reconfiguration unit 4 will be described here.

[0117] Figure 14 This is a flowchart illustrating the tensor update method, which is a processing step of the computing device involved in Embodiment 2.

[0118] Figure 15 It means Figure 12 The diagram illustrates the shrinking, decomposition, approximation, and reconfiguration processes in the shown computing device.

[0119] For example, reconfiguration unit 4 stores adjacency factor information before the merging unit 1 performs the merging process. Figure 15 As shown, adjacency factor information is the factor information that exists in the factor information other than the factor information between multiple small tensors, and is adjacent to each small tensor.

[0120] The reconfiguration unit 4 obtains the approximate tensor set from the approximation unit 3.

[0121] like Figure 15 As shown, the reconfiguration unit 4 reconfigures the adjacency factor information of the tensor group. Figure 14 Step ST4).

[0122] The reconfiguration process of reconfiguration unit 4 will be explained in detail below.

[0123] Figure 16 This is an explanatory diagram illustrating a specific example of the reconfiguration process performed by the reconfiguration unit 4.

[0124] Figure 16 An example of reconfiguring the adjacency factor information S1 of a tensor group is shown.

[0125] The reconfiguration unit 4 performs a shrinking process on the tensor T2 adjacent to the right side of the tensor group, introducing the adjacency factor information S1 and the factor information S2. However, after shrinking, S1, T2, and S2 are still stored in memory.

[0126] Then, the reconfiguration unit 4 obtains factor information S by performing decomposition processing such as QR decomposition on the condensation result. ' 1.

[0127] Next, the reconfiguration unit 4 multiplies the right-hand small tensor T1 in the graph of the two small tensors contained in the approximate tensor set by the representation factor information S. ' The inverse matrix S of a matrix of 1 ' 1 -1 .

[0128] The reconfiguration unit 4 performs the above-described processing, thereby enabling the reconfiguration of the adjacency factor information S1 for the approximate tensor group.

[0129] In the above implementation method 2, Figure 12The computational device shown is configured to include a reconfiguration unit 4, which reconfigures the factor information adjacent to each small tensor (i.e., the adjacent factor information) within the factor information existing in the factor information between multiple small tensors, other than the factor information between them, for the tensor group after approximation processing by the approximation unit 3. Therefore, Figure 12 The computing device shown can shorten the computing time compared with the computing device disclosed in Non-Patent Document 1. Furthermore, compared with… Figure 1 Compared to the computing device shown, it can improve computing accuracy.

[0130] exist Figure 12 In the shown computing device, the reconfiguration unit 4 reconfigures the adjacency factor information of the tensor group. When reconfiguring the adjacency factor information, the reconfiguration unit 4 can also adjust the values ​​of the adjacency factor information.

[0131] When the matrix representing the adjacency factor information S1 contains small singular value components, it may cause numerical instability. Therefore, this can be addressed by removing the key dimension of the tensor, or by using the inverse matrix S of the matrix representing the adjacency factor information S1. ' 1 -1 The singular values ​​it contains are approximately zero, enabling numerically stable computation.

[0132] Implementation method 3.

[0133] In Embodiment 3, a computing device will be described, wherein the shrinking unit 1 of the computing device performs shrinking processing on multiple small tensors by introducing multiple factor information existing between the multiple small tensors.

[0134] The structure of the computing device involved in Embodiment 3 is the same as the structure of the computing device involved in Embodiment 1 or the structure of the computing device involved in Embodiment 2.

[0135] Therefore, the structural diagram of the computing device involved in Embodiment 3 is as follows: Figure 1 or Figure 12 .

[0136] Figure 17 This is an illustrative diagram representing an example of multiple factor information existing between multiple small tensors.

[0137] exist Figure 17 In the example, there are 4 factor information between the two small tensors.

[0138] exist Figure 17 In the example, the contraction part 1 shifts the first factor information from the right by 3 positions to the left, the second factor information from the right by 2 positions to the left, and the third factor information from the right by 1 position to the left. The process of shifting factor information is a well-known technique, so a detailed explanation is omitted.

[0139] Therefore, as Figure 18 As shown, the four factor information exists between two adjacent small tensors.

[0140] Figure 18 This is an explanatory diagram showing the factor information after the shift.

[0141] The shrinking section 1 performs shrinking processing on two small tensors by introducing four factor information that exists between the two small tensors.

[0142] In the above-described embodiment 3, the computing device is configured as a shrinking unit 1 to perform shrinking processing on multiple small tensors, incorporating multiple factor information existing between the multiple small tensors. Therefore, the computing device can perform shrinking processing on multiple small tensors even when multiple factor information exists between the multiple small tensors.

[0143] Implementation method 4.

[0144] In Embodiment 4, a computing device is described in which the shrinking unit 1 performs shrinking processing on multiple small tensors by introducing factor information existing between the multiple small tensors only when the computing processing time takes priority over the computing accuracy.

[0145] The structure of the computing device involved in Embodiment 4 is the same as the structure of the computing device involved in Embodiment 1 or the structure of the computing device involved in Embodiment 2.

[0146] Therefore, the structural diagram of the computing device involved in Embodiment 4 is as follows: Figure 1 or Figure 12 .

[0147] Figure 19 This is a flowchart illustrating the shrinking process of the shrinking unit 1 in the computing device according to Embodiment 4.

[0148] Next, the operation of the arithmetic device according to Embodiment 4 will be described. The operation of the arithmetic device according to Embodiment 1 is the same as that of the arithmetic device except for the shrinking section 1; therefore, only the operation of the shrinking section 1 will be described here.

[0149] Users can set the processing time to take precedence over the precision of the operation, or vice versa, as settings for the computing device.

[0150] Figure 20A This is an explanatory diagram showing a structural example of a switching object.

[0151] Figure 20B This is an illustrative diagram showing an example of a user interface used for settings.

[0152] It can library computations that use tensor networks and switch operations according to user specifications.

[0153] As a switch Figure 20A The parameters of the structure on the left (emphasizing computational precision) and the structure on the right (emphasizing speed: prioritizing computational processing time) shown in the diagram include, for example, whether to prioritize high-speed computation, whether to use all operators, and whether to perform all swaps. A swap refers to the physical index σ. i The swaps are performed sequentially, but for high accuracy, it is sometimes preferable to perform all swaps.

[0154] exist Figure 20B The user interface shown allows users to set, for example, the range of tensor updates, the range of mini-tensors representing an L-order tensor, the number of mini-tensors representing an L-order tensor, and the number of factor information used for updates. Figure 20B In the example, it is possible to set the number of factor information used for updating in the factor information existing to the left of the second small tensor from the left in the graph, and the number of factor information used for updating in the factor information existing to the right of the third small tensor from the left in the graph.

[0155] The number of factor information required can also be changed according to the numbering of the small tensors representing the L-order tensor, thus enabling the setting of variable values. Although omitted in Figure 20, it is also possible to set the numbering of the exchanges used for updates.

[0156] Users can also configure computing devices to anticipate increased computing speed. For example, predictions based on AI (Artificial Intelligence) can be used to anticipate increased computing speed.

[0157] If a setting prioritizes computation time over computation precision ( Figure 19 Step ST21: If yes), then similarly to the computing device of embodiments 1 to 3, the shrinking unit 1 performs shrinking processing on multiple small tensors by introducing factor information existing between the multiple small tensors. Figure 19 Step ST22).

[0158] If a setting prioritizes computational precision over computational processing time is implemented ( Figure 19 Step ST21: If not), then similarly to the processing device of Non-Patent Document 1, the shrinking unit 1 performs shrinking processing on multiple small tensors by introducing all factor information that has a connection relationship with each small tensor. Figure 19 Step ST23).

[0159] In Embodiment 4 described above, the computing device is configured such that, when processing time takes precedence over processing precision, the shrinking unit 1 performs shrinking processing on multiple small tensors by introducing factor information existing between the multiple small tensors; and when processing precision takes precedence over processing time, the shrinking unit 1 performs shrinking processing on multiple small tensors by introducing all factor information that has a connection relationship with each small tensor. Therefore, the computing device can perform shrinking processing that prioritizes either processing precision or processing time.

[0160] In the computing device according to Embodiment 4, if a setting prioritizes computing processing time over computing precision, the shrinking unit 1 performs shrinking processing on multiple small tensors by introducing factor information existing between the multiple small tensors. However, this is only one example. The shrinking unit 1 may also perform shrinking processing on multiple small tensors by introducing factor information existing between the multiple small tensors only when a faster computing processing time can be expected, even when a setting prioritizes computing processing time over computing precision.

[0161] As a case where the computational processing time can be expected to be high-speed, for example, when the number of times including the movement factor information is above a threshold.

[0162] Implementation method 5.

[0163] In Embodiment 5, a computing device in which the shrinking unit 1 performs shrinking processing on multiple shrinking object tensors in parallel when there are multiple shrinking object tensors containing multiple small tensors will be described.

[0164] The structure of the computing device in Embodiment 5 is the same as that of the computing device in Embodiment 1 or the computing device in Embodiment 2.

[0165] Therefore, the structural diagram of the computing device involved in Embodiment 5 is as follows: Figure 1 or Figure 12 .

[0166] Figure 21 is an illustrative diagram of an example of multiple shrunk object tensors that are shrunk in parallel.

[0167] Figure 21A Four condensed object tensors are shown. Figure 21B Two condensed object tensors are shown.

[0168] exist Figure 21A In the example, the shrinking part 1 performs shrinking processing on four shrinking object tensors in parallel.

[0169] exist Figure 21B In the example, the shrinking part 1 performs shrinking processing on two shrinking object tensors in parallel.

[0170] The shrinking process of the computing device in Embodiment 5 is the same as that of the computing devices in Embodiments 1 to 4.

[0171] When the computing device according to Implementation 5 performs shrinking processing on multiple shrinking object tensors, multiple shrinking processes are performed in parallel.

[0172] According to Embodiment 5 above, the computing device involved in Embodiment 3 is configured such that there are multiple shrinking target tensors containing multiple small tensors, and the shrinking unit 1 performs shrinking processing on the multiple shrinking target tensors in parallel. Therefore, compared with the computing device involved in Embodiment 1, the computing device involved in Embodiment 3 can achieve a faster computing processing time.

[0173] In embodiments 1 to 5, the shape of the product of small tensors is shown as follows: Figure 22A The example shown is a one-dimensional shape. However, this is just one example; the shape of the product of small tensors can vary even further. Figure 22B As shown, a two-dimensional, two-row shape can also be applied. Furthermore, the shape of the product of small tensors, even if... Figure 22C As shown, a two-dimensional, two-column shape can also be applied. Furthermore, the shape of the product of small tensors, even if... Figure 22D Larger shapes, such as two-dimensional rows or two-dimensional columns, as shown, can also be used.

[0174] When the product of small tensors has a one-dimensional shape or a two-dimensional two-row shape, the same path can be repeated during the exchange, thus enabling efficient updating of factor information.

[0175] For example, when using multiple operators that swap long distances to update a continuous interval, it is particularly preferable to choose an update path that points towards the longer side, given the option to select the update path. If the longer side consists of two rows, choose an update path that points towards the rows; if the longer side consists of two columns, choose an update path that points towards the columns. Thus, by using the previous operator, the updated factor information can be reflected in the next operator, enabling more precise calculations.

[0176] Figure 22A This is an illustrative diagram illustrating an example where the shape of the product of small tensors is a one-dimensional shape.

[0177] Figure 22B This is an illustrative diagram illustrating an example where the product of small tensors is a two-dimensional, two-row shape.

[0178] Figure 22C This is an illustrative diagram illustrating an example where the product of small tensors is a two-dimensional, two-column shape.

[0179] Figure 22DThis is an illustrative diagram representing a larger example of two-dimensional rows or two-dimensional columns.

[0180] However, it can also be a small tensor product composed of one or two rows of shapes, or a small tensor product that partially contains three or more rows of shapes.

[0181] When the product of small tensors has a two-dimensional shape, the shape of the product of small tensors is not limited to a two-dimensional quadrilateral. For example, it can also be a polygon, a bond intersection, or an N-dimensional solid shape.

[0182] Furthermore, this disclosure allows for free combination of various embodiments, modification of any constituent element of each embodiment, or omission of any constituent element in each embodiment.

[0183] Industrial availability

[0184] This disclosure applies to computing devices and tensor update methods.

[0185] Explanation of reference numerals in the attached figures

[0186] 1... Shrinking section; 2... Decomposition section; 3... Approximation section; 4... Reconfiguration section; 11... Shrinking circuit; 12... Decomposition circuit; 13... Approximation circuit; 14... Reconfiguration circuit; 21... Memory; 22... Processor; 31... Tensor acquisition section; 32... Tensor representation section; 33... Shrinking processing section.

Claims

1. A computing device, characterized in that, It has a shrinking part that represents an L-order tensor as a product of multiple tensors, i.e., smaller tensors, having fewer elements than the L-order tensor, and performs shrinking processing on the multiple smaller tensors to introduce factor information existing between the multiple smaller tensors, where L is an integer greater than 2.

2. The computing device according to claim 1, characterized in that, The shrinking section performs shrinking processing on the plurality of small tensors by introducing factor information existing between the plurality of small tensors and by applying operators to the plurality of small tensors.

3. The computing device according to claim 2, characterized in that, It has a decomposition unit that performs decomposition processing on the merging result obtained by the merging process of the merging unit and outputs a tensor group containing multiple small tensors and factor information.

4. The computing device according to claim 3, characterized in that, It has an approximation unit that performs approximate processing on the factor information contained in the tensor set output from the decomposition unit.

5. The computing device according to claim 4, characterized in that, The system includes a reconfiguration unit that reconfigures the factor information adjacent to each small tensor, i.e., the adjacent factor information, in the factor information existing in the factor information between the plurality of small tensors, other than the factor information between the multiple small tensors, for the tensor group after approximation processing by the approximation unit.

6. The computing device according to claim 1, characterized in that, The shrinking section performs shrinking processing on the plurality of small tensors by introducing multiple factor information existing between the plurality of small tensors.

7. The computing device according to claim 1, characterized in that, When prioritizing computational processing time over computational precision, the shrinking section performs shrinking processing on the plurality of small tensors, incorporating factor information existing between the plurality of small tensors. When prioritizing computational precision over computational processing time, the shrinking unit performs shrinking processing on the plurality of small tensors by introducing all factor information that has a connection relationship with each small tensor.

8. The computing device according to claim 1, characterized in that, It has multiple condensed object tensors containing the multiple smaller tensors. The shrinking unit performs the shrinking process on the plurality of shrinking object tensors in parallel.

9. The computing device according to claim 1, characterized in that, The product of the small tensors can be a one-dimensional shape, a two-dimensional 2-row shape, or a two-dimensional 2-column shape.

10. A tensor update method, characterized in that, The shrinking part represents an L-order tensor as a product of multiple tensors, i.e., smaller tensors, with fewer elements than the L-order tensor. The shrinking part then introduces factor information between the multiple smaller tensors, where L is an integer greater than 2.

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