Determining parasitic elements of interconnects of an electronic circuit layout

Abstract

The present invention relates to a method for determining a parasitic element of an interconnect of an electronic circuit layout. To facilitate the determination of the parasitic element, the method comprises determining an interconnect parasitic model for the interconnect from a plurality of interconnect parasitic models based on a comparison between at least one performance indicator associated with each interconnect parasitic model, and determining the parasitic element of the interconnect based on the determined interconnect parasitic model.

Description

Technical Field

[0001] This disclosure generally relates to electronic design automation (EDA), and more specifically to the identification of parasitic elements interconnected in electronic circuit layouts. Such electronic design automation systems and parasitic element identification systems are collectively referred to herein as product systems. Background Technology

[0002] The development of electronic devices with electronic circuitry typically involves a series of steps known as the design flow. This design flow usually begins with a specification for the new electronic device to be implemented using electronic circuitry, such as a printed circuit board (PCB) or an integrated circuit (IC). The specification of the electronic device can be transformed into an electronic device design, such as a netlist, for example by schematic capture tools or by synthesizing the logic design (sometimes called a register-transfer-level (RTL) description of the electronic device). The netlist can be specified in Electronic Design Exchange Format (EDIF) or a similar format, which describes the nets or connections between various components or parts in the electronic device design.

[0003] The design process can continue by validating the functionality of the electronic device design, for example, through simulation, modeling, or prototyping the electronic device design and verifying that the simulation or modeling results correspond to the expected output from the electronic device design. Functionality can also be validated by performing formal verification or static checks using one or more solvers on various properties of the electronic device design that may be problematic during the operation of the electronic device built using the design.

[0004] Once the electronic device design is functionally validated, the design flow can utilize logic design to generate a layout design for the electronic device. This process can be implemented in different ways, but is typically achieved using a layout tool that places and interconnects individual components or parts into a representation of the electronic circuit. For example, layout tools implemented in computing systems can present a graphical view of the electronic circuit and allow designers to use the layout tool to place components from a library onto the electronic circuit in the graphical view.

[0005] The layout of electronic circuits can then be physically verified, for example, to address functional yield challenges in IC design. Such physical verification helps ensure accurate circuit behavior with precise device parameters, while parasitic extraction tools help provide accurate and high-performance extraction for all design styles. In some respects, this patent application disclosure focuses primarily on the physical verification of electronic circuit layouts.

[0006] Currently, there are product systems and solutions that support the identification of parasitic elements interconnected in electronic circuit layouts. Such product systems can benefit from improvements. Summary of the Invention

[0007] Various disclosed embodiments include methods and computer systems that can be used to facilitate the identification of parasitic elements interconnected in an electronic circuit layout.

[0008] According to a first aspect of the invention, a computer-implemented method for determining parasitic elements interconnected in an electronic circuit layout may include: determining an interconnect parasitic model from a plurality of interconnect parasitic models based on a comparison between at least one performance metric associated with each of a plurality of interconnect parasitic models; and determining the interconnect parasitic elements based on the determined interconnect parasitic model.

[0009] According to a second aspect of the invention, a computer system can be arranged and configured to perform the steps of the computer-implemented method according to the first aspect.

[0010] According to the third aspect, a computer program product may include computer program code that, when executed by a computer system according to the second aspect, causes the computer system to perform the method according to the first aspect.

[0011] According to the fourth aspect, a computer-readable medium may include a computer program product according to the third aspect. For example, the described computer-readable medium may be non-transitory and may also be a software component on a storage device.

[0012] The technical features of this disclosure have been broadly outlined above to enable those skilled in the art to better understand the detailed description that follows. Additional features and advantages of this disclosure that form the subject matter of the claims will be described below. Those skilled in the art will understand that they can readily utilize the disclosed concepts and specific embodiments as a basis for determining parasitic elements interconnected in an electronic circuit layout, or for achieving the same purpose of this disclosure. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure in its broadest form.

[0013] Furthermore, before proceeding with the detailed description below, it should be understood that various definitions of certain words and phrases are provided throughout this document, and those skilled in the art will understand that such definitions apply in many (if not most) cases to the prior and future uses of such defined words and phrases. While some terms may encompass various embodiments, the appended claims may expressly limit these terms to specific embodiments.

[0014] The implementation method will be described in more detail below. Attached Figure Description

[0015] Figures 1-2 Functional block diagrams of first and second example systems are depicted to facilitate the determination of parasitic elements interconnected in the electronic circuit layout of a product system.

[0016] Figures 3-7 Different aspects of various exemplary methods for facilitating the determination of parasitic elements interconnected in the electronic circuit layout of a product system are described.

[0017] Figures 8-9 Functional block diagrams of third and fourth example systems are depicted to facilitate the determination of parasitic elements interconnected in the electronic circuit layout of a product system.

[0018] Figures 10-11 Flowcharts are provided for example methods of facilitating the identification of parasitic elements interconnected in the electronic circuit layout of a product system.

[0019] Figure 12 A block diagram of a data processing system in which implementation methods can be carried out is depicted. Detailed Implementation

[0020] Various techniques relating to systems and methods for determining parasitic elements interconnected in an electronic circuit layout of a product system will now be described with reference to the accompanying drawings, in which the same reference numerals consistently denote the same elements. The drawings discussed below and the various embodiments used to describe the principles of this disclosure in this patent document are merely illustrative and should not be construed in any way as limiting the scope of this disclosure. Those skilled in the art will understand that the principles of this disclosure can be implemented in any suitably arranged device. It should be understood that functions described as being performed by certain system elements can be performed by multiple elements. Similarly, for example, an element can be configured to perform functions described as being performed by multiple elements. Numerous innovative teachings of this patent document will be described with reference to exemplary, non-limiting embodiments.

[0021] refer to Figure 1 This document depicts a functional block diagram of a first example computer system or data processing system 100 that facilitates the determination of parasitic elements 124 of interconnects 122 of an electronic circuit layout 120. The processing system 100 may include an electronic circuit verification (ECV) system 118, which, in some examples, may include at least one processor 102 configured to execute at least one application software component 106 from memory 104 accessed by the processor 102. The application software component 106 may be configured (i.e., programmed) to cause the processor 102 to perform the various actions and functions described herein. For example, the described application software component 106 may include one or more components and / or corresponding to an application for determining parasitic elements 124 of interconnects 122 of the electronic circuit layout 120, wherein the application software component 106 may, for example, be configured to generate product data and store it in a data repository 108 such as a database.

[0022] For example, ECV system 118 may be cloud-based, internet-based, and / or operated by a provider of parasitic elements 124 that support the interconnection 122 that determines the electronic circuit layout 120. In some examples, a user may be located near or away from ECV system 118, such as anywhere else, and may connect to ECV system 118 using a mobile device, such as via the internet, where the mobile device may include input device 110 and display device 112. In some examples, ECV system 118 may be installed and run on a user's device, such as a computer, laptop, tablet, local computing facility, or the like.

[0023] It should be understood that determining the parasitic elements 124 of the interconnects 122 of an electronic circuit layout 120 can be a challenging and time-consuming process, potentially requiring highly skilled engineers with years of training. For example, it may require advanced knowledge of electronics, physics, and other scientific fields, or the conscious selection of numerous options, each involving many manual steps—a lengthy and inefficient process. Furthermore, depending on other methods, determining the parasitic elements 124 of the interconnects 122 of a more complex electronic circuit layout 120 can take days or weeks even on a high-performance computer, potentially leading to incorrectly determined parasitic elements 124, or even making it simply infeasible.

[0024] To achieve enhanced determination of parasitic elements 124 of the interconnects 122 of the electronic circuit layout 120, the described product system or processing system 100 may include at least one input device 110 and at least one display device 112 (such as a display screen). The described processor 102 may be configured to generate a graphical user interface (GUI) 114 via the display device 112. Such a GUI 114 may include GUI elements such as buttons, links, search boxes, lists, text boxes, images, and scroll bars, which a user can use to provide input via the input device 110, thereby causing determination of the parasitic elements 124 of the interconnects 122 of the electronic circuit layout 120. For example, the GUI 114 may include an ECV user interface (UI) 116 provided to the user.

[0025] In an exemplary embodiment, in order to determine parasitic elements 124 of interconnects 122 of electronic circuit layout 120, application software component 106 and / or processor 102 may be configured to determine interconnect parasitic models 128 from a plurality of interconnect parasitic models 128 of interconnect 122 based on a comparison of at least one performance metric 130 associated with each interconnect parasitic model 128.

[0026] Here, electronic circuit layout 120 can be understood, for example, as the layout design for an electronic device obtained after the functional verification step and the completion of the placement step in the design flow described above. The electronic circuit 152 corresponding to electronic circuit layout 120 may, for example, include an integrated circuit (also called a microchip, chip, or IC), a small electronic device composed of multiple interconnected electronic components such as transistors, resistors, and capacitors. These components can be etched onto a small piece of semiconductor material (typically silicon). Integrated circuits are used in a wide range of electronic devices, including computers, smartphones, and televisions, to perform various functions such as processing and storing information. They have had a significant impact on the field of electronics by enabling device miniaturization and enhanced functionality. In some examples, electronic circuit 152 corresponding to electronic circuit layout 120 may include a printed circuit board (PCB) (also called a printed wiring board (PWB)), a medium used to connect or “wire” the aforementioned components to each other in a circuit. In some examples, electronic circuit 152 and the corresponding electronic circuit layout 120 may include millions or even billions of the mentioned components, such as transistors.

[0027] For example, a corresponding interconnect 122 can be understood as a wiring or one or more metallization layers through which various components (such as transistors, capacitors, resistors, etc.) can be electrically interconnected using wiring on the wafer. In some examples, an electronic circuit layout 120 having multiple interconnects 122 may include the geometric, physical, or material properties of the corresponding interconnects 122.

[0028] Furthermore, in the context of an electrical network, parasitic element 124 can be understood, for example, as a circuit element present in an electrical component or interconnection 122 but undesirable for its intended purpose, such as a resistor R, an inductor L, or a capacitor C. For example, a resistor is designed to have resistance but may also have undesirable parasitic capacitance. Parasitic element 124 can be modeled, for example, as a lumped component in an equivalent circuit. Here, the lumped element model (also called a lumped parameter model or lumped component model) is a simplified representation of a physical system or circuit that assumes all components are concentrated at a single point and that their behavior can be described by an idealized mathematical model. The lumped element model simplifies the description of system or circuit behavior to a topology.

[0029] The interconnect parasitic model 128 can be, for example, a simplified representation or model of the parasitic elements 124 of the corresponding interconnect 122. In some examples, the interconnect parasitic model 128 of the corresponding interconnect 122 can be very simple, considering only one or more resistors R and one or more capacitors C. More complex parasitic models 128 of the corresponding interconnect 122 can, for example, consider one or more resistors R, one or more inductors L, and one or more capacitors C. Furthermore, the interconnect parasitic model 128 of the corresponding interconnect 122 can, for example, be a so-called full-wave model, which in many examples can provide an accurate representation or model of the parasitic elements 124 of the corresponding interconnect 122. For the full-wave model, the corresponding interconnect 122 can be modeled using the finite element method (FEM), where the material and three-dimensional geometric details of the corresponding interconnect 122 need to be defined. Here, multiple interconnect parasitic models 128 can, for example, include at least two interconnect parasitic models 128, such as two or three of the models described above considering resistors R, capacitors C, and optionally inductors L, or a full-wave model. Additionally, other suitable interconnect parasitic models 128 can also be used.

[0030] A corresponding performance metric 130 associated with each interconnect parasitic model 128 may, for example, indicate the corresponding performance 136 of the electronic circuit layout 120 when the corresponding interconnect 122 is modeled using the corresponding interconnect parasitic model 128. For example, if a given interconnect 122 is modeled using two different interconnect parasitic models 128-1 and 128-2, then two corresponding performance metrics 130-1 and 130-2 may indicate the corresponding performance 136-1 and 136-2 of the electronic circuit layout 120 using the two different interconnect parasitic models 128-1 and 128-2 for that interconnect 122. In some examples, the corresponding performance 136 of the corresponding interconnect 122 may be considered.

[0031] In some examples, performance 136 or performance metric 130 may include delay, gain, noise, IR drop, and / or skew associated with the corresponding interconnect 122 or electronic circuit layout 120. Here, delay and noise may be, for example, signal delay and signal noise, respectively. These quantities are explained in more detail below. For example, noise associated with electronic circuit layout 120 may be determined based on two or three different interconnect parasitic models 128. Thus, two or three different noise values ​​may be determined and compared as described below.

[0032] Here, one of several interconnect parasitic models 128 can be selected by comparing the corresponding performance metrics 130. In some examples, the interconnect parasitic model 128 that best matches the corresponding (“modeled” performance metric 130 with the corresponding true performance metric 130 can be selected. Here, the true performance metric 130 may involve the (as accurate as possible) determination of the performance metric 130 of the corresponding interconnect 122 or electronic circuit layout 120, for example, using a field solver that calculates electromagnetic parameters by directly solving Maxwell's equations. In other examples, one of the least complex interconnect parasitic models 128 that has an acceptable consistency between the corresponding (“modeled” performance metric 130 and the corresponding performance metric 130 of the most complex parasitic model 128 can be selected. In these examples, if the less complex interconnect parasitic model 128 cannot provide an acceptable consistency between the corresponding (“modeled” performance metric 130 and the corresponding performance metric 130 of the most complex parasitic model 128, then the most complex interconnect parasitic model 128 can be selected.

[0033] In some examples, an interconnect parasitic model 128 may be selected that provides acceptable consistency between the corresponding (“modeled”) performance metric 130 and the corresponding performance metric 130 of the most complex parasitic model 128 or the corresponding true performance metric 130, while involving acceptable computational resources (e.g., for determining the parasitic elements 124 of the interconnect 122). In these other examples, a reasonable trade-off between accuracy and computational overhead associated with the interconnect parasitic model 128 may be a favorable criterion for determining the most suitable interconnect parasitic model 128.

[0034] In some examples, application software component 106 and / or processor 102 may be further configured to determine parasitic elements 124 of interconnect 122 based on the determined parasitic model 128.

[0035] The determined parasitic model 128 can then be used to determine, for example, directly or indirectly, the parasitic elements 124 of the interconnect 122. For example, the parasitic elements 124 of the interconnect 122 may include one or more resistors R, one or more inductors L, and one or more capacitors C, wherein the corresponding values ​​of these parasitic elements 124 can be determined based on the determined parasitic model 128. An example of determining the parasitic elements 124 of the interconnect 122 based on the determined parasitic model 128 is provided below.

[0036] In some examples, application software component 106 and / or processor 102 may be further configured to: provide an electronic circuit layout 120 including a plurality of interconnects 122; determine at least one characteristic 126 of a corresponding interconnect 122; assign at least a first interconnect parasitic model 128-1 and a second interconnect parasitic model 128-2 to the corresponding interconnect 122; determine corresponding performance metrics 130-1, 130-2 of the first interconnect parasitic model 128-1 and the second interconnect parasitic model 128-2 of the corresponding interconnect 122 using the corresponding characteristic 126 of the corresponding interconnect 122; select at least one of the first interconnect parasitic model 128-1 and the second interconnect parasitic model 128-2 for the corresponding interconnect 122 using the corresponding performance metrics 130-1, 130-2; and determine parasitic elements 124 of the corresponding interconnect 122 using an extraction tool 132 corresponding to the corresponding selected interconnect parasitic model 128.

[0037] In some examples, providing an electronic circuit layout 120 including multiple interconnects 122 may involve the user or engineer determining the electronic circuit layout 120 and the multiple interconnects 122. The electronic circuit layout 120 and the multiple interconnects 122 may be provided and stored in a data repository 108 of the ECV system 118, for example, by a user using the ECV UI 116 and / or input device 110. In some examples, the electronic circuit layout 120 and the multiple interconnects 122 may be received, for example, via an application programming interface (API) from another data source 108'. Similar methods may also be used to provide other input information, as explained in more detail below.

[0038] To determine at least one characteristic 126 of a corresponding interconnect 122, an electronic circuit layout 120 comprising a plurality of interconnects 122 can be used to extract the corresponding characteristic 126 of the corresponding interconnect 122. The corresponding characteristic 126 of the corresponding interconnect 122 may, for example, include geometric, physical, or material properties of the corresponding interconnect 122. The geometric properties of the corresponding interconnect 122 may include the geometry of the circuit path, such as the length l, width w, and thickness of the corresponding interconnect 122, and if the corresponding interconnect 122 is composed of two or more interconnect portions, it includes the individual portions constituting the corresponding interconnect 122. The physical properties of the corresponding interconnect 122 may, for example, include the resistance R or inductance L of the corresponding interconnect 122. The material properties of the corresponding interconnect 122 may include the electrical conductivity, magnetic permeability, or thermal conductivity of the material used to make the corresponding interconnect 122.

[0039] For example, at least one characteristic 126 of the corresponding interconnect 122 includes sufficient information about the corresponding interconnect 122 to determine an interconnect parasitic model 128 that can characterize the parasitic elements 124 of the corresponding interconnect 122 fairly well, as will be explained in more detail below. In some examples, the corresponding characteristic 126 may be provided in advance and stored in a data repository 108.

[0040] For example, application software component 106 and / or processor 102 may be further configured to assign at least a first interconnect parasitic model 128-1 and a second interconnect parasitic model 128-2 to the corresponding interconnect 122.

[0041] As described above, the corresponding interconnect parasitic model 128 may, for example, be a simplified representation or model of the parasitic element 124 of the corresponding interconnect 122. At least two different interconnect parasitic models 128-1 and 128-2 are assigned to the corresponding interconnect 122, wherein these at least two interconnect parasitic models 128-1 and 128-2 may have advantages and disadvantages, such as different levels of accuracy in modeling the true behavior of the corresponding interconnect 122, and the simplicity or complexity of the corresponding interconnect parasitic model 128 requiring more or less computational resources for subsequently determining the parasitic element 124 of the corresponding interconnect 122.

[0042] Furthermore, as mentioned above, at least two of the first interconnect parasitic model 128-1 and the second interconnect parasitic model 128-2 may, for example, include two or three of the aforementioned models that take into account resistance R, capacitance C, and optional inductance L, or a full-wave model. Alternatively, other suitable interconnect parasitic models 128 may also be used.

[0043] In another example, application software component 106 and / or processor 102 may be further configured to use the corresponding characteristics 126 of the corresponding interconnect 122 to determine the corresponding performance metrics 130-1, 130-2 of the first interconnect parasitic model 128-1 and the second interconnect parasitic model 128-2 of the corresponding interconnect 122.

[0044] For a given interconnect 122, the determined characteristic 126 can, for example, be used as input to the corresponding interconnect parasitic models 128-1, 128-2, thereby obtaining two or more more or less accurate models of interconnect 122. Different interconnect parasitic models 128-1, 128-2 for a given interconnect 122 can be used as input to calculate corresponding performance 136-1, 136-2 or corresponding performance metrics 130-1, 130-2, which may include, for example, delay, gain, noise, IR drop, and / or skew associated with the given interconnect 122 or electronic circuit layout 120, as already mentioned above.

[0045] In some examples, application software component 106 and / or processor 102 may be further configured to select at least one of a first interconnect parasitic model 128-1 and a second interconnect parasitic model 128-2 for the corresponding interconnect 122 using corresponding performance metrics 130-1, 130-2.

[0046] For example, performance metrics 130-1 and 130-2 of a given interconnect 122 can be compared with each other or with the corresponding true performance metric 130 to select one of the interconnect parasitic models 128-1 and 128-2 to be used. As mentioned above, one of the least complex interconnect parasitic models 128 with acceptable consistency between the corresponding (“modeled” performance metric 130 and the corresponding performance metric 130 of the most complex parasitic model 128 can be selected; otherwise, if there is no acceptable consistency, the most complex interconnect parasitic model 128 can be selected. Furthermore, the interconnect parasitic model 128 with the best consistency between the corresponding (“modeled” performance metric 130 and the corresponding true performance metric 130 can be selected, wherein the true performance metric 130 may involve the (as accurate as possible) determination of the performance metric 130 of the corresponding interconnect 122 or electronic circuit layout 120.

[0047] To select one of the interconnect parasitic models 128-1 and 128-2, one can, for example, use the reasonable trade-offs between accuracy and computational cost associated with interconnect parasitic model 128 mentioned above.

[0048] For example, application software component 106 and / or processor 102 may be further configured to use parasitic extraction tool 132 corresponding to the corresponding selected interconnect parasitic model 128 to determine the parasitic elements 124 of the corresponding interconnect 122.

[0049] While the impact of wiring was negligible in early integrated circuits, and wires were not considered electrical components of the circuit, below the 0.5-micron technology node, the resistance and capacitance of interconnects 122 began to have a significant impact on circuit performance 136. As process technology continues to shrink, the inductive effect of interconnects 122 also becomes important.

[0050] For this reason, parasitic extraction tools 132 have been developed and are commercially available from various vendors. For example, parasitic extraction tools 132 include a field solver and an approximate solution. The field solver calculates electromagnetic parameters by directly solving Maxwell's equations, thus providing a physically accurate solution. However, due to the high computational burden, the field solver is only suitable for very small designs or a portion of a design. In some examples, an approximate solution with pattern matching techniques may be the only feasible method for extracting parasitic parameters for a complete modern integrated circuit design.

[0051] According to the proposed method, for a given interconnect 122, a parasitic extraction tool 132 can be used to determine the parasitic elements 124 of the given interconnect 122, wherein the parasitic extraction tool 132 corresponds to a selected interconnect parasitic model 128 for the interconnect 122. Therefore, for example, if the selected interconnect parasitic model 128 is simple and only considers one or more resistors R and one or more capacitors C, a correspondingly simple approximate solution parasitic extraction tool 132 considering only one or more resistors R and one or more capacitors C can be used. Furthermore, for example, if the selected interconnect parasitic model 128 is more complex and considers one or more resistors R, one or more inductors L, and one or more capacitors C, a correspondingly more complex approximate solution parasitic extraction tool 132 considering one or more resistors R, one or more inductors L, and one or more capacitors C can be used. Furthermore, if the selected interconnect parasitic model 128 is a full-wave model, a correspondingly precise approximate solution, full-wave, or even field solver parasitic extraction tool 132 can be used, which considers correspondingly precise effects.

[0052] Therefore, in some examples, the proposed method allows for the determination of parasitic elements 124 of the corresponding interconnect 122 with sufficient accuracy by using a parasitic extraction tool 132 corresponding to the selected interconnect parasitic model 128, while minimizing the computational overhead involved. Thus, the proposed method can, for example, help ensure accurate circuit behavior with sufficiently precise device parameters, while cleverly using appropriate, accurate, and efficient parasitic extraction tools to provide the required high-precision and efficient extraction for all design styles.

[0053] For example, application software component 106 and / or processor 102 may also be configured to provide application scenario 134 of electronic circuit layout 120; and further use application scenario 134 to determine corresponding performance indicators 130 of corresponding interconnects 122, wherein application scenario 134 includes digital application scenario 134 and analog application scenario 134, and wherein the corresponding performance 136 includes delay, gain, noise, IR drop and / or skew for digital application scenario 134 and / or analog application scenario 134.

[0054] Here, in some examples, digital application scenario 134 and analog application scenario 134 can be understood as making electronic circuit 152 corresponding to electronic circuit layout 120 usable to generate all process digital or analog signals. Analog signals are, for example, signals with continuous time that represent some other quantity (i.e., similar to another quantity). For example, in analog audio signals, the instantaneous signal voltage changes continuously with the pressure of the sound wave. Digital signals can be, for example, discrete-time, quantized amplitude signals. In other words, it can be a sampled signal consisting of samples of values ​​taken from a discrete set (a countable set that can be mapped to a subset of integers). If the discrete set is finite, the discrete values ​​can be represented by digital words of finite width. Most typically, these discrete values ​​can be represented as fixed-point words (proportional to or compressed with the waveform value) or floating-point words.

[0055] Delays can include, for example, group delay and phase delay, which are two related ways of describing how the frequency components of a signal are delayed over time as it passes through a linear time-invariant system (such as a microphone, coaxial cable, amplifier, loudspeaker, telecommunications system, Ethernet cable, digital filter, or analog filter). Phase delay describes the time offset of the sinusoidal component (steady-state sine wave). Group delay describes the time offset of the envelope of a wave packet, which is a group or set of oscillations propagating together around a frequency, for example, formed by multiplying a sine wave by an envelope (such as a cone function) (amplitude modulation). These delays are typically frequency-dependent, meaning that different frequency components experience different delays. As a result, the waveform of the signal experiences distortion as it passes through the system. This distortion can cause problems such as poor fidelity in analog video and analog audio, or high bit error rates in digital bitstreams.

[0056] Gain is a measure of the ability of a two-port circuit (typically an amplifier) ​​to increase the power or amplitude of a signal from its input port to its output port by adding energy from a power source conversion to the signal. Gain is generally defined as the average ratio of the signal amplitude or power at the output port to the amplitude or power at the input port, and is usually expressed in logarithmic decibels (dB) ("dB gain"). A gain greater than one (greater than zero dB) is considered amplification and is a defining property of active components or active circuits, while passive circuits will have a gain less than one.

[0057] Noise can be understood, for example, as unwanted disturbances in an electrical signal.

[0058] The IR drop is related to the voltage drop across the network or electronic circuit layout 120, which is caused by the resistance of the interconnects 122 that make up the network. For example, an excessive voltage drop in the power grid can reduce the switching speed and noise margin of the circuit and inject noise that may cause functional failure.

[0059] Skew, especially clock skew (sometimes called timing skew), can be understood, for example, as a phenomenon in synchronous digital circuit systems where clock signals from the same source arrive at different components at different times due to gate delays or (in more advanced semiconductor technology) wire signal propagation delays. The instantaneous difference between the readings of any two clocks is called their skew.

[0060] In some examples, the corresponding performance 136 includes delay or IR drop for digital application scenario 134, and gain, noise, IR drop and / or skew for analog application scenario 134.

[0061] For example, if delay is used as a performance metric 130, the following values ​​can be observed in the electronic circuit layout 120. Modeling a given interconnect 122 of the electronic circuit layout 120 using a simple interconnect parasitic model 128-1 (considering one or more resistors R and one or more capacitors C) and employing the corresponding simple, approximate solution parasitic extraction tool 132-1, the total delay is 5 ps. Modeling a given interconnect 122 of the electronic circuit layout 120 using a more complex interconnect parasitic model 128-2 (considering one or more resistors R, one or more inductors L, and one or more capacitors C) and employing the corresponding more complex, approximate solution parasitic extraction tool 132-2, the total delay is 5.001 ps. Modeling a given interconnect 122 of the electronic circuit layout 120 using a full-wave interconnect parasitic model 128-3 and employing the corresponding complex, full-wave parasitic extraction tool 132-3, the total delay is 5.005 ps.

[0062] In this example, since the difference in the total delay determined as performance metric 130 is relatively small, it may not be necessary to select the full-wave parasitic extraction tool 132-3. Therefore, the simple, approximate solution parasitic extraction tool 132-1 can be selected.

[0063] For example, the corresponding characteristics 126 of the corresponding interconnect 122 include at least one of the wiring length l, the minimum width w of the metal layer, and the minimum size of the metal layer, or any combination thereof.

[0064] Here, the wiring length *l* can be the geometric length between the start and end points of the corresponding interconnect 122. The corresponding interconnect 122 can electrically connect two electrical components, such as a resistor R, an inductor L, a capacitor C, or a transistor, wherein the wiring length *l* can be the geometric length of the corresponding interconnect 122 between the two electrical components connected via the corresponding interconnect 122. The minimum width *w* of the metal layer of the corresponding interconnect 122 can, for example, be the geometric width of the corresponding interconnect 122 at its narrowest point, wherein the minimum width *w* can, for example, be perpendicular to the wiring direction of the corresponding interconnect 122 and, for example, parallel to the wafer on which the corresponding interconnect 122 is arranged. Furthermore, the minimum dimensions can include the wiring length *l*, the minimum width *w*, and / or the thickness of the metal layer of the corresponding interconnect 122. See also Figure 4 And a corresponding description of the exemplary interconnect 122.

[0065] One or more of these characteristics 126 of the corresponding interconnect 122 can be used as input to a classifier model to estimate an approximate interconnect parasitic model 128 for each interconnect 122.

[0066] In another example, the electronic circuit layout 120 includes logic elements and / or memory elements, wherein if two or more interconnects 122 include parallel buses connecting the same logic elements and / or the same memory elements, then the two or more interconnects 122 are considered as one corresponding interconnect 122.

[0067] For the purposes of the proposed method, grouping interconnects 122 into a single interconnect 122 may, for example, help save computational overhead and accelerate the determination of parasitic elements 124 of the corresponding interconnects 122 of the electronic circuit layout 120.

[0068] In some examples, the corresponding interconnected parasitic model 128 includes at least one of RC model 128-1, RLC model 128-2, and full-wave model 128-3, wherein the corresponding parasitic extraction tool 132 includes RC parasitic extraction tool 132-1 for RC model 128-1, RLC parasitic extraction tool 132-2 for RLC model 128-2, or full-wave parasitic extraction tool 132-3 for full-wave model 128-3.

[0069] In some examples, the simple interconnection parasitic model 128-1 considering one or more resistors R and one or more capacitors C described above can correspond to RC model 128-1, which in some examples can model the corresponding interconnection 122 as an RC circuit or a lumped RC circuit. For example, RC model 128-1 can utilize Pi model or T model, which are named according to their shape and the arrangement of resistors R and capacitors C. See also Figure 6The diagram illustrates a simple Pi model with two C / 2 capacitors and one R resistor. A simple T model can correspondingly have two R / 2 resistors and one C capacitor. If the RC model 128-1 is selected using the corresponding performance specification 130, the parasitic elements 124 of the corresponding interconnect 122 can be determined using the RC parasitic extraction tool 132-1.

[0070] Furthermore, the more complex parasitic model 128-2 considering one or more resistors R, one or more inductors L, and one or more capacitors C can, for example, correspond to an RLC model 128-2, which in some examples models the corresponding interconnect 122 as an RLC circuit or a lumped RLC circuit. In some examples, the RLC model 128-2 provides a good model for low and medium frequencies f. If the RLC model 128-2 is selected using the corresponding performance metric 130, the RLC parasitic extraction tool 132-2 can be used to determine the parasitic elements 124 of the corresponding interconnect 122.

[0071] Similarly, the most accurate interconnect parasitic model 128-3 can correspond, for example, to the full-wave model 128-3. Here, the full-wave model 128-3 can, for example, consider so-called S-parameters (scattering parameters), which can implicitly represent how the discontinuities of the network inserted into the transmission line affect the voltage and current in the transmission line. For example, a two-dimensional S-matrix can be established for the electrical component, providing the frequency correlation between the incident, reflected, and transmitted waves at each port over the wave frequency range. Therefore, the S-parameters can, for example, provide amplitude and phase sensing in the frequency domain, rather than transient voltage and current. If the full-wave model 128-3 is selected using the corresponding performance metric 130, the parasitic elements 124 of the corresponding interconnect 122 can be determined using the full-wave parasitic extraction tool 132-3.

[0072] For example, application software component 106 and / or processor 102 may also be configured to determine at least a first modeling performance 136-1 of electronic circuit layout 120 using a first interconnect parasitic model 128-1 for the corresponding interconnect 122, and to determine a second modeling performance 136-2 of electronic circuit layout 120 using a second interconnect parasitic model 128-2 for the corresponding interconnect 122; and to determine corresponding performance metrics 130-1, 130-2 using the first modeling performance 136-1 and the second modeling performance 136-2.

[0073] Referring to the delay example above as performance metric 130, the delay (value) of 5 ps based on the simple interconnect parasitic model 128-1 (e.g., RC model 128-1), 5.001 ps based on the more complex parasitic model 128-2 (e.g., RLC model 128-2), and 5.005 ps based on the full-wave interconnect parasitic model 128-3 (e.g., full-wave model 128-3) can, in some examples, also be understood as the corresponding modeling performance metric 136-1, 136-2, 136-3. These modeling performance metric 136-1, 136-2, 136-3 can, for example, be used as input to derive slightly different corresponding performance metrics 130-1, 130-2, 130-3, which can be understood as the corresponding performance sensitivity. In the first latency example, performance metric 130 can be defined as the ratio of one of the corresponding modeling performances 136-1, 136-2, and 136-3 to another of the corresponding modeling performances 136-1, 136-2, and 136-3, for example: the ratio r of the latency according to RC model 128-1 to the latency according to RLC model 128-2. RC-RLC 5ps / 5.001ps; the ratio r of the delay according to RLC model 128-2 to the delay according to full-wave model 128-3. RLC-FW 5.001ps / 5.005ps; the ratio r of the delay according to RC model 128-1 to the delay according to full-wave model 128-3. RC-FW 5ps / 5.005ps. The corresponding performance metric 130 or ratio can also be expressed as a relative percentage difference, for example, the ratio of latency according to RC model 128-1 to latency according to RLC model 128-2: 100 (5ps - 5.001ps) / 5.001ps. Since the delay determined based on the simple and lightweight RC model 128-1 produces only about 0.1% relative difference compared to the delay determined based on the full-wave model 128-3, the simple, approximate solution RC parasitic extraction tool 132-1 can be chosen. Typically, in some examples, if the ratio r... RC-RLC r RLC-FW r RC-FW If the values ​​are relatively small (e.g., the corresponding absolute values ​​<0.01 or 1%), then a simple and lightweight RC model 128-1 is sufficient, and therefore it can be chosen, allowing the RC parasitic extraction tool 132-1, which approximates the solution, to determine the parasitic element 124. If the ratio r RC-RLC and r RC-FW Relatively large (e.g., the corresponding absolute value > 0.01 or 1%) and the ratio r RLC-FWIf the value is relatively small (e.g., absolute value < 0.01 or 1%), a more complex RLC model 128-2 may be necessary, as the RC model 128-1 may not be sufficient, and a full-wave model 128-3 may not be required. Therefore, the parasitic element 124 can be determined using the approximate solution RLC parasitic extraction tool 132-2. If the ratio r RC-RLC r RLC-FW r RC-FW If the values ​​are relatively large (e.g., the corresponding absolute value > 0.01 or 1%), then it may be necessary to select the full-wave model 128-3, because neither the RC model 128-1 nor the RLC model 128-2 may be sufficient. Therefore, the full-wave parasitic extraction tool 132-2 can be used to determine the parasitic element 124.

[0074] In the second delay example, performance index 130 can be defined as the ratio of one of the corresponding modeled performances 136-1, 136-2, and 136-3 to the actual performance 136r, for example, determined using a field solver. The field solver can calculate electromagnetic parameters by directly solving Maxwell's equations, for example, the ratio r of the delay obtained from RC model 128-1 to the actual delay (assumed to be 5.006 ps). RC-real 5ps / 5.006ps; the ratio r of latency to actual latency obtained from RLC model 128-2. RLC-real 5.001ps / 5.006ps; the ratio r of the delay obtained from the full-wave model 128-3 to the actual delay. FW-real 5.005ps / 5.006ps. The corresponding performance metric 130 or ratio can also be expressed as a relative difference (percentage), for example, the ratio of latency to actual latency obtained according to RC model 128-1: 100 (5ps - 5.006ps) / 5.006ps. Since the delay determined based on the simple and lightweight RC model 128-1 produces only about 0.1% relative difference compared to the true delay, a simple, approximate solution RC parasitic extraction tool 132-1 can be chosen. Overall, in some examples, if the ratio r RC-real r RLC-real r FW-real If the values ​​are relatively small (e.g., their absolute values ​​< 0.01 or 1%), then a simple and lightweight RC model 128-1 may suffice, and thus it can be chosen so that the parasitic element 124 can be determined using the RC parasitic extraction tool 132-1 with approximate solutions. If the ratio r RC-real Relatively large (e.g., absolute value > 0.01 or 1%), while the ratio r RLC-real r FW-realIf the values ​​are relatively small (e.g., their absolute values ​​< 0.01 or 1%), a more complex RLC model 128-2 may need to be chosen, as the RC model 128-1 may not be sufficient, and a full-wave model 128-3 may not be necessary. Therefore, the parasitic element 124 can be determined using the RLC parasitic extraction tool 132-2 with approximate solutions. If the ratio r RC-real r RLC-real (and possibly even r) FW-real If the parasitic elements 124 are relatively large (e.g., their absolute values ​​are >0.01 or 1%), then it may be necessary to select the full-wave model 128-3, because neither the RC model 128-1 nor the RLC model 128-2 may be sufficient. Therefore, the full-wave parasitic extraction tool 132-2 can be used to determine the parasitic elements 124.

[0075] In some examples, the ratio of the modeling performance index 130 obtained according to the corresponding interconnection parasitic model 128 to the performance index 130 or the true performance index 130r obtained according to the most complex parasitic model 128 is considered.

[0076] In a further example, one or more of the aforementioned performance metrics 130 can be used to determine the corresponding performance metric 130. If at least two performance metrics 130 are used, a weighting factor can be introduced to reflect that one performance metric 130 is more important than the others.

[0077] As mentioned above, the corresponding performance 136 and performance metric 130 may depend on the application scenario 134.

[0078] In a further example, the interconnect parasitic model 128 is enumerated in an increasing order of complexity, wherein the application software component 106 and / or processor 102 can also be configured to select the interconnect parasitic model 128 with the lowest complexity whose corresponding performance metric 130 is within a preconfigurable threshold for the corresponding interconnect.

[0079] For example, the RC model 128-1 described above could be a first interconnect parasitic model 128-1 because it is relatively simple and lightweight, and only considers one or more resistors R and one or more capacitors C. Furthermore, the RLC model 128-2 described above could be a second interconnect parasitic model 128-2 because it has moderate complexity and considers one or more resistors R, one or more inductors L, and one or more capacitors C. The full-wave model 128-3 described above could be a third interconnect parasitic model 128-3 because it has high complexity. In some examples, only two of these three interconnect parasitic models 128 may be used, and / or additional interconnect parasitic models 128 may be used.

[0080] In the context of the first delay example above (according to which performance metric 130 can be defined as the ratio of one of the corresponding modeling performances 136-1, 136-2, 136-3 to another of the corresponding modeling performances 136-1, 136-2, 136-3), the corresponding ratio r RC-RLC r RLC-FW r RC-FW The absolute value of 0.01 or 1% could be, for example, a preconfigurable threshold. Accordingly, in the context of the second latency example above (according to which performance metric 130 can be defined as the ratio of one of the corresponding modeling performances 136-1, 136-2, 136-3 to the actual performance 136r), the corresponding ratio r... RC-real r RLC-real r FW-real The absolute value of 0.01 or 1% could be a preconfigurable threshold, for example. In both examples, the preconfigurable threshold could be other values, or could be selected or adjusted during the proposed method: the preconfigurable threshold could also be selected as, for example, 0.002, 0.005, 0.02, 0.05, or any other constructive value that helps to find a reasonable trade-off between the accuracy and computational overhead associated with the corresponding interconnected parasitic model 128.

[0081] In some examples, if the absolute value of the ratio of the modeling performance metric 130-1 obtained according to the first (i.e., the simplest) interconnect parasitic model 128-1 to the performance metric 130 or the true performance metric 130r obtained according to the most complex parasitic model 128 is less than a preconfigurable threshold, then the simplest interconnect parasitic model 128-1 is selected; otherwise, the next interconnect parasitic model 128-2 is tested. If the absolute value of the ratio of the modeling performance metric 130-2 obtained according to the second (i.e., the next more complex) interconnect parasitic model 128-2 to the performance metric 130 or the true performance metric 130r obtained according to the most complex parasitic model 128 is less than a preconfigurable threshold, then the second interconnect parasitic model 128-2 is selected; otherwise, the next interconnect parasitic model 128-3 is tested, and so on. If the most complex interconnect parasitic model 128 has been tested, the process can stop, wherein, in some examples, the most complex interconnect parasitic model 128 can be selected if a less complex interconnect parasitic model 128 that was previously tested was not selected.

[0082] For example, application software component 106 and / or processor 102 may also be configured to determine parasitic elements 124 of electronic circuit layout 120 using a corresponding parasitic extraction tool 132 corresponding to the corresponding selected interconnect parasitic model 128 for the corresponding interconnect 122.

[0083] The proposed method for determining the parasitic elements 124 of a single interconnect 122 using a suitable extraction tool 132 can then be performed for all interconnects 122 of the electronic circuit layout 120. Thus, the parasitic elements 124 of the electronic circuit layout 120 can be determined, wherein, in some examples, a reasonable trade-off can be achieved between accuracy and the computational overhead involved.

[0084] In a further example, application software component 106 and / or processor 102 may also be configured to: determine a parasitic netlist including the determined parasitic element 124 of electronic circuit layout 120.

[0085] Here, in the context of EDA or design flow, a netlist can be understood, for example, as a list of interconnects 122 of an electronic circuit layout 120 or corresponding electronic circuit 150 that electrically connects the electronic components of the electronic circuit layout 120 or corresponding electronic circuit 152. In some examples, the netlist may also include the electronic components of the electronic circuit layout 120 or corresponding electronic circuit 152. Here, a parasitic netlist may include defined parasitic elements 124 of the interconnects 122, and in some examples, may also include parasitic elements 124 of the components. In some examples, the aforementioned parasitic elements 124 may be connected in the parasitic netlist.

[0086] For example, a parasitic netlist can provide a sufficient model of the interconnects 122 of the electronic circuit layout 120 or the corresponding electronic circuit 152, as well as optional components. Here, the parasitic netlist can be sufficiently accurate and computationally lightweight as possible.

[0087] In some examples, application software component 106 and / or processor 102 may also be configured to determine at least one physical property 138 of electronic circuit layout 120 using the determined parasitic elements 124 of the corresponding interconnect 122.

[0088] In some examples, the corresponding physical property 138 may correspond to the aforementioned performance metric 130, which may include delay, gain, noise, IR drop, and / or skew. In other examples, the corresponding physical property 138 may include heat dissipation, electromagnetic interference (EMI) indication, or mechanical stress occurring during the operation of the corresponding electronic circuit 152. Here, the corresponding physical property 138 can be determined, for example, using commercially available simulation tools that can use the identified parasitic element 124 or the identified parasitic netlist as input to determine the corresponding physical property 138.

[0089] In some examples, using the parasitic elements 124 of the corresponding interconnects 122 to determine the corresponding physical properties 138 of the electronic circuit layout 120 can be understood as an actual physical verification of the electronic circuit layout 120.

[0090] For example, application software component 106 and / or processor 102 may also be configured to: transfer electronic circuit layout 120 to electronic circuit manufacturing machine 150, and optionally cause electronic circuit manufacturing machine 150 to manufacture one or more electronic circuits 150 according to the transferred electronic circuit layout 120.

[0091] In some examples, the transfer of the electronic circuit layout 120 to the electronic circuit manufacturing machine 150 and, optionally, the manufacture of one or more electronic circuits 150 by the electronic circuit manufacturing machine 150 are only performed or triggered if the corresponding physical properties of the determined electronic circuit layout 120 meet the preconfigurable expectations, such as for heat dissipation, electromagnetic interference (EMI) indications, or mechanical stresses that occur during the operation of the corresponding electronic circuit 152.

[0092] For example, the identified parasitic element 124 can be displayed to the user via ECV UI 116.

[0093] It should be understood that the aforementioned application software component 106 and / or processor 102 can perform similar methods for determining the parasitic elements 124 of the interconnects 122 of the electronic circuit layout 120. Furthermore, Figure 1 The illustration shows a computer-readable medium 160 that may include a computer program product 162, wherein the computer program product 162 may be encoded with executable instructions that, when executed, cause the computer system 100 and / or the ECV system 118 to perform the methods described above.

[0094] Figure 2 A functional block diagram of a second example system 100 is depicted, which facilitates the determination of parasitic elements 124 of interconnects 122 in an electronic circuit layout 120 within a product system.

[0095] An interconnect parasitic model 128 can be determined from a plurality of interconnect parasitic models 128 of interconnect 122 based on a comparison of at least one performance metric 130 associated with each of the interconnect parasitic models 128. The parasitic elements 124 of the interconnect 122 can then be determined based on the determined parasitic model 128. These steps may include, for example, providing an electronic circuit layout 120 including a plurality of interconnects 122. At least one characteristic 126 of a corresponding interconnect 122 can then be determined, and at least a first interconnect parasitic model 128-1 and a second interconnect parasitic model 128-2 can be assigned to the corresponding interconnect 122. The corresponding characteristic 126 of the corresponding interconnect 122 can then be used to determine the corresponding performance metrics 130-1, 130-2 of at least the first interconnect parasitic model 128-1 and the second interconnect parasitic model 128-2 of the corresponding interconnect 122. The corresponding performance metrics 130-1, 130-2 can then be used to select the corresponding interconnect 122 from at least one of the first interconnect parasitic model 128-1 and the second interconnect parasitic model 128-2. The parasitic elements 124 of the corresponding interconnect 122 can be determined using the extraction tool 132 corresponding to the selected interconnect parasitic model 128.

[0096] Figure 3 One aspect of a first example method is described to facilitate the determination of parasitic elements 124 of interconnects 122 of electronic circuit layout 120 in a product system.

[0097] It can provide an electronic circuit layout 120 including multiple interconnects 122, which in Figure 3 The diagrams are labeled "circuit schematic" and "layout". Interconnects 122 in the electronic circuit layout 120 can then be identified, labeled "split interconnects". For example, based on the characteristics 126 and performance metrics 130 of the corresponding interconnects 122, a "classifier model" can be applied to identify the most suitable interconnect parasitic model 128 and corresponding extraction tool 132 for the corresponding interconnect 122, for example, in terms of accuracy and computational overhead. Here, an "RC extractor" 132-1, an "RLC extractor" 132-2, and a "full-wave extractor" can be selected, with details provided above.

[0098] Figure 4 One aspect of a second example method is described to facilitate the determination of parasitic elements 124 of interconnects 122 of electronic circuit layout 120 in a product system.

[0099] Interconnect 122 is depicted above, wherein interconnect 122 may, for example, be disposed on a wafer. Characteristic 126 of interconnect 122 may include a length l, which is the sum of the lengths of interconnect portions with lengths l1, l2, and l3 respectively. Furthermore, characteristic 126 of interconnect 122 may include a width w at the narrowest portion of interconnect 122. For example, characteristic 126 of interconnect 122 may include a resistance R of interconnect 122, which is equal to ρ l / A, where ρ is the material-specific resistivity, l is the aforementioned length, and A is the cross-sectional area of ​​interconnect 122 (e.g., at the narrowest portion of interconnect 122). In some examples, characteristic 126 of interconnect 122 may include ε l The capacitance C is proportional to w / (distance to ground), where ε is the dielectric constant, and l and w are the length and width mentioned above.

[0100] Figure 5 An aspect of a third example method is described, which helps to identify parasitic elements 124 of interconnects 122 of electronic circuit layout 120 in a product system.

[0101] An interconnect 122 and three interconnect parasitic models 128-1, 128-2, and 128-3 can be provided. These three interconnect parasitic models 128-1, 128-2, and 128-3 can then be used to determine three corresponding performance metrics (“sensitivity”) 130-1, 130-2, and 130-3 for the interconnect 122, where, for example, characteristic 126 of the interconnect 122 can be used. The “decision-maker” can then select the interconnect parasitic model 128 most suitable for the corresponding interconnect 122 and accordingly select an extraction tool 132, for example, in terms of accuracy and computational overhead. Here, the “decision-maker” can adopt the corresponding performance metrics 130-1, 130-2, and 130-3 as described above.

[0102] Figure 6 An aspect of a fourth example method is described, which helps to identify parasitic elements 124 of interconnects 122 of electronic circuit layout 120 in a product system.

[0103] Interconnect 122 can be modeled as (e.g., lumped) RC interconnect parasitic model 128-1, which in this example is a simple Pi model with two C / 2 capacitors and one R resistor.

[0104] Figure 7 An aspect of a fifth example method is described, which helps to identify parasitic elements 124 of interconnects 122 of electronic circuit layout 120 in a product system.

[0105] like Figure 7The impedance Z of the very simplified interconnect 122 or the very simplified parasitic interconnect model 128 can be a function of frequency f or an equivalent sinusoidal angular frequency ω (=2πf). Impedance Z can have resistance R and impedance ωL as components, where Z=R+jωL, j is the imaginary unit.

[0106] As long as the frequency is low (e.g., below the depicted cross threshold), the effect of inductance L is negligible, and interconnect 122 can be modeled without inductance L. In the real world, the threshold may be unknown for a real interconnect 122 and may vary depending on the circumstances. Therefore, in some examples, it may be advantageous to determine the aforementioned performance metric 130 (e.g., the aforementioned performance sensitivity) to identify the most suitable interconnect parasitic model 128 for the corresponding interconnect 122 and select the extraction tool 132 accordingly.

[0107] Figure 8 A functional block diagram of a third example system 100 is depicted, which helps to determine the parasitic elements 124 of the interconnects 122 of the electronic circuit layout 120 in the product system.

[0108] An interconnect parasitic model 128 can be determined from a plurality of interconnect parasitic models 128 of interconnect 122 based on a comparison between at least one performance metric 130 associated with each interconnect parasitic model 128. Parasitic elements 124 of interconnect 122 can then be determined based on the determined parasitic model 128. These steps may include, for example, providing an electronic circuit layout 120 comprising a plurality of interconnects 122. At least one characteristic 126 of a corresponding interconnect 122 can then be determined, and at least a first interconnect parasitic model 128-1 and a second interconnect parasitic model 128-2 can be assigned to the corresponding interconnect 122. The corresponding characteristics 126 of the corresponding interconnect 122 can then be used to determine the corresponding performance 136-1, 136-2 and the corresponding performance metrics 130-1, 130-2 of at least the first interconnect parasitic model 128-1 and the second interconnect parasitic model 128-2. Then, using the corresponding performance metrics 130-1 and 130-2, at least one of the first interconnect parasitic model 128-1 and the second interconnect parasitic model 128-2 can be selected for the corresponding interconnect 122. Then, using the extraction tool 132 corresponding to the corresponding selected interconnect parasitic model 128, the parasitic elements 124 of the corresponding interconnect 122 can be determined.

[0109] Figure 9 A functional block diagram of a fourth example system 100 is depicted, which helps to determine the parasitic elements 124 of the interconnects 122 of the electronic circuit layout 120 in the product system.

[0110] Fourth example system 100 and Figure 8The third example system 100 described above shares several similarities with the previous example system. Additionally, at least one physical property 138 of the electronic circuit layout 120 can be determined using the parasitic elements 124 of the corresponding interconnects 122. In some examples, the corresponding physical property 138 may correspond to the aforementioned performance metrics 130, which may include delay, gain, noise, IR drop, and / or skew. In other examples, the corresponding physical property 138 may include thermal properties, electromagnetic interference (EMI) parameters, or mechanical stresses occurring during the operation of the corresponding electronic circuit 152. Here, the corresponding physical property 138 can be determined, for example, using commercially available simulation tools that can use the identified parasitic elements 124 or the identified parasitic netlist as input to determine the corresponding physical property 138.

[0111] In some examples, using the parasitic elements 124 of the corresponding interconnects 122 to determine the corresponding physical properties 138 of the electronic circuit layout 120 can be understood as the actual physical verification of the electronic circuit layout 120.

[0112] It should be understood that with the advent of 3DIC (three-dimensional integrated circuits) and high-frequency applications (such as 5G and 6G), the need for accurate extraction of parasitic elements from the layout is crucial. Three main parasitic extraction solvers exist for modeling parasitic elements in integrated circuits: RC, RLC, and full-wave solvers. To obtain accurate and precise parasitic element models of integrated circuits at high frequencies, full-wave solvers can be used, for example; however, the main problems with full-wave solvers are 1) extraction runtime and 2) large netlists. Current full-wave solvers, while accurate, face the challenges of long extraction runtimes and large, complex netlists, which can exceed the capacity of post-layout simulators and lead to considerable simulation runtimes.

[0113] Typically, parasitic elements in a layout can be represented using RC, RLC, or full-wave models. Each type of model has its own layout parasitic extractor. Compared to the other two models, the RC extractor offers the smallest netlist, the lowest post-layout simulation runtime, and the lowest post-layout simulation accuracy, while the full-wave extractor offers the largest netlist, the longest post-layout simulation runtime, and the highest post-layout simulation accuracy. For high-frequency applications, designers use RLC and full-wave solvers to model parasitic elements in the layout.

[0114] Currently, using other methods, designers face many challenges in determining appropriate parasitic models for their layouts. They conduct extensive manual experimentation, which is time-consuming. Furthermore, using a full-wave solver for everything is generally impractical, as it is time-consuming and produces large and complex netlists. Additionally, circuit simulators may not be able to absorb the full-wave netlist for the entire layout. Currently, there is no systematic method to help layout designers identify appropriate parasitic models for every interconnect in the layout.

[0115] The proposed method offers one or more of the following advantages, for example: the proposed process automates the hybrid extraction process. Therefore, designers can easily extract layout parasitic parameters, for example, without any manual intervention. Furthermore, the proposed process can help provide very accurate parasitic extraction and post-layout simulation results for 3DIC and high-frequency applications. In some examples, the proposed process can further help provide: a smaller netlist size compared to a full-wave solver netlist, which provides the required post-layout simulation accuracy; and faster parasitic extraction runtime, because the process ensures that the full-wave solver is executed only on interconnects that are highly sensitive to it.

[0116] In some cases, manually determining the appropriate parasitic model (RC, RLC, or full-wave) can be very difficult for designers, especially at boundary frequencies. For example, the proposed hybrid approach can help designers identify the appropriate parasitic model in such gray areas. Applications of this process include, for example, 3DIC, RF and microwave circuits, signal integrity analysis, power integrity analysis, and high-frequency applications. For instance, in 3DIC, high-speed serial links and bridges (parallel buses connecting logic and memory) in the intermediate layer are examples of situations where users struggle to decide which model to use at high frequencies. The proposed process simplifies such decisions and helps users easily extract the appropriate parasitic model.

[0117] Figure 10 A flowchart depicts an example method for identifying parasitic elements in the interconnections of an electronic circuit layout in a product system. The method may begin at M02 and may include multiple actions performed by the operation of at least one processor.

[0118] These actions may include: action M04, determining an interconnect parasitic model from a plurality of interconnect parasitic models based on a comparison between at least one performance metric associated with each interconnect parasitic model; and action M06, determining the parasitic elements of the interconnect based on the determined interconnect parasitic model. The method may end at M08.

[0119] It should also be understood that method M may include other actions and features discussed above regarding the computer implementation of methods for determining parasitic elements interconnecting electronic circuit layouts.

[0120] Figure 11 A flowchart depicts another example method for identifying parasitic elements in the interconnections of an electronic circuit layout in a product system. This method may include... Figure 9 Actions M02 to M06 of the example method described above. Method M may further include: action M10 of providing an electronic circuit layout comprising multiple interconnects; action M12 of determining at least one characteristic of a corresponding interconnect; action M14 of assigning at least a first interconnect parasitic model and a second interconnect parasitic model to the corresponding interconnect; action M16 of determining corresponding performance indicators of at least the first interconnect parasitic model and the second interconnect parasitic model using the corresponding characteristics of the corresponding interconnect; action M18 of selecting at least one of the first interconnect parasitic model and the second interconnect parasitic model for the corresponding interconnect using the corresponding performance indicators; and action M20 of determining parasitic elements of the corresponding interconnect using a parasitic extraction tool corresponding to the corresponding selected interconnect parasitic model. The method may end at M22.

[0121] In some examples, actions M04 and M18, as well as actions M06 and M20, may at least partially overlap.

[0122] Figure 12 A block diagram depicts a data processing system 1000 (also referred to as a computer system) in which implementations can be carried out, for example as part of a product system, and / or as another system operatively configured by software or otherwise to perform the processes described herein. The data processing system 1000 may, for example, include the computer or IT system or data processing system 100 mentioned above. The depicted data processing system includes at least one processor 1002 (e.g., CPU) that can be connected to one or more bridges / controllers / buses 1004 (e.g., Northbridge, Southbridge). One of the buses 1004 may, for example, include one or more I / O buses, such as a PCI Express bus. In the depicted example, main memory 1006 (RAM) and a graphics controller 1008 may also be connected to the various buses. The graphics controller 1008 may be connected to one or more display devices 1010. It should also be noted that in some implementations, one or more controllers (e.g., graphics controller, Southbridge) may be integrated with the CPU (on the same chip or die). Examples of CPU architectures include IA-32, x86-64, and ARM processor architectures.

[0123] Other peripheral devices connected to one or more buses may include a communication controller 1012 (Ethernet controller, WiFi controller, cellular controller), which can be used to connect to a local area network (LAN), wide area network (WAN), cellular network and / or other wired or wireless network 1014 or communication devices.

[0124] Other components connected to various buses may include one or more I / O controllers 1016, such as USB controllers, Bluetooth controllers, and / or dedicated audio controllers (connected to speakers and / or microphones). It should also be understood that various peripheral devices can be connected to the I / O controller via various ports and connections, including input devices 1018 (e.g., keyboards, mice, pointers, touchscreens, touchpads, drawing tablets, trackballs, buttons, keypads, game controllers, gamepads, cameras, microphones, scanners, motion sensing devices capturing motion gestures), output devices 1020 (e.g., printers, speakers), or any other type of device that can be used to provide input to or receive output from the data processing system. It should also be understood that many devices referred to as input or output devices can both provide communication input to and receive output from the data processing system. For example, processor 1002 may be integrated into a housing (e.g., a tablet computer) that includes a touchscreen that functions as both an input device and a display device. Furthermore, it should be understood that some input devices (e.g., laptops) may include multiple different types of input devices (e.g., touchscreens, touchpads, keyboards). It should also be understood that other peripheral hardware 1022 connected to the I / O controller 1016 may include any type of device, machine, or component configured to communicate with the data processing system.

[0125] Additional components connected to various buses may include one or more storage controllers 1024 (e.g., SATA). The storage controller may connect to storage devices 1026, such as one or more storage drives and / or any associated removable media, which can be any suitable non-transitory, machine-usable, or machine-readable storage medium. Examples include non-volatile devices, volatile devices, read-only devices, writable devices, ROM, EPROM, magnetic tape storage, floppy disk drives, hard disk drives, solid-state drives (SSDs), flash memory, optical disc drives (CD, DVD, Blu-ray), and other known optical, electrical, or magnetic storage devices and / or computer media. Additionally, in some examples, storage devices such as SSDs may be directly connected to I / O buses 1004 such as the PCI Express bus.

[0126] A data processing system according to one embodiment of this disclosure may include an operating system 1028, software / firmware 1030, and data storage 1032 (which may be stored on storage device 1026 and / or memory 1006). Such an operating system may employ a command-line interface (CLI) shell and / or a graphical user interface (GUI) shell. A GUI shell allows multiple display windows to be simultaneously presented in the graphical user interface, each providing an interface for a different application or a different instance of the same application system. A cursor or pointer in the graphical user interface may be manipulated by a user using a pointing device such as a mouse or a touchscreen. The position of the cursor / pointer may be changed and / or events such as clicking a mouse button or touching a touchscreen may be generated to trigger a desired response. Examples of operating systems that may be used in the data processing system may include Microsoft Windows, Linux, UNIX, iOS, and Android operating systems. Additionally, examples of data storage include data files, data tables, relational databases (e.g., Oracle, Microsoft SQL Server), database servers, or any other structure and / or device capable of storing data that can be retrieved by a processor.

[0127] The communication controller 1012 may be connected to a network 1014 (not part of the data processing system 1000), which may be any public or private data processing system network or combination of networks known to those skilled in the art, including the Internet. The data processing system 1000 may communicate via network 1014 with one or more other data processing systems (such as server 1034, which is also not part of the data processing system 1000). However, alternative data processing systems may correspond to multiple data processing systems implemented as part of a distributed system in which processors associated with several data processing systems can communicate via one or more network connections and can collectively perform tasks described as being performed by a single data processing system. Therefore, it should be understood that when referring to a data processing system, such a system may be implemented on several data processing systems organized as a distributed system that communicate with each other via a network.

[0128] Furthermore, the term "controller" refers to any device, system, or part thereof that controls at least one operation, whether such device is implemented in hardware, firmware, software, or some combination thereof. It should be noted that the functionality associated with any particular controller can be centralized or distributed, local or remote.

[0129] Additionally, it should be understood that the data processing system may be implemented as a virtual machine in a virtual machine architecture or cloud environment. For example, processor 1002 and associated components may correspond to a virtual machine running in a virtual machine environment on one or more servers. Examples of virtual machine architectures include VMware ESXi, Microsoft Hyper-V, Xen, and KVM.

[0130] Those skilled in the art will understand that the hardware depicted for a data processing system may differ for a particular implementation. For example, the data processing system 1000 in this example may correspond to a computer, workstation, server, PC, laptop computer, tablet computer, mobile phone, and / or any other type of device / system capable of processing data and implementing the functions and features discussed herein associated with the operation of a data processing system, computer, processor, and / or controller. The examples depicted are provided for illustrative purposes only and are not intended to limit the structure of this disclosure.

[0131] Additionally, it should be noted that the processor described herein may reside in a server remote from the display and input devices described herein. In such instances, the described display and input devices may be contained in client devices that communicate with the server (and / or a virtual machine running on the server) via a wired or wireless network (including the Internet). In some embodiments, such client devices may, for example, execute remote desktop applications, or may correspond to portal devices that execute remote desktop protocols with the server to transmit input from input devices to the server and receive visual information from the server for display via the display device. Examples of such remote desktop protocols include Teradici's PCoIP, Microsoft's RDP and RFB protocols. In such instances, the processor described herein may correspond to a virtual processor of a virtual machine running in the physical processor of the server.

[0132] As used herein, the terms “component” and “system” are intended to encompass hardware, software, or a combination of hardware and software. Thus, for example, a system or component can be a process, a process executing on a processor, or a processor itself. Furthermore, a component or system can reside on a single device or be distributed across several devices.

[0133] Additionally, as used herein, a processor corresponds to any electronic device configured to process data via hardware circuitry, software, and / or firmware. For example, the processor described herein may correspond to one or more (or combinations thereof) of a microprocessor, CPU, FPGA, ASIC, or any other integrated circuit (IC) or other type of circuit capable of processing data in a data processing system (which may take the form of a controller board, computer, server, mobile phone, and / or any other type of electronic device).

[0134] Those skilled in the art will recognize that, for simplicity and clarity, the complete structure and operation of all data processing systems suitable for use with this disclosure are not depicted or described. Instead, only the parts of the data processing system that are unique to this disclosure or necessary for understanding this disclosure are depicted and described. The remaining construction and operation of the data processing system 1000 may conform to any of the various current embodiments and practices known in the art.

[0135] Furthermore, it should be understood that the words or phrases used herein should be interpreted broadly unless explicitly limited in some instances. For example, the terms “comprise” and “include” and their derivatives mean unrestricted inclusion. The singular forms “a,” “an,” and “the” are intended to also include the plural forms unless the context clearly indicates otherwise. Additionally, the term “and / or” as used herein refers to and covers any and all possible combinations of one or more associated listed items. The term “or” is inclusive, meaning and / or unless the context clearly indicates otherwise. The phrases “associated with” and “associated with” and their derivatives may mean including, being included, interconnected, containing, being contained within, connected to or linked with, coupled to or coupled with, able to communicate with, cooperate with, interleaved, juxtaposed, adjacent, bound to or bound with, having, possessing the properties of, etc.

[0136] Furthermore, although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, functions, or actions, these elements, functions, or actions should not be limited by these terms. Rather, these numerical adjectives are used to distinguish different elements, functions, or actions. For example, without departing from the scope of this disclosure, a first element, function, or action may be referred to as a second element, function, or action, and similarly, a second element, function, or action may be referred to as a first element, function, or action.

[0137] Furthermore, phrases such as "the processor is configured to perform one or more functions or processes" can indicate that the processor is operatively configured or operablely configured to perform a function or process via software, firmware, and / or wiring circuitry. For example, a processor configured to perform a function / process can correspond to a processor executing software / firmware programmed to cause the processor to perform that function / process, and / or can correspond to a processor having software / firmware in memory or a storage device available for the processor to execute that function / process. It should also be noted that a processor "configured" to perform one or more functions or processes can also correspond to processor circuitry (e.g., ASIC or FPGA designs) specifically manufactured or "wired" to perform a function or process. Additionally, the phrase "at least one" preceding an element configured to perform more than one function (e.g., a processor) can correspond to one or more elements (e.g., processors) each implementing multiple functions, and can also correspond to two or more elements (e.g., processors) each performing different functions of the one or more different functions.

[0138] In addition, the term "proximity" can mean: an element is relatively close to but does not touch another element; or the element touches the other part, unless the context clearly indicates otherwise.

[0139] Although an exemplary embodiment of this disclosure has been described in detail, those skilled in the art will understand that various changes, substitutions, modifications and improvements may be made to this disclosure without departing from the spirit and scope of this disclosure in its broadest form.

[0140] Nothing described in this patent document should be construed as implying that any particular element, step, action, or function is a necessary element that must be included within the scope of the claims: the scope of the patented subject matter is defined only by the permitted claims.

[0141] List of reference numerals

[0142] 100 processing system

[0143] 102 processor

[0144] 104 Memory

[0145] 106 Application Software Components

[0146] 108 Internal Data Storage

[0147] 110 Input Devices

[0148] 112 Display devices

[0149] 114 Graphical User Interface (GUI)

[0150] 116 Electronic Circuit Verification UI

[0151] 118 Electronic Circuit Verification System

[0152] 120 Electronic Circuit Layout

[0153] 122 Interconnection

[0154] 124 Parasitic Elements

[0155] 126 characteristics

[0156] 128 Parasitic Model

[0157] 130 performance indicators

[0158] 132 Parasite Extraction Tools

[0159] 134 Application Scenarios

[0160] 136 Performance

[0161] 138 Physical Properties

[0162] 150 Electronic circuit manufacturing machines

[0163] 152 Electronic Circuits

[0164] 160 Computer-readable media

[0165] 162 Computer program products

[0166] R resistor

[0167] L Inductance

[0168] C capacitor

[0169] Z impedance

[0170] ω is the sinusoidal angular frequency (2πf, f: frequency).

[0171] l length

[0172] w represents the width.

Claims

1. A computer-implemented method for determining parasitic elements in the interconnections of an electronic circuit layout, the computer method comprising: An interconnection parasitic model is determined from the plurality of interconnection parasitic models based on a comparison between at least one performance metric associated with each of the plurality of interconnection parasitic models; and The parasitic elements of the interconnect are determined based on the established interconnect parasitic model.

2. The computer-implemented method according to claim 1 further includes: Provides the electronic circuit layout including multiple interconnections; Determine at least one characteristic of a corresponding interconnect among the plurality of interconnects; At least the first interconnect parasitic model and the second interconnect parasitic model are assigned to the corresponding interconnect; Using at least one of the characteristics of the corresponding interconnect, determine the corresponding performance metrics of at least the first interconnect parasitic model and the second interconnect parasitic model of the corresponding interconnect; Using the corresponding performance metrics, at least one of the first interconnect parasitic model and the second interconnect parasitic model is selected for the corresponding interconnect; as well as The parasitic elements of the corresponding interconnect are determined using a parasitic extraction tool corresponding to the selected interconnect parasitic model.

3. The computer-implemented method according to any one of the preceding claims further includes: Provide application scenarios for the aforementioned electronic circuit layout; as well as The application scenario is also used to determine the corresponding performance metrics of the corresponding interconnect. The application scenarios include digital application scenarios and analog application scenarios, and The corresponding performance indicators include delay, gain, noise, IR drop, skew, or any combination thereof for the digital application scenario, the analog application scenario, or both the digital and analog application scenarios.

4. The computer-implemented method according to claim 2 or 3, wherein, The corresponding characteristics of the corresponding interconnect include the minimum size of the metal layer of the corresponding interconnect, the minimum width of the metal layer, the wiring length, or any combination thereof.

5. The computer-implemented method according to any one of the preceding claims, in, The electronic circuit layout includes logic elements, memory elements, or both logic elements and memory elements, and Wherein, when two or more of the plurality of interconnects include a parallel bus connecting the same logic element, the same memory element, or the same logic element and the same memory element, the two or more interconnects are considered to be corresponding interconnects.

6. The computer-implemented method according to any one of the preceding claims, in, The corresponding interconnection parasitic models include RC models, RLC models, full-wave models, or any combination thereof, and The corresponding extraction tools include an RC extraction tool for the RC model, an RLC extraction tool for the RLC model, or a full-wave extraction tool for the full-wave model.

7. The computer-implemented method according to any one of the preceding claims further includes: At least a first modeling performance of the electronic circuit layout is determined using a first interconnect parasitic model for the respective interconnects, and a second modeling performance of the electronic circuit layout is determined using a second interconnect parasitic model for the respective interconnects. as well as The corresponding performance metrics are determined using the first modeling performance and the second modeling performance.

8. The computer-implemented method according to any one of the preceding claims, in, The multiple interconnected parasitic models are listed in ascending order of complexity, and The method for the corresponding interconnection further includes selecting the interconnection parasitic model with the lowest complexity whose performance index is within a pre-configurable threshold.

9. The computer-implemented method according to any one of claims 2 to 8, further comprising: The parasitic elements of the electronic circuit layout are determined using a corresponding extraction tool that corresponds to the selected parasitic model of the corresponding interconnect.

10. The computer-implemented method according to any one of the preceding claims further comprises: Determine the parasitic netlist of the determined parasitic elements, including the electronic circuit layout.

11. The computer-implemented method according to any one of the preceding claims further includes: At least one physical property of the electronic circuit layout is determined using the identified parasitic elements of the corresponding interconnections.

12. The computer-implemented method according to any one of the preceding claims further includes: The electronic circuit layout is then transferred to the electronic circuit manufacturing machine.

13. A computer system arranged and configured to perform the steps of a computer-implemented method according to any one of the preceding claims.

14. A computer program product comprising computer program code, which, when executed by a computer system, causes the computer system to perform the method of any one of claims 1 to 12.

15. A computer-readable medium comprising a computer program product, the computer program product including computer program code that, when executed by a computer system, causes the computer system to perform the method of any one of claims 1 to 12.

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