Three-dimensional architecture for large-scale quantum processors

Abstract

Described herein is a superconducting quantum processor package comprising: a package substrate having an external connector port; an interposer having opposing first and second surfaces, the first surface of the interposer facing the package substrate, the interposer carrying a first quantum readout device coupled to the external connector port; a first qubit substrate having opposing top and bottom surfaces, the bottom surface of the first qubit substrate facing the second surface of the interposer, the first qubit substrate carrying a first qubit circuit having interleaved qubits and couplers, the first qubit circuit coupled to the first quantum readout device, wherein the first qubit circuit, the first quantum readout device, and the external connector port form a first readout communication path; and a first amplification device located in the first readout communication path, coupled between the first quantum readout device and the external connector port, to amplify a readout signal from the first quantum readout device.

Description

Cross-references to related applications

[0001] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 621,143, filed January 16, 2024, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] This disclosure generally relates to a three-dimensional architecture for superconducting quantum processors. Background Technology

[0003] Superconducting quantum bit technology is a leading platform for developing large-scale quantum processors. A superconducting quantum processor is an electronic device fabricated on a specialized substrate (such as high-resistivity silicon or sapphire) using advanced nanofabrication processes. The fabrication process involves photolithography, deposition, and etching steps widely used in the semiconductor industry.

[0004] Currently, state-of-the-art quantum processors typically have tens to hundreds of superconducting qubits, manufactured using academic / prototype nanofabrication facilities with poor reproducibility and relatively low yields. Furthermore, until recently, quantum chips for superconducting qubits were primarily fabricated in planar geometries, where the qubits and other components found on the quantum chip are arranged on a single substrate. As the number of qubits increases, more space is required, and the limits of 2D architectures have been reached. There is a need to expand to integrated 3D architectures to accommodate even more qubits. It should be noted that a useful quantum processor needs to be manufactured with tens of thousands to millions of qubits in high yield and reliability.

[0005] Therefore, improvements are needed. Summary of the Invention

[0006] This paper describes advanced nanofabrication and 3D packaging architectures for large-scale superconducting quantum processors. As used herein, large-scale is understood to mean a quantum processor comprising 100 or more qubits, such as, but not limited to, 500 qubits, 1000 qubits, 10,000 qubits, 100,000 qubits, etc.

[0007] Typically, in some aspects, the subject matter of this disclosure can be embodied in a superconducting quantum processor package comprising: a package substrate having an external connector port; an interposer having opposing first and second surfaces, the first surface of the interposer facing the package substrate, the interposer carrying a first quantum readout device coupled to the external connector port; a first qubit substrate having opposing top and bottom surfaces, the bottom surface of the first qubit substrate facing the second surface of the interposer, the first qubit substrate carrying a first qubit circuit having interleaved qubits and couplers, the first qubit circuit coupled to the first quantum readout device, wherein the first qubit circuit, the first quantum readout device, and the external connector port form a first readout communication path; and a first amplification device located in the first readout communication path, coupled between the first quantum readout device and the external connector port, to amplify the readout signal from the first quantum readout device.

[0008] Implementations of superconducting quantum processor packaging may include one or more of the following features or other features described herein. For example, in some implementations, the first amplification device is carried by the interposer layer.

[0009] In some embodiments, the package further includes a first amplifier substrate having opposing top and bottom surfaces, the bottom surface of the first amplifier substrate facing the second surface of the interposer layer, wherein the first amplification device is carried by the first amplifier substrate, and wherein the first amplifier substrate is independent of and adjacent to the first qubit substrate.

[0010] In some embodiments, the first amplification device includes at least one amplifier and at least one circulator coupled thereto.

[0011] In some implementations, the circulator is coupled between the external connector port, the first quantum readout device, and the amplifier.

[0012] In some embodiments, the first amplification device includes a Josephson parametric amplifier (JPA).

[0013] In some embodiments, the interposer is bonded to the package substrate via a ball grid array (BGA).

[0014] In some embodiments, the first quantum bit substrate is bonded to the interposer layer via a first superconducting microsphere lattice.

[0015] In some implementations, the first quantum readout device includes a plurality of resonators associated with the transmission line.

[0016] In some implementations, the resonator is arranged in a curved pattern and aligned with the qubits in the first qubit circuit that are also aligned in the curved pattern.

[0017] In some implementations, the first quantum readout device includes at least one filter.

[0018] In some implementations, the external connector port is bidirectional and performs both read and input operations.

[0019] In some implementations, the external connector port includes multiple output lines, and the first amplification device includes multiple amplifiers, each corresponding to one of the multiple output lines.

[0020] In some embodiments, the package further includes: a second quantum readout device carried in the interposer; a second qubit substrate, independent of the first qubit substrate and having opposing top and bottom surfaces, the bottom surface of the second qubit substrate facing the second surface of the interposer, the second qubit substrate carrying a second qubit circuit having interleaved qubits and couplers, the second qubit circuit being coupled to the second quantum readout device; and a coupling substrate facing and covering the top surfaces of the first and second qubit substrates, the coupling substrate carrying at least one coupler configured to selectively couple at least one qubit from the first qubit circuit to at least one qubit from the second qubit circuit.

[0021] In some embodiments, the package also includes a second amplification device coupled between the second quantum readout device and the external connector port to amplify the readout signal from the second quantum bit circuit.

[0022] In some embodiments, the package further includes a second amplification device coupled between the second quantum readout device and a second external connector port on the package substrate to amplify the readout signal from the second quantum bit circuit.

[0023] In some embodiments, the package further includes: a third quantum readout device and a fourth quantum readout device, carried in an interposer; and a third quantum bit substrate and a fourth quantum bit substrate, independent of the first quantum bit substrate and the second quantum bit substrate, respectively carrying the third quantum bit circuit and the fourth quantum bit circuit, and respectively coupled to the third quantum readout device and the fourth quantum readout device. The coupling substrate covers the first quantum bit substrate, the second quantum bit substrate, the third quantum bit substrate, and the fourth quantum bit substrate, and the at least one coupler is configured to selectively couple at least one qubit from any one of the first quantum bit circuit, the second quantum bit circuit, the third quantum bit circuit, and the fourth quantum bit circuit to at least one qubit from any other one of the first quantum bit circuit, the second quantum bit circuit, the third quantum bit circuit, and the fourth quantum bit circuit.

[0024] In some embodiments, the package also includes a third amplification device and a fourth amplification device, respectively coupled to the third quantum readout device and the fourth quantum readout device.

[0025] In some embodiments, the second amplification device, the third amplification device, and the fourth amplification device are carried in the intermediate layer.

[0026] In some embodiments, the second amplification device, the third amplification device, and the fourth amplification device are respectively carried by the second amplifier substrate, the third amplifier substrate, and the fourth amplifier substrate, which are independent of the first qubit substrate, the second qubit substrate, the third qubit substrate, and the fourth qubit substrate and are located on the interposer layer.

[0027] Details of one or more embodiments are set forth in the accompanying drawings and the description below. Other features will be apparent from the specification, drawings, and claims. Attached Figure Description

[0028] Figure 1 This is an example embodiment of a flip-chip architecture used for packaging superconducting quantum processors;

[0029] Figure 2 This is an example embodiment of a flip-chip architecture with superconducting vias for packaging superconducting quantum processors;

[0030] Figure 3 This is an example embodiment with a fan-shaped through-silicon via;

[0031] Figure 4 This is an example embodiment of a quantum bit substrate coupled by a coupler in an intermediate layer;

[0032] Figure 5 This is an example embodiment of a quantum bit substrate coupled by a coupler in a coupling substrate;

[0033] Figure 6 yes Figure 5 An example embodiment of a quantum bit substrate interconnection architecture, wherein an interposer layer is wire-bonded to a packaging substrate;

[0034] Figure 7 yes Figure 4 An example embodiment of a quantum bit substrate interconnection architecture, wherein an interposer layer is wire-bonded to a packaging substrate;

[0035] Figure 8 This is a top view schematic diagram of an example quantum readout device;

[0036] Figure 9 It is covered Figure 8 A top view of an example qubit circuit on a quantum readout device;

[0037] Figure 10 This is a side view schematic diagram of an example embodiment of a superconducting quantum processor package with amplification devices in an interposer layer;

[0038] Figure 11 This is a side view schematic diagram of an example embodiment of a superconducting quantum processor package having an amplification device in an amplifier substrate;

[0039] Figure 12A and Figure 12B This is an example embodiment of the amplification device;

[0040] Figure 13A and Figure 13B This is a side view schematic diagram of an example embodiment of a superconducting quantum processor package with bidirectional external connector ports;

[0041] Figure 14 This is another example embodiment of the amplification device; and

[0042] Figures 15A to 15C This is a top view of an example layout of a superconducting quantum processor package having a substrate with multiple qubits and one or more amplification substrates. Detailed Implementation

[0043] This disclosure relates to advanced nanofabrication and 3D packaging processes for large-scale superconducting quantum processors. This involves fabrication processes and architectures for superconducting multi-chip modules to reduce the impact of defects on yield. It also relates to the use of various vertical strategies, such as through-silicon vias, flip chips, the use of multiple interposers, and various combinations of vertical stacking, to address the need to increase qubit counts within the limited space available on the substrate. These processes are combined with the use of superconducting materials such as aluminum, indium, titanium nitride, and niobium in a series of subtractive patterning, etching, photolithography, and deposition processes to produce ultra-low-loss superconducting devices.

[0044] This disclosure relates to qubit circuits comprising interleaved qubits and couplers. In some embodiments, the qubit circuits used in some or all of the 3D architectures described herein correspond to the superconducting qubit circuits described in U.S. Patent No. 10,622,998, the contents of which are incorporated herein by reference in their entirety. A qubit is a superconducting qubit, such as, but not limited to, charge qubits, flux qubits, phase qubits, passage qubits, transducers, differential transducers, etc. In other embodiments, a qubit is a spin qubit or any quantum object having multiple discrete energy levels, wherein at least two energy levels can be selectively addressed. A qubit can be a fixed-frequency or tunable-frequency qubit. A qubit can be configured to simultaneously represent and manipulate information about more than one state. In some embodiments, qubits are formed from quantum circuit elements, including circuit elements such as superconducting coplanar waveguides, quantum LC oscillators, superconducting quantum interference devices (SQUIDs) (e.g., RF-SQUIDs or DC-SQUIDs), etc. Quantum circuit elements may include circuit elements that are partially formed of superconducting materials (e.g., aluminum, titanium nitride, or niobium).

[0045] Quantum bits and couplers are interleaved, and couplers can also be implemented as qubits. In some embodiments, the couplers have the same architecture as the qubits. However, qubits and couplers do not necessarily have the same architecture or type. Couplers can be frequency-tunable and can be tuned by applying a frequency-changing signal to the transmission line associated with each coupler.

[0046] Quantum bits are carried by a quantum bit substrate and can be formed on and / or within the substrate. The quantum bit substrate can be formed from a low-loss dielectric material suitable for quantum circuit elements, such as silicon or sapphire wafers. Other materials can be used for quantum bit substrates, either as an alternative or in combination with them.

[0047] refer to Figure 1This diagram illustrates a first example embodiment of a superconducting quantum processor package 100. In this architecture, a qubit substrate 102 is attached to an interposer 104. The interposer 104 may be composed of one or more layers of materials, such as low-loss dielectric materials suitable for quantum circuits, such as single-crystal silicon or sapphire. The interposer 104 may include quantum circuit elements and / or classical circuit elements. The qubit substrate 102 may be connected to the interposer 104 via an array of interconnects 108. In some embodiments, the interconnects 108 are bump bonds arranged to couple data between qubits on the qubit chip 102 and circuit elements on the interposer 104. The bump bonds may include superconducting materials to avoid energy loss and decoherence of the qubits located on the qubit substrate 102. Suitable superconducting materials used as bump bonds include, but are not limited to, indium, lead, rhenium, palladium, or niobium with a thin layer of gold. The bump bonds may be formed on interconnect pads on both the qubit substrate 102 and the interposer 104. In some embodiments, the interconnects 108 are microspheres, such as indium microspheres. While indium bump bonding is typically formed via electroplating or evaporation and compressed face-to-face using a flip-chip bonder, microspheres can be manually placed on the surface of the interposer 104 or the qubit substrate 102 and pressed together using a transfer stage. This eliminates the need for patterning and forming indium microbumps. Other materials and types of interconnects can also be used.

[0048] Intermediate layer 104 is located on package substrate 106, inside the cutout. In some embodiments, package substrate 106 is a printed circuit board (PCB). Intermediate layer 104 is connected to the PCB via wire bond 110, which is connected to pads surrounding the periphery of intermediate layer 104.

[0049] refer to Figure 2 Another embodiment of the superconducting quantum processor package 202 is shown. In this embodiment, the interposer 204 is connected to the package substrate 206 from the bottom rather than from the side. To transition to the underside connection between the interposer 204 and the package substrate 206, interconnects 212, such as a ball grid array (BGA) or other types of interconnects, are used. Through-silicon vias 210 are also added to the interposer 204 from the bottom surface to the top surface to allow the connection between the package substrate 206 and the qubit substrate 202 instead of wire bonding. A superconducting material must be added inside the via 210.

[0050] In some embodiments, interconnect 208 is a 5-micron-scale superconducting bump bond and is fabricated using a deposition system. In some embodiments, interconnect 212 is on the order of 100 microns and cannot be deposited. Electroplating can be used to fabricate BGAs.

[0051] Deep silicon etching, known as the Bosch process, can be used to create through-holes. However, this technique can produce fan-shaped 304, such as... Figure 3 As shown, this makes depositing the superconducting material 306 within the via 302 more challenging. If nothing is done to smooth the inner walls of the via, the superconducting material 306 may break during the deposition process or fail to reach the bottom of the via 302. The wafer used can vary in size. In cases of low aspect ratios for the via 302, shadow evaporation can be used to smooth the via 302. In some embodiments, the wafer has a diameter of 8 inches and a thickness of approximately 750 micrometers. The via 302 can have a diameter of approximately 10-50 micrometers. Therefore, the aspect ratio between the diameter and depth of the via is very large. For the large aspect ratio of the via, and in some embodiments, a pad is placed inside the via to smooth the sharp fan-shaped edges on the inner walls. In some embodiments, silicon oxide is formed on the inner walls of the via to smooth the sharp fan-shaped edges. In some embodiments, low-temperature etching is used to completely avoid the fan-shaped edges. A constant aspect ratio should be maintained throughout the entire depth of the via.

[0052] Quantum bits are typically fabricated on a single wafer. As the number of qubits increases, the wafer size increases. If something falls onto the wafer, all qubits may be lost. To increase qubit yield, a large number of qubit wafers can be broken down into multiple chips, each with approximately 20-50 qubits. Each chip can use more or fewer qubits. Using a chip-level approach can shorten development cycles and reduce costs. As used herein, the chip is referred to as a qubit substrate in a superconducting quantum processor package, and multiple qubit substrates can be provided in the same package. In some embodiments, qubits in different qubit substrates can be coupled together via an interposer, such as... Figure 4 As shown in the example embodiment. For example, a first qubit substrate 402A carries a first qubit circuit 404A having a plurality of interleaved qubits and couplers. A second qubit substrate 402B carries a second qubit circuit 404B having a plurality of interleaved qubits and couplers. Couplers 406 are located on an interposer layer 412 and are configured to selectively couple at least one qubit in the first qubit circuit 402B of the first qubit substrate 402A to at least one qubit in the second qubit circuit 404B of the second qubit substrate 402B (according to the interleaved architecture of qubits and couplers). Couplers 406 are coupled to qubit circuits 404A and 404B via superconducting interconnects 408.

[0053] It should be noted that, using this method, the interposer 412 includes a via 410 and one or more couplers 406 (and other components). The equipment used to fabricate the via 410 can be located on the semiconductor side of the facility, in an area that also contains gold. Couplers containing Josephson junctions are superconducting structures that cannot be exposed to gold. There are strict regulations that components exposed to gold cannot be used in gold-free quantum facilities. This means that the coupler 406 needs to be fabricated first, then the via 410, and the coupler 406 needs to be protected from potential gold contamination.

[0054] In some embodiments, a resist layer is added on top of the coupler (on the interposer) before the through-hole is fabricated, and this layer is removed by stripping at the end of the process. However, there is always a risk that resist residue may remain on the coupler.

[0055] In some embodiments, the coupling substrate carries a coupler that couples qubits from different qubit circuits originating from different qubit substrates, such as... Figure 5 As shown in the example embodiment, a coupling substrate 506 is placed on and covers qubit substrates 502A and 502B, each qubit substrate 502A and 502B carrying qubit circuits 504A and 504B, respectively. Interconnects 510 are used to connect the coupling substrate 506 to the qubit substrates 502A and 502B. Interconnects 510 may be the same as or different from interconnects 512 used to connect qubit substrates 502A and 502B to the interposer layer 514, provided that electrical connections can be made between couplers 508 and qubit circuits 504A and 504B. Therefore, the coupler substrate 506 carries one or more couplers 508, allowing the interposer layer 514 to be fabricated independently of the coupler substrate 506 without the challenges of having to fabricate vias 516 and couplers 508 on the same component. However, this method results in the 502A and 504A qubit substrates being double-sided, which increases complexity because a process is required for double-sided wafers.

[0056] In some embodiments, the quantum bit substrates 602A, 602B and coupling substrate 604 are used without vias in the interposer 606. In this case, the interposer 606 is disposed in a cutout on the package substrate 608, and wire bonding 610 electrically connects the interposer 606 to the package substrate 608, as shown below. Figure 6 As shown in the example embodiments.

[0057] In some embodiments, the qubits from the first qubit circuit 704A and the qubits from the first qubit substrate 702A and the second qubit substrate 702B of the second qubit circuit 704B are respectively connected via couplers 706 carried by an interposer 708. The interposer 708 is disposed in a cutout on the package substrate 710, and wire bonding 712 electrically connects the interposer 708 to the package substrate 710, as shown below. Figure 7 As shown in the example embodiments.

[0058] It should be understood that although the examples herein show two qubit substrates and one coupling substrate, more qubit substrates can be provided in the same package, and each pair of qubit substrates can be coupled together using the coupling substrate. In some embodiments, the coupling substrate can span four qubit substrates and selectively couple a qubit from any of the four qubit substrates to another qubit from any of the four qubit substrates.

[0059] The readout of qubits in a qubit circuit can be implemented using a quantum readout device, which can be carried by an interposer. A quantum readout device includes at least one resonator and at least one transmission line. In some embodiments, the quantum readout device includes multiple readout resonators, and each readout resonator is associated with a corresponding qubit. In some embodiments, each readout transmission line has an input port for transmitting an input signal and an output port for receiving an output signal. Note that a single port of the transmission line can be used for both input and output. In this case, an input signal is applied at a port of the transmission line, and the reflection of the input signal is measured at the same port as the output signal. As used herein, the expression "perform a readout" encompasses the steps of applying one or more input signals at a port of the transmission line, and subsequently measuring one or more output signals at the same port or different ports of the transmission line. Additional processing steps of the measured raw data can also be included in the readout, and therefore, additional components can be provided in the quantum readout device. In some embodiments, multiple readout resonators are connected to a single transmission line. Alternatively, each readout resonator can be associated with a separate transmission line.

[0060] refer to Figure 8This illustration shows an embodiment of a quantum readout device 800 according to a specific and non-limiting example. A plurality of resonators 802A, 802B, 802C, 802D, 802E are associated with a transmission line 804 having an input port 806A and an output port 806B. In some embodiments, a filter 808 is associated with resonator 802A to filter the readout signal. Filter 808 may be a frequency filter (e.g., a bandpass filter, high-pass filter, low-pass filter, step impedance filter, etc.) to impede propagating photons emitted from the qubit at the qubit frequency, and thus prevent energy leakage of the qubit through unwanted attenuation channels. In some embodiments, filter 808 is a Purcell filter. Although only one filter 808 is shown, a filter may be provided for each resonator of the quantum readout device 800.

[0061] The quantum readout device 800 can be capacitively or inductively coupled to the qubit circuit. In some embodiments, the quantum readout device in the interposer and the qubit circuit of the qubit substrate are aligned for coupling. Figure 9 This is a top view of a qubit circuit with a quantum readout device superimposed. For ease of understanding, the interposer and qubit substrate are omitted. The qubit circuit consists of qubits 902A, 902B, 902C, 902D, and 902E interleaved with couplers 904A, 904B, 904C, and 904D. Qubits 902A, 902B, 902C, 902D, and 902E cover resonators 906A, 906B, 906C, 906D, and 906E, respectively, to allow capacitive or inductive coupling between them. In this example, qubits 902A, 902B, 902C, 902D, and 902E and resonators 906A, 906B, 906C, 906D, and 906E are arranged in a curved pattern around transmission line 908, which is also shaped accordingly. Other arrangements can also be used. Although five qubits and a resonator are shown in the example, more or fewer than five can be used.

[0062] Superconducting quantum processor packages are maintained at cryogenic temperatures for operation, such as in dilution refrigerators. A dilution refrigerator is a cryogenic system that provides continuous cooling from ambient temperature down to milliKelvin. A dilution refrigerator consists of a cryostat, within which the superconducting quantum processor package is housed. Control and readout of the qubits within the quantum processor package are performed by classical control electronics located outside the cryostat while communicating with the quantum processor housed within its core. It should be understood that, depending on the specific application, some components of the classical control electronics involved in qubit control and readout may also be partially or entirely integrated within the cryostat. Signals can be transmitted between the quantum processor and the classical control electronics via interconnects, such as multiple coaxial cables entering and exiting the cryostat. Other types of cables, such as optical fibers or fiber optic radio frequency transmission, can also be used to transmit control signals to and / or from the quantum processor within and outside the cryostat.

[0063] Superconducting quantum processor packages can be coupled to cables (microwave, optical, etc.) via various types of connectors. Connectors can be coaxial connectors, such as RF connectors, including SMA connectors, SMP connectors, SMMP connectors, etc. In some embodiments, the connectors are high-density (HD) connectors, thereby providing multiple lines within a single connector housing. Therefore, a superconducting quantum processor package includes one or more external connector ports carried by a package substrate for connection to one or more cables.

[0064] When performing a qubit readout, a probe tone can be generated to sample the frequency of the quantum readout device and measure the phase shift depending on the qubit's state / frequency. However, the signal obtained from the quantum readout device on the output line may experience significant attenuation, thereby reducing the signal-to-noise ratio and making measurements more difficult. To mitigate the attenuation of the readout signal from the quantum readout device, an amplifier can be used. According to the embodiments described herein, the amplifier can be incorporated within the superconducting quantum processor package.

[0065] refer to Figure 10An example embodiment of a superconducting quantum processor package with amplification devices is shown. A quantum bit substrate 1002 carries a quantum bit circuit 1008, which is aligned with a quantum readout device 1010 carried by an interposer layer 1004. The interposer layer 1004 is located above a package substrate 1006, which carries at least one external connector port, in this case external connector ports 1012 and 1014. In this example, a signal enters through external connector port 1014 and travels through the package substrate 1006 and the interposer layer 1004 to reach a transmission line in the quantum readout device 1010. Various conductive paths are provided to allow signals to travel through the package 1000, such as one or more conductive vias, one or more conductive lines, microspheres, bump bonding, ball grid arrays, or combinations thereof. The conductive paths may be arranged in the respective layers of substrates 1002, 1004, and 1006. An amplification device 1016 is disposed in the readout communication path between the quantum readout device 1010 and the external connector port 1012 to amplify the readout signal from the quantum readout device 1010.

[0066] like Figure 10 As shown, the amplification device 1016 can be carried by the interposer 1004 and coupled to the quantum readout device 1010 via a conductive path. In some embodiments, the amplification device is placed on the surface of the interposer 1004 opposite to the quantum readout device 1010 to minimize its interaction with the qubits in the quantum bit circuit 1008 in the quantum bit substrate 1002.

[0067] In some embodiments, the amplification device is placed on a substrate independent of the substrate carrying the qubit circuitry and the substrate carrying the quantum readout device. An example embodiment of this implementation is described in... Figure 11 As shown in the diagram. The superconducting quantum processor package 1100 includes a package substrate 1106 and an external connector port 1112. The quantum bit substrate 1102 carries a quantum bit circuit 1108, which is aligned with a quantum readout device 1110 carried by an interposer layer 1104. The amplifier substrate 1120 carries an amplifier device 1116 coupled between the quantum readout device 1110 and the external connector port 1112. Thus, as Figure 10 In the example shown, the amplification device 1116 is still located in the readout communication path and can still amplify the readout signal from the quantum readout device 1110.

[0068] refer to Figure 12A and Figure 12B Two example embodiments of the amplification device are shown. Figure 12AIn this embodiment, amplification device 1202 is shown comprising at least one amplifier 1204 and at least one circulator 1206. In some embodiments, amplifier 1204 is a parametric amplifier, such as a Josephson parametric amplifier (JPA). The JPA may be a high-gain, broadband cryogenic amplifier designed for amplifying low-power microwave signals. In this way, the JPA introduces very low noise into the signal, such that its noise temperature is close to the quantum limit. The JPA operates at the lowest temperature of the dilution cryostat, i.e., below 50 millikrvin. Although not shown, DC current and RF signal pump signals are supplied to the JPA. In some embodiments, amplifier 1204 is a traveling wave parametric amplifier (TWPA). The TWPA may be a Josephson junction TWPA, a dynamic inductor TWPA, etc. More than one amplifier 1204 may be used to further improve the signal-to-noise ratio. Circulator 1206 may be used to block reflected signals from amplifier 1204. Figure 12B In one embodiment, another circulator 1212 is also provided in the amplification device 1222 at the output of amplifier 1204 to protect amplifier 1204 from noise passing through the output line in reverse. Figure 12A and Figure 12B The embodiments can be used with superconducting quantum processor packages 1000 and 1100. The readout signal from quantum readout devices 1010 and 1110 enters amplification devices 1202 and 1222 through input terminal 1208 and exits through output terminal 1210 to continue its path toward external connector ports 1012 and 1112.

[0069] In some embodiments, and as Figure 13A and Figure 13B As shown, the bidirectional external coupler port 1312 can be used for signal input and output transmission. Signals enter through the external coupler port 1312 and travel through the package substrate 1306 and the interposer layer 1304 to reach the transmission line in the quantum readout device 1310. The readout signal measured from the quantum bit circuit 1308, carried by the quantum bit substrate 1302, returns via the same path, from the quantum readout device 1310 to the amplification device 1316 and then to the external coupler port 1312. Figure 13A In this structure, the amplification device 1316 is supported by an intermediate layer. Figure 13B In the amplifier, the amplification device 1316 is supported by the amplifier substrate 1318.

[0070] In embodiments using the bidirectional external connector port 1312, it is possible to... Figure 14The example shows the configuration of amplifier 1316. An input signal is received at port 1410 and flows through circulator 1406 toward port 1408, preventing it from flowing through amplifier 1404. Port 1408 is connected to a quantum readout device. The signal received from the quantum readout device at port 1408 flows through circulator 1406 toward amplifier 1404. The amplified signal is reflected back to circulator 1406 and travels through port 1410 into amplifier 1402, which is connected to an external coupler port, such as bidirectional external coupler port 1312. Other embodiments of amplifier 1316 may also be used.

[0071] In some embodiments, the superconducting quantum processor package includes a plurality of qubit substrates and one or more amplification substrates, each amplification substrate carrying one or more amplification devices. Figures 15A-15C An example implementation is shown in the figure. Figure 15A A top view of a first example embodiment is shown. Package 1500 includes a package substrate 1502 and an interposer 1504. A pair of qubit substrates 1506A and 1506B are disposed on the interposer 1504, and a coupling substrate 1508 covers the qubit substrates 1506A and 1506B to selectively couple at least one qubit from a qubit circuit in qubit substrate 1506A to at least one qubit from a qubit circuit in qubit substrate 1506B. An amplification substrate 1510 is disposed along the outer edges of the first qubit substrate 1506A and the second qubit substrate 1506B. Amplification devices 1512A and 1512B are carried by the amplification substrate 1510 and coupled to quantum readout devices (not shown) in the interposer 1504, respectively. Various other embodiments can be used for superconducting quantum processor packages having multiple qubit substrates and amplification substrates. For example, and as... Figure 15BAs shown in the example, four qubit substrates 1056A, 1506B, 1506C, 1506D and one coupling substrate 1508 may exist. Amplifying substrates 1510A and 1510B may be disposed on each outer edge of the paired qubit substrates, such that amplifying device 1512A is associated with a quantum readout device coupled to the qubit circuit carried by qubit substrate 1506A, amplifying device 1512B is associated with a quantum readout device coupled to the qubit circuit carried by qubit substrate 1506B, amplifying device 1512C is associated with a quantum readout device coupled to the qubit circuit carried by qubit substrate 1506C, and amplifying device 1512D is associated with a quantum readout device coupled to the qubit circuit carried by qubit substrate 1506D. Alternatively, each pair of qubit substrates may be associated with a coupling substrate, such that an embodiment with four qubit substrates has two coupling substrates, an embodiment with six qubit substrates has three coupling substrates, an embodiment with eight qubit substrates has four coupling substrates, and so on.

[0072] Amplification substrates can be placed around the periphery of the qubit substrate using various configurations. In some embodiments, each amplification substrate carries a single amplification device, such as... Figure 15C The example is shown below. In this example, amplifying substrates 1522A, 1522B, 1522C, and 1522D are disposed at the corners of the interposer 1504 and respectively carry amplifying devices 1512A, 1512B, 1512C, and 1512D. Combinations of the features shown in superconducting quantum processor packages 1500, 1520, and 1530 can be used. For example, the amplifying substrates do not need to be symmetrically disposed on the interposer. Furthermore, package configurations with one amplifying substrate carrying multiple amplifying devices and another amplifying substrate carrying a single amplifying device can exist. Moreover, although the embodiments herein have shown each qubit substrate carrying a single qubit circuit, each qubit substrate can provide multiple qubit circuits. Qubit circuits carried by the same qubit substrate can be electrically independent of each other and associated with different quantum readout devices in the interposer. Therefore, various layouts for placing the amplifying substrates and / or amplifying devices (in the interposer or in the amplifying substrates) can be used to optimize the spacing in the package and the appropriate connections of various conductive paths provided on the layers of the package.

[0073] The fabrication process of a superconducting quantum processor includes photolithography, etching, characterization, deposition, and packaging steps. In addition to the equipment typically required for fabricating a superconducting quantum processor, the additional equipment required for the various architectures described herein may include one or more of the following: indium deposition tools; indium natural oxide etching tools (e.g., atmospheric plasma etching); CVD or ALD tools for coating the sidewalls of vias with superconducting materials; and polishing machines for thinning wafers to expose the vias.

[0074] The described embodiments and examples are illustrative and not restrictive. Actual implementations of the features may combine some or all of these aspects, and the features described herein should not be considered as indications of future or existing product plans. The applicant is involved in basic and applied research, and in some cases, the described features have been developed on an exploratory basis.

[0075] The terms “connection” or “coupled to” can include direct coupling (where two elements coupled to each other are in contact with each other) and indirect coupling (where at least one additional element is located between the two elements).

[0076] While embodiments have been described in detail, it should be understood that various changes, substitutions, and modifications can be made herein without departing from the scope. Furthermore, the scope of this application is not intended to be limited to the specific embodiments of the processes, machines, articles, material compositions, means, methods, and steps described in the specification.

[0077] As will be readily understood by those skilled in the art from the content of this disclosure, existing or later-developed processes, machines, articles, material compositions, means, methods, or steps can be used to perform substantially the same functions or achieve substantially the same results as the corresponding embodiments described herein. Therefore, the appended claims are intended to include such processes, machines, articles, material compositions, means, methods, or steps within their scope.

[0078] As you can understand, the examples described and illustrated above are intended to be illustrative only.

Claims

1. A superconducting quantum processor package, comprising: A packaging substrate having an external connector port; An interposer having opposing first and second surfaces, the first surface of the interposer facing the package substrate, the interposer carrying a first quantum readout device coupled to the external connector port; A first qubit substrate has opposing top and bottom surfaces, the bottom surface of the first qubit substrate facing the second surface of the interposer layer, the first qubit substrate carrying a first qubit circuit with interleaved qubits and couplers, the first qubit circuit being coupled to a first quantum readout device, wherein the first qubit circuit, the first quantum readout device and the external connector port form a first readout communication path. as well as A first amplification device, located in the first readout communication path and coupled between the first quantum readout device and the external connector port, amplifies the readout signal from the first quantum readout device.

2. The superconducting quantum processor package according to claim 1, wherein, The first amplification device is supported by the intermediate layer.

3. The superconducting quantum processor package of claim 1 further includes a first amplifier substrate having opposing top and bottom surfaces, the bottom surface of the first amplifier substrate facing the second surface of the interposer layer, wherein the first amplification device is carried by the first amplifier substrate, and wherein the first amplifier substrate is independent of and adjacent to the first qubit substrate.

4. The superconducting quantum processor package according to any one of claims 1 to 3, wherein, The first amplification device includes at least one amplifier and at least one circulator coupled thereto.

5. The superconducting quantum processor package according to claim 4, wherein, The circulator is coupled between the external connector port, the first quantum readout device, and the amplifier.

6. The superconducting quantum processor package according to any one of claims 1 to 5, wherein, The first amplification device includes a Josephson parametric amplifier (JPA).

7. The superconducting quantum processor package according to any one of claims 1 to 6, wherein, The interposer layer is bonded to the package substrate via a ball grid array (BGA).

8. The superconducting quantum processor package according to any one of claims 1 to 7, wherein, The first quantum bit substrate is bonded to the intermediary layer via a first superconducting microsphere lattice.

9. The superconducting quantum processor package according to any one of claims 1 to 8, wherein, The first quantum readout device includes multiple resonators associated with the transmission line.

10. The superconducting quantum processor package according to claim 9, wherein, The resonator is arranged in a curved pattern and is aligned with the qubit in the first qubit circuit, which is also aligned in the curved pattern.

11. The superconducting quantum processor package according to any one of claims 1 to 10, wherein, The first quantum readout device includes at least one filter.

12. The superconducting quantum processor package according to any one of claims 1 to 11, wherein, The external connector port is bidirectional and performs both read and input operations.

13. The superconducting quantum processor package according to claim 1, wherein, The external connector port includes multiple output lines, and the first amplification device includes multiple amplifiers, each amplifier corresponding to one of the multiple output lines.

14. The superconducting quantum processor package according to any one of claims 1 to 13, further comprising: A second quantum readout device is carried in the intermediate layer; A second qubit substrate, independent of the first qubit substrate and having opposing top and bottom surfaces, the bottom surface of the second qubit substrate facing the second surface of the interposer layer, the second qubit substrate carrying a second qubit circuit having interleaved qubits and couplers, the second qubit circuit being coupled to a second quantum readout device. as well as A coupling substrate facing and covering the top surfaces of the first qubit substrate and the second qubit substrate, the coupling substrate carrying at least one coupler configured to selectively couple at least one qubit from the first qubit circuit to at least one qubit from the second qubit circuit.

15. The superconducting quantum processor package of claim 14 further includes a second amplification device coupled between the second quantum readout device and the external connector port to amplify the readout signal from the second qubit circuit.

16. The superconducting quantum processor package of claim 14 further includes a second amplification device coupled between the second quantum readout device and a second external connector port on the package substrate to amplify the readout signal from the second quantum bit circuit.

17. The superconducting quantum processor package according to any one of claims 14 to 16, further comprising: The third and fourth quantum readout devices are housed within the intermediate layer; and The third and fourth qubit substrates are independent of the first and second qubit substrates, respectively carrying the third and fourth qubit circuits, and respectively coupled to the third and fourth quantum readout devices. The coupling substrate covers the first qubit substrate, the second qubit substrate, the third qubit substrate, and the fourth qubit substrate, and the at least one coupler is configured to selectively couple at least one qubit from any one of the first qubit circuit, the second qubit circuit, the third qubit circuit, and the fourth qubit circuit to at least one qubit from any other one of the first qubit circuit, the second qubit circuit, the third qubit circuit, and the fourth qubit circuit.

18. The superconducting quantum processor package according to claim 17 further includes a third amplification device and a fourth amplification device respectively coupled to the third quantum readout device and the fourth quantum readout device.

19. The superconducting quantum processor package according to claim 18, wherein, The second amplification device, the third amplification device, and the fourth amplification device are carried in the intermediate layer.

20. The superconducting quantum processor package according to claim 18, wherein, The second amplification device, the third amplification device, and the fourth amplification device are respectively supported by the second amplifier substrate, the third amplifier substrate, and the fourth amplifier substrate. The second amplifier substrate, the third amplifier substrate, and the fourth amplifier substrate are independent of the first quantum bit substrate, the second quantum bit substrate, the third quantum bit substrate, and the fourth quantum bit substrate and are located on the interposer layer.

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