Sub-pixel and display device comprising the same

Abstract

The sub-pixel includes a first transistor for generating a first driving current corresponding to a data voltage, a first capacitor including a first electrode for receiving a scan voltage and a second electrode connected to a control electrode of the first transistor, a driving transistor for generating a second driving current, a second capacitor including a first electrode connected to the first transistor and a second electrode connected to a control electrode of the driving transistor, and a light emitting element for receiving the second driving current and emitting light.

Description

Technical Field

[0001] The disclosure generally relates to a sub-pixel and a display device having the sub-pixel. Background Technology

[0002] With the development of information technology, display devices, as the connection medium between users and information, have become increasingly important. Therefore, display devices such as liquid crystal displays (LCDs), organic light-emitting diode (OLED) displays, and inorganic light-emitting diode (ILD) displays are being used more and more frequently.

[0003] Recently, research has been actively conducted on microLEDs, which offer higher response speeds and achieve higher brightness compared to existing LEDs. In the case of inorganic light-emitting elements such as microLEDs, when using pulse amplitude modulation (PAM) pixel driving methods similar to those used in organic LEDs, it can be difficult to accurately achieve the desired brightness because the peak wavelength varies with current density. Therefore, in the case of microLEDs, a pulse width modulation (PWM) pixel driving method can be used, where brightness is represented by controlling the time it takes for current to flow through the light-emitting element. Summary of the Invention

[0004] Technical issues The embodiment provides a sub-pixel driven using a PWM method.

[0005] The embodiment also provides a display device having the sub-pixel.

[0006] Technical solution According to the disclosed aspects, a sub-pixel is provided, which may include: a first transistor that generates a first drive current corresponding to a data voltage; a first capacitor that includes a first electrode for receiving a scan voltage and a second electrode connected to a control electrode of the first transistor; a drive transistor that generates a second drive current; a second capacitor that includes a first electrode connected to the first transistor and a second electrode connected to the control electrode of the drive transistor; and a light-emitting element that receives the second drive current to emit light.

[0007] In an embodiment, the sub-pixel may further include: a second transistor that provides a data voltage to the first transistor in response to a write gate signal; a third transistor that allows the first transistor to be connected by a diode in response to a first compensation gate signal; a fourth transistor that provides a first power voltage to the first transistor in response to a first transmit signal; and a reset transistor that provides an initialization voltage to the first transistor in response to a second transmit signal.

[0008] In one embodiment, the first transistor may include a control electrode connected to a first capacitor, a first electrode connected to a second capacitor, and a second electrode. A second transistor may be connected to the second electrode of the first transistor. A third transistor may be connected to both the control electrode and the first electrode of the first transistor. A fourth transistor may be connected to the first electrode of the first transistor. A reset transistor may be connected to the second electrode of the first transistor.

[0009] In an embodiment, the second transistor may be an N-type transistor.

[0010] In this embodiment, the second transistor may be a P-type transistor.

[0011] In an embodiment, the third transistor may be an N-type transistor.

[0012] In an embodiment, a sub-pixel may include: a compensation transistor that allows a driving transistor to be connected to a diode in response to a second compensation gate signal; an initialization transistor that provides an initialization voltage to the driving transistor in response to an initialization gate signal; an emission control transistor that connects the driving transistor to a light-emitting element in response to a second emission signal; and a discharge transistor that provides a second electrical voltage to the anode electrode of the light-emitting element in response to a first emission signal.

[0013] In one embodiment, the driving transistor may include a control electrode connected to a second capacitor, a first electrode receiving a first electrical voltage, and a second electrode. A compensation transistor may be connected to both the control electrode and the second electrode of the driving transistor. An initialization transistor may be connected to the control electrode of the driving transistor.

[0014] In one embodiment, the driving transistor may include a control electrode connected to a second capacitor, a first electrode receiving a first electrical voltage, and a second electrode. A compensation transistor may be connected to both the control electrode and the second electrode of the driving transistor. An initialization transistor may be connected to the second electrode of the driving transistor.

[0015] In this embodiment, the compensation transistor may be an N-type transistor.

[0016] In this embodiment, the first transistor may be an N-type transistor, and the driving transistor may be a P-type transistor.

[0017] In an embodiment, the sub-pixel may further include a third capacitor, which includes a first electrode receiving a first electrical voltage and a second electrode connected to a control electrode of a driving transistor.

[0018] According to another aspect of the disclosure, a display device may be provided, which may include: a display panel including at least one sub-pixel; and a display panel driver configured to drive the display panel, wherein each of the at least one sub-pixel may include: a first transistor generating a first drive current corresponding to a data voltage; a first capacitor including a first electrode receiving a scan voltage and a second electrode connected to a control electrode of the first transistor; a drive transistor generating a second drive current; a second capacitor including a first electrode connected to the first transistor and a second electrode connected to the control electrode of the drive transistor; and a light-emitting element receiving the second drive current to emit light.

[0019] In an embodiment, each of at least one sub-pixel may further include: a reset transistor that provides an initialization voltage to a first transistor in response to a second transmit signal; and an initialization transistor that provides an initialization voltage to a drive transistor in response to an initialization gate signal. The initialization voltage can be determined based on the grayscale.

[0020] In an embodiment, when the grayscale has a first grayscale, the initialization voltage may have a first voltage, and when the grayscale has a second grayscale that is less than the first grayscale, the initialization voltage may have a second voltage that is greater than the first voltage.

[0021] In this embodiment, a frame may include a first subframe and at least one second subframe. The light-emitting element may emit light in at least one second subframe. The number of at least one second subframe can be determined based on the emission frequency.

[0022] In an embodiment, at least one subpixel may include multiple subpixels. The multiple subpixels may be arranged in multiple rows. The display panel driver may be configured to allow a subpixel positioned in a first portion of the multiple rows to emit light, and then allow a subpixel positioned in a second portion of the multiple rows to emit light.

[0023] In an embodiment, at least one subpixel may include multiple subpixels, which may be arranged in multiple rows. The display panel driver may be configured to emit light sequentially at the first emission frequency at a second emission frequency higher than the first emission frequency, and the display panel driver may also be configured to allow a subpixel of the multiple subpixels arranged in a first portion of the multiple rows to emit light, and then allow a subpixel of the multiple subpixels arranged in a second portion of the multiple rows to emit light.

[0024] In an embodiment, each of at least one sub-pixel may include: a second transistor providing a data voltage to a first transistor in response to a write gate signal; a third transistor allowing the first transistor to be connected to a diode in response to a first compensation gate signal; a fourth transistor providing a first power voltage to the first transistor in response to a first transmit signal; a reset transistor providing an initialization voltage to the first transistor in response to a second transmit signal; a compensation transistor allowing a drive transistor to be connected to a diode in response to a second compensation gate signal; an initialization transistor providing an initialization voltage to the drive transistor in response to an initialization gate signal; an transmit control transistor connecting the drive transistor to a light-emitting element in response to the second transmit signal; and a discharge transistor providing a second power voltage to the anode electrode of the light-emitting element in response to the first transmit signal.

[0025] At least one sub-pixel may further include: a third capacitor, comprising a first electrode receiving a first electrical voltage and a second electrode connected to a control electrode of a driving transistor.

[0026] Beneficial effects According to the disclosure, the PWM method can be used to drive sub-pixels with only a small number of transistors, thereby ensuring a high pixel per inch (PPI).

[0027] In the disclosed sub-pixel, the first transistor can be used as an N-type transistor, and the source electrode of the sixth transistor can be fixed to a first electrical voltage, thereby minimizing the brightness variation caused by hysteresis characteristics.

[0028] According to the disclosed sub-pixel, the third and seventh transistors can be implemented as N-type transistors, thereby reducing leakage current.

[0029] According to the disclosed sub-pixel, the change in the second drive current caused by the IR drop of the first power voltage can be compensated by a third capacitor. Attached Figure Description

[0030] Figure 1 This is a schematic block diagram illustrating an embodiment of the display device.

[0031] Figure 2 It is shown Figure 1 A schematic block diagram of an embodiment of any of the sub-pixels shown.

[0032] Figure 3 yes Figure 1 A schematic diagram of the equivalent circuit of one of the sub-pixels shown.

[0033] Figure 4 It is shown Figure 1 The diagram shows the driving operation of the display device.

[0034] Figure 5 It is shown Figure 1 The diagram shows a schematic timing diagram of an example of a display device performing a display scanning operation.

[0035] Figure 6 It is shown Figure 1 The schematic timing diagram shows an example of the display device performing a self-scanning operation.

[0036] Figures 7 to 9 This is a schematic diagram illustrating an example of a display device according to a disclosed embodiment controlling the transmission time based on the transmission frequency.

[0037] Figure 10 This is a table illustrating an example of a display device adjusting an initialization voltage based on grayscale according to a disclosed embodiment.

[0038] Figure 11 It shows the basis Figure 10 The graph shows an example of the second driving current in grayscale.

[0039] Figure 12 This is a schematic diagram of the equivalent circuit of any one of the sub-pixels of a display device according to a disclosed embodiment.

[0040] Figure 13 It is shown Figure 12 The schematic timing diagram shows an example of a display device driving a frame to perform a display scanning operation on the first subframe.

[0041] Figure 14 This is a schematic diagram of the equivalent circuit of any one of the sub-pixels of a display device according to a disclosed embodiment.

[0042] Figure 15 It is shown Figure 14 The schematic timing diagram shows an example of a display device driving a frame to perform a display scanning operation on the first subframe.

[0043] Figure 16 This is a schematic block diagram illustrating an embodiment of the display system.

[0044] Figures 17 to 20 It is shown Figure 16 The image shows a perspective view of an application example of the display system. Detailed Implementation

[0045] In the following description, numerous specific details are set forth for purposes of explanation to provide a thorough understanding of the various embodiments or implementations disclosed. As used herein, “embodiment” and “implementation” are interchangeable terms as non-limiting examples of the apparatus or methods disclosed herein. However, it will be apparent that various embodiments may be practiced without these specific details or with one or more equivalent arrangements. These various embodiments are not necessarily exclusive, nor are they intended to limit the disclosure. For example, a particular shape, configuration, and characteristic of an embodiment may be used or implemented in another embodiment.

[0046] Unless otherwise stated, the illustrated embodiments should be understood as providing disclosed features. Therefore, unless otherwise stated, features, components, modules, layers, films, panels, regions and / or aspects (hereinafter individually or collectively referred to as “elements”) of various embodiments may be combined, separated, interchanged and / or rearranged without departing from the inventive concept.

[0047] Crosshairs and / or shading are typically used in accompanying drawings to clearly define the boundaries between adjacent elements. Thus, unless otherwise stated, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for the specific material, material properties, dimensions, scale, commonalities between the elements shown, or any other characteristics, properties, etc., of the elements. Furthermore, the dimensions and relative dimensions of elements may be exaggerated in the accompanying drawings for clarity and / or descriptive purposes. A particular sequence of processes may be performed differently than described when embodiments can be implemented differently. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description. Moreover, the same reference numerals and / or figure marks denote the same elements.

[0048] When a component or layer is referred to as being "on," "connected to," or "bonded to" another component or layer, the component or layer may be directly on, directly connected to, or directly bonded to the other component or layer, or an intermediary component or layer may be present. However, when a component or layer is referred to as being "directly on," "directly connected to," or "directly bonded to" another component or layer, an intermediary component or layer is not present. Therefore, the term "connection" can refer to a physical connection, electrical connection, and / or fluid connection with or without an intermediary component. Furthermore, the X, Y, and Z axes are not limited to the three axes of a Cartesian coordinate system (such as the x, y, and z axes) and can be interpreted in a broader sense. For example, the X, Y, and Z axes can be perpendicular to each other, or they can be different directions that are not perpendicular to each other.

[0049] For the purposes of this disclosure, "at least one of A and B" can be interpreted as only A, only B, or any combination of A and B. Furthermore, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0050] Although the terms “first,” “second,” etc., may be used here to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, without departing from the publicly stated teachings, the first element discussed below may be referred to as the second element.

[0051] For descriptive purposes, spatial relative terms such as “below,” “under,” “below,” “down,” “above,” “above,” “higher,” and “side” (e.g., as in “sidewall”) may be used herein to describe the relationship between one element and another as shown in the accompanying drawings. Spatial relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture other than those depicted in the drawings. For example, if the device in the drawings is flipped, an element described as “below” or “under” other elements or features would subsequently be oriented “above” other elements or features. Thus, the term “below” can encompass both above and below orientations. Furthermore, the device may be otherwise oriented (e.g., rotated 90 degrees or in other orientations), thus interpreting the spatial relative descriptive terms used herein accordingly.

[0052] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” as used herein are also intended to include the plural forms. Furthermore, when the terms “comprising,” “including,” and / or variations thereof are used in this specification, they indicate the presence of the stated features, integrals, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. It should also be noted that, as used herein, the terms “basically,” “about,” and other similar terms are used as approximate terms rather than terms of degree, and are therefore used to explain the inherent deviations in measured values, calculated values, and / or provided values ​​that will be recognized by those skilled in the art.

[0053] Various embodiments are described herein with reference to cross-sectional views and / or exploded views that serve as schematic diagrams of examples and / or intermediate structures. Thus, variations in the shapes illustrated will be anticipated, for example, due to manufacturing techniques and / or tolerances. Therefore, the embodiments disclosed herein are not necessarily to be construed as limited to the shapes of the specifically shown areas, but will include deviations in shape caused, for example, by manufacturing processes. In this way, the areas shown in the drawings can be schematic in nature, and the shapes of these areas may not reflect the actual shapes of the areas of the device, so they are not intended to be limiting.

[0054] In accordance with the conventions of the art, some embodiments are described and illustrated in the accompanying drawings in the form of functional blocks, components (parts), and / or modules. Those skilled in the art will appreciate that these blocks, components (parts), and / or modules are physically implemented by electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wiring connections, etc.) formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Where said blocks, components (parts), and / or modules are implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and can optionally be driven by firmware and / or software. It is also contemplated that each block, component (part), and / or module can be implemented by dedicated hardware, or implemented as a combination of dedicated hardware performing some functions and processors performing other functions (e.g., one or more programmed microprocessors and associated circuitry). Furthermore, without departing from the scope of the inventive concept, each block, component (part), and / or module of some embodiments can be physically divided into two or more interactive and discrete blocks, components (parts), and / or modules. Furthermore, without departing from the scope of the inventive concept, blocks, parts (parts) and / or modules of some embodiments can be physically combined into more complex blocks, parts (parts) and / or modules.

[0055] Unless otherwise defined or implied herein, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in common dictionaries) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field and the disclosure, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0056] The disclosed embodiments will be described in detail below with reference to the accompanying drawings.

[0057] Figure 1 This is a schematic block diagram illustrating an embodiment of the display device.

[0058] Reference Figure 1 The display device DD may include a display panel DP and a display panel driver. The display panel driver may include a gate driver 120, a data driver 130, a voltage generator 140, and a controller 150.

[0059] The display panel DP may include sub-pixels SP. Sub-pixels SP can be connected to gate driver 120 via first gate line GL1 to m-th gate line GLm. Sub-pixels SP can be connected to data driver 130 via first data line DL1 to n-th data line DLn.

[0060] Subpixels (SPs) can produce two or more colors of light. For example, each subpixel SP can produce red, green, blue, cyan, magenta, yellow, white, and other colors of light.

[0061] Two or more subpixels within subpixel SP can constitute pixel PXL. For example, pixel PXL can include, for instance, subpixels SP. Figure 1 The three sub-pixels are shown. Thus, pixel PXL can emit light of various colors with varying brightness based on the combination of light emitted from the sub-pixels included therein.

[0062] Gate driver 120 can be connected to sub-pixels SP arranged in the row direction via first gate lines GL1 to m-th gate lines GLm. Gate driver 120 can output gate signals to first gate lines GL1 to m-th gate lines GLm in response to gate control signal GCS. In an embodiment, gate control signal GCS may include a start signal indicating the start of each frame, a horizontal synchronization signal, etc.

[0063] The gate signal may include a first transmit signal, a second transmit signal, a first compensated gate signal, a second compensated gate signal, and an initialization gate signal, which will be described later.

[0064] The gate driver 120 may be disposed on one side of the display panel DP. However, the embodiments are not limited thereto. For example, the gate driver 120 may be divided into two or more drivers that may be physically and / or logically separated, and these drivers may be disposed on one side of the display panel DP and on the opposite side of the display panel DP. Thus, in some embodiments, the gate driver 120 may be disposed in various forms at the periphery of the display panel DP.

[0065] Data driver 130 can be connected to sub-pixels SP arranged in the column direction via first data lines DL1 to nth data lines DLn. Data driver 130 can receive image data DATA and data control signal DCS from controller 150. Data driver 130 can operate in response to data control signal DCS. In an embodiment, data control signal DCS may include source start pulse, source shift clock, source output enable signal, etc.

[0066] The data driver 130 can receive voltage from the voltage generator 140. The data driver 130 can apply a data signal having a grayscale voltage corresponding to the image data DATA to the first data lines DL1 to the nth data line DLn using the received voltage. When a gate signal is applied to each of the first gate lines GL1 to the mth gate line GLm, the data signal corresponding to the image data DATA can be applied to the first data lines DL1 to the nth data line DLn. Therefore, the corresponding sub-pixel SP can generate light corresponding to the data signal. Thus, an image can be displayed on the display panel DP.

[0067] In one embodiment, gate driver 120 and data driver 130 may include complementary metal-oxide-semiconductor (CMOS) circuit elements.

[0068] Voltage generator 140 can operate in response to a voltage control signal VCS from controller 150. Voltage generator 140 can be configured to generate multiple voltages and provide the generated voltages to components of display device DD. Voltage generator 140 can generate multiple voltages by receiving an input voltage from outside display device DD and adjusting the received voltage.

[0069] Voltage generator 140 can generate a first electrical voltage and a second electrical voltage. The generated first and second electrical voltages can be supplied to the sub-pixel SP via the power line PL. In other embodiments, at least one of the first and second electrical voltages can be supplied from outside the display device DD.

[0070] Furthermore, voltage generator 140 can also provide various voltages and / or signals. For example, voltage generator 140 can provide one or more initialization voltages applied to sub-pixel SP. For example, in a sensing operation for sensing the electrical characteristics of the transistors and / or light-emitting elements of sub-pixel SP, a reference voltage (e.g., a predetermined or selectable reference voltage) can be applied to the first data lines DL1 to the nth data lines DLn, and voltage generator 140 can generate the reference voltage and transmit it to the data driver 130. For example, in a display operation for displaying an image on a display panel DP, a common pixel control signal can be applied to sub-pixel SP, and voltage generator 140 can generate the pixel control signal. In an embodiment, voltage generator 140 can provide pixel control signals to sub-pixel SP via pixel control line PXCL. Figure 1 The diagram shows a pixel control line PXCL connected between voltage generator 140 and display panel DP. However, the embodiment is not limited to this. For example, the pixel control line PXCL can be connected between gate driver 120 and display panel DP. Pixel control signals can be transmitted from voltage generator 140 to pixel control line PXCL via gate driver 120.

[0071] The controller 150 can control the overall operation of the display device DD. The controller 150 can receive input image data IMG and the corresponding control signal CTRL from an external source. The controller 150 can provide a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS in response to the control signal CTRL.

[0072] The controller 150 can convert the input image data IMG into a format suitable for a display device DD or a display panel DP, thereby outputting image data DATA. In an embodiment, the controller 150 can align the input image data IMG row by row to a format suitable for sub-pixels SP, thereby outputting image data DATA.

[0073] Two or more of the components—data driver 130, voltage generator 140, and controller 150—may be mounted on an integrated circuit (e.g., a single integrated circuit). Figure 1 As shown, the data driver 130, voltage generator 140, and controller 150 may be included in a driver integrated circuit (DIC). The data driver 130, voltage generator 140, and controller 150 may be functionally separated components within the driver integrated circuit (DIC). In other embodiments, at least one of the data driver 130, voltage generator 140, and controller 150 may be configured as a component distinct from the driver integrated circuit (DIC).

[0074] Figure 2 It is shown Figure 1A schematic block diagram of an embodiment of any of the sub-pixels shown. Figure 3 yes Figure 1 A schematic diagram of the equivalent circuit of one sub-pixel in the diagram is shown. Figure 2 In, it is shown Figure 1 The sub-pixels SPij shown are arranged in the i-th row (i can be an integer greater than or equal to 1 and less than or equal to m) and the j-th column (j can be an integer greater than or equal to 1 and less than or equal to n) of the sub-pixels SP.

[0075] Reference Figure 2 Subpixel SPij may include subpixel circuit SPC and light-emitting element LD.

[0076] The light-emitting element (LD) can be connected between the first power voltage node VDDN and the second power voltage node VSSN. The first power voltage node VDDN can be connected to... Figure 1 One of the power lines PL shown is used to receive a first power voltage. A second power voltage node VSSN can be connected to the other power line PL to receive a second power voltage. The first power voltage can have a higher voltage level than the second power voltage.

[0077] The light-emitting element (LD) can be connected between the anode electrode AE ​​and the cathode electrode CE. The anode electrode AE ​​can be connected to a first power voltage node VDDN via a sub-pixel circuit SPC. For example, the anode electrode AE ​​can be connected to the first power voltage node VDDN via one or more transistors included in the sub-pixel circuit SPC. The cathode electrode CE can be connected to a second power voltage node VSSN. The light-emitting element LD can be configured to emit light according to the current flowing from the anode electrode AE ​​to the cathode electrode CE.

[0078] Sub-pixel circuits (SPCs) can be connected to Figure 1 The i-th gate line GL1 to the m-th gate line GLm shown in the figure are the first gate line GL1 and the m-th gate line GLm. Figure 1 The j-th data line DLj is shown among the first data lines DL1 to the nth data line DLn. In response to the gate signal received via the i-th gate line GL1, the sub-pixel circuit SPC controls the light-emitting element LD to emit light based on the data signal received via the j-th data line DLj. In an embodiment, the sub-pixel circuit SPC may also be connected to... Figure 1 The pixel control line PXCL is shown in the diagram. The sub-pixel circuit SPC can further control the light-emitting element LD in response to the control signal received through the pixel control line PXCL.

[0079] For these operations, the subpixel circuit SPC may include circuit elements (e.g., transistors and one or more capacitors).

[0080] The transistors in the sub-pixel circuit SPC may include P-type transistors and / or N-type transistors. In an embodiment, the transistors in the sub-pixel circuit SPC may include metal-oxide-semiconductor field-effect transistors (MOSFETs). In an embodiment, the transistors in the sub-pixel circuit SPC may include amorphous silicon semiconductors, monocrystalline silicon semiconductors, polycrystalline silicon semiconductors, oxide semiconductors, etc.

[0081] Reference Figure 3 The sub-pixel SPij may include: a first transistor T1 that generates a first drive current corresponding to the data voltage VDATA; a second transistor T2 that provides the data voltage VDATA to the first transistor T1 in response to a write gate signal GW[i]; a third transistor T3 that allows the first transistor T1 to be diode-connected in response to a first compensation gate signal GC1[i]; a fourth transistor T4 that provides a first power voltage VDD to the first transistor T1 in response to a first transmit signal EM1[i]; a fifth transistor T5 (e.g., a reset transistor) that provides an initialization voltage VAINT to the first transistor T1 in response to a second transmit signal EM2[i]; a first capacitor C1 that includes a first electrode receiving a scan voltage SV and a second electrode connected to a control electrode of the first transistor T1; a sixth transistor T6 (e.g., a drive transistor) that generates a second drive current; and a second capacitor C2 that includes a capacitor connected to the first transistor T1. The first electrode and the second electrode connected to the control electrode of the sixth transistor T6; the seventh transistor T7 (e.g., a compensation transistor), which allows the sixth transistor T6 to be diode-connected in response to the second compensation gate signal GC2[i]; the eighth transistor T8 (e.g., an initialization transistor), which provides an initialization voltage VAINT to the sixth transistor T6 in response to the initialization gate signal GI[i]; the ninth transistor T9 (e.g., an emission control transistor), which connects the sixth transistor T6 to the light-emitting element LD in response to the second emission signal EM2[i]; the tenth transistor T10 (e.g., a discharge transistor), which provides a second power voltage VSS to the anode electrode AE ​​of the light-emitting element LD in response to the first emission signal EM1[i]; the third capacitor C3, which includes a first electrode receiving the first power voltage VDD and a second electrode connected to the control electrode of the sixth transistor T6; and the light-emitting element LD, which receives a second drive current to emit light.

[0082] For example, the first transistor T1 may include a control electrode connected to the first node N1, a first electrode connected to the second node N2, and a second electrode connected to the third node N3; the second transistor T2 may include a control electrode for receiving a write gate signal GW[i], a first electrode for receiving a data voltage VDATA, and a second electrode connected to the third node N3; the third transistor T3 may include a control electrode for receiving a first compensation gate signal GC1[i], a first electrode connected to the second node N2, and a second electrode connected to the first node N1; the fourth transistor T4 may include a control electrode for receiving a first transmit signal EM1[i], a first electrode for receiving a first power voltage VDD, and a second electrode connected to the second node N2; the fifth transistor T5 may include a control electrode for receiving a second transmit signal EM2[i], a first electrode for receiving an initialization voltage VAINT, and a second electrode connected to the third node N3; and the sixth transistor... T6 may include a control electrode connected to the fourth node N4, a first electrode receiving the first power voltage VDD, and a second electrode connected to the fifth node N5. The seventh transistor T7 (e.g., a compensation transistor) may include a control electrode receiving the second compensation gate signal GC2[i], a first electrode connected to the fifth node N5, and a second electrode connected to the fourth node N4. The eighth transistor T8 may include a control electrode receiving the initialization gate signal GI[i], a first electrode receiving the initialization voltage VAINT, and a second electrode connected to the fourth node N4. The ninth transistor T9 may include a control electrode receiving the second transmission signal EM2[i], a first electrode connected to the fifth node N5, and a second electrode connected to the anode electrode AE. The tenth transistor T10 may include a control electrode receiving the first transmission signal EM1[i], a first electrode receiving the second power voltage VSS, and a second electrode connected to the anode electrode AE.

[0083] For example, the first capacitor C1 may include a first electrode that receives the scan voltage SV and a second electrode that is connected to the first node N1, the second capacitor C2 may include a first electrode that is connected to the second node N2 and a second electrode that is connected to the fourth node N4, and the third capacitor C3 may include a first electrode that receives the first power voltage VDD and a second electrode that is connected to the fourth node N4.

[0084] Since the third capacitor C3 can be connected between the first power voltage VDD and the fourth node N4, the source-gate voltage of the sixth transistor T6 can be maintained even if the first power voltage VDD may decrease due to IR drop. Therefore, the change in the second drive current caused by IR drop can be compensated.

[0085] In the embodiments, the first transistor T1, the second transistor T2, the third transistor T3, the seventh transistor T7, and the eighth transistor T8 can be implemented using N-type transistors, and the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the ninth transistor T9, and the tenth transistor T10 can be implemented using P-type transistors. However, the disclosure is not limited to the type of each transistor.

[0086] Since the first transistor T1 can be configured as an N-type transistor, and the first power voltage VDD can be applied to the first electrode of the sixth transistor T6, the brightness variation caused by the hysteresis characteristics of the first transistor T1 and the sixth transistor T6 can be minimized.

[0087] Thus, the PWM method, which will be described later, can be used to drive the sub-pixels SPij with only a small number of transistors, enabling the display device to ensure a high pixel per inch (PPI).

[0088] Figure 4 It is shown Figure 1 The diagram shows the driving operation of the display device. Figure 5 It is shown Figure 1 The diagram shows a schematic timing diagram of an example of a display device performing a display scanning operation. Figure 6 It is shown Figure 1 The schematic timing diagram shows an example of the display device performing a self-scanning operation.

[0089] Reference Figure 1 , Figure 3 and Figure 4 A display scan operation (DISPLAY SCAN) or a self-scan operation (SELF SCAN) can be performed within a single frame (e.g., a single frame). When performing a display scan operation (DISPLAY SCAN), a data voltage VDATA can be written; and when performing a self-scan operation (SELF SCAN), a light emission operation can be performed without writing the data voltage VDATA.

[0090] At the maximum drive frequency of the display panel's DP (e.g., at a drive frequency of 240Hz), a display scan operation of one frame (e.g., a single frame) can be repeated continuously. A display scan operation of one frame (e.g., a single frame) can constitute a drive frame (e.g., a single drive frame).

[0091] At drive frequencies other than the maximum drive frequency of the display panel DP (e.g., in the case of a drive frequency of 240Hz) (i.e., 120Hz, 80Hz, 60Hz and 48Hz), a display scan operation DISPLAY SCAN can be performed in one frame (e.g., a single frame), and a self-scan operation SELF SCAN can be performed in at least one frame.

[0092] Specifically, at a drive frequency of 120Hz, a display scan operation (DISPLAY SCAN) of one frame (e.g., a single frame) and a self-scan operation (SELF SCAN) of one frame (e.g., a single frame) can be repeated. A single frame of display scan operation (DISPLAY SCAN) and a single frame of self-scan operation (SELF SCAN) can constitute a drive frame (i.e., the same image can be displayed during a drive frame (e.g., a single drive frame)). At a drive frequency of 80Hz, a display scan operation (DISPLAY SCAN) of one frame (e.g., a single frame) and a self-scan operation (SELF SCAN) of two frames can be repeated. A single frame of display scan operation (DISPLAY SCAN) and a self-scan operation (SELF SCAN) of two frames can constitute a drive frame (e.g., a single drive frame). At a drive frequency of 60Hz, a display scan operation (DISPLAY SCAN) of one frame (e.g., a single frame) and a self-scan operation (SELF SCAN) of three frames can be repeated. A single frame (e.g., a single-frame) display scan operation (DISPLAY SCAN) and three frames of self-scan operations (SELF SCAN) can constitute a driving frame (e.g., a single-drive frame). At a driving frequency of 48Hz, a single frame (e.g., a single-frame) display scan operation (DISPLAY SCAN) and four frames of self-scan operations (SELF SCAN) can be repeated. A single frame (e.g., a single-frame) display scan operation (DISPLAY SCAN) and four frames of self-scan operations (SELF SCAN) can constitute a driving frame (e.g., a single-drive frame).

[0093] Thus, the controller 150 can change the drive frequency by adjusting the length of the SELF SCAN operation.

[0094] Reference Figures 3 to 6 A frame FR may include a first subframe SF1 and at least one second subframe SF2. A data voltage VDATA may be written to the first subframe SF1 of the frame FR when performing a display scan operation (DISPLAY SCAN). A data voltage VDATA may not be written to the first subframe SF1 of the frame FR when performing a self-scan operation (SELF SCAN). A light-emitting element (LD) may emit light in the second subframe SF2.

[0095] exist Figure 5 and Figure 6 In this case, the number of second subframes SF2 in frame FR is 2. However, the disclosure is not limited to this.

[0096] Reference Figures 3 to 5 The first subframe SF1 of the frame FR that performs the display scan operation (DISPLAY SCAN) may include a first initialization period (IP1), a compensation period (CP), a second initialization period (IP2), and a write period (WP).

[0097] During the first initialization period IP1, the fourth transistor T4, the eighth transistor T8, and the tenth transistor T10 can be turned on. For example, during the first initialization period IP1, the first transmit signal EM1[i] can have a low voltage level, and the initialization gate signal GI[i] can have a high voltage level. The first power voltage VDD can be applied to the second node N2, and the initialization voltage VAINT can be applied to the fourth node N4. Therefore, the second capacitor C2 can be initialized. The second power voltage VSS can be applied to the anode electrode AE ​​of the light-emitting element LD. Therefore, the voltage charged in the light-emitting element LD can be released.

[0098] During the compensation period CP, the fourth transistor T4, the seventh transistor T7, and the tenth transistor T10 can be turned on. For example, the first transmit signal EM1[i] can have a low voltage level, and the second compensation gate signal GC2[i] can have a high voltage level. The voltage of the fourth node N4 can be charged to a voltage that reduces the threshold voltage of the sixth transistor T6 from the first power voltage VDD. The first power voltage VDD can be applied to the second node N2, and the second power voltage VSS can be applied to the anode electrode AE ​​of the light-emitting element LD.

[0099] During the second initialization period IP2, the third transistor T3, the fourth transistor T4, and the tenth transistor T10 can be turned on. For example, the first transmit signal EM1[i] can have a low voltage level, and the first compensation gate signal GC1[i] can have a high voltage level. The first power voltage VDD can be applied to the first node N1. Therefore, the first capacitor C1 can be initialized. The first power voltage VDD can be applied to the second node N2, and the second power voltage VSS can be applied to the anode electrode AE ​​of the light-emitting element LD.

[0100] During the write phase WP, the second transistor T2 and the third transistor T3 can be turned on, while the fourth transistor T4 and the tenth transistor T10 can be turned off. For example, the first transmit signal EM1[i] can have a high voltage level, and the first compensation gate signal GC1[i] and the write gate signal GW[i] can also have high voltage levels. The data voltage VDATA can be applied to the third node N3, and the voltage of the first node N1 can be charged to a voltage corresponding to the data voltage VDATA and the threshold voltage of the first transistor T1. Therefore, the data voltage VDATA can be written into the first capacitor C1. The voltage of the fourth node N4 can be changed in accordance with the voltage change of the second node N2.

[0101] The second subframe SF2 of frame FR may include the third initialization period IP3 and the transmission period EP.

[0102] During the third initialization period IP3, the fourth transistor T4 and the tenth transistor T10 can be turned on. For example, the first transmit signal EM1[i] can have a low voltage level. A first power voltage VDD can be applied to the second node N2. The voltage of the fourth node N4 can be changed correspondingly to the voltage change of the second node N2. A second power voltage VSS can be applied to the anode electrode AE ​​of the light-emitting element LD. Therefore, the voltage charged into the light-emitting element LD can be changed.

[0103] The scan voltage SV can be reduced before the transmission period EP in the second subframe SF2. The voltage of the first node N1 can be changed accordingly to the voltage change of the scan voltage SV.

[0104] During the emission period EP, the fifth transistor T5 and the ninth transistor T9 can be turned on. For example, the second emission signal EM2[i] can have a low voltage level. The scan voltage SV can be gradually increased. Before the scan voltage SV increases, the first transistor T1 may not generate the first drive current. As the scan voltage SV increases, the voltage of the control electrode of the first transistor T1 can increase, and the first transistor T1 can generate the first drive current. When the first drive current flows through the first transistor T1, the voltage of the second node N2 decreases. As the voltage of the second node N2 decreases, the voltage of the control electrode of the sixth transistor T6 can decrease, and the sixth transistor T6 can generate the second drive current. The light-emitting element LD can receive the second drive current to emit light.

[0105] The time it takes for the first transistor T1 to generate the first drive current can vary depending on the data voltage VDATA written into the first capacitor C1. For example, as the data voltage VDATA increases, the time it takes for the first transistor T1 to generate the first drive current can become faster. Therefore, the time it takes for the sixth transistor T6 to generate the second drive current can also become faster. For example, the emission time of the light-emitting element LD can vary depending on the data voltage VDATA, and the light-emitting element LD can represent various gray levels according to the emission time.

[0106] Reference Figure 3 , Figure 4 and Figure 6 During the SELF SCAN operation, the data voltage VDATA may not be written in the first subframe SF1 of frame FR. For example, in the first subframe SF1 of frame FR during the SELF SCAN operation, the first transmit signal EM1[i] and the second transmit signal EM2[i] may have high voltage levels, and the initialization gate signal GI[i], the first compensation gate signal GC1[i], the second compensation gate signal GC2[i], and the write gate signal GW[i] may have low voltage levels.

[0107] Figures 7 to 9 This is a schematic diagram illustrating an example of a display device according to a disclosed embodiment controlling the transmission time based on the transmission frequency.

[0108] In addition to the display device changing the number of second subframes according to the emission frequency, allowing the first portion of the row to emit light according to the emission frequency, and then allowing the second portion of the row to emit light, the display device according to these embodiments is configured to... Figure 1 The display devices shown are substantially the same. Therefore, identical or similar components are indicated by the same reference numerals, and repeated descriptions will be omitted.

[0109] Reference Figure 1 and Figures 5 to 8 The controller 150 can increase the transmission time of frame FR according to the transmission frequency. For example, the controller 150 can adjust the number of second subframes SF2 according to the transmission frequency. In embodiments, the transmission frequency can be set by the user or according to a user-defined mode. In embodiments, the transmission frequency can vary according to the ambient illuminance of the display device. However, the disclosure is not limited to the method of determining the transmission frequency.

[0110] The number of second subframes SF2 can increase as the transmission frequency increases. For example, the number of second subframes SF2 in frame FR at a first transmission frequency EF1 can be 1, and the number of second subframes SF2 in frame FR at a second transmission frequency EF2, which is higher than the first transmission frequency EF1, can be 2. For example, as the transmission frequency increases, the number of times the light-emitting element LD emits light in frame FR can increase, and the emission time in frame FR can increase. Therefore, relative to the same data voltage VDATA, the user can see higher brightness.

[0111] The length of the first subframe SF1 can be constant, and the length of the second subframe SF2 can vary depending on the number of second subframes SF2. However, although the length of the second subframe SF2 can be changed, the period during which the second transmitted signal EM2[i] in the second subframe SF2 has a low voltage level (i.e., the transmission time) can be constant.

[0112] Reference Figure 1 , Figures 5 to 7 and Figure 9 When the emission frequency does not exceed a specific frequency, the controller 150 may allow the rows including subpixels SP to emit light sequentially. When the emission frequency exceeds the specific frequency, the controller 150 may allow the first portion of the rows including subpixels SP (e.g., odd-numbered rows) to emit light, and then allow the second portion of the rows including subpixels SP (e.g., even-numbered rows) to emit light.

[0113] For example, the controller 150 can sequentially apply second transmission signals EM2[1], EM2[2], EM2[3], EM2[4], ... with low voltage levels to the first gate line GL1 to the m-th gate line GLm at a first transmission frequency EF1 and a second transmission frequency EF2. For example, at a third transmission frequency EF3 higher than the second transmission frequency EF2, the controller 150 can sequentially apply second transmission signals EM2[1], EM2[3], ... with low voltage levels to the odd-numbered gate lines, and then sequentially apply second transmission signals EM2[2], EM2[4], ... with low voltage levels to the even-numbered gate lines.

[0114] For example, at the third transmission frequency EF3, the controller 150 can use the period during which the second transmission signal EM2[i] has a high voltage level at the second transmission frequency EF2. Therefore, although the number of second subframes SF2 is the same at the second transmission frequency EF2 and the third transmission frequency EF3, the light can be perceived by the user as if the transmission time has been further increased at the third transmission frequency EF3, and the user can perceive a higher brightness.

[0115] In these embodiments, two methods can be used: one is to change the number of second subframes according to the transmission frequency, and the other is to allow the first part of the row to transmit light according to the transmission frequency and then allow the second part of the row to transmit light. However, the disclosure may use only one of the two methods.

[0116] Figure 10 This is a table illustrating an example of a display device adjusting an initialization voltage based on grayscale according to a disclosed embodiment. Figure 11 It shows the basis Figure 10 The graph shows an example of the second driving current in grayscale.

[0117] In addition to adjusting the initialization voltage VAINT, the display device according to these embodiments is configured to... Figure 1 The display devices shown are substantially the same. Therefore, identical or similar components are indicated by the same reference numerals, and repeated descriptions will be omitted.

[0118] Reference Figure 10 and Figure 11 The initialization voltage VAINT can be determined based on the grayscale GRAY. For example, if the grayscale GRAY has a first grayscale (e.g., grayscale 60G to grayscale 255G), the initialization voltage VAINT can have a first voltage V1. If the grayscale GRAY has a second grayscale (e.g., grayscale 0G to grayscale 59G), the initialization voltage VAINT can have a second voltage V2 that is higher than the first voltage V1.

[0119] As the initialization voltage VAINT increases, the peak current of the second drive current ILD can decrease. For example, as Figure 11 As shown, the peak current at a grayscale with an initialization voltage VAINT of the first voltage V1 (e.g., grayscale 255G and grayscale 60G) can be a first peak current PC1, and the peak current at a grayscale with an initialization voltage VAINT of the second voltage V2 (e.g., grayscale 57G and grayscale 31G) can be a second peak current PC2, which is smaller than the first peak current PC1. When the peak current is the same at all grayscales, the second drive current ILD at low grayscales may not reach its peak current. If the second drive current ILD does not reach its peak current, the advantages of the PWM method may disappear. Therefore, the initialization voltage VAINT can be increased at low grayscales so that the second drive current ILD can reach its peak current even at low grayscales.

[0120] In these embodiments, it is shown that the initialization voltage VAINT can be changed in two parts. However, the disclosure is not limited thereto.

[0121] Figure 12This is a schematic diagram of the equivalent circuit of any one of the sub-pixels of a display device according to a disclosed embodiment. Figure 13 It is shown Figure 12 The schematic timing diagram shown is an example of a display device driver that can perform a display scanning operation on the first subframe of a frame.

[0122] In addition to the seventh transistor T7 and the display scan operation (see...), Figure 4 In addition to the first subframe SF1 of the frame, the display device according to these embodiments is configured to be in conjunction with... Figure 1 The display devices shown are substantially the same. Therefore, identical or similar components are indicated by the same reference numerals, and repeated descriptions will be omitted.

[0123] Reference Figure 12 Subpixel SPij may include a seventh transistor T7, which includes a control electrode receiving the second compensation gate signal GC2[i], a first electrode connected to the fifth node N5, and a second electrode connected to the fourth node N4. Therefore, the transistor (e.g., a single transistor) is connected to the control electrode of the sixth transistor T6, thus reducing leakage current through the transistor connected to the control electrode of the sixth transistor T6.

[0124] Reference Figure 12 and Figure 13 The first subframe SF1 of the frame FR that performs the display scan operation (DISPLAY SCAN) may include the initialization period (IP), the initialization compensation period (ICP), and the write period (WP).

[0125] During the initialization period IP, transistors T4, T7, T8, and T10 can be turned on. For example, during the initialization period IP, the first transmit signal EM1[i] can have a low voltage level, and the initialization gate signal GI[i] and the second compensation gate signal GC2[i] can have a high voltage level. A first power voltage VDD can be applied to the second node N2, and an initialization voltage VAINT can be applied to the fourth node N4. Therefore, the second capacitor C2 can be initialized. A second power voltage VSS can be applied to the anode electrode AE ​​of the light-emitting element LD. Therefore, the voltage charged in the light-emitting element LD can be released.

[0126] During the initialization compensation period (ICP), transistors T3, T4, T7, and T10 can be turned on. For example, the first transmit signal EM1[i] can have a low voltage level, and the first compensation gate signal GC1[i] and the second compensation gate signal GC2[i] can have high voltage levels. The voltage of the fourth node N4 can be charged to a voltage that reduces the threshold voltage of the sixth transistor T6 from the first power voltage VDD. The first power voltage VDD can be applied to the first node N1. Therefore, the first capacitor C1 can be initialized. The first power voltage VDD can be applied to the second node N2, and the second power voltage VSS can be applied to the anode electrode AE ​​of the light-emitting element LD.

[0127] During the write phase WP, the second transistor T2 and the third transistor T3 can be turned on, while the fourth transistor T4 and the tenth transistor T10 can be turned off. For example, the first transmit signal EM1[i] can have a high voltage level, and the first compensation gate signal GC1[i] and the write gate signal GW[i] can also have high voltage levels. The data voltage VDATA can be applied to the third node N3, and the voltage of the first node N1 can be charged to a voltage corresponding to the data voltage VDATA and the threshold voltage of the first transistor T1. Therefore, the data voltage VDATA can be written into the first capacitor C1. The voltage of the fourth node N4 can be changed in accordance with the voltage change of the second node N2.

[0128] Figure 14 This is a schematic diagram of the equivalent circuit of any one of the sub-pixels of a display device according to a disclosed embodiment. Figure 15 It is shown Figure 14 The schematic timing diagram shown is an example of a display device driver that can perform a display scanning operation on the first subframe of a frame.

[0129] Except that the second transistor T2 can be a P-type transistor, the display device according to these embodiments is configured to be with Figure 1 The display devices shown are substantially the same. Therefore, identical or similar components are indicated by the same reference numerals, and repeated descriptions will be omitted.

[0130] Reference Figure 14 and Figure 15 The second transistor T2 can be a P-type transistor. Therefore, the write speed of the data voltage VDATA can be increased. Since the second transistor T2 can be a P-type transistor, the write gate signal GW[i] can have a low voltage level during the write period WP.

[0131] Figure 16 This is a schematic block diagram illustrating an embodiment of the display system.

[0132] Reference Figure 16 The display system 1000 may include a processor 1100 and a display device 1200.

[0133] Processor 1100 can perform various tasks and calculations. In embodiments, processor 1100 may include an application processor (AP), a graphics processing unit (GPU), a microprocessor, a central processing unit (CPU), etc. Processor 1100 can be connected to other components of display system 1000 via a bus system to control the components of display system 1000.

[0134] Processor 1100 can send image data IMG and control signal CTRL to display device 1200. Display device 1200 can display an image based on image data IMG and control signal CTRL. Display device 1200 can be configured to interact with a reference... Figure 1 The described display device DD is the same. Image data IMG and control signal CTRL can be provided as follows: Figure 1 The input image data IMG and control signal CTRL are shown in the figure.

[0135] Display system 1000 may include a computing system for providing image display functionality, such as a smartwatch, mobile phone, smartphone, portable computer, tablet PC, watch phone, car display, smart glasses, portable multimedia player (PMP), navigation system, or ultra-mobile computer (UMPC). Display system 1000 may include at least one of head-mounted display (HMD) device, virtual reality (VR) device, mixed reality (MR) device, and augmented reality (AR) device.

[0136] Figures 17 to 20 It is shown Figure 16 The image shows a perspective view of an application example of the display system.

[0137] Reference Figure 17 , Figure 16 The display system 1000 shown can be applied to a smartwatch 2000, which includes a display unit 2100 and a strap unit 2200.

[0138] The smartwatch 2000 can be a wearable electronic device. For example, the smartwatch 2000 may have a structure in which the strap 2200 can be mounted on the user's wrist. The display system 1000 and / or the display device 1200 may be applied to the display 2100 to provide the user with image data including time information.

[0139] Reference Figure 18 , Figure 16The display system 1000 shown can be applied to an automotive display system 3000. The automotive display system 3000 may include a computing system installed inside or outside the vehicle to provide image data.

[0140] For example, the display system 1000 and / or display device 1200 can be applied to at least one of the information panel 3100, instrument panel 3200, passenger display 3300, head-up display 3400, side mirror display 3500 and rear seat display 3600 that can be installed in a vehicle.

[0141] Reference Figure 19 , Figure 16 The display system 1000 shown can be applied to smart glasses 4000. Smart glasses 4000 can be a wearable electronic device that can be worn on a user's face. For example, smart glasses 4000 can be a wearable device for augmented reality (AR).

[0142] The smart glasses 4000 may include a frame 4100 and a lens portion 4200. The frame 4100 may include a housing 4110 supporting the lens portion 4200 and temples 4120 for allowing a user to wear the smart glasses 4000. The temples 4120 may be hinged to the housing 4110 to fold or unfold relative to the housing 4110.

[0143] The battery, touchpad, microphone, camera, etc., can be built into the frame 4100. For example, a projector for outputting light, a processor for controlling light signals, etc., can be built into the frame 4100.

[0144] The lens portion 4200 may be an optical component that allows light to pass through or to reflect light. For example, the lens portion 4200 may include glass, transparent synthetic resin, etc.

[0145] To enable the user's eyes to recognize visual information, the lens section 4200 allows the image caused by the light signal transmitted from the projector of the frame 4100 to be reflected by the rear surface of the lens section 4200 (e.g., the surface facing the user's eyes). For example, the user can recognize information displayed on the lens section 4200, including time, data, etc. The projector and / or lens section 4200 can be a display device. The display device 1200 can be applied to the projector and / or lens section 4200.

[0146] Reference Figure 20 , Figure 16 The display system 1000 shown can be applied to a head-mounted display device 5000.

[0147] The head-mounted display device 5000 can be a wearable electronic device that can be worn on a user's head. For example, the head-mounted display device 5000 can be a wearable device for virtual reality (VR) or mixed reality (MR).

[0148] The head-mounted display device 5000 may include a headband 5100 and a display housing 5200. The headband 5100 may be connected to the display housing 5200. The headband 5100 may include a horizontal strap and / or a vertical strap for securing the head-mounted display device 5000 to a user's head. The horizontal strap may be configured to surround the sides of the user's head, and the vertical strap may be configured to surround the top of the user's head. However, the embodiments are not limited thereto. For example, the headband 5100 may be implemented in the form of eyeglass frames, helmets, etc.

[0149] The display housing 5200 can accommodate the display system 1000 and / or the display device 1200.

[0150] The disclosure can be applied to display devices and electronic devices including such display devices. For example, the disclosure can be applied to digital TVs, 3D TVs, mobile phones, smartphones, tablet computers, VR devices, personal computers (PCs), home appliances, laptop computers, PDAs, PMPs, digital cameras, music players, portable game consoles, navigation systems, etc.

[0151] Example embodiments have been disclosed herein, and although specific terminology has been used, they are used and interpreted in a general and descriptive sense only and not for limiting purposes. In some instances, unless specifically indicated otherwise, it will be apparent to those skilled in the art at the time of filing that features, characteristics, and / or elements described in connection with specific embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the disclosure set forth in the appended claims.

Claims

1. A sub-pixel, the sub-pixel comprising: The first transistor generates a first drive current corresponding to the data voltage; The first capacitor includes a first electrode that receives a scan voltage and a second electrode that is connected to a control electrode of the first transistor. Drive the transistor to generate a second drive current; The second capacitor includes a first electrode connected to the first transistor and a second electrode connected to the control electrode of the driving transistor; as well as The light-emitting element receives the second driving current to emit light.

2. The sub-pixel according to claim 1, wherein the sub-pixel further comprises: The second transistor provides the data voltage to the first transistor in response to the write gate signal; The third transistor, in response to the first compensation gate signal, allows the first transistor to be connected by a diode; The fourth transistor provides a first power voltage to the first transistor in response to the first transmit signal; as well as A reset transistor provides an initialization voltage to the first transistor in response to a second transmit signal.

3. The sub-pixel according to claim 2, wherein, The first transistor includes a control electrode connected to the first capacitor, a first electrode connected to the second capacitor, and a second electrode. The second transistor is connected to the second electrode of the first transistor. The third transistor is connected to the control electrode of the first transistor and the first electrode of the first transistor. The fourth transistor is connected to the first electrode of the first transistor, and The reset transistor is connected to the second electrode of the first transistor.

4. The sub-pixel according to claim 2, wherein, The second transistor is an N-type transistor.

5. The sub-pixel according to claim 2, wherein, The second transistor is a P-type transistor.

6. The sub-pixel according to claim 2, wherein, The third transistor is an N-type transistor.

7. The sub-pixel according to claim 1, wherein the sub-pixel further comprises: A compensation transistor, in response to a second compensation gate signal, allows the driving transistor to be connected by a diode; Initialize the transistor by providing an initialization voltage to the driving transistor in response to an initialization gate signal; An emission control transistor is provided, which, in response to a second emission signal, connects the driving transistor to the light-emitting element; as well as A discharge transistor provides a second electrical voltage to the anode electrode of the light-emitting element in response to a first emission signal.

8. The sub-pixel according to claim 7, wherein, The driving transistor includes a control electrode connected to the second capacitor, a first electrode receiving a first electrical voltage, and a second electrode. The compensation transistor is connected to the control electrode of the driving transistor and the second electrode of the driving transistor, and The initialization transistor is connected to the control electrode of the driving transistor.

9. The sub-pixel according to claim 7, wherein, The driving transistor includes a control electrode connected to the second capacitor, a first electrode receiving a first electrical voltage, and a second electrode. The compensation transistor is connected to the control electrode of the driving transistor and the second electrode of the driving transistor, and The initialization transistor is connected to the second electrode of the driving transistor.

10. The sub-pixel according to claim 7, wherein, The compensation transistor is an N-type transistor.

11. The sub-pixel according to claim 1, wherein, The first transistor is an N-type transistor, and The driving transistor is a P-type transistor.

12. The sub-pixel according to claim 1, wherein the sub-pixel further comprises: The third capacitor includes a first electrode that receives a first electrical voltage and a second electrode that is connected to the control electrode of the driving transistor.

13. A display device, the display device comprising: The display panel includes at least one sub-pixel; as well as A display panel driver is configured to drive the display panel. Each of the at least one sub-pixel includes: The first transistor generates a first drive current corresponding to the data voltage; The first capacitor includes a first electrode that receives a scan voltage and a second electrode that is connected to a control electrode of the first transistor. Drive the transistor to generate a second drive current; The second capacitor includes a first electrode connected to the first transistor and a second electrode connected to a control electrode of the driving transistor; and The light-emitting element receives the second driving current to emit light.

14. The display device according to claim 13, wherein, Each of the at least one sub-pixel also includes: A reset transistor, which provides an initialization voltage to the first transistor in response to a second transmit signal; and The transistor is initialized by providing the initialization voltage to the driving transistor in response to the initialization gate signal, and The initialization voltage is determined based on the grayscale level.

15. The display device according to claim 14, wherein, When the grayscale has a first grayscale, the initialization voltage has a first voltage; and When the gray level has a second gray level that is lower than the first gray level, the initialization voltage has a second voltage that is higher than the first voltage.

16. The display device according to claim 13, wherein, A frame includes a first subframe and at least one second subframe. The light-emitting element emits light in at least one second subframe, and The number of the at least one second subframe is determined based on the transmission frequency.

17. The display device according to claim 13, wherein, The at least one sub-pixel includes a plurality of sub-pixels arranged in a plurality of rows, and The display panel driver is configured to allow a sub-pixel located in a first portion of the plurality of rows to emit light, and then allow a sub-pixel located in a second portion of the plurality of rows to emit light.

18. The display device according to claim 13, wherein, The at least one sub-pixel includes multiple sub-pixels, which are arranged in multiple rows. The display panel driver is configured to allow the plurality of sub-pixels included in the plurality of rows to emit light sequentially at a first emission frequency; and The display panel driver is further configured to allow a sub-pixel located in a first portion of the plurality of rows to emit light at a second emission frequency higher than the first emission frequency, and then allow a sub-pixel located in a second portion of the plurality of rows to emit light.

19. The display device according to claim 13, wherein, Each of the at least one sub-pixel includes: The second transistor provides the data voltage to the first transistor in response to the write gate signal; The third transistor, in response to the first compensation gate signal, allows the first transistor to be connected by a diode; The fourth transistor provides a first power voltage to the first transistor in response to the first transmit signal; A reset transistor provides an initialization voltage to the first transistor in response to a second transmit signal; A compensation transistor, in response to a second compensation gate signal, allows the driving transistor to be connected by a diode; Initialize the transistor by providing the initialization voltage to the driving transistor in response to the initialization gate signal; An emission control transistor, in response to the second emission signal, connects the driving transistor to the light-emitting element; and A discharge transistor provides a second electrical voltage to the anode electrode of the light-emitting element in response to the first emission signal.

20. The display device according to claim 19, wherein, The at least one sub-pixel further includes: a third capacitor, comprising a first electrode receiving the first electrical voltage and a second electrode connected to the control electrode of the driving transistor.

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