Three-dimensional memory device with compact word line driver transistor layout

Abstract

A memory device includes memory blocks and word line driver circuitry including pairs of word line driver transistors. Each of the memory blocks includes a word line sub-block. Each of the pairs of word line driver transistors includes a respective first word line driver transistor and a respective second word line driver transistor that share a common input node and have different respective first and second output nodes. A first subset of adjacent pairs of output nodes laterally spaced apart by a first portion of a dielectric isolation structure having a first width is electrically connected to a word line partition within a same word line sub-block, and a second subset of adjacent pairs of output nodes laterally spaced apart by a second portion of the dielectric isolation structure having a second width greater than the first width is electrically connected to a word line within a different word line sub-block.

Description

Related applications

[0001] This application claims priority to the following applications: U.S. Non-Provisional Application No. 18 / 423,770, filed January 26, 2024; and U.S. Non-Provisional Application No. 18 / 785,932, filed July 26, 2024; the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates generally to the field of semiconductor devices, and more particularly to three-dimensional memory devices having a compact word line driver transistor layout. Background Technology

[0003] A three-dimensional vertical NAND string with one bit per cell was disclosed in an article by T. Endoh et al. entitled “Novel Ultra High Density Memory With AStacked-Surrounding Gate Transistor (S-SGT) Structured Cell”, IEDM Proceedings (2001), pp. 33-36. Summary of the Invention

[0004] According to one aspect of this disclosure, a memory device includes: a plurality of memory blocks, wherein each of the plurality of memory blocks includes a corresponding three-dimensional array of memory elements and a corresponding word line block, the corresponding word line block including word lines for controlling the corresponding three-dimensional array of memory elements, wherein the corresponding word line block includes a corresponding plurality of word line sub-blocks, the corresponding plurality of word line sub-blocks containing a corresponding subset of all word lines within the corresponding word line block; and word line driver circuitry including a plurality of rows of word line driver transistor pairs, wherein: each row of word line driver transistor pairs includes a corresponding plurality of word line driver transistor pairs arranged along a first horizontal direction and located within corresponding openings in a dielectric isolation structure in a plan view; each of the word line driver transistor pairs... The word line driver transistor pair includes a corresponding first word line driver transistor and a corresponding second word line driver transistor, which share a corresponding common input node and have a first output node and a second output node. The first output node and the second output node are laterally spaced apart from each other along a second horizontal direction and electrically connected to corresponding word lines within the plurality of memory blocks. A first subset of adjacent pairs of output nodes, which are laterally spaced apart by a corresponding first portion of a dielectric isolation structure having a first width, is electrically connected to word lines within the same word line sub-block, and a second subset of adjacent pairs of output nodes, which are laterally spaced apart by a corresponding second portion of a dielectric isolation structure having a second width greater than the first width, is electrically connected to word lines within different word line sub-blocks.

[0005] According to another aspect of this disclosure, a method of forming a memory device includes: providing a memory die comprising a plurality of memory blocks, wherein each of the plurality of memory blocks comprises a corresponding three-dimensional array of memory elements and a corresponding word line block, the corresponding word line block comprising word lines for controlling the corresponding three-dimensional array of memory elements, wherein the corresponding word line block comprises a corresponding plurality of word line sub-blocks, the corresponding plurality of word line sub-blocks comprising a corresponding subset of all word lines within the corresponding word line block; providing a logic die comprising word line driver circuitry, the word line driver circuitry comprising a plurality of rows of word line driver transistor pairs, wherein each row of word line driver transistor pairs comprises a corresponding plurality of word line driver transistor pairs, the corresponding plurality of word line driver transistor pairs being arranged along a first horizontal direction and located within corresponding openings in a dielectric isolation structure in a plan view, each of these word line driver transistor pairs... A word line driver transistor pair includes a corresponding first word line driver transistor and a corresponding second word line driver transistor, which share a corresponding common input node and have a first output node and a second output node. The first output node and the second output node are laterally spaced apart from each other along a second horizontal direction. A first subset of adjacent pairs of output nodes, laterally spaced apart by a first portion of a dielectric isolation structure having a first width, is electrically connected to a word line within the same word line subblock. A second subset of adjacent pairs of output nodes, laterally spaced apart by a second portion of a dielectric isolation structure having a second width greater than the first width, is electrically connected to word lines within different word line subblocks. A logic die is bonded to a memory die such that each of the first output node and the second output node is electrically connected to a corresponding word line within the plurality of memory blocks.

[0006] According to one aspect of this disclosure, a memory device includes: a plurality of memory blocks, the plurality of memory blocks including respective word lines; and word line driver circuitry including a row of first word line driver transistors having a source-drain orientation and an additional row of second word line driver transistors having the same source-drain orientation as the first word line driver transistors. The first word line driver transistors include a first output node electrically connected to a word line in the first memory block of the plurality of memory blocks; the second word line driver transistors include a second output node electrically connected to a word line in the first memory block of the plurality of memory blocks; and the row of the first word line driver transistors is laterally offset along the source-drain orientation from the additional row of the second word line driver transistors.

[0007] According to another aspect of this disclosure, a memory device includes: a plurality of memory blocks, the plurality of memory blocks including respective word lines; and word line driver circuitry including a first word line driver transistor having a source-drain orientation, and a second, third, and fourth word line driver transistors having the same source-drain orientation as the first word line driver transistor. The first word line driver transistor includes a first output node having a first length, the first output node being electrically connected to a word line in a first memory block of the plurality of memory blocks. The second word line driver transistor includes a second output node having a first length, the second output node being electrically connected to another word line in the first memory block. The third word line driver transistor includes a first output node having a second length, the first output node being electrically connected to yet another word line in the first memory block. The fourth word line driver transistor includes a second output node having a second length, the second output node being electrically connected to a word line in a second memory block of the plurality of memory blocks. The first and second word line driver transistors are laterally spaced apart along a source-drain orientation by a first lateral spacing. The third word line driver transistor and the fourth word line driver transistor are laterally spaced apart by a second lateral spacing along the source-drain direction. The second lateral spacing is larger than the first lateral spacing, and / or the second length is longer than the first length.

[0008] According to another aspect of this disclosure, a semiconductor structure includes a bonding assembly of a memory die and a logic die. The memory die includes a plurality of memory blocks comprising corresponding alternating stacks of insulating layers and word lines, and a corresponding set of rows of memory opening-filled structures extending vertically through the corresponding alternating stacks and arranged along a first horizontal direction, wherein the memory blocks are laterally spaced from each other at a uniform inter-block spacing along a second horizontal direction perpendicular to the first horizontal direction. The logic die includes: a first two-dimensional array of first word line driver transistors and a second two-dimensional array of second word line driver transistors. The first two-dimensional array includes multiple rows of first word line driver transistors, and the second two-dimensional array includes multiple rows of second word line driver transistors. Each row of the first word line driver transistors is arranged along a first horizontal direction, and each row of the second word line driver transistors is arranged along the first horizontal direction. Each of the first and second word line driver transistors includes a first output node and a second output node. The first output node is electrically connected to a corresponding first word line in the word lines of the memory block and is laterally spaced from a common input node along a second horizontal direction via a corresponding first control gate electrode. The second output node is electrically connected to a corresponding second word line in the word lines of the memory block and is laterally spaced from the common input node along a direction opposite to the second horizontal direction via a corresponding second control gate electrode. The multiple rows of the first word line driver transistors are periodically modulated on a first inter-row spacing along the second horizontal direction, the first inter-row spacing being measured by the lateral spacing between adjacent pairs of first word line driver transistors laterally spaced along the second horizontal direction. Attached Figure Description

[0009] Figure 1A This is a schematic vertical cross-sectional view of an exemplary structure after the formation of the memory opening filling structure and the support column structure, according to an embodiment of the present disclosure.

[0010] Figure 1B yes Figure 1A A top view of an exemplary structure. Vertical plane AA is... Figure 1A The cutting plane of the vertical cross-sectional view.

[0011] Figure 1C This is a vertical cross-sectional view of the area of ​​the structure that fills the memory opening, which is an exemplary structure.

[0012] Figure 2A This is a vertical cross-sectional view of an exemplary structure after the formation of lateral isolation trenches, according to an embodiment of the present disclosure.

[0013] Figure 2B yes Figure 2A A top view of an exemplary structure. Vertical plane AA is... Figure 2A The cutting plane of the vertical cross-sectional view.

[0014] Figure 3 This is a schematic vertical cross-sectional view of an exemplary structure after the formation of a conductive layer, according to an embodiment of the present disclosure.

[0015] Figure 4A This is a vertical cross-sectional view of an exemplary structure after the formation of the lateral isolation trench filling structure, the layer contact via structure, and the drain contact via structure, according to an embodiment of the present disclosure.

[0016] Figure 4B yes Figure 4A A top view of an exemplary structure. Vertical plane AA is... Figure 4A The cutting plane of the vertical cross-sectional view.

[0017] Figure 5A This is a schematic vertical cross-sectional view of an exemplary structure after the formation of a bit-line hierarchical metal interconnect structure according to an embodiment of the present disclosure.

[0018] Figure 5B yes Figure 5A A top view of an exemplary structure. Vertical plane AA is... Figure 5A The cutting plane of the vertical cross-sectional view.

[0019] Figure 6 This is a vertical cross-sectional view of an exemplary structure after the formation of a memory die, according to an embodiment of the present disclosure.

[0020] Figure 7 This is a vertical cross-sectional view of a logic die according to an embodiment of this disclosure.

[0021] Figure 8 This is a vertical cross-sectional view of an exemplary structure after a logic die has been attached to a memory die, according to an embodiment of the present disclosure.

[0022] Figure 9 This is a vertical cross-sectional view of an exemplary structure after the substrate has been removed, according to an embodiment of the present disclosure.

[0023] Figure 10A This is a vertical cross-sectional view of an exemplary structure after the source structure has been formed, according to an embodiment of the present disclosure.

[0024] Figure 10B yes Figure 10A An enlarged view of the area of ​​an exemplary structure.

[0025] Figure 11This is a vertical cross-sectional view of an exemplary structure after the formation of the back-side dielectric layer and the source contact structure, according to an embodiment of the present disclosure.

[0026] Figure 12 This is a plan view of a first configuration of an exemplary structure, wherein word line driver transistors in a logic die are juxtaposed above blocks in a memory die.

[0027] Figures 13A to 13D This is a plan view of a second configuration of an exemplary structure according to an embodiment of the present disclosure, wherein word line driver transistors in a logic die are shown.

[0028] Figure 14A and Figure 14B This is a plan view of a third configuration of an exemplary structure according to an embodiment of the present disclosure, wherein word line driver transistors in a logic die are juxtaposed above blocks in a memory die.

[0029] Figure 15A and Figure 15B This is a plan view of a fourth configuration of an exemplary structure according to an embodiment of the present disclosure, wherein word line driver transistors in a logic die are shown.

[0030] Figure 16 This is a plan view of a fifth configuration of an exemplary structure according to an embodiment of the present disclosure, wherein word line driver transistors in a logic die are shown.

[0031] Figure 17 This is a plan view of a sixth configuration of an exemplary structure according to an embodiment of the present disclosure, wherein word line driver transistors in a logic die are shown.

[0032] Figure 18 This is a plan view of a seventh configuration of an exemplary structure according to an embodiment of the present disclosure, wherein word line driver transistors in a logic die are shown.

[0033] Figure 19A and Figure 19B This is a first schematic diagram illustrating the spatial overlap between a group of transistors in a logic die and a memory block in a memory die according to an embodiment of the present disclosure.

[0034] Figure 19C and Figure 19D yes Figure 19A or Figure 19B A plan view of two types of transistors in the same transistor group shown.

[0035] Figure 20 This is a second schematic diagram illustrating the spatial overlap between a group of transistors in a logic die and a memory block in a memory die according to an embodiment of the present disclosure.

[0036] Figure 21A A first exemplary organization scheme within a word line block in a memory die according to an embodiment of the present disclosure is illustrated.

[0037] Figure 21B A second exemplary organization scheme within a word line block in a memory die according to an embodiment of the present disclosure is illustrated.

[0038] Figure 21C A third exemplary organization scheme within a word line block in a memory die according to an embodiment of the present disclosure is illustrated.

[0039] Figure 22A This is a first exemplary layout of a word line driver circuit in a logic die according to an embodiment of the present disclosure, which is juxtaposed with a schematic plan view of a lateral isolation trench filling structure in a memory die.

[0040] Figure 22B This is a second exemplary layout of a word line driver circuit in a logic die according to an embodiment of the present disclosure, which is juxtaposed with a schematic plan view of a lateral isolation trench filling structure in a memory die.

[0041] Figure 22C This is a third exemplary layout of a word line driver circuit in a logic die according to an embodiment of the present disclosure, which is juxtaposed with a schematic plan view of a lateral isolation trench filling structure in a memory die. Detailed Implementation

[0042] As discussed above, embodiments of this disclosure relate to a three-dimensional memory device having a compact word line driver transistor layout, various aspects of which are described below. Embodiments of this disclosure can be used to form various structures including multi-level memory structures, non-limiting examples of which include three-dimensional memory devices comprising multiple memory strings.

[0043] The accompanying drawings are not to scale. Multiple instances of an element may be reproduced where only a single instance is illustrated, unless otherwise explicitly described or clearly indicated that a reproduction of the element does not exist. Ordinal numbers such as “first,” “second,” and “third” are used only to identify similar elements, and different ordinal numbers may be used in the specification and claims of this disclosure. The term “at least one” element refers to all possibilities, including the possibility of a single element and the possibility of multiple elements.

[0044] Like reference numerals denote the same or similar elements. Unless otherwise specified, elements with the same reference numerals are considered to have the same composition and the same function. Unless otherwise specified, “contact” between elements means direct contact between elements providing an edge or surface shared by these elements. If two or more elements are not in direct contact with each other or are not in direct contact with each other, the two elements are “separated” from each other or “separated” from each other. As used herein, an element located “on” a second element may be located on the outer side of the surface of the second element or on the inner side of the second element. As used herein, if there is physical contact between the surface of an element and the surface of a second element, the element is “directly” located “on” the second element. As used herein, if there is a conductive path consisting of at least one conductive material between an element and a second element, the element is “electrically connected” to the second element. As used herein, a “prototype” structure or a “process” structure refers to a transient structure whose shape or composition is subsequently modified.

[0045] As used herein, a “layer” refers to a portion of material comprising a region of thickness. A layer may extend over the entire underlying or overlying structure, or its extension may be less than the extension of the underlying or overlying structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between any pair of horizontal planes between the top and bottom surfaces of a continuous structure, or at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, and may include one or more layers, or may have one or more layers on, above, and / or below it.

[0046] Typically, a semiconductor die or semiconductor package may include a memory chip. Each semiconductor package contains one or more dies (e.g., one, two, or four). A die is the smallest unit capable of independently executing commands or reporting status. Each die contains one or more planes (typically one or two). Despite some limitations, the same, concurrent operations can be performed on each plane. Each plane contains multiple blocks, which can be the smallest unit that can be erased in a single erase operation. Alternatively, a block may include multiple sub-blocks. In this case, a sub-block can be the smallest unit that can be erased in a single erase operation. Each block contains multiple pages, which are programmable smallest units, i.e., the smallest units on which read operations can be performed. If sub-blocks are used, each sub-block contains a corresponding number of pages.

[0047] As used in this article, "semiconductor material" refers to a material with an electrical conductivity of 1 x 10⁻⁶. -5 S / m to 1x10 5Materials in the S / m range. As used herein, "semiconductor material" refers to a material in which the electrical conductivity is in the absence of electrical dopants and is 1 × 10⁻⁶. -5 Materials in the range of S / m to 1 S / m, and which, after appropriate doping with an electrical dopant, can produce conductivity in the range of 1 S / m to 1 × 10⁻⁶. 7 Doped materials in the S / m range. As used herein, “electrical dopant” refers to a p-type dopant that adds holes to the valence band within the band structure, or an n-type dopant that adds electrons to the conduction band within the band structure. As used herein, “conductive material” refers to a material with a conductivity greater than 1 x 10⁻⁶. 5 Materials with a conductivity of S / m. As used herein, "insulating material" or "dielectric material" refers to a conductivity less than 1 x 10⁻⁶. -5 Materials with a S / m ratio. As used herein, "heavily doped semiconductor material" refers to a semiconductor material doped with an electrically conductive agent at a sufficiently high atomic concentration to become a conductive material, which is formed as a crystalline material or transformed into a crystalline material through an annealing process (e.g., from an initial amorphous state), i.e., providing a value greater than 1 x 10⁻⁶. 5 The conductivity is S / m. "Doped semiconductor material" can be a heavily doped semiconductor material, or it can be a semiconductor material comprising electrically dopants (i.e., p-type dopants and / or n-type dopants) at a concentration of 1 x 10⁻⁶. -5 S / m to 1x10 7 Conductivity in the S / m range. "Intrinsic semiconductor material" refers to a semiconductor material that is not doped with an electrically conductive agent. Therefore, a semiconductor material can be semiconductor or conductive, and can be intrinsic or doped. A doped semiconductor material can be semiconductor or conductive, depending on the atomic concentration of the electrically conductive agent therein. As used herein, "metallic material" refers to a conductive material that includes at least one metallic element. All conductivity measurements were performed under standard conditions.

[0048] refer to Figures 1A to 1C This illustrates an exemplary structure according to embodiments of the present disclosure. The exemplary structure includes a substrate 9, which may be a semiconductor substrate or a conductive substrate. For example, substrate 9 may include a commercially available silicon wafer. Alternatively, substrate 9 may include any material that can be selectively removed relative to the material of insulating layer 32 and portions of dielectric material to be subsequently formed.

[0049] An alternating stack of a first material layer and a second material layer may be formed over the substrate 9. The first material layer may be an insulating layer, and the second material layer may be a spacer material layer. In one embodiment, the spacer material layer may include a sacrificial material layer 42. In this case, an alternating stack (32, 42) of insulating layer 32 and sacrificial material layer 42 may be formed over the substrate 9. Insulating layer 32 comprises an insulating material such as undoped silicate glass or doped silicate glass, and sacrificial material layer 42 comprises a sacrificial material such as silicon nitride or a silicon-germanium alloy. In one embodiment, insulating layer 32 (i.e., the first material layer) may include a silicon oxide layer, and sacrificial material layer 42 (i.e., the second material layer) may include a silicon nitride layer.

[0050] The alternating stacks (32, 42) may include multiple repetitions of a unit layer stack comprising an insulating layer 32 and a sacrificial material layer 42. The total number of repetitions of the unit layer stacks within the alternating stacks (32, 42) may be, for example, in the range of 8 to 1,024, such as 32 to 256, but smaller and larger repetitions may also be used. Hereinafter, the topmost insulating layer of the insulating layers 32 will be referred to as the topmost insulating layer 32T. The bottommost insulating layer of the insulating layers 32 is the insulating layer 32 closest to the substrate 9, which will be referred to herein as the bottommost insulating layer 32B.

[0051] Each insulating layer in the insulating layers 32, except for the topmost insulating layer 32, may have a thickness in the range of 20 nm to 100 nm, such as 30 nm to 60 nm, but smaller and larger thicknesses are also possible. Each sacrificial material layer in the sacrificial material layers 42 may have a thickness in the range of 20 nm to 100 nm, such as 30 nm to 60 nm, but smaller and larger thicknesses are also possible. In one embodiment, the topmost insulating layer 32 may have a thickness of approximately half that of the other insulating layers 32.

[0052] An exemplary structure includes a memory array region 100 and a contact region 300, in which a three-dimensional array of memory elements will subsequently be formed, and in which a layer contact via structure for contact word lines will subsequently be formed. A drain selection hierarchical isolation structure 72 may be formed through a subset of material layers in the alternating stacks (32, 42) located in the top portion of the alternating stacks (32, 42). The drain selection hierarchical isolation structure 72 may extend laterally along a first horizontal direction hd1.

[0053] While an embodiment in which the spacer material layer is formed as sacrificial material layer 42 is described, in an alternative embodiment, the spacer material layer may be formed as a conductive layer. Generally, the spacer material layer of this disclosure may be formed as a conductive layer, or may subsequently be at least partially replaced with a conductive layer.

[0054] A stepped surface is formed in the contact area 300. As used herein, a “stepped surface” refers to a set of surfaces comprising at least two horizontal surfaces and at least two vertical surfaces, such that each horizontal surface is adjacent to a first vertical surface extending upward from an edge of the horizontal surface and to a second vertical surface extending downward from a second edge of the horizontal surface. A stepped cavity is formed within the volume, from which alternatingly stacked portions (32, 42) are removed by forming the stepped surface. A “stepped cavity” refers to a cavity having a stepped surface.

[0055] The stepped cavity can have various stepped surfaces, such that the horizontal profile shape of the stepped cavity gradually varies according to the vertical distance from the top surface of the substrate 9. In one embodiment, the stepped cavity can be formed by repeatedly performing a set of processing steps. This set of processing steps may include, for example, a first type of etching process and a second type of etching process, the first type of etching process vertically increasing the depth of the cavity by one or more levels, and the second type of etching process laterally extending the area vertically etched in a subsequent first type of etching process. As used herein, a “hierarchy” comprising alternating plurality of structures is defined as the relative positions of a pair of first and second material layers within the structure.

[0056] Each sacrificial material layer 42 within the alternating stacks (32, 42), except for the topmost sacrificial material layer 42, extends laterally further than any overlying sacrificial material layer 42 within the alternating stacks (32, 42) in the mezzanine area. The stepped surface of the alternating stacks (32, 42) extends continuously from the bottommost layer (such as the bottommost insulating layer 32B) within the alternating stacks (32, 42) to the topmost layer (such as the topmost insulating layer 32T) within the alternating stacks (32, 42).

[0057] A stepped dielectric material portion 65 (i.e., an insulating filler portion) can be formed in a stepped cavity by depositing a dielectric material therein. For example, a dielectric material such as silicon oxide can be deposited in the stepped cavity. Excess portions of the deposited dielectric material can be removed, for example, from the top surface of the topmost insulating layer 32T by chemical mechanical planarization (CMP). The remaining portion of the deposited dielectric material filling the stepped cavity constitutes the stepped dielectric material portion 65. As used herein, a “stepped” element refers to an element having a stepped surface and a horizontal cross-sectional region that increases or decreases in steps as a function of the vertical distance from the top surface of the substrate on which the element is situated. If silicon oxide is used for the stepped dielectric material portion 65, the silicon oxide of the stepped dielectric material portion 65 may or may not be doped with dopants such as B, P, and / or F.

[0058] A first etch mask layer (not shown) may be formed over the alternating stacks (32, 42), and this first etch mask layer may be photolithographically patterned to form openings in the contact region 300. An anisotropic etching process may be performed to transfer the pattern of the openings in the first etch mask layer through the stepped dielectric material portion 65 and the alternating stacks (32, 42). Support openings may optionally be formed through the stepped dielectric material portion 65 and the alternating stacks (32, 42) in the contact region 300. Each support opening may extend vertically into the substrate 9. In one embodiment, the bottom surface of the support opening may be formed at or below the top surface of the substrate 9. The support openings may have a diameter in the range of 60 nm to 400 nm (e.g., 120 nm to 300 nm), but may employ smaller and larger thicknesses.

[0059] Dielectric filler material (such as silicon oxide) can be deposited in the support openings using a conformal deposition process. Excess portions of the dielectric filler material can be removed, for example, from the top surface of the topmost insulating layer 32T using a recess etching process. Each portion of the dielectric filler material filling the corresponding support opening constitutes a support pillar structure 20, which can be used to provide structural support to the insulating layer 32 and the stepped dielectric material portion 65 during the replacement of the sacrificial material layer 42 with a conductive layer. Alternatively, the support openings can be formed simultaneously with the memory openings in a later step, and the support pillar structure 20 can be formed in the support openings while the memory opening filler structure is formed in the memory openings, as will be described below.

[0060] A second etch mask layer may be formed over the alternating stacks (32, 42) and may be photolithographically patterned to form openings in the memory array region 100. An anisotropic etch process may be performed to transfer the pattern of the openings in the second etch mask layer through the alternating stacks (32, 42). The memory openings may be formed through the alternating stacks (32, 42) in the memory array region 100.

[0061] Each cluster of memory apertures may include multiple rows of memory apertures. Each row of memory apertures may include multiple memory apertures arranged at uniform spacing along a first horizontal direction hd1. The rows of memory apertures may be laterally spaced from each other along a second horizontal direction hd2 that may be perpendicular to the first horizontal direction hd2. In one embodiment, each cluster of memory apertures may be formed as a two-dimensional periodic array of memory apertures. The diameter of the memory apertures may be in the range of 60 nm to 400 nm (such as 120 nm to 300 nm), but smaller and larger thicknesses may be used. In an alternative embodiment, the same patterned photoresist layer is used to simultaneously form support apertures with the memory apertures.

[0062] Memory aperture filling structures 58 may be formed in each memory aperture. For example, a layer stack including a memory material layer 54 may be conformally deposited in each memory aperture. In an exemplary example, the layer stack may include an optional barrier dielectric layer 52, a memory material layer 54, and an optional dielectric pad 56. The memory material layer 54 includes a memory material, i.e., a material in which data bits can be stored. The memory material layer 54 may include a charge storage material (such as silicon nitride), a ferroelectric material, a phase change memory material, or any other memory material that can store data bits by inducing changes in resistivity, ferroelectric polarization, or any other measurable physical property. Where the memory material layer 54 includes a charge storage material, the optional dielectric pad 56 may include a tunneling dielectric layer.

[0063] A semiconductor channel material layer can be deposited over each memory film 50 by performing a conformal deposition process. If the semiconductor channel material layer is doped, it may have doping of a first conductivity type, which may be p-type or n-type. The thickness of the semiconductor channel material layer may be in the range of 5 nm to 50 nm (e.g., 10 nm to 30 nm), but smaller and larger thicknesses are also possible.

[0064] A dielectric core layer comprising a dielectric filling material (such as silicon oxide) can be deposited in the remaining volume of the memory opening. While conformal deposition processes (such as chemical vapor deposition) can be used to deposit the dielectric core layer, the conformality of conformal deposition processes may not be perfect. Therefore, the thickness of the bottom portion of the dielectric core layer at the bottom of each memory opening may be less than the thickness of the upper portion of the dielectric core layer at the top of each memory opening. The dielectric core layer may be vertically recessed such that each remaining portion of the dielectric core layer has a top surface at or near a horizontal plane including the bottom surface of the topmost insulating layer 32. Each remaining portion of the dielectric core layer constitutes a dielectric core 62.

[0065] Doped semiconductor material with a second conductivity type can be deposited in each recessed region above the dielectric core 62. The second conductivity type is the opposite of the first conductivity type. For example, if the first conductivity type is p-type, then the second conductivity type is n-type, and vice versa. The dopant concentration in the deposited semiconductor material can be 5 x 10⁻⁶. 18 / cm 3 Up to 2x10 21 / cm 3 Within a certain range, but smaller or larger dopant concentrations can also be used. The doped semiconductor material can be, for example, doped polysilicon.

[0066] Excess portions of the deposited semiconductor material doped with a second conductivity type, as well as horizontal portions of the semiconductor channel layer, can be removed, for example, from above a horizontal plane including the top surface of the top insulating layer 32T, via chemical mechanical planarization (CMP) or recess etching processes. Each remaining portion of the doped semiconductor material with the second conductivity type constitutes a drain region 63. Each retained portion of the semiconductor channel layer (doped with a first conductivity type) constitutes a vertical semiconductor channel 60.

[0067] Each portion of the layer stack, including the memory material layer 54 retained in the respective memory opening, constitutes a memory film 50. In one embodiment, the memory film 50 may include an optional barrier dielectric layer 52, a memory material layer 54, and an optional dielectric pad 56. Each adjacent combination of the memory film 50 and the vertical semiconductor channel 60 constitutes a memory stack structure 55. Each combination of the memory stack structure 55, the dielectric core 62, and the drain region 63 within the memory opening constitutes a memory opening fill structure 58. Each memory opening fill structure 58 includes a respective vertical stack of memory elements, which may include portions of the memory material layer 54 located at each level of the sacrificial material layer 42 (or generally, at each level of the spacer material layer that may be formed as a conductive layer or may subsequently be at least partially replaced by a conductive layer). In an alternative embodiment, a support pillar structure 20 may be formed in a support opening simultaneously with the formation of the memory opening fill structure 58 in the memory opening. In this case, the support pillar structure 20 comprises the same material as the memory opening fill structure 58.

[0068] refer to Figure 2A and Figure 2B A dielectric material, such as undoped silicate glass (i.e., silicon oxide) or doped silicate glass, can be deposited over the alternating stacks (32, 42) to form a contact-level dielectric layer 80. The thickness of the contact-level dielectric layer 80 can be in the range of 100 nm to 600 nm, such as 200 nm to 400 nm, but smaller and larger thicknesses are also possible.

[0069] A photoresist layer (not shown) may be applied over the contact-level dielectric layer 80 and may be photolithographically patterned to form elongated openings extending laterally along a first horizontal direction hd1 between adjacent clusters of the memory aperture-filled structure 58. An anisotropic etching process may be performed to transfer the pattern of the openings in the photoresist layer through the contact-level dielectric layer 80, the alternating stacks (32, 42), and the stepped dielectric material portions 65. Lateral isolation trenches 79 extending laterally along the first horizontal direction hd1 may be formed through the alternating stacks (32, 42), the stepped dielectric material portions 65, and the contact-level dielectric layer 80. Each lateral isolation trench 79 may include a pair of corresponding longitudinal sidewalls parallel to the first horizontal direction hd1 and extending vertically from the top surface of the contact-level dielectric layer 80 to the top surface of the substrate 9. The photoresist layer may then be removed, for example, by ashing.

[0070] refer to Figure 3 For example, an isotropic etching process can be used to introduce an etchant into the lateral isolation trench 79, which selectively etches the material of the sacrificial material layer 42 relative to the material of the insulating layer 32. Lateral recesses are formed in the volume of the sacrificial material layer 42 removed therefrom. The sacrificial material layer 42 can be selectively removed with respect to the materials of the insulating layer 32, the stepped dielectric material portion 65, and the outermost layer of the memory film 50. In one embodiment, the sacrificial material layer 42 may comprise silicon nitride, and the materials of the insulating layer 32 and the stepped dielectric material portion 65 may comprise silicon oxide.

[0071] The etching process for selectively removing the second material from the outermost layer of the first material and memory film 50 can be a wet etching process using a wet etching solution, or a vapor-phase (dry) etching process in which an etchant is introduced in the vapor phase into the lateral isolation trench 79. For example, if the sacrificial material layer 42 comprises silicon nitride, the etching process can be a wet etching process in which the exemplary structure is immersed in a wet etching bath containing phosphoric acid, which selectively etches silicon nitride relative to silicon oxide, silicon, and various other materials used in the art. The support pillar structure 20, the stepped dielectric material portion 65, and the memory stack structure 55 provide structural support, while the lateral recess exists within the volume previously occupied by the sacrificial material layer 42.

[0072] Each lateral recess can be a laterally extending cavity with a lateral dimension greater than the vertical extent of the cavity. In other words, the lateral dimension of each lateral recess can be greater than the height of the lateral recess. Multiple lateral recesses can be formed in the volume of the second material from which the sacrificial material layer 42 is removed. Compared to the lateral recesses, the memory opening in which the memory stack structure 55 is formed is referred to herein as a front opening or a front cavity.

[0073] Each of the plurality of lateral recesses may extend substantially parallel to the top surface of the substrate 9. The lateral recesses may be vertically defined by the top surface of the underlying insulating layer 32 and the bottom surface of the overlying insulating layer 32. In one embodiment, each lateral recess may always have a consistent height.

[0074] An external barrier dielectric layer may optionally be formed. The external barrier dielectric layer (if present) comprises a dielectric material that serves as the control gate dielectric for the control gate subsequently formed in the lateral recess. The external barrier dielectric layer is optional if barrier dielectric layer 52 is present within each memory opening. An external barrier dielectric layer is present if barrier dielectric layer 52 is omitted.

[0075] At least one conductive material can be deposited in the lateral recess by providing at least one reactive gas to the lateral recess via a lateral isolation trench 79. A metal barrier layer can be deposited in the lateral recess. The metal barrier layer comprises a conductive metal material that can be used as a diffusion barrier layer and / or adhesion promoting layer for a subsequently deposited metal filler material. The metal barrier layer may comprise a conductive metal nitride material, such as TiN, TaN, WN, or a stack thereof, or may comprise a conductive metal carbide material, such as TiC, TaC, WC, or a stack thereof. In one embodiment, the metal barrier layer can be deposited using a conformal deposition process, such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The thickness of the metal barrier layer can range from 2 nm to 8 nm (e.g., 3 nm to 6 nm), but smaller and larger thicknesses are also possible. In one embodiment, the metal barrier layer may consist substantially of a conductive metal nitride, such as TiN.

[0076] A metal filler material is deposited in a plurality of lateral recesses, on the sidewalls of at least one lateral isolation trench 79, and above the top surface of the contact layer dielectric layer 80 to form a metal filler material layer. The metal filler material can be deposited using conformal deposition methods, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or combinations thereof. In one embodiment, the metal filler material layer may consist substantially of at least one elemental metal. The at least one elemental metal of the metal filler material layer may be selected from, for example, tungsten, cobalt, ruthenium, titanium, and tantalum. In one embodiment, the metal filler material layer may consist substantially of a single elemental metal. In one embodiment, a fluorine-containing precursor gas (such as WF6) may be used to deposit the metal filler material layer. In one embodiment, the metal filler material layer may be a tungsten layer including residual levels of fluorine atoms as impurities. The metal filler material layer is separated from the insulating layer 32 and the memory stack structure 55 by a metal barrier layer, which is a metal barrier layer that prevents fluorine atoms from diffusing through it.

[0077] Multiple conductive layers 46 may be formed in multiple lateral recesses, and a continuous metal material layer may be formed on the sidewalls of each lateral isolation trench 79 and over the contact-level dielectric layer 80. Each conductive layer 46 includes a portion of a metal barrier layer and a portion of a metal filler layer, these portions being located between a pair of vertically adjacent dielectric material layers (such as a pair of insulating layers 32). The continuous metal material layer includes continuous portions of the metal barrier layer and continuous portions of the metal filler layer, these continuous portions being located in the lateral isolation trench 79 or over the contact-level dielectric layer 80.

[0078] The deposited metal material of the continuous conductive material layer is etched back from the sidewalls of each lateral isolation trench 79 and from above the contact-level dielectric layer 80 by performing an isotropic etching process of at least one conductive material in the lateral isolation trench 79. Each remaining portion of the metal material deposited in the lateral recess constitutes a conductive layer 46. Each conductive layer 46 may be a wire structure. Therefore, the sacrificial material layer 42 is replaced by the conductive layer 46. Generally, the conductive layer 46 can be formed by providing a metal precursor gas into the lateral isolation trench 79 and the lateral recess.

[0079] At least one uppermost conductive layer 46 may include at least one drain-side selected gate electrode 46D. At least one bottommost conductive layer 46 may include at least one source-side selected gate electrode 46S. The remaining conductive layers 46 may include word lines 46W. Each word line serves as a common control gate electrode for multiple vertical NAND strings (e.g., memory aperture-filled structure 58).

[0080] refer to Figure 4A and Figure 4B A dielectric filler material (such as silicon oxide) can be deposited in the lateral isolation trench 79. Excess portions of the dielectric filler material can be removed from above the contact-level dielectric layer 80. Each remaining portion of the dielectric filler material filling a corresponding lateral isolation trench 79 constitutes a lateral isolation trench fill structure 76, which may be a dielectric wall structure. In an alternative embodiment, insulating spacers with a tubular configuration can be formed in the peripheral portion of each lateral isolation trench 79, and through-stacked conductive via structures can be formed within a corresponding insulating spacer. In this case, each lateral isolation trench fill structure 76 may include a combination of a through-stacked conductive via structure and insulating spacers laterally surrounding the through-stacked conductive via structure. The region between adjacent lateral isolation trench fill structures 76 corresponds to a corresponding memory block (99A, 99B), such as... Figure 4B As shown.

[0081] Contact via structures (88, 86) can be formed through the contact-level dielectric layer 80 and optionally through the stepped dielectric material portion 65. For example, a drain contact via structure 88 can be formed through the contact-level dielectric layer 80 on each drain region 63. A layer contact via structure 86 can be formed on the conductive layer 46 through the contact-level dielectric layer 80 and through the stepped dielectric material portion 65.

[0082] refer to Figure 5A and Figure 5B A bitline level dielectric layer 120 may be formed over the contact level dielectric layer 80. Bitline level cavities may be formed through the bitline level dielectric layer 120 and may be filled with at least one conductive material (which may include at least one metallic material) to form bitline level metal lines (128, 126). Bitline level metal lines 128 may include bitlines 128 extending laterally along a second horizontal direction hd2, and bitline level interconnect metal lines 126 (not shown separately) that can be used to provide electrical connections to the layer contact via structure 86.

[0083] Referring to FIG. 60, additional dielectric material layers and additional metal interconnect structures may be formed above the bit-line level dielectric layer 120. The additional dielectric material layers may include at least one via-level dielectric layer, at least one additional line-level dielectric layer, and / or at least one additional line and via-level dielectric layer. The additional metal interconnect structures may include metal via structures, metal line structures, and / or integrated metal line and via structures. The dielectric material layers formed above the contact-level dielectric layer 80 are collectively referred to herein as memory-side dielectric material layer 960. The additional metal interconnect structures are collectively referred to as memory-side dielectric material layer 960. Memory-side dielectric material layer 960 includes bit-line level dielectric material layers with embedded bit lines, which are subsets of memory-side metal interconnect structures 980.

[0084] Metal bonding pads (referred herein to as memory-side bonding pads 988) may be formed at the topmost layer of the memory-side dielectric material layer 960. The memory-side bonding pads 988 may be electrically connected to the memory-side metal interconnect structure 980 and various nodes of the three-dimensional memory array, which includes alternating stacks of insulating layers 32 and conductive layers 46 and memory opening-filling structures 58. Thus, a memory die 900 may be provided.

[0085] A memory-side dielectric material layer 960 is formed over alternating stacks (32, 46). A memory-side metal interconnect structure 980 is embedded in the memory-side dielectric material layer 960. A memory-side bonding pad 988 may be embedded within the memory-side dielectric material layer 960, and specifically embedded in the topmost layer of the memory-side dielectric material layer 960. The memory-side bonding pad 988 may be electrically connected to the memory-side metal interconnect structure 980.

[0086] In summary, the memory die 900 includes a memory array (32, 46, 58), a memory-side metal interconnect structure 980, and memory-side bonding pads 988 embedded within a memory-side dielectric material layer 960. The memory array may include a three-dimensional memory array comprising alternating stacks of insulating layer 32 and conductive layer 46, and also includes a two-dimensional array of NAND strings (e.g., memory aperture-filled structure 58) extending vertically through the alternating stacks (32, 46). In one embodiment, the conductive layer 46 includes word lines and select gate electrodes for the two-dimensional array of NAND strings. In one embodiment, the memory-side metal interconnect structure 980 includes bit lines for the two-dimensional array of NAND strings.

[0087] refer to Figure 7 A logic die 700 may be provided. The logic die 700 includes a logic-side substrate 709, peripheral circuitry 720 located on the logic-side substrate 709 and including logic-side semiconductor devices (such as field-effect transistors), a logic-side metal interconnect structure 780 embedded within a logic-side dielectric material layer 760, and logic-side bonding pads 778. The peripheral circuitry 720 may be configured to control the operation of a memory array within the memory die 900. Specifically, the peripheral circuitry 720 may be configured to drive various electrical components within the memory array, including (but not limited to) a conductive layer 46, a drain region 63, and subsequently formed source contact structures. The peripheral circuitry 720 may be configured to control the vertical stacking of memory elements in the memory array within the memory die 900. Specifically, the peripheral circuitry 720 includes word line driver transistors configured to drive word lines 46W in the memory die 900.

[0088] refer to Figure 8 The logic die 700 can be attached to the memory die 900, for example, by bonding logic-side bonding pads 788 to memory-side bonding pads 988 at a bonding interface. The bonding between the memory die 900 and the logic die 700 can be performed using a wafer-to-wafer bonding process (in which a two-dimensional array of memory dies 900 is bonded to a two-dimensional array of logic dies 700), a die-to-die bonding process, or a die-to-die bonding process. The logic-side bonding pads 788 within each logic die 700 can be bonded to the memory-side bonding pads 988 within the corresponding memory die 900.

[0089] refer to Figure 9 The substrate 9 can be removed, for example, by grinding, polishing, pyrolysis, isotropic etching processes, anisotropic etching processes, and / or combinations thereof. In one embodiment, at least one final step of at least one removal process for removing the substrate 9 may include a selective wet etching process that selectively etches the material of the substrate 9 (such as the semiconductor material of the substrate 9) relative to the dielectric material of the memory film 50. In an exemplary example, if the substrate 9 comprises a semiconductor material, the final step of the at least one removal process may include a wet etching process using thermal trimethyl-2-hydroxyethyl ammonium hydroxide (“thermal TMY”) or tetramethylammonium hydroxide (TMAH). The entire substrate 9 can be removed by a selective wet etching process. The back-side end surface of the support pillar structure 20 may be physically exposed after the substrate 9 is removed.

[0090] refer to Figure 10A and Figure 10B The end portions of each memory opening filling structure 58 can be removed. In one embodiment, the end portions of each memory film 50 can be removed by performing a series of wet etching processes. The horizontal end portions of each vertical semiconductor channel 60 can be physically exposed. In one embodiment, the sequence of the wet etching processes can be selective for the material of the vertical semiconductor channel 60.

[0091] One or more source structures (e.g., one or more source lines) 22 may be formed in the contact vertical semiconductor channel 60. The source structure 22 may include heavily doped semiconductor material and / or metal material (e.g., metal and / or conductive metal nitride or silicide). Figure 10B The illustration shows an optional external barrier dielectric layer 44, each external barrier dielectric layer embedding a corresponding conductive layer 46. Alternatively, the optional external barrier dielectric layer 44 may be omitted.

[0092] refer to Figure 11 Subsequently, a back-side dielectric layer 26 and a source contact structure 6 may be formed that are in contact with one or more source structures 22.

[0093] While the bonding assembly of memory die 900 and logic die 700 has been described above, in an alternative embodiment, peripheral circuitry 720 and the memory array (32, 46, 58) may be located in the same die. In this alternative embodiment, peripheral circuitry 720 may be formed over substrate 9, and then the memory array (32, 46, 58) may be formed over peripheral circuitry 720.

[0094] Figure 12This is a plan view of a first configuration of an exemplary structure, wherein word line driver transistors 722 in logic die 700 are juxtaposed above memory blocks in memory die 900. In the illustrated example, the region of the first memory block 99A is designated "Block A," and the region of the second memory block 99B is designated "Block B." Generally, memory die 900 includes a plurality of memory blocks (99A, 99B) comprising alternating stacks of insulating layer 32 and word lines 46W, and corresponding sets of rows of memory opening filling structures 58 extending vertically through the respective alternating stacks and arranged along a first horizontal direction hd1. The memory blocks (99A, 99B) are laterally spaced from each other along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1 with a uniform block spacing p_bb. The first horizontal direction hd1 may be the direction of word lines 46W, and the second horizontal direction hd2 may be the direction of bit lines 128. Figure 4B In one described embodiment, adjacent memory blocks (99A, 99B) may be spaced apart from each other along the second horizontal direction hd2 by corresponding lateral isolation trench fill structures 76. Thus, each region of the memory die 900 between two adjacent lateral isolation trench fill structures 76 may include a corresponding memory block (99A, 99B).

[0095] The peripheral circuitry 720 in the logic die 700 includes multiple sets of word line driver transistors 722. For example, a first set of word line driver transistors 722 labeled "Transistor Group A" and a second set of word line driver transistors 722 labeled "Transistor Group B" may be arranged in the logic die 700 along a first horizontal direction hd1, which is the word line direction in the three-dimensional memory array in the memory die 900. The first set of word line driver transistors 722 includes a first word line driver transistor 722A, and the second set of word line driver transistors 722 includes a second word line driver transistor 722B.

[0096] In one embodiment, the logic die 700 includes a first word line driver transistor 722A (such as a first group of word line driver transistors 722 in transistor group A) and a second word line driver transistor 722B (such as a second group of word line driver transistors 722 in transistor group B). Each of the first word line driver transistor 722A and the second word line driver transistor 722B includes a first output node 1 (i.e., a bias voltage output node) and also includes a second output node 2 (i.e., a bias voltage output node). The first output node is electrically connected to a corresponding first word line 46W and is laterally spaced from a common input node 3 (i.e., a bias voltage input node) along a second horizontal direction hd2 via a corresponding first control gate electrode 11. The second output node is electrically connected to a corresponding second word line 46W and is laterally spaced from the common input node (i.e., a bias voltage input node 3) along a direction opposite to the second horizontal direction hd2 via a corresponding second control gate electrode 12. In one embodiment, within each first word line driver transistor 722A and each second word line driver transistor 722A, a first output node, a second output node, and a common input node include a corresponding first source / drain region, a corresponding second source / drain region, and a corresponding third source / drain region, which are part of a corresponding active semiconductor region 4 laterally surrounded by a dielectric isolation structure (such as a shallow isolation trench structure). The active semiconductor region 4 includes the source / drain regions (1, 2, 3) and a semiconductor channel region between the source / drain regions. Bias voltage output nodes (1 and 2) may include transistor drain regions, and bias voltage input node 3 may include transistor source regions, and vice versa.

[0097] In one embodiment, a first word line driver transistor 722A is arranged in rows extending along a first horizontal direction hd1 and spaced apart from each other along a second horizontal direction hd2. In one embodiment, a second word line driver transistor 722B is arranged in an additional row extending along the first horizontal direction hd1 and spaced apart from each other along the second horizontal direction hd2. In one embodiment, the rows of the first word line driver transistors 722A and the additional rows of the second word line driver transistors 722B are offset laterally along the second horizontal direction hd2 by a lateral offset distance, such as a uniform first lateral offset distance LOD1.

[0098] In one embodiment, each source / drain region of the first word line driver transistor 722A and the second word line driver transistor 722B electrically connected to the corresponding word line 46W in the same corresponding memory block 99A or 99B has regional overlap with the corresponding memory block 99A or 99B in a plan view along the vertical direction, and has no regional overlap with any other memory block in the plan view. In other words, the source or drain region of the word line driver transistor 722 electrically connected to the word line 46W in the corresponding memory block 99A is located above or below the same corresponding memory block 99A, but not above or below other memory blocks 99B.

[0099] In one embodiment, for each of the first word line driver transistor 722A and the second word line driver transistor 722A, the corresponding first source / drain region 1 overlaps only with the corresponding first memory block in memory block 99A in a plan view along the vertical direction, and the corresponding second source / drain region 2 overlaps only with the corresponding second memory block in memory block 99B, which is different from the first memory block 99A. For example, the source or drain region 1 of the first word line driver transistor 722A electrically connected to the word line 46W in the first memory block 99A is located above or below the first memory block 99A. Similarly, the first source or drain region 1 of the second word line driver transistor 722B electrically connected to the word line 46W in the first memory block 99A is also located above or below the first memory block 99A. However, the second source or drain region 2 of the same second word line driver transistor 722B that is electrically connected to the word line 46W in the second memory block 99B is not located above or below the first memory block 99A, but is located above or below the second memory block 99B.

[0100] In one embodiment, all metal interconnect structures 780 that provide electrical connections between word lines 46W in the respective memory block 99A and the output node 1 of the first word line driver transistor 722A or the second word line driver transistor 722A are located entirely within the area of ​​the respective memory block 99A in a plan view along the vertical direction.

[0101] In one embodiment, for each of the first word line driver transistor 722A and the second word line driver transistor 722B, the active semiconductor region 4 has the same active region length along the second horizontal direction hd2; and the same active region length is equal to or greater than the uniform inter-block spacing p_bb.

[0102] In one embodiment, word line driver transistor 722 spans the boundary (e.g., lateral trench isolation fill structure 76) between adjacent memory blocks 99A and 99B. For example, the active semiconductor region 4 of each word line driver transistor in word line driver transistor 722 spans the boundary (e.g., lateral trench isolation fill structure 76) between adjacent memory blocks 99A and 99B (i.e., located above or below the boundary), such that the output nodes 1 and 2 of the same word line driver transistor 722 are located above or below different corresponding memory blocks 99A and 99B.

[0103] In one embodiment, the geometric center of each first word line driver transistor 722A within a row of first word line driver transistors 722A in transistor group A may be laterally offset by a first distance D1 along a second horizontal direction hd2 with respect to the boundary (e.g., lateral trench isolation fill structure 76) between an adjacent pair of memory blocks 99A and 99B; and the geometric center of each second word line driver transistor 722B within a row of second word line driver transistors 722B in transistor group B may be laterally offset by a second distance D2 along the opposite direction of the second horizontal direction hd2 with respect to the boundary (e.g., lateral trench isolation fill structure 76) between an adjacent pair of memory blocks 99A and 99B. The sum of the first distance D1 and the second distance D2 is different from the uniform transistor row spacing TRRP.

[0104] In one implementation, rows of the first word line driver transistor 722A are spaced along the second horizontal direction hd2 with a uniform transistor row spacing TRRP; additional rows of the second word line driver transistor 722B are arranged to be spaced along the second horizontal direction hd2 with a uniform transistor row spacing TRRP; the uniform transistor row spacing TRRP is (n+1) / n times the uniform block spacing p_bb; and n is an integer greater than 1 and less than 7. In other words, n can be an integer selected from 2, 3, 4, 5, and 6.

[0105] In one embodiment, each row of the output nodes (1, 2) of the word line driver transistor 722 constitutes a track for output node 1 or 2. Therefore, each row of the word line driver transistor 722 includes two tracks for the output node. For example, a row of the first word line driver transistor 722A spanning the boundary region (which may include a lateral trench isolation fill structure 76) between the first memory block 99A and the second memory block 99B includes track-1 for output node 2 located above or below the first memory block 99A, and track-2 for output node 1 located above or below the second memory block 99B. Figure 12 Five tracks are shown (track-0, track-1, track-2, track-3 and track-4).

[0106] Generally, the tracks within transistor group A can be laterally offset along the second horizontal direction hd2 from the tracks within transistor group B. Each track of the output node having regional overlap with the corresponding memory block 99A or 99B can be electrically connected to the corresponding word line 46W within the corresponding memory block 99A or 99B.

[0107] In one embodiment, the integer n is 2; the memory blocks include a first memory block (such as block A) 99A and a second memory block (such as block B) 99B; and each of the first word line driver transistor 722A and the second word line driver transistor 722B having an output node 1 or 2 electrically connected to a word line 46W in the first memory block 99A includes another output node 2 or 1 electrically connected to a corresponding word line 46W in another memory block (e.g., the second memory block 99B) that is not the first memory block 99A.

[0108] In one embodiment, the first word line driver transistor 722A includes a first row of first word line driver transistors 722A (which may be located in, for example, rails -1 and rails -2) and a second row of first word line driver transistors 722A (which may be located in, for example, rails -3 and rails -4) spaced apart along the second horizontal direction hd2. The second word line driver transistor 722B includes a first row of second word line driver transistors 722B (which may be located in, for example, rails -0 and rails -1) and a second row of second word line driver transistors 722B (which may be located in, for example, rails -2 and rails -3) spaced apart along the second horizontal direction hd2. In one embodiment, word lines 46W in a first memory block (such as block A) 99A are electrically connected via interconnect structure 780 to a first output node 1 of a first row first word line driver transistor 722A (located on track -1), a second output node 2 of a first row second word line driver transistor 722B (located on track -1), and a first output node 1 of a second row second word line driver transistor 722B (located on track 2). Word lines 46W in a second memory block B (such as block B) 99B are electrically connected to a second output node 2 of a first row first word line driver transistor 722A (located on track -2), a first output node 1 of a second row first word line driver transistor 722A (located on track -3), and a second output node 2 of a second row second word line driver transistor 722B (located on track -3).

[0109] In one embodiment, a corresponding first word line 46W is located in a corresponding first memory block 99A; and a corresponding second word line 46W is located in a corresponding second memory block 99B, which is an adjacent memory block to the first memory block 99A. In one embodiment, the memory die 900 includes rows of layer contact via structures 86 arranged along a first horizontal direction hd1; and each row of layer contact via structures 86 has word lines 46W in alternating stacks (32, 46) of electrical and / or physical contacts.

[0110] Figures 13A to 13D This is a plan view of a second configuration of an exemplary structure according to an embodiment of the present disclosure, showing word line driver transistors 722 in a logic die 700. Each row of layer contact via structures 86 is formed within a region of a corresponding memory block in a memory die 900. Each adjacent pair of rows of layer contact via structures 86 is formed over a corresponding adjacent pair of memory blocks 99A, 99B in the memory die 900.

[0111] refer to Figure 13A Transistor group A and transistor group B may be laterally spaced from each other along a first horizontal direction hd1. Each transistor group may be electrically connected to multiple rows of layer contact via structure 86, which are electrically connected to word lines 46W in the corresponding memory block.

[0112] refer to Figure 13B Two instances of transistor group A and two instances of transistor group B can be arranged along a first horizontal direction hd1, and are mirror-symmetrical along a vertical plane perpendicular to the first horizontal direction hd1. A subset of the layer contact via structure 86 can be arranged as an array extending across the boundary between the instances of transistor group A and the instances of transistor group B. Figure 13C and 13D Alternative arrangements of two instances of transistor group A and two instances of transistor group B are shown.

[0113] Figure 14A and Figure 14B This is a plan view of a third configuration of an exemplary structure according to an embodiment of the present disclosure, wherein word line driver transistors 722 in logic die 700 are juxtaposed above blocks in memory die 900. Figure 14A and Figure 14B The example illustrates the case where the integer n is 3.

[0114] In one embodiment, the memory block includes a first memory block (such as block A) 99A, a second memory block (such as block B) 99B, and a third memory block (such as block C) 99C. Each of a first word line driver transistor 722 and a second word line driver transistor 722 having an output node electrically connected to a word line 46W in the first memory block includes another output node electrically connected to a corresponding word line 46W in a memory block that is not the first memory block.

[0115] In one embodiment, a first word line driver transistor 722 is arranged in rows extending along a first horizontal direction hd1 and spaced apart from each other along a second horizontal direction hd2. A second word line driver transistor 722 is arranged in additional rows extending along the first horizontal direction hd1 and spaced apart from each other along the second horizontal direction hd2. A third word line driver transistor 722 is arranged in further additional rows extending along the first horizontal direction hd1 and spaced apart from each other along the second horizontal direction hd2. In one embodiment, the rows of the first word line driver transistors 722 and the additional rows of the second word line driver transistors 722 are offset by a uniform lateral offset distance along the second horizontal direction hd2, such as a first lateral offset distance LOD1. In one embodiment, the rows of the second and third word line driver transistors 722 are offset by a uniform lateral offset distance along the second horizontal direction hd2, such as a second lateral offset distance LOD2. The first lateral offset distance LOD1 differs from the uniform transistor row spacing TRRP. The second lateral offset distance LOD2 differs from the uniform transistor inter-row spacing TRRP.

[0116] In one embodiment, the geometric center of each first word line driver transistor 722 within a row of first word line driver transistors 722 in transistor group A may be laterally offset by a first distance D1 along a second horizontal direction hd2 to the boundary between an adjacent pair of memory blocks (such as the boundary between block A and block B); and the geometric center of each second word line driver transistor 722 within a row of second word line driver transistors 722 in transistor group B may be laterally offset by a second distance D1 along the opposite direction of the second horizontal direction hd2 to the boundary between an adjacent pair of memory blocks (such as the boundary between block A and block B). The sum of the first distance D1 and the second distance D2 is different from the uniform transistor row spacing TRRP. In one embodiment, the geometric center of each third word line driver transistor 722 within a row of third word line driver transistors 722 in transistor group C may be laterally offset by a third distance D3 along a second horizontal direction hd2 to the boundary between an adjacent pair of memory blocks (such as the boundary between block A and block B), the third distance being different from the first distance D1. The sum of the third distance D3 and the second distance D2 is different from the uniform transistor row spacing TRRP.

[0117] In one embodiment, the first word line driver transistor 722 includes a first row of first word line driver transistors 722 (located in rails 1 and 2) and a second row of first word line driver transistors 722 (located in rails 3 and 4) spaced apart along the second horizontal direction hd2; the second word line driver transistor 722 includes a first row of second word line driver transistors 722 (located in rails 0 and 1), a second row of second word line driver transistors 722 (located in rails 2 and 3) and a third row of second word line driver transistors 722 (located in rails 4 and 5) spaced apart along the second horizontal direction hd2. In one embodiment, the first output node of the first word line driver transistor 722 (located in rail 1), the second output node of the first word line driver transistor 722 (located in rail 1), and the first output node of the second word line driver transistor 722 (located in rail 2) are electrically connected to the corresponding word line 46W in the first memory block; the second output node of the first word line driver transistor 722 (located in rail 2), the first output node of the second word line driver transistor 722 (located in rail 3), and the second output node of the second word line driver transistor 722 (located in rail 3) are electrically connected to the corresponding word line 46W in the second memory block. The second output node of the second word line driver transistor 722 (located in rail 4) and the first output node of the third word line driver transistor 722 (located in rail 4) are electrically connected to the corresponding word line 46W in the third memory block.

[0118] refer to Figure 14AThe third word line driver transistor 722C may be disposed within transistor group C, which is laterally offset from transistor group B along a first horizontal direction hd1. The third word line driver transistor 722C includes a first row of third word line driver transistors 722C (located in rails -0 and -1), a second row of third word line driver transistors 722C (located in rails -2 and -3), and a third row of third word line driver transistors 722C (located in rails -4 and -5) spaced apart along a second horizontal direction hd2. In one embodiment, the second output node 2 of the first row third word line driver transistor 722C (located in rail-1) is electrically connected to the corresponding word line 46W in the first memory block (i.e., block A) 99A; the first output node 1 of the second row third word line driver transistor 722C (located in rail-2) is electrically connected to the corresponding word line 46W in the second memory block B (i.e., block B) 99B; and the second output node 2 of the second row third word line driver transistor 722C (located in rail-3) and the first output node 1 of the third row third word line driver transistor 722C (located in rail-4) are electrically connected to the corresponding word line 46W in the third memory block (i.e., block C) 99C.

[0119] refer to Figure 14B The third word line driver transistor 722C may be disposed within transistor group C, which is laterally offset from transistor group B along a first horizontal direction hd1. The third word line driver transistor 722C includes a first row of third word line driver transistors 722C (located in rails-1 and rails-2) and a second row of third word line driver transistors 722C (located in rails-3 and rails-4) spaced along a second horizontal direction hd2. In one embodiment, the first output node 1 of the first row third word line driver transistor 722C (located in rail-1) is electrically connected to the corresponding word line 46W in the first memory block (i.e., block A) 99A; the second output node 2 of the first row third word line driver transistor 722C (located in rail-2) and the first output node 1 of the second row third word line driver transistor 722C (located in rail-3) are electrically connected to the corresponding word line 46W in the second memory block B (i.e., block B) 99B; and the second output node 2 of the second row third word line driver transistor 722C (located in rail-4) is electrically connected to the corresponding word line 46W in the third memory block (i.e., block C) 99C.

[0120] Figure 15A and Figure 15BThis is a plan view of a fourth configuration of an exemplary structure according to an embodiment of the present disclosure, showing word line driver transistors 722 in a logic die 700. Each row of layer contact via structures 86 is formed in a region of a corresponding memory block in a memory die 900. Each adjacent pair of rows of layer contact via structures 86 is formed over a corresponding adjacent pair of memory blocks in a memory die 900.

[0121] refer to Figure 15A Transistor groups A, B, and C are laterally spaced from each other along a first horizontal direction hd1. Each transistor group is electrically connected to multiple rows of layer contact via structure 86, which are electrically connected to word lines 46W in the corresponding memory blocks.

[0122] refer to Figure 15B Two instances of transistor group A, two instances of transistor group B, and two instances of transistor group C can be arranged along the first horizontal direction hd1 and are mirror-symmetrical along a vertical plane perpendicular to the first horizontal direction hd1.

[0123] Figure 16 This is a plan view of a fifth configuration of an exemplary structure according to an embodiment of the present disclosure, wherein word line driver transistor 722 in logic die 700 is shown.

[0124] In the fifth configuration, a pair of output nodes 1 and 2 of adjacent word line driver transistors 722, laterally spaced along the second horizontal direction hd2 by a dielectric isolation structure (such as a shallow trench isolation structure) 723, can be electrically connected to the same memory block (e.g., 99A or 99B). For example, the output nodes 1 and 2 of the word line driver transistors 722 located in each dashed region can be electrically connected to word lines 46W within the same memory block (99A or 99B). In this case, the maximum value of the voltage difference between adjacent pairs of output nodes 1 and 2 of adjacent transistors 722 electrically connected to word lines 46W in the same memory block 99A can be less than the maximum value of the voltage difference between two output nodes 1 and 2 of adjacent transistors 722 electrically connected to word lines in different memory blocks 99A and 99B. Therefore, the lateral dimension of the dielectric isolation structure 723 along the second horizontal direction hd2 can be reduced, and the layout of the word line driver transistors 722 can become more compact. Therefore, according to one aspect of this disclosure, adjacent pairs of output nodes 1 and 2 of adjacent transistors 722 that are laterally spaced apart from each other by a dielectric isolation structure 723 can be electrically connected to word lines 46W located in the same memory block 99A or 99B, and the lateral spacing between adjacent pairs of output nodes can be reduced.

[0125] Figure 17This is a plan view of a sixth configuration of an exemplary structure according to an embodiment of the present disclosure, showing a word line driver transistor 722 in a logic die 700. In the illustrated example, the output nodes 1 and 2 of the word line driver transistor 722 located in each dashed region are electrically connected to word lines 46W within the same memory block (99A, 99B, or 99C).

[0126] Figure 18 This is a plan view of a seventh configuration of an exemplary structure according to an embodiment of the present disclosure, wherein word line driver transistor 722 in logic die 700 is shown. Figure 19A and Figure 19B This is a first schematic diagram illustrating the spatial overlap between a seventh configured transistor group in a logic die 700 and a memory block in a memory die 900 according to an embodiment of the present disclosure. Figure 19A and Figure 19B In this context, the memory block 99 is numbered using numbers such as n-1, n, n+1, n+2, n+3, n+4, n+5, and n+6. The memory block 99 to which the output of the word line driver transistor 722 is electrically connected is indicated by "transistor output wiring for transistor group A or B".

[0127] In this embodiment, the row of the first word line driver transistor 722A in transistor group A can be laterally offset along the second horizontal direction hd2 from the row of the second word line driver transistor 722B in transistor group B, as described above. Figures 12 to 17 As described. Alternatively, the row of the first word line driver transistor 722A in transistor group A may not be laterally offset from the row of the second word line driver transistor 722B along the second horizontal direction hd2. In this case, the first word line driver transistor 722A in transistor group A may be located in the same row extending along the first horizontal direction hd1 as the second word line driver transistor 722B. In other words, a single row of word line driver transistors 722 extending along the first horizontal direction hd1 may include both the first word line driver transistor 722A and the second word line driver transistor 722B.

[0128] As discussed above, each word line driver transistor 722 includes a first output node (i.e., bias voltage output node 1) and a second output node (i.e., bias voltage output node 2). The first output node is electrically connected to the corresponding first word line 46W of the memory block 99 and is laterally spaced from the common input node (i.e., bias voltage input node 3) via a corresponding first control gate electrode 11 along a second horizontal direction hd2 (e.g., along the source-to-drain direction). The second output node is electrically connected to the corresponding second word line 46W of the memory block 99 and is laterally spaced from the common input node 3 via a corresponding second control gate electrode along a direction opposite to (i.e., 180 degrees different from) the second horizontal direction hd2 (e.g., drain-to-source direction). The source-to-drain direction and the drain-to-source direction are collectively referred to as the source-drain direction.

[0129] refer to Figure 19A and Figure 19B Each vertically adjacent pair of numbers (such as combinations of n-1 and n) in the "Transistor Output Routing for Transistor Group A" column represents a pair of memory blocks 99 to which at least one (or both) of the two output nodes (1, 2) of each word line driver transistor 722 in transistor group A is connected. Similarly, each vertically adjacent pair of numbers (such as combinations of n and n-1) in the "Transistor Output Routing for Transistor Group B" column represents a pair of memory blocks 99 to which at least one (or both) of the two output nodes (1, 2) of each word line driver transistor 722 in transistor group B is connected.

[0130] According to one aspect of this disclosure, at least a subset of adjacent pairs of output nodes 1 and 2 of adjacent word line driver transistors 722 spaced apart by a dielectric isolation structure (such as a shallow trench isolation structure) 732 along a second horizontal direction hd2 (e.g., along the source-drain direction) may be electrically connected to word lines 46W within the same memory block 99 (such as memory block n). In this case, a reduced lateral spacing (referred to herein as a first spacing s1) between these output nodes 1 and 2 may be used instead of the nominal lateral spacing (referred herein as a second spacing s2) between output nodes 1 and 2 electrically connected to word lines of different memory blocks 99. In other words, if the output nodes (i.e., source or drain regions) 1 and 2 of the laterally adjacent word line driver transistors 722 in the same transistor group, separated by the dielectric isolation structure 723 along their source-drain direction, are electrically connected to the word line 46W of the same memory block 99, then the width s1 of the dielectric isolation structure 723 along the source-drain direction may be smaller than the width s2 of the dielectric isolation structure 723 that separates the nodes (i.e., source or drain regions) 1 and 2 of the laterally adjacent word line driver transistors 722 in the same transistor group, which are electrically connected to the word line 46W of different memory blocks 99.

[0131] As mentioned above, in contrast to Figure 16 The maximum voltage difference between adjacent paired output nodes 1 and 2 of word lines 46W electrically connected to adjacent transistors 722 in the same memory block 99 can be less than the maximum voltage difference between two output nodes 1 and 2 of word lines electrically connected to adjacent transistors 722 in different memory blocks 99. In this case, due to the smaller voltage difference, the width of the dielectric isolation structure 723 between output nodes electrically connected to word lines in the same memory block can be reduced. The difference between the first interval s1 and the second interval s2 can be between 10% and 80%, such as between 30% and 50%, for example between 100nm and 1000nm, such as between 200nm and 400nm.

[0132] In an exemplary example, if the erase voltage for operation of the three-dimensional memory device is approximately 30V, the first spacing s1 can be 350nm to 450nm, and the second spacing s2 can be 750nm to 850nm. By employing a reduced first spacing s1 for a subset of the lateral spacing along the second horizontal direction hd2 between adjacent pairs of word line driver transistors 722, the overall lateral dimension of the array of word line driver transistors 722 along the second horizontal direction hd2 (e.g., along the transistor source-drain direction) can be reduced, and the total area occupied by the word line driver transistors 722 can be reduced.

[0133] In a seventh configuration of the exemplary structure, the memory die 900 includes a plurality of memory blocks 99, each comprising a corresponding alternating stack of insulating layers 32 and word lines 46W, and a corresponding set of rows of memory opening-filling structures (e.g., vertical NAND strings) 58 extending vertically through the corresponding alternating stacks and arranged along a first horizontal direction hd1. The memory blocks 99 are laterally spaced from each other along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1 with a uniform inter-block spacing p_bb.

[0134] The logic die 700 includes a first two-dimensional array (e.g., transistor group A) of first word line driver transistors 722A and a second two-dimensional array of second word line driver transistors 722B. The first two-dimensional array includes multiple rows of the first word line driver transistors 722A, and the second two-dimensional array includes multiple rows of the second word line driver transistors 722B. Each row of the first word line driver transistors 722A is arranged along a first horizontal direction hd1, and each row of the second word line driver transistors 722B is arranged along the first horizontal direction hd1. Each of the first word line driver transistors 722A and the second word line driver transistors 722B includes a first output node 1 and a second output node 2. The first output node is electrically connected to a corresponding first word line 46W of the memory block 99 and is laterally spaced from a common input node 3 along a second horizontal direction hd2 via a corresponding first control gate electrode 11. The second output node is electrically connected to a corresponding second word line 46W of the memory block 99 and is laterally spaced from the common input node 3 along a direction opposite to the second horizontal direction hd2 via a corresponding second control gate electrode 12.

[0135] The multiple rows of the first word line driver transistors 722A are periodically modulated on a first inter-row spacing along the second horizontal direction hd2. The first inter-row spacing is measured by the lateral spacing between adjacent pairs of first word line driver transistors 722A that are laterally spaced along the second horizontal direction hd2.

[0136] exist Figure 19A In the illustrated example, the first row spacing of the multiple rows of the first word line driver transistor 722A along the second horizontal direction hd2 can have a sequence: s1, s1, s2, s1, s1, s2, etc. Therefore, the first row spacing along the second horizontal direction hd2 can be periodically modulated such that every third spacing has a value s2, while all other spacings have a value s1. Thus, two-thirds of the adjacent transistors 722 spaced apart along the source-drain direction by the dielectric isolation structure 723 have a decreasing spacing s1, while one-third of the transistors 722 have a larger nominal spacing s2.

[0137] exist Figure 19BIn the illustrated example, the first row spacing of the multiple rows of the first word line driver transistor 722A along the second horizontal direction hd2 can have a sequence: s1, s2, s2, s1, s2, s2, etc. Therefore, the first row spacing along the second horizontal direction hd2 can be periodically modulated such that every third spacing has a value s1, while all other spacings have a value s2. Thus, one-third of the adjacent transistors 722 spaced apart along the source-drain direction by the dielectric isolation structure 723 have a decreasing spacing s1, while two-thirds of the transistors 722 have a larger nominal spacing s2.

[0138] Therefore, the inter-row spacing of the transistors has two values. If the two rows of the word line driver transistor 722 are separated by interval s1, then the two rows of the word line driver transistor 722 can have a first inter-row spacing TRRP1. If the two rows of the word line driver transistor 722 are separated by interval s2, then the two rows of the word line driver transistor 722 can have a second inter-row spacing TRRP2. The difference between the second inter-row spacing TRRP2 and the first inter-row spacing TRRP1 can be the same as the difference between intervals s2 and s1.

[0139] In one embodiment, each instance of a first interline spacing s1 is provided between the second output node 2 of a corresponding first word line driver transistor in the first word line driver transistor 722A and the first output node 1 of a corresponding additional first word line driver transistor in the first word line driver transistor 722A. If the second output node 2 of the corresponding first word line driver transistor in the first word line driver transistor 722A and the first output node 1 of the corresponding additional first word line driver transistor in the first word line driver transistor 722A are electrically connected to word lines 46W within the same memory block 99, the first interline spacing has a first value s1. Conversely, if the second output node 2 of the corresponding first word line driver transistor in the first word line driver transistor 722A and the first output node 1 of the corresponding additional first word line driver transistor in the first word line driver transistor 722A are electrically connected to word lines 46W in two different memory blocks 99, the first interline spacing has a second value s2 greater than the first value s1.

[0140] In one embodiment, the sequence of first inter-row spacings measured along the second horizontal direction hd2 (e.g., along the source-drain direction of transistor 722) is periodic, such that every nth value of the first inter-row spacing is the same. The integer n can be greater than 1 and less than 13. In one embodiment, each first word line driver transistor in the first word line driver transistor 722A has a first transistor length along the second horizontal direction hd2 (e.g., along the source-drain direction); and the sum of n times the first transistor length and n consecutive sequences of the first inter-row spacings is equal to (n+1) times the uniform block spacing p_bb. Figure 19A and Figure 19B In the example shown, n is 3. Therefore, each memory block 99 contains word lines 46W, which are electrically connected to word line driver transistors 722, which are located in three different rows in two different transistor groups.

[0141] In one embodiment, a plurality of rows of the second word line driver transistors 722B are periodically modulated on a second inter-row spacing along a second horizontal direction hd2, the second inter-row spacing being measured by the lateral spacing between adjacent pairs of second word line driver transistors 722B spaced laterally along the second horizontal direction hd2. In one embodiment, a corresponding first word line 46W is located in a corresponding first memory block 99 of a memory block; and a corresponding second word line 46W is located in a corresponding second memory block 99 of a memory block, the second memory block being an adjacent memory block to the first memory block.

[0142] exist Figure 19C and Figure 19D In another embodiment illustrated, the active region length of some word line driver transistors 722 may differ from the active region length of other word line driver transistors 722 in the same transistor group.

[0143] Figure 19C Example 1 illustrates two laterally adjacent word line driver transistors 722 in the same transistor group (e.g., group A). ​​These two laterally adjacent word line driver transistors have corresponding output nodes 1 and 2 electrically connected to word lines 46W of the same memory block 99 (e.g., block n) and are separated by a first interval s1 along their source-drain direction (e.g., a second horizontal direction). In this case, due to the small voltage difference between the word lines of the same memory block 99, the output nodes 1 and 2 (i.e., source or drain regions) of these transistors 722 have a relatively small first length L1 along their source-drain direction.

[0144] Figure 19DExample shows two laterally adjacent word line driver transistors 722 in the same transistor group (e.g., group A). ​​These two laterally adjacent word line driver transistors have corresponding output nodes 1 and 2 electrically connected to word lines 46W of different memory blocks 99 (e.g., block n and block n+1), and are separated by a second interval s2 along their source-drain direction (e.g., a second horizontal direction). In this case, due to the large voltage difference between the word lines of the different blocks 99, the output nodes 1 and 2 (i.e., source or drain regions) of these transistors 722 have a relatively large second length L2 along their source-drain direction. The second length L2 is greater than the first length L1. For example, the second length L2 may be 10% to 80% larger than the first length L1, such as 30% to 50%. The reduced source or drain length L1 of some word line switching transistors 722 also reduces the footprint of the word line driver circuitry.

[0145] if Figure 19C and Figure 19D The transistor 722 shown is located in Figure 19A In transistor group A, two-thirds of the adjacent transistors 722 separated by dielectric isolation structure 723 along the source-drain direction have a reduced spacing s1 and a reduced source or drain length L1, while one-third of the transistors 722 have a larger nominal spacing s2 and a larger source or drain length L2.

[0146] if Figure 19C and Figure 19D The transistor 722 shown is located in Figure 19B In transistor group A, one-third of the adjacent transistors 722 separated by dielectric isolation structure 723 along the source-drain direction have a reduced spacing s1 and a reduced source or drain length L1, while two-thirds of the transistors 722 have a larger nominal spacing s2 and a larger source or drain length L2.

[0147] Figure 20 This is a second schematic diagram illustrating the spatial overlap between a group of transistors in a logic die 700 and a memory block in a memory die 900 according to an embodiment of the present disclosure. Figure 20 An example is shown using three transistor groups (i.e., transistor group A, transistor group B, and transistor group C). In Figure 20 In this diagram, each memory block 99 is represented by BLK##, where ## represents the block number. "Block 99 number within the memory array" indicates the memory block 99 within the memory die 900. The memory block 99 name within the transistor output wiring for various transistor groups indicates the memory block containing the word line 46W to which the output node of the word line driver transistor 722 is electrically connected.

[0148] At least a subset of adjacent paired output nodes 1 and 2 of adjacent transistors spaced apart by a dielectric isolation structure (such as a shallow trench isolation structure) 723 along the second horizontal direction hd2 can be electrically connected to word lines 46W within the same memory block 99 (such as memory block n). In this case, a reduced lateral spacing (referred to herein as the first spacing s1) can be used instead of the larger nominal lateral spacing (referred herein as the second spacing s2) discussed above.

[0149] exist Figure 20 In the illustrated example, approximately 1 / 6 of all lateral intervals along the second horizontal direction hd2 can be the first interval s1, and approximately 5 / 6 of all lateral intervals along the second horizontal direction hd2 can be the second interval s2. Therefore, the first interrow interval along the second horizontal direction hd2 has periodic modulation, such that every sixth interval has the value s1, while all other intervals have the value s2.

[0150] Generally speaking, the proportion of the first interval s1 in all intervals along the second horizontal direction hd2 can be expressed as m / n, where n is a positive integer in the range of 1 to 12, and m is a positive integer not greater than n.

[0151] Various embodiments of this disclosure can be used to reduce the footprint of the word line driver transistor 722 in the logic die 700 and to reduce the lateral extent of the electrical wiring for electrically connecting the output node of the word line driver transistor 722 in the logic die 700 to the layer contact via structure 86 in the memory die 900.

[0152] As used herein, a “memory block” or simply a “block” refers to a combination of all memory elements (e.g., memory cells) located within a specific region, and a set of all word lines used to control the set of all memory elements. For example, a specific region may be a region between adjacent pairs of lateral isolation trench fill structures 76. The set of all word lines may include a subset of all conductive layers 46 located within a specific region (such as a region between adjacent pairs of lateral isolation trench fill structures 76). The remaining conductive layers 46 may include selected gate electrodes and optional dummy word lines. As discussed above, each memory stack structure 55 is an adjacent combination of vertical semiconductor channels 60 and memory films 50. The set of all memory elements may include the set of all portions of the memory film 50 used as memory elements within a specific region (such as a region between adjacent pairs of lateral isolation trenches 76). Memory elements may be located at the level of word lines within alternating stacks of insulating layers 32 and conductive layers 46 within a specific region.

[0153] As used herein, a “word line block” refers to the set of all word lines in a given memory block. Therefore, a memory block includes both a set of memory elements and a word line block. If the set of memory elements comprises the set of all portions of the memory film 50 used as memory elements (e.g., memory cells) within a specific region, then a word line block may include the set of all word lines required to access all memory cells within the specific region. If the set of memory elements comprises the set of all portions of the memory film 50 used as memory elements within a region between adjacent pairs of lateral isolation trenches 76, then a word line block includes all word lines within adjacent pairs of lateral isolation trenches 76.

[0154] In a three-dimensional NAND memory device, a page is defined as the smallest set of memory cells that can be programmed or sensed in a single operation. A single programming operation or a single sensing operation activates a single word line and multiple bit lines. Thus, a page comprises a set of all memory cells accessible via a single word line, which includes a conductive layer 46 located between adjacent pairs of laterally isolated trench-filled structures 76. Data in memory cells within the same page can be accessed in parallel by activating the respective word lines. Thus, multiple data bits stored in different cells can be accessed in parallel by activating a single word line and all bit lines connected to a vertical semiconductor channel 60 laterally surrounded by the activated word line. If the alternating stacks (32, 46) of insulating layer 32 and conductive layer 46 comprise N word lines, then a memory block 99 comprising the alternating stacks (32, 46) and all memory stack structures 55 extending vertically through the alternating stacks (32, 46) comprises N pages. The number N can range from 2 to 1,024 (such as 64 to 512), but larger numbers are also possible.

[0155] In a conventional word-line hierarchical architecture, a memory block constitutes the smallest device unit containing memory elements that can be erased in a single erase operation. In this case, all memory cells accessed by the word lines of the memory block are erased in a single erase operation. Therefore, the erase operation of a memory block is controlled by a word-line block, which includes all word lines that access the memory elements within the memory block.

[0156] As the total number of word lines N increases to more than 128, smaller cells within a memory block can be used as the smallest units that can be erased in a single erase operation. Such units are referred to herein as “memory sub-blocks” or “sub-blocks.” A memory block may include multiple memory sub-blocks, and each memory sub-block may include a corresponding subset of memory elements within the memory block. Memory sub-blocks can be organized such that each memory element belongs to its corresponding memory sub-block and not to any other memory sub-block. Furthermore, each page within a memory block belongs to its corresponding memory sub-block and not to any other memory sub-block.

[0157] In one embodiment, when all word lines within the alternating stacks of insulating layer 32 and conductive layer 46 are sequentially numbered with non-negative integers starting from 0 and incrementing by 1, each memory sub-block may include a set of all memory elements accessed by a corresponding set of word lines labeled with a corresponding consecutive set of integers. In this case, memory sub-blocks within a memory block may be vertically stacked within a three-dimensional array of memory elements, and the memory sub-blocks may be labeled with numbers from bottom to top, for example, with non-negative integers starting from 0 and incrementing by 1. For example, a memory block may include a memory sub-block labeled "00" and accessed by the bottommost set of word lines, a memory sub-block labeled "01" and accessed by the set of word lines overlying the bottommost set of word lines, and so on.

[0158] When a memory block comprising a set of memory elements is divided into memory subblocks comprising corresponding subsets of memory elements, a word line block comprising all word lines for accessing all memory elements within the memory block is divided into word line subblocks comprising corresponding subsets of word lines. Each subset of word lines within a corresponding word line subblock accesses a corresponding subset of memory elements for that corresponding memory subblock. As discussed above, each word line access is located at the same level as the word line and within a memory element page of the corresponding memory stack structure 55.

[0159] Generally speaking, the various word lines within each word line block or each word line sub-block can be organized into multiple word line clusters, i.e., multiple word line subsets. Such word line clusters are referred to as word line partitions in this paper. The number K of word lines in each word line partition can be in the range of 8 to 64, such as in the range of 16 to 48, but fewer or more than K can also be used.

[0160] In one implementation, when all word lines within the alternating stacks of insulating layer 32 and conductive layer 46 are sequentially numbered using non-negative integers starting from 0 and incrementing by 1, each word line partition may include a corresponding set of word lines labeled with a corresponding consecutive set of integers. In this case, word line partitions may be labeled with numbers from bottom to top, for example, using non-negative integers starting from 0 and incrementing by 1. For example, word line partitions may include a word line partition labeled "00" and including the bottommost word line set, a word line partition labeled "01" and overriding the bottommost word line set, and so on.

[0161] refer to Figures 21A to 21C This illustrates various exemplary organization schemes for word line blocks. Figure 21A A first exemplary organization scheme within a word line block in a memory die 900 according to an embodiment of the present disclosure is illustrated. Figure 21B A second exemplary organization scheme within a word line block in a memory die 900 according to an embodiment of the present disclosure is illustrated. Figure 21CA third exemplary organization scheme within a word line block in a memory die 900 according to an embodiment of the present disclosure is illustrated.

[0162] exist Figure 21A In the illustrated first exemplary organization scheme for word line blocks, the total number of word lines N in each word line block is 216, and the total number of word lines K in each word line partition is 36. A word line block includes two word line sub-blocks, namely word line sub-block 00 and word line sub-block 01. Each word line sub-block (00 and 01) includes a corresponding set of three word line partitions (i.e., 00 to 02 and 03 to 05, respectively). Each word line partition may include a corresponding set of K word lines. Each word line within a word line block may include a set of conductive layers 46 located between a pair of laterally adjacent lateral isolation trenches 76 in the memory die 900. Each word line partition may include a corresponding set of word lines labeled with a consecutive set of integers when all word lines within a word line block are sequentially numbered using non-negative integers starting from 000 and incrementing by 1. Word line partitions can be labeled with non-negative integers starting at 00 and incrementing by 1, such that each word line partition labeled with a larger number comprises a set of K word lines labeled with a consecutive set of integers, instead of any integer label within another consecutive set of integers used to label any underlying word lines.

[0163] exist Figure 21B In the illustrated second exemplary organization scheme for word line blocks, the total number of word lines N in each word line block is 288, and the total number of word lines K in each word line partition is 36. The numerical labeling scheme for word line sub-blocks, word line partitions, and word lines in the second exemplary organization scheme may be similar to the numerical labeling scheme used in the first exemplary organization scheme.

[0164] exist Figure 21C In the illustrated third exemplary organization scheme for word line blocks, the total number of word lines N in each word line block is 432, and the total number of word lines K in each word line partition is 36. The digital labeling scheme for word line sub-blocks, word line partitions, and word lines in the third exemplary organization scheme may be similar to the digital labeling scheme used in the first exemplary organization scheme.

[0165] The word line driver transistor 722, sharing the same active semiconductor region 4, consists of two word line driver transistors. These two word line driver transistors include two output nodes (1 and 2) and a common input node 3, as shown below. Figure 12 , Figure 14A , Figure 14B , Figure 16 , Figure 17 and Figure 18As illustrated. Each set of word line driver transistors 722 sharing the same active semiconductor region 4 is referred to hereinafter as word line driver transistor pair 722, so as to note that the two transistors are formed within the same active semiconductor region 4 and that the two transistors have two different output nodes (1 and 2) and a common input node 3.

[0166] Generally, when one of two output nodes (1 or 2) adjacent to a portion of the dielectric isolation structure 723 is electrically biased to the erase word line bias voltage and the other output node (1 or 2) is electrically biased to a different bias voltage, a maximum voltage difference occurs between a portion of the following adjacent set of output nodes across the dielectric isolation structure 723: the output node (1 or 2) of the first word line driver transistor pair 722 and the output node (2 or 1) of the second word line driver transistor pair 722. For example, the different bias voltages can be the programming word line bias voltage or the gate word line bias voltage. Therefore, if an adjacent set of output nodes (1 and 2) of the first word line driver transistor pair 722 and the second word line driver transistor pair 722 are connected to a pair of word lines belonging to different word line blocks or different word line sub-blocks, then the portion of the dielectric isolation structure 723 located between the adjacent set of output nodes (1 and 2) of the first word line driver transistor pair 722 and the second word line driver transistor pair 722 provides the nominal lateral spacing (i.e., the second spacing s2) discussed above for that portion.

[0167] This maximum voltage difference can occur across this portion of the dielectric isolation structure 723 if two adjacent output nodes (1 or 2) of a portion of the dielectric isolation structure 723 are electrically biased within the same word line subblock (which belongs to the same word line block): the output node (1 or 2) of the first word line driver transistor pair 722 and the output node (2 or 1) of the second word line driver transistor pair 722. This is because the memory subblock is the smallest unit for performing an erase operation, and therefore, all word lines in the word line subblock are electrically biased during the erase operation at the erase word line bias voltage, or, in the absence of an erase operation on the corresponding memory subblock, at a voltage different from (and significantly lower in magnitude than) the erase word line bias voltage. Therefore, if an adjacent set of output nodes (1 and 2) of the first word line driver transistor pair 722 and the second word line driver transistor pair 722 are connected to a pair of word lines belonging to the same word line block and the same word line sub-block, the reduced lateral spacing (i.e., the first spacing s1) discussed above can be used without adversely affecting the device isolation characteristics of the portion of the dielectric isolation structure 723 located between the adjacent set of output nodes (1 and 2) of the first word line driver transistor pair 722 and the second word line driver transistor pair 722.

[0168] According to the embodiments of this disclosure, for cases where memory sub-blocks are used, i.e., where a memory block comprises multiple memory sub-blocks to which an erase operation can be performed independently, modifications can be made. Figures 12 to 20 Various layouts of the illustrated word line driver circuitry are shown. Specifically, in each portion of the dielectric isolation structure 723, a nominal lateral spacing (i.e., a second spacing s2) is used, which provides lateral electrical isolation for any adjacent set of output nodes (1 and 2) of the first word line driver transistor pair 722 and the second word line driver transistor pair 722 connected to a pair of word lines belonging to different word line blocks or different word line subblocks. In each portion of the dielectric isolation structure 723, a reduced lateral spacing (i.e., a first spacing s1) smaller than the nominal lateral spacing is used, which provides lateral electrical isolation for any adjacent set of output nodes (1 and 2) of the first word line driver transistor pair 722 and the second word line driver transistor pair 722 connected to a pair of word lines belonging to the same word line subblock (and therefore, belonging to the same word line block).

[0169] Figure 22A This is a first exemplary layout of the word line driver circuit in a logic die 700 according to an embodiment of the present disclosure, which is juxtaposed with a schematic plan view of the lateral isolation trench fill structure 76 in a memory die 900. Figure 22B This is a second exemplary layout of the word line driver circuit in the logic die 700 according to an embodiment of the present disclosure, which is juxtaposed with a schematic plan view of the lateral isolation trench fill structure 76 in the memory die 900. Figure 22C This is a third exemplary layout of the word line driver circuit in the logic die 700 according to an embodiment of the present disclosure, which is juxtaposed with a schematic plan view of the lateral isolation trench fill structure 76 in the memory die 900.

[0170] Figure 22A , Figure 22B and Figure 22C Each of these is a plan view illustrating the layout of the word line driver transistor pair 722 after the logic die 700 is bonded to the memory die 900. Therefore, the location of the lateral trench isolation fill structure 76 is shown relative to the position of the word line driver transistor pair 722. Each solid rectangle, labeled "Block X Subblock Y Partition Z," represents a row of word line driver transistors located on the same track, where each of X, Y, and Z is a number identifying the corresponding block, subblock, and partition. See reference... Figures 12 to 20 The word line driver transistors belonging to adjacent tracks, aligned along the first horizontal direction hd1, are formed in the same active semiconductor region 4 and constitute a pair of word line driver transistors 722. Figure 22A , Figure 22B and Figure 22C Each solid rectangle marked with "Block X Subblock Y Partition Z" may include a set of all word line driver transistors for driving the word line set identified by the word line block identified by the number X, the word line subblock identified by the number Y, and the word line partition identified by the number Z. Therefore, Figure 22A , Figure 22B and Figure 22C Each solid rectangle marked with "Block X Subblock Y Partition Z" may contain K word line driver transistors. As discussed above, K is the total number of word lines in each word line partition.

[0171] Figure 22A , Figure 22B In Figure 22, each pair of adjacent solid rectangles represents a set of K word line driver transistor pairs 722. Thus, each pair of adjacent solid rectangles represents two word line driver sets configured to drive two word line partitions. According to one aspect of this disclosure, the arrangement of word line partitions driven by each set of K word line driver transistors located at the corresponding track and in the corresponding transistor group is selected to use a reduced lateral spacing s1. Specifically, for subsets of adjacent paired output nodes (1 and 2) laterally spaced from each other along the second horizontal direction hd2, the block numbers match and the sub-block numbers match, while the partition numbers do not match. Since the word line voltage is the same across all partitions within a sub-block during the erase operation, the maximum voltage difference condition discussed above does not occur if, for adjacent paired output nodes (1 and 2) laterally spaced from each other along the second horizontal direction hd2 through a portion of the dielectric isolation structure 723, the block numbers match and the sub-block numbers match. Therefore, a reduced lateral spacing s1 can be used for all such adjacent paired output nodes (1 and 2). If the block number or sub-block number does not match for an adjacent pair of output nodes (1 and 2) that are laterally spaced apart along a portion of the dielectric isolation structure 723 along the second horizontal direction hd2, then the nominal lateral spacing s2 is used.

[0172] The pattern of the lateral isolation trench fill structure 76 along the second horizontal direction hd2 may have a first periodicity P1. In one embodiment, multiple rows of word line driver transistor pairs 722 are arranged in a periodic pattern with a second periodicity P2 along the second horizontal direction hd2, which differs from the first periodicity P1. Generally, the periodicity of the arrangement of word line driver transistor pairs 722 along the second horizontal direction hd2 may be proportional to the first periodicity P1 of the pattern of the lateral isolation trench fill structure 76 along the second horizontal direction hd2. Generally, the periodicity of the arrangement of word line driver transistor pairs 722 along the second horizontal direction hd2 is M times the first periodicity P1 of the pattern of the lateral isolation trench fill structure 76 along the second horizontal direction hd2. The integer M may be greater than 2. Within the lateral dimension of the periodicity of the arrangement of word line driver transistor pairs 722 along the second horizontal direction hd2, the number J of rows of word line driver transistor pairs 722 is an integer greater than 1 and less than M. In one embodiment, M and J may be disproportionate. In other words, M is not an integer multiple of J, and J is not an integer multiple of M.

[0173] exist Figure 22A , Figure 22B and Figure 22C In the illustrated exemplary layout, the periodicity of the word line driver transistor pair 722 along the second horizontal direction hd2 is four times the first periodicity P1 of the pattern of the lateral isolation trench fill structure 76 along the second horizontal direction hd2. Figure 22A , Figure 22B and Figure 22C In the illustrated first and second exemplary layouts, the number J of rows of word line driver transistor pairs 722 is 3 within the periodic lateral dimension of the layout of the word line driver transistor pairs 722 along the second horizontal direction hd2.

[0174] Figure 22A and Figure 22B An exemplary configuration of word line driver circuitry for four word line blocks is illustrated. Each word line block comprises two word line sub-blocks. Each word line sub-block comprises three word line partitions. As described above... Figures 12 to 20 In the illustrated case, adjacent rows of word line driver transistors within the same track can be laterally offset along the second horizontal direction hd2. Figure 22A An example layout is illustrated in which lateral offset occurs along a second horizontal direction hd2 between rows of word line driver transistors within the same track, every other transistor group boundary along a first horizontal direction hd1. Figure 22B An example layout is illustrated in which lateral offset occurs along a second horizontal direction hd2 between rows of word line driver transistors within the same track at the boundary between each group of transistors along a first horizontal direction hd1.

[0175] Figure 22C An exemplary configuration of word line driver circuitry for four word line blocks is illustrated. Each word line block includes two word line sub-blocks. Each word line sub-block includes six word line partitions.

[0176] Referring together to all the accompanying drawings and according to various embodiments of the present disclosure, a memory device may include: a plurality of memory blocks 99, wherein each of the plurality of memory blocks 99 includes a corresponding three-dimensional array of memory elements and a corresponding word line block, the corresponding word line block including word lines (including conductive layer 46) for controlling the corresponding three-dimensional array of memory elements, wherein the corresponding word line block includes a corresponding plurality of word line sub-blocks, the corresponding plurality of word line sub-blocks containing a corresponding subset of all word lines within the corresponding word line block; and word line driver circuitry including a plurality of rows of word line driver transistor pairs 722, wherein: each row of word line driver transistor pairs 722 includes a corresponding plurality of word line driver transistor pairs 722, the corresponding plurality of word line driver transistor pairs being arranged along a first horizontal direction hd1 and located within a corresponding opening in a dielectric isolation structure 723 in a plan view; word line driver Each word line driver transistor pair in transistor pair 722 includes a corresponding first word line driver transistor and a corresponding second word line driver transistor, which share a corresponding common input node and have a first output node and a second output node. The first output node and the second output node are laterally spaced apart from each other along a second horizontal direction hd2 and electrically connected to corresponding word lines (including corresponding conductive layers 46) within a plurality of memory blocks 99. First subsets of adjacent pairs of output nodes, which are laterally spaced apart by a corresponding first portion having a first width through dielectric isolation structure 723, are electrically connected to word lines within the same word line subblock. Second subsets of adjacent pairs of output nodes, which are laterally spaced apart by a corresponding second portion having a second width greater than the first width through dielectric isolation structure 723, are electrically connected to word lines within different word line subblocks.

[0177] In one implementation, a first subset of adjacent pairs of output nodes is spaced apart by a first interval s1 along a second horizontal direction hd2; and a second subset of adjacent pairs of output nodes is spaced apart by a second interval s2 along the second horizontal direction hd2, which is greater than the first interval s1.

[0178] In one embodiment, multiple rows of word line driver transistor pairs 722 are arranged as transistor groups along a first horizontal direction hd1; and each transistor group includes a corresponding subset of the multiple rows of word line driver transistor pairs 722 such that the lateral extents of adjacent transistor groups along the first horizontal direction hd1 do not overlap. In one embodiment, for a first transistor group and a second transistor group, the first row of word line driver transistor pairs 722 in the first transistor group is laterally offset along a second horizontal direction hd2 from the second row of word line driver transistor pairs 722 in the second transistor group that is closest to the first row of word line driver transistor pairs 722.

[0179] In one embodiment, each word line subblock includes a corresponding word line partition containing a corresponding subset of word lines within each word line block; and the word line driver circuitry is configured to perform an erase operation within a selected word line subblock of a selected word line block, without performing any erase operation within another word line subblock of the selected word line block. In one embodiment, the first subsets of adjacent paired output nodes are electrically connected to different word line partitions within the same word line subblock.

[0180] In one embodiment, when all word lines within a plurality of memory blocks 99 are sequentially numbered from bottom to top using non-negative integers starting from 0 and incrementing by 1, and when all sub-blocks are sequentially numbered from bottom to top using non-negative integers starting from 0 and incrementing by 1, adjacent pairs of output nodes, laterally spaced apart by corresponding portions of the dielectric isolation structure 723, are electrically connected to a pair of word lines within the corresponding sub-block having the same sub-block number. In one embodiment, each word line within each word line block has a region of overlap with any other word line within each word line block in a plan view.

[0181] In one embodiment, each of the first and second output nodes includes a corresponding source or drain region; a first subset of the first and second output nodes is electrically connected to a corresponding word line (including one conductive layer of conductive layer 46) in the word lines of the plurality of memory blocks 99 and has a region of overlap with the corresponding word line; and a second subset of the first and second output nodes is electrically connected to a corresponding word line (including one conductive layer of conductive layer 46) in the word lines of the plurality of memory blocks 99, but does not have any region of overlap with the corresponding word line. In one embodiment, the plurality of memory blocks 99 are laterally spaced from each other by lateral isolation trench fill structures 76, which extend laterally along a first horizontal direction hd1 and have a first periodicity P1 along a second horizontal direction hd2.

[0182] In one embodiment, multiple rows of word line driver transistor pairs 722 are arranged in a periodic pattern with a second periodicity P2 along a second horizontal direction hd2, which is different from the first periodicity P1. In one embodiment, the second periodicity P2 is M times the first periodicity P1, where M is an integer greater than 2. In one embodiment, the total number J of rows of word line driver transistor pairs 722 within the periodic pattern is greater than 1 and less than M, and this number of rows is within the distance of the second periodicity P2 along the second horizontal direction hd2. In one embodiment, M is an integer selected from 3, 4, 5, or 6.

[0183] In one embodiment, a plurality of memory blocks 99 are located in a memory die 900; word line driver circuitry is located in a logic die 700; and the memory die 900 is bonded to the logic die 700. In one embodiment, the word lines (including conductive layer 46) of a corresponding word line block within each of the plurality of memory blocks 99 are interleaved with insulating layer 32 to provide a corresponding alternating stack of insulating layer 32 and word lines (including conductive layer 46). In one embodiment, a corresponding set of rows of memory aperture fill structures 58 extend vertically through the corresponding alternating stacks, wherein each memory aperture fill structure 58 includes a memory element (e.g., a portion of memory film 50) and a corresponding vertical stack of vertical semiconductor channels, and each row of memory aperture fill structures 58 is arranged along a first horizontal direction hd1. In one embodiment, the memory blocks 99 are laterally spaced from each other along a second horizontal direction hd2 by lateral isolation trench fill structures 76, which separate adjacent pairs of alternating stacks of corresponding insulating layers 32 and corresponding word lines.

[0184] According to another aspect of this disclosure, a method of forming a memory device is provided. The method includes: providing a memory die 900 including a plurality of memory blocks 99, wherein each of the plurality of memory blocks 99 includes a corresponding three-dimensional array of memory elements and a corresponding word line block (including a corresponding conductive layer 46), the corresponding word line block including word lines for controlling the corresponding three-dimensional array of memory elements, wherein the corresponding word line block includes a corresponding plurality of word line sub-blocks, the corresponding plurality of word line sub-blocks containing a corresponding subset of all word lines within the corresponding word line block; providing a logic die 700 including word line driver circuitry, the word line driver circuitry including a plurality of rows of word line driver transistor pairs 722, wherein each row of word line driver transistor pairs 722 includes a corresponding plurality of word line driver transistor pairs 722, the corresponding plurality of word line driver transistor pairs being arranged along a first horizontal direction hd1 and located within corresponding openings in a dielectric isolation structure 723 in a plan view, each word line driver transistor pair 722 being... The transistor pair includes a corresponding first word line driver transistor and a corresponding second word line driver transistor, which share a corresponding common input node and have a first output node and a second output node. The first output node and the second output node are laterally spaced apart from each other along a second horizontal direction hd2. The first subset of the adjacent paired output nodes, which are laterally spaced apart by a corresponding first portion of a dielectric isolation structure 723 having a first width, are electrically connected to word lines within the same word line subblock. The second subset of the adjacent paired output nodes, which are laterally spaced apart by a corresponding second portion of a dielectric isolation structure 723 having a second width greater than the first width, are electrically connected to word lines within different word line subblocks. The logic die 700 is bonded to the memory die 900 such that each of the first output node and the second output node is electrically connected to a corresponding word line (including a corresponding conductive layer 46) within a plurality of memory blocks 99.

[0185] In one embodiment, each of the first output node and the second output node includes a corresponding source or drain region; after the step of bonding the logic die 700 to the memory die 900, the first subsets of the first output node and the second output node are electrically connected to the corresponding word lines in the word lines (including the conductive layer 46) of the plurality of memory blocks 99 and have a region overlap with the corresponding word lines; after the step of bonding the logic die 700 to the memory die 900, the second subsets of the first output node and the second output node are electrically connected to the corresponding word lines in the word lines (including the conductive layer 46) of the plurality of memory blocks 99, but do not have any region overlap with the corresponding word lines.

[0186] In various embodiments, the width of the first portion of the dielectric isolation structure 723 located in the same facing sub-block region can be reduced from the second interval s2 for the second portion of the dielectric isolation structure 723 located in different facing sub-block regions to the interval s1. This reduces the total area of ​​the word line switching circuit, thereby increasing device density.

[0187] While the foregoing relates to specific preferred embodiments, it should be understood that this disclosure is not limited thereto. Those skilled in the art will envision various modifications that can be made to the disclosed embodiments, and such modifications are intended to fall within the scope of this disclosure. Compatibility is assumed between all embodiments that are not alternatives to each other. Unless otherwise expressly stated, the words “comprising” or “including” envision that the words “substantially constitute…” or “consist of…” replace all embodiments for which the words “comprising” or “including” are used. Whenever two or more elements are listed as alternatives in the same or different paragraphs, a Markush group comprising the list of two or more elements is also implicitly disclosed. Whenever the auxiliary verb “capable” is used in this disclosure to describe the formation of an element or the execution of a processing step, it is also clearly envisioned that embodiments in which such element or such processing step is not performed are included, provided that the resulting apparatus or device is capable of providing equivalent results. Therefore, whenever omitting such an element or the formation of such a processing step can provide the same or equivalent result, the auxiliary verb "can" applied to the formation of an element or the execution of a processing step should also be interpreted as "can" or "may, or may not," with these equivalent results including slightly superior and slightly inferior results. In cases where embodiments employing specific structures and / or configurations are illustrated in this disclosure, it should be understood that this disclosure can be practiced with any other functionally equivalent compatible structures and / or configurations, provided that such substitutions are not expressly prohibited or otherwise known to be impossible for a person skilled in the art. If any publications, patent applications, and / or patents are cited herein, each of such documents is incorporated herein by reference in its entirety.

Claims

1. A memory device, the memory device comprising: A plurality of memory blocks, wherein each of the plurality of memory blocks includes a corresponding three-dimensional array of memory elements and a corresponding word line block, the corresponding word line block including word lines for controlling the corresponding three-dimensional array of memory elements, wherein the corresponding word line block includes a corresponding plurality of word line sub-blocks, the corresponding plurality of word line sub-blocks containing a corresponding subset of all word lines within the corresponding word line block; and Word line driver circuitry, the word line driver circuitry comprising multiple rows of word line driver transistor pairs, in: Each row of the word line driver transistor pairs includes a corresponding plurality of word line driver transistor pairs, which are arranged along a first horizontal direction and located in a corresponding opening in a dielectric isolation structure in a plan view; Each word line driver transistor pair in the word line driver transistor pair includes a corresponding first word line driver transistor and a corresponding second word line driver transistor, the corresponding first word line driver transistor and the corresponding second word line driver transistor sharing a corresponding common input node and having a first output node and a second output node, the first output node and the second output node being laterally spaced apart from each other along a second horizontal direction and electrically connected to a corresponding word line within the plurality of memory blocks; The first subsets of adjacent paired output nodes, laterally spaced apart by corresponding first portions of the dielectric isolation structure, are electrically connected to word lines within the same word line sub-block; and The second subsets of the adjacent paired output nodes, which are laterally spaced apart by the corresponding second portions of the dielectric isolation structure having a second width greater than the first width, are electrically connected to word lines within different word line sub-blocks.

2. The memory device according to claim 1, wherein: The first subset of adjacent paired output nodes is spaced apart by a first interval along the second horizontal direction; and The second subset of adjacent paired output nodes is spaced apart by a second interval, which is greater than the first interval, along the second horizontal direction.

3. The memory device according to claim 1, wherein: The plurality of rows of the word line driver transistor pairs are arranged as a group of transistors arranged along the first horizontal direction; and Each transistor group includes a corresponding subset of the plurality of rows of the word line driver transistor pairs, such that adjacent transistor groups do not overlap in lateral extent along the first horizontal direction.

4. The memory device of claim 3, wherein for the first transistor group and the second transistor group in the transistor group, the first row word line driver transistor pair in the first transistor group is laterally offset along the second horizontal direction from the second row word line driver transistor pair in the second transistor group that is closest to the first row word line driver transistor pair.

5. The memory device according to claim 1, wherein: Each word line subblock includes a corresponding word line partition, and the corresponding word line partition contains a corresponding subset of word lines within each word line block; and The word line driver circuit is configured to perform an erase operation within a selected word line sub-block of a selected word line block, without performing any erase operation within another word line sub-block of the selected word line block.

6. The memory device of claim 5, wherein the first subset of the adjacent paired output nodes is electrically connected to different word line partitions within the same word line subblock.

7. The memory device of claim 5, wherein when all word lines within the plurality of memory blocks are sequentially numbered from bottom to top using non-negative integers starting from 0 and incrementing by 1, and when all sub-blocks are sequentially numbered from bottom to top using non-negative integers starting from 0 and incrementing by 1, each pair of adjacent pairs of output nodes, laterally spaced apart by a corresponding portion of the dielectric isolation structure, is electrically connected to a pair of word lines within the corresponding sub-block having the same sub-block number.

8. The memory device of claim 5, wherein each word line within each word line block has an area overlap with any other word line within the same word line block in the plan view.

9. The memory device according to claim 1, wherein: Each of the first output node and the second output node includes a corresponding source or drain region; The first output node and the first subset of the second output node are electrically connected to the corresponding word lines of the plurality of memory blocks and have regional overlap with the corresponding word lines; and The first output node and the second subset of the second output node are electrically connected to the corresponding word lines of the plurality of memory blocks, but do not overlap with the corresponding word lines in any region.

10. The memory device of claim 9, wherein the plurality of memory blocks are laterally spaced from each other by a lateral isolation trench filling structure that extends laterally along the first horizontal direction and has a first periodicity along the second horizontal direction.

11. The memory device of claim 10, wherein the plurality of rows of the word line driver transistor pairs are arranged in a periodic pattern having a second periodicity along the second horizontal direction, the second periodicity being different from the first periodicity.

12. The memory device of claim 11, wherein the second periodicity is M times the first periodicity, where M is an integer greater than 2.

13. The memory device of claim 12, wherein the total number of rows of word line driver transistor pairs within the periodic pattern is greater than 1 and less than M, the number of rows being within the range of the distance of the second periodicity along the second horizontal direction.

14. The memory device of claim 12, wherein M is an integer selected from 3, 4, 5 or 6.

15. The memory device according to claim 1, wherein: The plurality of memory blocks are located in the memory die; The word line driver circuit is located in the logic die; and The memory die is bonded to the logic die.

16. The memory device of claim 15, wherein the word lines of the respective word line blocks within each of the plurality of memory blocks are interleaved with an insulating layer to provide a respective alternating stacking of the insulating layer and the word lines.

17. The memory device of claim 16, wherein a corresponding set of rows of memory aperture filling structures extends vertically through the corresponding alternating stack, wherein each memory aperture filling structure in the memory aperture filling structure includes a corresponding vertical stack of memory elements and a vertical semiconductor channel, and each row of the memory aperture filling structure is arranged along the first horizontal direction.

18. The memory device of claim 17, wherein the memory blocks are laterally spaced from each other along the second horizontal direction by a lateral isolation trench filling structure that separates adjacent pairs of alternately stacked insulating layers and corresponding word lines.

19. A method of forming a memory device, the method comprising: A memory die is provided, the memory die comprising a plurality of memory blocks, wherein each of the plurality of memory blocks comprises a corresponding three-dimensional array of memory elements and a corresponding word line block, the corresponding word line block comprising word lines for controlling the corresponding three-dimensional array of memory elements, wherein the corresponding word line block comprises a corresponding plurality of word line sub-blocks, the corresponding plurality of word line sub-blocks comprising a corresponding subset of all word lines within the corresponding word line block; A logic die is provided, the logic die including word line driver circuitry, the word line driver circuitry including multiple rows of word line driver transistor pairs, wherein each row of word line driver transistor pairs includes a corresponding plurality of word line driver transistor pairs, the corresponding plurality of word line driver transistor pairs being arranged along a first horizontal direction and located within corresponding openings in a dielectric isolation structure in a plan view, each word line driver transistor pair including a corresponding first word line driver transistor and a corresponding second word line driver transistor, the corresponding first word line driver transistor and the corresponding second word line driver transistor sharing a corresponding common input node and having a first output node and a second output node, the first output node and the second output node being laterally spaced apart from each other along a second horizontal direction, a first subset of adjacent paired output nodes laterally spaced apart by a corresponding first portion of the dielectric isolation structure having a first width being electrically connected to word lines within the same word line subblock, and a second subset of the adjacent paired output nodes laterally spaced apart by a corresponding second portion of the dielectric isolation structure having a second width greater than the first width being electrically connected to word lines within different word line subblocks; as well as The logic die is bonded to the memory die such that each of the first output node and the second output node is electrically connected to a corresponding word line within the plurality of memory blocks.

20. The method of claim 19, wherein: Each of the first output node and the second output node includes a corresponding source or drain region; After the step of bonding the logic die to the memory die, the first subset of the first output node and the second output node are electrically connected to the corresponding word lines of the plurality of memory blocks and have regional overlap with the corresponding word lines; and After the step of bonding the logic die to the memory die, the second subset of the first output node and the second output node are electrically connected to the corresponding word lines of the plurality of memory blocks, but do not have any area overlap with the corresponding word lines.

21. A memory device, the memory device comprising: Multiple memory blocks, wherein the multiple memory blocks include corresponding word lines; and A word line driver circuit, the word line driver circuit including a row of first word line driver transistors having a source-drain orientation and an additional row of second word line driver transistors having the same source-drain orientation as the first word line driver transistors, in: The first word line driver transistor includes a first output node electrically connected to a word line in a first memory block of the plurality of memory blocks; The second word line driver transistor includes a second output node electrically connected to the word line of the first memory block in the plurality of memory blocks; and The row of the first word line driver transistor is laterally offset from the additional row of the second word line driver transistor along the source-drain direction.

22. The memory device of claim 21, wherein: The first output node includes the first source or drain region of the first word line driver transistor; and The second output node includes the second source or drain region of the second word line driver transistor.

23. The memory device of claim 22, wherein each first source or drain region of the first word line driver transistor and each second source or drain region of the second word line driver transistor have regional overlap with the first memory block in a plan view along the vertical direction, and have no regional overlap with any other memory block among the plurality of memory blocks in the plan view.

24. The memory device of claim 21, wherein: The plurality of memory blocks are located in the memory die; The word line driver circuit is located in the logic die; and The memory die is bonded to the logic die.

25. The memory device of claim 24, wherein: Each of the plurality of memory blocks includes a corresponding alternating stack of insulating layers and word lines, and includes a corresponding set of rows of memory opening filling structures that extend vertically through the corresponding alternating stacks and are arranged along a first horizontal direction; The memory blocks are laterally spaced from each other along a second horizontal direction that is perpendicular to the first horizontal direction and parallel to the source-drain direction; and in: The first word line driver transistors are arranged in the rows that extend along the first horizontal direction and are spaced apart from each other along the second horizontal direction; The second word line driver transistors are arranged in the additional rows that extend along the first horizontal direction and are spaced apart from each other along the second horizontal direction; and The row of the first word line driver transistor and the additional row of the second word line driver transistor are offset laterally by a distance along the second horizontal direction.

26. The memory device of claim 25, wherein: The first output node and the second output node are electrically connected to the word lines in the first memory block via an interconnect structure; and All interconnect structures that provide electrical connections between word lines in the first memory block and the first output node of the first word line driver transistor or the second output node of the second word line driver transistor are located entirely within the area of ​​the first memory block in a plan view along the vertical direction.

27. The memory device of claim 25, wherein: The rows of the first word line driver transistors are arranged along the second horizontal direction with uniform transistor row spacing; The additional rows of the second word line driver transistors are arranged along the second horizontal direction with the uniform transistor row spacing; The uniform transistor row spacing is (n+1) / n times the uniform block spacing; and n is an integer greater than 1 and less than 7.

28. The memory device of claim 27, wherein: n is 2; The plurality of memory blocks further includes a second memory block; and Each of the first word line driver transistor and the second word line driver transistor, having an output node electrically connected to a word line in the first memory block, includes another output node electrically connected to a corresponding word line in the second memory block.

29. The memory device of claim 28, wherein: The first word line driver transistor includes a first row of first word line driver transistors and a second row of first word line driver transistors spaced apart along the second horizontal direction; The second word line driver transistor includes a first row of second word line driver transistors and a second row of second word line driver transistors spaced apart along the second horizontal direction; The word lines in the first memory block are electrically connected to the first output node of the first word line driver transistor in the first row, the second output node of the second word line driver transistor in the first row, or the first output node of the second word line driver transistor in the second row. and The word lines of the second memory block are electrically connected to the second output node of the first word line driver transistor of the first row, the first output node of the first word line driver transistor of the second row, or the second output node of the second word line driver transistor of the second row.

30. The memory device of claim 27, wherein: n is 3; The plurality of memory blocks further includes a second memory block and a third memory block; and Each of the first word line driver transistor and the second word line driver transistor, having an output node electrically connected to the word line in the first memory block, includes another output node electrically connected to the corresponding word line in a memory block that is not the first memory block.

31. The memory device according to claim 30, wherein: The first word line driver transistor includes a first row of first word line driver transistors and a second row of first word line driver transistors spaced apart along the second horizontal direction; The second word line driver transistor includes a first row of second word line driver transistors, a second row of second word line driver transistors, and a third row of second word line driver transistors spaced apart along the second horizontal direction; The first output node of the first row first word line driver transistor, the second output node of the first row second word line driver transistor, and the first output node of the second row second word line driver transistor are electrically connected to the corresponding word lines in the first memory block; The second output node of the first word line driver transistor in the first row, the first output node of the first word line driver transistor in the second row, and the second output node of the second word line driver transistor in the second row are electrically connected to the corresponding word lines in the second memory block. and The second output node of the second row first word line driver transistor and the first output node of the third row second word line driver transistor are electrically connected to the corresponding word lines in the third memory block.

32. The memory device of claim 25, wherein: The memory die further includes rows of layer contact via structures arranged along the first horizontal direction; and Each row of the layer contact via structure contacts the word line within the corresponding alternating stack in the alternating stack.

33. The memory device of claim 25, wherein the plurality of rows of the first word line driver transistors are periodically modulated on a first inter-row spacing along the second horizontal direction, the first inter-row spacing being measured by a lateral spacing between adjacent pairs of first word line driver transistors spaced laterally along the second horizontal direction.

34. The memory device of claim 21, wherein the first word line driver transistor further comprises a second output node electrically connected to a word line in a second memory block of the plurality of memory blocks, a common input node, a first gate electrode located between the common input node and the first output node, and a second gate electrode located between the common input node and the first output node.

35. A memory device, the memory device comprising: Multiple memory blocks, wherein the multiple memory blocks include corresponding word lines; and A word line driver circuit, comprising a first word line driver transistor having a source-drain orientation, and a second, third, and fourth word line driver transistors having the same source-drain orientation as the first word line driver transistor. in: The first word line driver transistor includes a first output node having a first length, the first output node being electrically connected to a word line in a first memory block of the plurality of memory blocks; The second word line driver transistor includes a second output node having the first length, the second output node being electrically connected to a word line in the first memory block; The third word line driver transistor includes a first output node having a second length, the first output node being electrically connected to a word line in the first memory block; The fourth word line driver transistor includes a second output node having the second length, the second output node being electrically connected to a word line in a second memory block of the plurality of memory blocks; The first word line driver transistor and the second word line driver transistor are laterally spaced apart by a first lateral spacing along the source-drain direction; The third word line driver transistor and the fourth word line driver transistor are laterally spaced apart by a second lateral spacing along the source-drain direction; and There exists at least one of the following conditions: (i) the second lateral spacing is greater than the first lateral spacing, or (ii) the second length is longer than the first length.

36. The memory device of claim 35, wherein the second lateral spacing is greater than the first lateral spacing.

37. The memory device of claim 35, wherein the second length is longer than the first length.

38. The memory device of claim 35, wherein the second length is longer than the first length, and the second lateral spacing is greater than the first lateral spacing.

39. The memory device according to claim 35, wherein: The first output node includes the source or drain region of the first word line driver transistor; The second output node includes the source or drain region of the second word line driver transistor; The third output node includes the source or drain region of the third word line driver transistor; and The fourth output node includes the source or drain region of the fourth word line driver transistor.

40. The memory device of claim 35, wherein: The plurality of memory blocks are located in the memory die; The word line driver circuit is located in the logic die; and The memory die is bonded to the logic die.

Images