Linearity enhancement in cascode amplifiers and its automation

Abstract

The present disclosure provides various techniques for enhancing large signal linearity in a cascode amplifier by decoupling the cascode transistor operating mode from the input transistor operating mode. In various embodiments, the input transistor can remain biased in an operating mode selected for the amplification stage, and the cascode transistor can be biased in a different operating mode, e.g., an operating mode associated with a reduction in conduction angle, to delay the gain compression onset point and improve P1dB, also corresponding to an improvement in IIP3 in many implementations. The mode selection can be static or dynamically controlled, based on input reference signal level and / or output reference signal level and threshold conditions associated with P1dB and / or IIP3 requirements, implemented using feedforward sensing, feedback sensing, or hybrid feedforward plus feedback sensing. Exemplary embodiments include different selectable operating modes for the cascode device.

Description

Cross-references to related applications

[0001] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 766,351, filed March 3, 2025, entitled “Linearity Enhancement and Automation in a Common-Source Common-Gate Amplifier,” the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates generally to electronic circuit design, and more specifically to common-source cascode amplifier architecture and biasing and control techniques for common-source cascode amplifier circuits. Background Technology

[0003] Radio frequency (RF) systems and their applications, including sixth-generation (6G) and more advanced telecommunications networks, Wi-Fi systems, satellite and non-terrestrial networks (NTN), sensor-interconnected communication (ISAC), vehicle-to-everything (V2X) systems, Internet of Things (IoT) applications, industrial and private networks, defense and aerospace systems, and medical and wearable devices, have become an indispensable part of modern society.

[0004] Common-source cascode amplifier architectures are commonly used in RF and mixed-signal front-ends, including power amplifiers, low-noise amplifiers, variable-gain amplifiers, phase shifters, and receiver gain stages, where impedance environments and signal levels vary with operating conditions. In a typical common-source cascode configuration, the input transistor is arranged to receive the input signal and generate an amplified signal at an intermediate node. The common-source cascode transistor is coupled to the input transistor to reduce voltage variations at the intermediate node and suppress unwanted output-to-input feedback.

[0005] Conventionally, the bias of a cascode amplifier is selected to meet voltage margin constraints, gain targets, noise considerations, and stability requirements. For example, under Class A operating conditions, the input transistor can be biased to support low-noise performance and predictable small-signal gain. Typically, the cascode transistor is biased to maintain an appropriate voltage at the intermediate node and to keep it within the desired operating region, such as the saturation region, relative to the expected signal swing range. In many implementations, the input transistor bias is selected based on the operating class of the amplification stage, while simultaneously coordinating the cascode transistor to ensure consistent conduction behavior between the two devices.

[0006] However, conventional cascode biasing can limit large-signal operation. As the input signal amplitude increases, cascode amplifiers may experience gain compression, intermodulation distortion, and decreased linearity, which can be problematic in the presence of strong blocking signals, adjacent channel interference, or large-amplitude useful signals. In many receiver applications, linearity constraints arise from the need to withstand high-power interference while maintaining acceptable performance for weaker signals. Conventional methods to improve linearity may involve increasing bias current, increasing device size, adding auxiliary linearization circuitry, or changing load conditions, potentially increasing power consumption, area, and circuit complexity. Furthermore, cascode amplifiers are typically biased with a fixed bias condition chosen for the nominal operating point. In real-world systems, signal conditions change over time due to variations in channel conditions or external interference. Under some conditions, a fixed-bias cascode amplifier may be forced into unfavorable operating states, while under others it may lead to over-design.

[0007] Therefore, improved cascode amplifier technology is still needed to address the limitations of conventional biasing and control methods under varying signal conditions, while also adapting to practical integrated circuit constraints. Attached Figure Description

[0008] One or more embodiments of this disclosure are shown in the accompanying drawings by way of example rather than limitation, wherein the same reference numerals denote similar elements. These drawings are not necessarily drawn to scale.

[0009] Figure 1A An exemplary radio frequency (RF) signal chain environment in which the common-source cascode amplifier technology of this disclosure can be implemented is shown.

[0010] Figure 1B An exemplary cascode amplifier is shown, including a first transistor M1 and a second transistor M2 coupled in a typical cascode configuration, in which M1 and M2 are commonly biased in the same operating mode.

[0011] Figure 2A An exemplary cascode amplifier implementing the cascode amplifier technology of this disclosure is shown, wherein the second transistor M2 is biased in a manner different from the operating mode of the first transistor M1.

[0012] Figure 2B An exemplary gain-input power graph is shown, which compares to a conventional cascode amplifier (e.g., Figure 1B The amplifier shown) and an exemplary common-source cascode amplifier implementing the technology of this disclosure (e.g., Figure 2A (The amplifier shown).

[0013] Figure 3AAn exemplary common-source cascode amplifier implementing the technology of this disclosure is shown, wherein a control signal is used to selectively bias a second transistor M2 in a first operating mode or a second operating mode.

[0014] Figure 3B An exemplary gain-input power graph is shown, which compares the second transistor M2 (e.g., in...) Figure 3A The gain compression behavior of the common-source cascode amplifier shown in different operating modes.

[0015] Figure 4 An exemplary common-source cascode amplifier implementing the technology of this disclosure is shown, wherein a feedforward control device is configured to select the operating mode of a second transistor.

[0016] Figure 5 An exemplary cascode amplifier implementing the technology of this disclosure is shown, wherein a feedback control arrangement is configured to select the operating mode of the second transistor M2.

[0017] Figure 6 An exemplary common-source cascode amplifier implementing the technology of this disclosure is shown, wherein a hybrid control device uses feedforward and / or feedback information to select the operating mode of the second transistor M2.

[0018] Figure 7 An exemplary method for selecting the operating mode of the second transistor M2 based on the input signal level is shown.

[0019] Figure 8 An exemplary differential cascode amplifier implementing the technology of this disclosure is shown, wherein each cascode transistor M2 is selectively biased in different operating modes in response to one or more control signals.

[0020] Figure 9 An exemplary differential cascode amplifier implementing the technology of this disclosure is shown, wherein a capacitor neutralization network is coupled between differential nodes.

[0021] Figure 10 A block diagram of an exemplary power amplifier (PA) signal chain is shown, which includes a common-source or common-gate driver stage, a multi-mode cascode stage, an output matching network, and gain boosting and stabilization circuitry coupled between the driver stage and the multi-mode cascode stage.

[0022] Figure 11 A block diagram of an exemplary PA signal chain is shown, wherein an automatic mode selection network is configured to select the operating mode of a multi-mode cascode stage, and wherein the PA also includes an output matching network and gain boosting and stabilization circuitry.

[0023] Figure 12An exemplary graph is shown, illustrating how gain, efficiency, and frequency response vary in different operating modes of a multi-mode cascode PA. Detailed Implementation

[0024] Modern radio frequency (RF) receivers and mixed-signal front-ends increasingly require operation over wide dynamic ranges while maintaining stable performance under interference and rapidly changing channel conditions. In many practical deployments, an amplification stage may be needed to amplify very weak useful signals while also withstanding strong blocking signals and potentially time-varying adjacent-channel interference. These conflicting requirements place significant pressure on the linearity, power consumption, and robustness of amplifier architectures used in low-noise amplifiers (LNAs), variable-gain amplifiers (VGAs), and power amplifiers (PAs).

[0025] As mentioned above, conventional cascode amplifier bias is typically chosen to meet voltage margin constraints, gain targets, and stability requirements at the nominal operating point. However, actual operating conditions can vary significantly, potentially leading to amplifier gain compression and increased intermodulation distortion in large-signal scenarios (such as strong blocking signals, adjacent channel interference, or large-amplitude useful signals). Because conventional cascode configurations usually coordinate the biases of input transistor M1 and cascode transistor M2, with cascode transistor M2 typically biased to operate in the saturation region, the achievable linearity and power trade-offs are limited by the given operating class selected for the amplification stage. Furthermore, under certain conditions, a fixed bias may force the cascode amplifier into operating states associated with gain compression and increased intermodulation distortion, which is undesirable in transmitter and receiver applications where signal levels change rapidly.

[0026] Therefore, this paper introduces techniques that can be used to decouple the operating modes of devices within a cascode amplifier. Specifically, in one or more embodiments, the input transistor M1 can operate in a first operating mode corresponding to a first conduction angle, and the cascode transistor M2 coupled to the input transistor M1 can operate in a second operating mode corresponding to a second conduction angle smaller than the first conduction angle. In various implementations, the bias control circuitry can establish the operating modes by applying bias conditions to the input transistor M1 and the cascode transistor M2, and the bias control circuitry can be further configured to maintain a substantially constant bias of the input transistor M1 when adjusting the bias of the control terminal of the cascode transistor M2. Furthermore, in some embodiments, the bias control circuitry can selectively operate the cascode transistor M2 in two or more operating modes with different conduction angles based on signal levels associated with the amplifier circuitry (e.g., signal levels derived from the input signal and / or signal levels derived from the output signal). In such an embodiment, the bias control circuit can select an appropriate operating mode based on whether the signal level meets a threshold condition associated with a 1dB compression point (P1dB) requirement and / or a third-order input intercept point (IIP3) requirement, thereby enabling adaptive operation in response to changing signal conditions.

[0027] In summary, embodiments of this disclosure provide an implementation of a cascode amplifier that expands the available design flexibility relative to conventional biasing methods by enabling independent, and in some cases, dynamic, selection of the operating mode of the cascode transistor M2 relative to the input transistor M1. In this way, the techniques of this disclosure can support improved large-signal behavior, including improved linearity and reduced gain compression, without relying solely on conventional techniques (e.g., increasing bias current, increasing device size, or adding complex auxiliary linearization circuitry). Furthermore, the techniques of this disclosure can be implemented using a control architecture that uses feedforward and / or feedback sensing to select the operating mode of the cascode transistor M2, and can be integrated into practical front-ends such as low-noise amplifiers, power amplifiers, variable gain amplifiers, and phased array stages.

[0028] Numerous specific details are set forth below to provide a comprehensive understanding of the currently disclosed techniques. In other embodiments, the techniques described herein may be implemented without these specific details. In other instances, well-known features (such as specific manufacturing techniques) have not been described in detail to avoid unnecessarily obscuring this disclosure. References to “embodiment,” “an embodiment,” etc., in this specification mean that a particular feature, structure, material, or property described is included in at least one embodiment of this disclosure. Therefore, these phrases appearing in this specification do not necessarily all refer to the same embodiment. On the other hand, such references are not necessarily mutually exclusive. Furthermore, in one or more embodiments, particular features, structures, materials, or properties may be combined in any suitable manner. In addition, it should be understood that the various embodiments shown in the accompanying drawings are merely illustrative representations and are not necessarily drawn to scale.

[0029] Certain details relating to the structure or process typically associated with integrated circuit design, including the physical layout of typical passive components (e.g., inductors, capacitors, resistors, filters, and related sub-components), may not be set forth in the following description, as including such well-known details could obscure important aspects of the technology disclosed herein. Furthermore, while the following disclosure sets forth several embodiments of different aspects of the present disclosure, several other embodiments may have different configurations or different components than those described in this section. Therefore, the described technology may have other embodiments, with or without the additional elements described below.

[0030] For ease of discussion herein, the terms “coupling” and “connection” and their derivatives may be used to describe structural relationships between components. It should be understood that these terms are not intended to be synonyms. Rather, in certain embodiments, “connection” may be used to indicate that two or more elements are in direct contact with each other. Unless otherwise stated in the context, the term “coupling” may be used to indicate that two or more elements are in direct or indirect contact with each other (with the presence of other inserted elements), or that two or more elements cooperate or interact with each other (e.g., as a causal relationship), or both. Despite the foregoing, unless otherwise stated or clearly understood from the context, references to “series connection” or “parallel connection” of components refer to their functional electrical relationship, not to the requirement of uninterrupted physical conductors.

[0031] In this paper, for the purposes of discussion, the term "conduction angle" refers to the angular measure of the portion of a signal cycle in which a transistor conducts the current associated with the amplification of the periodic components of the signal. Conduction angles can be expressed over a 360° cycle, where a conduction angle close to 360° corresponds to conduction essentially throughout the entire cycle, and a smaller conduction angle corresponds to conduction only for a smaller portion of the cycle.

[0032] In this document, for the purposes of discussion, the term "operating mode" refers to the defined operating conditions of a circuit element (e.g., a transistor) established by one or more bias conditions. In the case of a transistor, the operating mode can be characterized by a conduction angle and can correspond to an operating category (e.g., Class A, Class AB, or Class B). Furthermore, the operating mode can refer to a discrete or continuous bias state selected by bias control circuitry, including different bias states corresponding to different conduction angles. As an example, Class A operating conditions are typically associated with a conduction angle of approximately 360°, Class B operating conditions with approximately 180°, and Class AB operating conditions between approximately 180° and approximately 360°. Additionally, in some implementations, operating categories where conduction occurs for less than half a signal cycle can be used, which may correspond to conduction angles less than approximately 180°.

[0033] Figure 1A Exemplary radio frequency (RF) signal chain environments 100 and 102 in which the common-source cascode amplifier technology of this disclosure can be implemented are shown. In example signal chain environment 100, antenna 110 is coupled to a receiver front end that includes a low-noise amplifier (LNA) 120 followed by a variable-gain amplifier (VGA) 130. In this receiver configuration, LNA 120 can be configured to provide low-noise amplification of the received RF signal, and VGA 130 can be configured to provide gain adjustment to accommodate changing signal conditions, such as variations in received signal strength or interference conditions. In example signal chain environment 102, antenna 112 is coupled to a transmitter chain that includes a power amplifier (PA) 122 driven by a pre-gain stage (shown as a driver or VGA 132). In this transmitter configuration, driver or VGA 132 can be configured to condition the signal provided to PA 122, and PA 122 can be configured to provide higher output power for transmission by antenna 112.

[0034] Environments 100 and 102 are provided as representative examples to illustrate that amplifier building blocks can be used in both the receive and transmit signal paths, and can operate under the following conditions where linearity, gain compression, and power consumption are design constraints. In many wireless deployments, signal conditions may include blocking signals and adjacent channel interference, especially in high-usage frequency bands, and linearity constraints may apply to amplifier building blocks in transceiver chains.

[0035] It's important to note that amplifier linearity is typically characterized using standard metrics such as the 1dB compression point (P1dB) and the third-order input intercept (IIP3). Generally, P1dB and IIP3 are correlated; typically, improving P1dB will correspondingly improve IIP3, and vice versa. Performance targets associated with P1dB and IIP3 can constrain the design choices of the amplification stage, including... Figure 1A The LNA 120, VGA 130, driver or VGA 132 and PA 122 shown, as well as other amplifier components used in RF systems, constitute the module.

[0036] Figure 1B An exemplary cascode amplifier 104 is illustrated, comprising a first transistor M1 140 and a second transistor M2 150 coupled in a typical cascode configuration, in which the first transistor M1 140 and the second transistor M2 150 are jointly biased in the same operating mode. In the illustrated arrangement, an input signal Vin is applied to the first transistor M1 140, generating an output signal Vout at the output node associated with the second transistor M2 150. In many conventional cascode implementations, the first transistor M1 140 is selected and biased to provide a desired operating class for the amplification stage, for example, Class A operating conditions for receiver front-end applications, or Class AB operating conditions for specific driver or PA applications. The choice of operating class can be determined by efficiency targets and linearity requirements, such as a target 1dB compression point (P1dB) and the associated third-order input intercept point (IIP3).

[0037] In such Figure 1B In the typical configuration shown, the second transistor M2 150 is typically biased to operate as a cascode device and remain in the saturation region over the expected signal swing. For example, the second transistor M2 150 can be biased to maintain the intermediate node between the first transistor M1 140 and the second transistor M2 150 within a desired voltage range and reduce voltage variations at the intermediate node. In this conventional practice, the biases of the first transistor M1 140 and the second transistor M2 150 can be coordinated such that the entire cascode amplifier 104 operates in a selected operating mode, and both the first transistor M1 140 and the second transistor M2 150 exhibit conduction behavior consistent with that selected operating mode.

[0038] In the example shown, the gate-drain capacitance Cgd 142 and the gate-source capacitance Cgs 144 are schematically illustrated to show parasitic capacitances that may exist in a real device and could lead to undesirable coupling between circuit nodes. It should be noted that the provided... Figure 1BThe conventional cascode bias and operating configuration is exemplified as a reference for embodiments of the technology described in the following figures. Although for clarity, Figure 1B The implementation of a field-effect transistor (FET) is shown, but the cascode amplifier 104 can be implemented using other transistor technologies in various integrated circuit processes.

[0039] Figure 2A An exemplary cascode amplifier 200 implementing the cascode amplifier technology of this disclosure is shown, wherein a second transistor M2 250 is biased in an operating mode different from that of the first transistor M1 240. In the illustrated implementation, the input signal Vin is coupled to the cascode amplifier 200 via an input matching network 220, and the first transistor M1 240 and the second transistor M2 250 are coupled between the power node VDD and the reference node in a cascode configuration. A source degradation network 230 is coupled to the first transistor M1 240 and can be configured to set the operating point and provide the desired degradation effect. Parasitic capacitances, such as gate-drain capacitance Cgd and gate-source capacitance Cgs, are schematically shown to illustrate that actual devices may include parasitic capacitances that could lead to undesirable coupling between circuit nodes.

[0040] exist Figure 2A In the example, the first transistor M1 240 can be biased in a selected operating mode for the amplification stage, and the second transistor M2 250 can be biased in a different operating mode. Figure 2A The operating condition is identified as Mode 1 for the second transistor M2 250. In various embodiments, a control signal 252 can be applied to the second transistor M2 250 to set a bias condition corresponding to the Mode 1 operating condition. For example, a bias control circuit (not shown in the image) Figure 2A(As shown in the diagram) The bias of the second transistor M2 250 can be configured to individually control the bias of the second transistor M2 250 to select an operating mode corresponding to a reduced conduction angle relative to the conduction angle associated with the operating mode of the first transistor M1 240. Specifically, in some embodiments, the bias control circuitry can set the operating mode of the second transistor M2 250 by adjusting the gate bias voltage applied to the gate terminal of the second transistor M2 250. For example, the bias control circuitry can select between two or more gate bias levels, each corresponding to a corresponding operating mode. Furthermore, the bias control circuitry can include a bias generator and, in some embodiments, a digital-to-analog converter (DAC) configured to generate a programmable gate bias voltage for the second transistor M2 250. In one or more examples, the bias control circuitry can use a switching bias network that selectively couples the gate of the second transistor M2 250 to one of a plurality of bias reference nodes, or it can adjust the bias current or bias voltage associated with the second transistor M2 250 to move the operating point of the second transistor M2 250.

[0041] In this way, the cascode amplifier 200 can decouple the conduction behavior of the second transistor M2 250 from that of the first transistor M1 240. This decoupling provides additional freedom in selecting the bias conditions of the second transistor M2 250 without altering the bias conditions of the first transistor M1 240. As a result, the cascode amplifier 200 can be configured such that the first transistor M1 240 remains biased in the desired operating mode of the amplification stage, while the second transistor M2 250 is biased in a different operating mode associated with a reduced conduction angle.

[0042] The cascode amplifier 200 also includes an output circuit 260 coupled to the output node Vout. In the example shown, the output circuit 260 includes a transformer (TF) coupled between the power supply node VDD and the output node Vout. In some implementations, the TF may be designed to provide impedance matching at the output node Vout. Furthermore, the characteristics of the TF and the associated output network can be selected such that the output circuit 260 attenuates out-of-band frequency components relative to the in-band frequency range. The output circuit 260 is shown by way of example, and other output networks may be used in various embodiments.

[0043] Figure 2BAn exemplary gain-input power plot 205 is shown, comparing a conventional cascode amplifier with an exemplary cascode amplifier implementing the techniques of this disclosure. In the illustrated plot 205, the gain is shown as a variation of the input power pin. The conventional gain compression characteristic is shown as a reference plot marked "conventional," which may correspond to a cascode amplifier where the input transistor and the cascode transistor are typically biased in the same operating mode, for example... Figure 1B The cascode amplifier 150. Graph 205 also illustrates the gain compression characteristics of an exemplary embodiment in which the cascode transistor operates in mode 1 (labeled "M2 in mode 1"), for example... Figure 2A The 200 is a common-source, cascode amplifier. It should be noted that... Figure 2B The specific curve shape and compression point location shown are provided as examples. Actual gain characteristics and compression behavior can depend on bias conditions, device size, load, operating frequency, and manufacturing process technology.

[0044] like Figure 2B As shown, the gain characteristics of "M2 in Mode 1" may differ from those of a conventional gain characteristic over at least a certain range of the input power range. For example, in some implementations, the gain of "M2 in Mode 1" may be lower at low input power relative to a "conventional" gain characteristic, while tending to approach the conventional gain near the compression region. Figure 2B The 1dB compression point reference (P1dB_Ref) associated with the normal gain compression characteristic and the 1dB compression point associated with the gain compression characteristic of "M2 in Mode 1" (P1dB_M2-Mode-1) are further identified. In the example shown, the input power Pin corresponding to P1dB_M2-Mode-1 is higher than the input power Pin corresponding to P1dB_Ref.

[0045] In this way, operating the second transistor M2 250 in Mode 1 extends the input power range within which the cascode amplifier 200 maintains the expected gain level before entering the compression region. This 1dB shift in the compression point corresponds to improved large-signal linearity of the cascode amplifier 200 when the amplifier needs to handle increased input power and signals from strong blocking or adjacent channel interference, which would otherwise push the amplifier into gain compression. Furthermore, because the operating mode adjustment is achieved by applying a bias to the second transistor M2 250 individually, this technique reduces the need for increased bias current or larger device size to meet the P1dB requirement. Therefore, in practical implementations, Mode 1 operating conditions can support an improved linearity and efficiency tradeoff.

[0046] also, Figure 2BThe gain behavior shown indicates that in some implementations, even with the gain reduction at low input power, the gain can still approach that of a conventional configuration near the compression region. Therefore, beyond the input P1dB_Ref associated with a conventional configuration, the cascode amplifier 200 can operate at approximately the same gain as a conventional cascode amplifier while still benefiting from the increased input P1dB. In systems where P1dB and the third-order input intercept (IIP3) are related, an increase in input P1dB can also indicate a corresponding improvement in IIP3.

[0047] In some additional or alternative embodiments, the bias control circuitry can selectively adjust the operating mode of the second transistor M2250 while maintaining the operating mode of the first transistor M1240. Related alternative mode embodiments are described in reference. Figures 3A to 3B Describe it.

[0048] Figure 3A An exemplary cascode amplifier 300 implementing the present disclosure is shown, wherein a control signal 354 is used to selectively bias a second transistor M2 350 into a first operating mode or a second operating mode. In the illustrated implementation, an input signal Vin is coupled to the cascode amplifier 300 via an input matching network 320, and a first transistor M1 340 and a second transistor M2 350 are coupled between a power node VDD and a reference node in a cascode configuration. A source degradation network 330 is coupled to the first transistor M1 340 and can be configured to set the operating point and provide the desired degradation effect.

[0049] The cascode amplifier 300 also includes an output circuit 360 coupled to the output node Vout. The output circuit 360 may include one or more passive and / or active components configured to provide the desired output load conditions to the cascode amplifier 300. More specifically, in some embodiments, the output circuit 360 may include a transformer (TF) coupled to the output node of the cascode amplifier, wherein the TF is configured to provide the desired output load conditions and impedance transformation for the transmission of the output signal Vout. In one example implementation, the TF may be implemented as a transformer having a primary winding coupled to the power node VDD and a secondary winding coupled to the output node Vout (or vice versa, depending on the selected topology), such that the TF provides a frequency-selective impedance transformation centered at a target frequency f0. In such an implementation, the TF may be designed as a narrowband output network, wherein the TF and the transformer winding establish a resonant response with the inherent parasitic capacitance of the associated node, which provides impedance matching over a relatively narrow frequency range near f0.

[0050] Additionally or alternatively, the output circuit 360 can be configured as a broadband output network by coupling one or more capacitors to one or more terminals of the TF. For example, one or more capacitors can be coupled to one or both windings of the TF (e.g., as parallel capacitors on the primary and / or secondary sides) to introduce additional resonant responses. By appropriately selecting the capacitor values, winding inductances, and coupling coefficients, the output circuit 360 can present two resonant peaks near f0 or a broadened passband response relative to a narrowband TF arrangement. In this way, the output circuit 360 can be configured for narrowband impedance matching or broadband impedance matching, depending on application constraints such as operating bandwidth, gain flatness targets, and out-of-band attenuation requirements. Furthermore, in various implementations, the TF-based output circuit 360 can also attenuate out-of-band frequency components relative to the desired in-band range based on its frequency-selective impedance behavior.

[0051] According to one or more embodiments, the common-source cascode amplifier 300 further includes a bias control circuit 352 coupled to the second transistor M2 350. In many embodiments, the bias control circuit 352 may be configured to apply a selected bias condition that causes the second transistor M2 350 to operate in mode 1 or mode 2 in response to a control signal 354.

[0052] More specifically, in Figure 3A In the example, control signal 354 can be provided to bias control circuit 352 to select the operating mode of second transistor M2 350. In some embodiments, control signal 354 can be a digital mode selection signal indicating a selection between mode 1 and mode 2. Additionally or alternatively, control signal 354 can be an analog control level corresponding to the bias level of second transistor M2 350. In response to control signal 354, bias control circuit 352 can apply a first bias condition to operate second transistor M2 350 in mode 1, and can apply a second bias condition to operate second transistor M2 350 in mode 2. Mode 1 and mode 2 can correspond to different conduction angles of second transistor M2 350. Meanwhile, first transistor M1 340 can remain biased in the selected operating mode for the amplification stage, including the noise-dependent performance-preserving operating mode selected in a low-noise amplifier (LNA) implementation.

[0053] The cascode amplifier 300 may further include a matching / peaking network 370 coupled to the second transistor M2 350. The matching / peaking network 370 may include one or more passive components (e.g., one or more inductors) configured to resonate with the parasitic capacitance at the associated node and to shape the impedance presented to the second transistor M2 350 over the operating frequency range. By selectively setting the operating mode of the second transistor M2 350 using control signal 354 and bias control circuitry 352, the cascode amplifier 300 can controllably adjust the conduction angle of the second transistor M2 350 while maintaining the bias conditions of the first transistor M1 340. This controllability allows the cascode amplifier 300 to operate under different large-signal conditions, including conditions favoring higher gain and conditions favoring higher linearity and efficiency, without redesigning the signal path. Therefore, the cascode amplifier 300 illustrates an implementation that further extends the mode decoupling of this disclosure, thereby enabling selectable operating modes of the second transistor M2 350.

[0054] Figure 3B An exemplary gain-input power plot 305 is shown to compare the gain compression behavior of the second transistor M2 350 in different operating modes. In plot 305, the gain is shown as a variation of the input power pin. A typical gain compression characteristic is shown as a reference plot labeled "typical," which may correspond to a cascode amplifier where the input transistor and the cascode transistor are typically biased in the same operating mode, for example, Figure 1B The common-source cascode amplifier 150. Graph 305 also shows the gain compression characteristic labeled "M2 in Mode 1," which corresponds to the operating condition where the second transistor M2 350 is biased in Mode 1. Graph 305 also shows the gain compression characteristic labeled "M2 in Mode 2," which corresponds to the operating condition where the second transistor M2 350 is biased in Mode 2. It should be noted that... Figure 3B The specific curve shape and compression point location shown are provided as examples. Actual gain characteristics and compression behavior can depend on bias conditions, device size, load, operating frequency, and manufacturing process technology.

[0055] Figure 3B The 1dB compression point reference value (P1dB_Ref) associated with the conventional gain compression characteristics is further identified. Figure 3BIt also identifies the 1dB compression point (P1dB_M2-Mode-1) associated with the gain compression characteristic of "M2 in Mode 1" and the 1dB compression point (P1dB_M2-Mode-2) associated with the gain compression characteristic of "M2 in Mode 2". In the example shown, the input power Pin corresponding to P1dB_M2-Mode-1 and P1dB_M2-Mode-2 is higher than the input power Pin corresponding to P1dB_Ref.

[0056] More specifically, such as Figure 3B As shown, operating the second transistor M2 350 in either mode 1 or mode 2 can produce corresponding gain characteristics different from conventional gain characteristics over at least a portion of the input power range. For example, at low input power, the gain associated with mode 2 can be lower than the gain associated with mode 1. Furthermore, in some embodiments, operating the second transistor M2 350 in mode 2 relative to mode 1 can further improve linearity and efficiency, and this improvement can incidentally reduce the gain at lower input power. According to various aspects of this embodiment, the gain characteristics of mode 1 and mode 2 can be separated as the input power Pin increases toward the compression region. Control signal 352 and bias control circuit 370 can be used to select the operating mode of the second transistor M2 350 that better matches the current signal conditions. In this way, the cascode amplifier 300 can perform gain and linearity fine-tuning by selecting a higher gain operating mode when the input power Pin is relatively low and a higher linearity and efficiency operating mode when the input power Pin is close to the compression region. Therefore, selectable operating modes can provide a controllable trade-off between gain, linearity, and power consumption over a range of input power levels, rather than relying on a single fixed bias condition.

[0057] Figure 4 An exemplary cascode amplifier 400 implementing the present disclosure is shown, wherein a feedforward control device is configured to select the operating mode of a second transistor M2. In the illustrated implementation, an input signal Vin is coupled to the cascode amplifier 400 via an input matching network, and a first transistor M1 and a second transistor M2 are coupled between a power node VDD and a reference node in a cascode configuration. The cascode amplifier 400 includes a source degradation network coupled to the first transistor M1, a matching / peaking network coupled at an intermediate node between the first transistor M1 and the second transistor M2, and an output circuit coupled to an output node Vout. The matching / peaking network may include one or more reactive elements (e.g., one or more peak inductors) configured to resonate with the parasitic capacitance associated with the intermediate node to shape the frequency response and support gain flatness and / or bandwidth targets in a selected operating frequency band. Figure 4Also shown is a feedforward smart network 452 coupled to the second transistor M2, wherein the feedforward smart network 452 is coupled to receive a signal level derived from the input signal Vin and is configured to select the operating mode of the second transistor M2 based on the signal level.

[0058] In various implementations, the feedforward intelligent network 452 may include input sensors (e.g., envelope detectors, power detectors, or other level detection circuitry) and control logic configured to compare detected input-related metrics with one or more threshold conditions associated with a 1dB compression point (P1dB) requirement and / or a third-order input intercept point (IIP3) requirement. Based on this comparison, the feedforward intelligent network 452 may bias the second transistor M2 in a selected operating mode, including a choice between a higher gain operating mode and a higher linearity operating mode with a reduced conduction angle. In this way, the cascode amplifier 400 can proactively adjust its large-signal behavior based on measured input conditions while maintaining the selected operating mode for the first transistor M1 in the amplification stage.

[0059] Figure 5 An exemplary cascode amplifier 500 implementing the technology of this disclosure is shown, wherein a feedback control device is configured to select the operating mode of a second transistor M2. The cascode amplifier 500 includes an input matching network coupled to an input signal Vin, a first transistor M1 and a second transistor M2 coupled in a cascode configuration, a source degradation network, a matching / peaking network coupled at an intermediate node between the first transistor M1 and the second transistor M2, and an output circuit coupled to an output node Vout. Figure 5 A feedback intelligent network 552 coupled to the second transistor M2 is also shown. In the illustrated arrangement, the feedback intelligent network 552 is coupled to receive information derived from the output node Vout and is configured to select the operating mode of the second transistor M2 based on monitored output-related metrics.

[0060] In some embodiments, the feedback intelligent network 552 may include an output sensor configured to sense output power, output amplitude, or another output-related level metric, and threshold logic configured to apply one or more threshold conditions associated with P1dB and / or IIP3 requirements. Based on whether the monitored output-related metric meets the threshold conditions, the feedback intelligent network 552 may bias the second transistor M2 in a selected operating mode. For example, when the monitored output-related metric indicates operation near the compression region, the feedback intelligent network 552 may select an operating mode that improves large-signal linearity, while when the monitored output-related metric indicates lower power conditions, it may select a higher-gain operating mode. Therefore, the cascode amplifier 500 can provide closed-loop adaptation of the operating mode of the second transistor M2 based on observed output behavior.

[0061] Figure 6 An exemplary cascode amplifier 600 implementing the technology of this disclosure is shown, wherein a hybrid control device uses feedforward and feedback information to select the operating mode of a second transistor M2. The cascode amplifier 600 includes an input matching network coupled to the input signal Vin, a first transistor M1 and a second transistor M2 coupled in a cascode configuration, a source degradation network, a matching / peaking network coupled at an intermediate node, and an output circuit coupled to the output node Vout. Figure 6 A feedforward and feedback intelligent network 652 coupled to the second transistor M2 is also shown. The intelligent network 652 is configured to receive information derived from the input signal Vin and information derived from the output node Vout, and select the operating mode of the second transistor M2 based on the received information.

[0062] In various embodiments, the intelligent network 652 may include both input and output sensors and may apply one or more threshold conditions associated with P1dB and / or IIP3 requirements to select between operating modes of the second transistor M2 with different conduction angles. For example, the intelligent network 652 may use feedforward sensing to anticipate an increase in input level and adjust the operating mode of the second transistor M2 before the gain compression start point, and may use feedback sensing to confirm or refine the selected operating mode based on observed output behavior. In some embodiments, the intelligent network 652 may apply priority rules, hysteresis, and / or minimum dwell time to reduce mode switching. In this way, the cascode amplifier 600 can provide adaptive selection of the operating mode of the second transistor M2 under varying signal conditions while maintaining the operating mode of the first transistor M1 selected for the amplification stage.

[0063] Figure 7An exemplary method 700 for controlling the operating mode of a cascode amplifier using the techniques of this disclosure is shown. Method 700 can be performed by, for example, bias control circuitry (e.g., bias control circuitry 352, 452, 552, or 652) configured to set bias conditions for the cascode transistor to select between one or more operating modes (e.g., normal, mode 1, and mode 2). In various implementations, the bias control circuitry can be implemented using analog circuitry, digital logic, or a combination thereof, and can cooperate with one or more sensing circuitry configured to provide signal levels associated with the cascode amplifier. Although arranged in a specific order for clarity, Figure 7 The steps can be performed in parallel, in a different order, or some steps can be omitted in various implementations. In some implementations, method 700 is performed during the operation of the cascode amplifier, such that the operating mode of the second transistor M2 is updated in response to changes in the monitored signal level.

[0064] At block 710, method 700 includes initializing a cascode amplifier using a first transistor M1 and a second transistor M2 in their default operating modes. In some embodiments, the default operating mode of the first transistor M1 may correspond to an operating mode selected for an amplification stage, such as an operating mode associated with the target noise performance of a receiver front-end gain stage. The default operating mode of the second transistor M2 may correspond to a nominal bias condition that provides the cascode amplifier with the expected voltage margin and expected output load interaction. In one or more implementations, the default operating mode biases the second transistor M2 to operate in the saturation region. In some embodiments, the default operating mode of the second transistor M2 corresponds to conventional cascode operating conditions, and method 700 maintains conventional cascode operating conditions when the monitored signal level indicates that operation remains within the 1 dB compression point associated with a conventional cascode amplifier. For example, in some sensor-related deployments, the input power to the cascode amplifier may be kept relatively low (e.g., on the order of approximately -50 dBm), and method 700 may maintain the second transistor M2 in its default operating mode.

[0065] At block 720, method 700 includes monitoring a signal level associated with a cascode amplifier. The monitored signal level can be derived from an input-side measurement, an output-side measurement, or a combination of input-side and output-side measurements. For example, in a feedforward implementation, the monitored signal level can be based on input-related metrics, such as input power level, input amplitude, or an envelope detection representation of the input signal. In a feedback implementation, the monitored signal level can be based on output-related metrics, such as output power level, output amplitude, or an envelope detection representation of the output signal. In a hybrid implementation, the monitored signal level can be based on both input-related and output-related metrics, including a combination of using one measurement to predict operating conditions and using another measurement to confirm or refine the operating mode selection. In some embodiments, the bias control circuitry may include a power sensor that samples the input power Pin and / or the output power Pout and provides the sampled power information to the bias control circuitry.

[0066] At decision box 730, method 700 includes determining whether the monitored signal level meets a threshold condition for mode change. The threshold condition may be associated with a 1dB compression point (P1dB) requirement for the amplification stage and / or a third-order input intercept point (IIP3) requirement. In some embodiments, the threshold condition may correspond to determining that operation is approaching a compression region where the increase in the output signal level is less than proportional to the increase in the input signal level. The threshold condition can be implemented using one or more threshold comparisons, one or more ranges, or a set of rules, and can be calibrated or adjusted for target operating frequency bands, target load conditions, and target performance requirements.

[0067] When the determination at block 730 is negative, method 700 proceeds to block 740 and maintains the current operating mode of the second transistor M2. Maintaining the current operating mode may include maintaining the current bias conditions applied to the control terminals of the second transistor M2, thereby avoiding a change in the operating mode when the monitored signal level indicates that the current operating mode is still appropriate.

[0068] When the determination at block 730 is yes, method 700 proceeds to block 750 and selects the operating mode of the second transistor M2 based on the monitored signal level. This selection may include choosing a mode associated with a decrease in conduction angle (relative to another mode) to alter the large-signal behavior of the cascode amplifier, including shifting the gain compression start point. In some embodiments, the selection may include choosing between mode 1 and mode 2 in a manner that balances gain with large-signal linearity and power consumption as the monitored signal level changes. For example, when the monitored signal level indicates operation is close to the compression region, the bias control circuit may select a higher linearity operating mode, and when the monitored signal level indicates lower power conditions, the bias control circuit may select a higher gain operating mode. It should be noted that in some embodiments, mode 2 corresponds to an operating mode of the second transistor M2 that further enhances linearity and efficiency relative to mode 1, resulting in a corresponding decrease in gain.

[0069] In block 760, method 700 includes applying a corresponding bias condition to the second transistor M2 to operate the second transistor M2 in a selected operating mode. The corresponding bias condition can be applied by selecting between two or more bias states or by setting a programmable bias level. For example, bias control circuitry can apply a digital mode selection signal that selects between discrete bias states corresponding to mode 1 and mode 2. Additionally or alternatively, bias control circuitry can apply an analog bias level that places the second transistor M2 at a selected operating point associated with desired conduction behavior. It should be noted that although two operating modes have been described for clarity, method 700 can be extended to additional operating modes of the second transistor M2, for example, by selecting between three or more bias states based on multiple thresholds or ranges.

[0070] In some implementations, method 700 can incorporate stability features to reduce unwanted mode switching near threshold boundaries. For example, bias control circuitry can implement hysteresis associated with a threshold condition and / or a minimum dwell time that holds the selected operating mode for a period of time before re-evaluating whether to change the mode. These features can be used to reduce frequent jitter when the monitored signal level varies near the threshold condition.

[0071] It should be noted that the method 700 described herein can be implemented using a more detailed decision process, wherein the threshold condition is achieved using measured or estimated gain compression metrics. For example, in a non-limiting feedforward example, the bias control circuitry can establish a small-signal gain baseline for the cascode amplifier, and a deviation of approximately 1 dB from this baseline can be considered an indication of approaching the compression region. The bias control circuitry can then adjust the bias condition of the second transistor M2 and re-evaluate the compression metrics to determine whether the P1 dB-related requirements and / or IIP3-related requirements are met. Therefore, the method 700 disclosed herein provides a framework that can utilize input-based sensing, output-based sensing, or hybrid sensing (e.g., refer to...). Figures 4 to 6 The example layout described is used to implement this, while still supporting threshold logic related to compression and linearity requirements.

[0072] More specifically, in the feedforward control embodiment, the feedforward intelligent network (e.g., Figure 4 The feedforward intelligent network 452 can control the operating mode of the cascode transistor (e.g., the second transistor M2) based on the input reference signal level. In some implementations, the feedforward intelligent network can establish a small-signal gain baseline for the cascode amplifier in a low-power region with an approximately linear response. For example, the feedforward intelligent network can base its operation on the input power measured when the second transistor M2 is biased in its default operating mode. and output power To estimate the small-signal gain (SSG). This is based on the input power. With the addition of [something], the feedforward intelligent network can continuously evaluate the current gain. .

[0073] In this embodiment, the feedforward intelligent network can increase the current gain. The near-compression region is detected by comparing the current gain with the baseline small-signal gain SSG. For example, when the current gain satisfies... At this time, the feedforward intelligent network can continue to operate the cascode amplifier without changing the bias of the second transistor M2. At the current gain... satisfy At that time, the feedforward intelligent network can treat the corresponding conditions as a 1dB compression metric and can evaluate the corresponding input reference compression point (e.g., (Input power at that point), this compression point can be considered as the current estimate of the 1dB compression point at the input. Then, the feedforward intelligent network can use this estimate. Compared to a target or requirement, which can be relative to a conventional reference value (e.g.) Use ) to specify.

[0074] When the estimated value If the requirements are not met, the feedforward intelligent network can adjust the bias of the second transistor M2 to shift its operating mode towards a smaller conduction angle. In one example, the feedforward intelligent network can "reduce" the bias of the second transistor M2 by selecting a lower gate bias level, selecting a different mode selection state, and / or changing the programmable bias setting. After adjusting the bias of the second transistor M2, the feedforward intelligent network can increase the input drive and re-evaluate the input power satisfying G=SSG-1dB under the adjusted bias conditions (e.g., obtain a corrected estimate for the adjusted bias). If the requirement is still not met and the adjusted bias continues to provide improvement, the feedforward intelligent network can iteratively perform this cycle of bias adjustment and re-evaluation. For example, the feedforward intelligent network can continue to reduce the bias of the second transistor M2 as long as (i) the required bias is met. (ii) The value reached previously, and (ii) the value currently reached. Exceeding previous levels This indicates that additional bias adjustments have resulted in additional improvements. When the requirement is met, or when further bias adjustments no longer produce improvements, the feedforward smart network can terminate the adjustment cycle and can operate under the bias conditions of the selected second transistor M2.

[0075] In a feedback control embodiment, a feedback intelligent network (e.g., Figure 5 The feedback intelligent network (552) can select the operating mode of the cascode transistor (e.g., the second transistor M2) based on the output reference signal level. In some implementations, when the cascode amplifier operates in the low-power region, the feedback intelligent network can use output-side measurements to establish a small-signal gain baseline for the cascode amplifier. For example, the feedback intelligent network can use measured output power... and known or estimated input references associated with the configuration-driven settings of the upstream level. To estimate the baseline gain SSG. During operation, the feedback intelligent network can use the measured output power. And input reference continuously estimate current gain .

[0076] Feedback-based intelligent networks can detect proximity to gain compression using baseline comparisons similar to those in feedforward implementations, but are constructed using output measurements. For example, when The feedback intelligent network can maintain the current bias conditions of the second transistor M2. When In this case, the feedback intelligent network can treat the condition as an indication of a 1dB compression condition and can evaluate the compression point estimate. In some implementations, the feedback intelligent network can evaluate the output reference 1dB compression point (e.g., Identified as (Output power). The feedback intelligent network can compare this estimate with the required value, which can be expressed as the target output power at the compressor and / or the required value derived from the P1dB and / or IIP3 constraints of the amplification stage.

[0077] When the feedback evaluation indication requirements are not met, the feedback intelligent network can adjust the bias conditions of the second transistor M2 to move it towards an operating mode with a reduced conduction angle. After bias adjustment, the feedback intelligent network can use the same baseline standard. The compression metric is reassessed, and the compression point estimate can be updated. The feedback intelligent network can iteratively perform a loop of bias adjustment until the requirement is met or until additional adjustments no longer produce additional improvement. In some embodiments, the feedback intelligent network can implement hysteresis and / or minimum dwell time, such that the operating mode of the second transistor M2 does not repeatedly switch when the output correlation metric changes near the threshold boundary.

[0078] In hybrid control embodiments, hybrid intelligent networks (e.g., Figure 6 The hybrid intelligent network (652) can use both input-derived and output-derived information to select the operating mode of the cascode transistor (e.g., the second transistor M2). In some implementations, the hybrid intelligent network can use feedforward sensing to predict the approach of gain compression and can use feedback sensing to confirm, refine, or stabilize the mode selection. For example, the hybrid intelligent network can establish a baseline gain SSG in the low-power region and can monitor input-dependent levels (e.g., input envelope or input power proxy) and output-dependent levels (e.g., output power or output envelope) during operation. The hybrid intelligent network can use measured... Estimate the current gain using known or estimated input references. and will This is considered an indication that the area is approaching the compression zone.

[0079] In this embodiment, the hybrid intelligent network can trigger an initial mode change using input-derived metrics before observing compression at the output. For example, when the input power proxy exceeds a first threshold associated with P1dB and / or IIP3 requirements, the hybrid intelligent network can preemptively adjust the bias of the second transistor M2 to move it toward an operating mode with a reduced conduction angle. The hybrid intelligent network can then use output-derived metrics to evaluate whether the preemptive mode selection achieves the desired compression point behavior, for example, by using baseline criteria. To update the estimates Or inferred When the output evaluation indication requirements are still not met, the hybrid intelligent network can further adjust the bias conditions of the second transistor M2 and re-evaluate the compression metric, thereby iterating in a manner similar to the feedforward and feedback embodiments.

[0080] In some implementations, the hybrid intelligent network can use priority logic, weighted logic, and / or state-based rules to combine input-derived decisions and output-derived decisions. For example, when the input correlation level changes rapidly, the hybrid intelligent network can prioritize feedforward decisions, and when the output-derived metrics indicate that the compression behavior has stabilized, it can prioritize feedback decisions. Additionally or alternatively, the hybrid intelligent network can apply hysteresis windows and minimum dwell times to reduce frequent switching between the operating modes of the second transistor M2. In this way, the hybrid control arrangement can provide both proactive adaptation to predicted large-signal stress conditions and closed-loop optimization improvements based on observed output behavior, while maintaining the operating mode of the first transistor M1 selected for the amplification stage.

[0081] In summary, embodiments of this disclosure provide flexible cascode amplifier control techniques, wherein the operating mode of the second transistor M2 can be selected, and in some cases dynamically selected, based on the monitored signal level associated with the cascode amplifier, while maintaining the predetermined operating mode of the first transistor M1 for the amplification stage. By operating the second transistor M2 in different operating modes with different conduction angles, the techniques of this disclosure can support improved large-signal behavior under varying signal conditions, such as varying blocking signal levels or adjacent channel interference, including delayed gain compression start points and improved linearity. Furthermore, the control methods of this disclosure can be implemented using feedforward, feedback, or hybrid monitoring and threshold logic associated with P1dB and / or IIP3 requirements, thereby providing a practical mechanism for adapting to cascode operating conditions, rather than solely relying on increasing bias current, increasing device size, or adding auxiliary linearization circuitry.

[0082] Figure 8An exemplary differential cascode amplifier 800 implementing the present disclosure in a differential signal path is shown. In the illustrated arrangement, the differential cascode amplifier 800 includes a first signal path configured to process a positive input signal Vin+ and a second signal path configured to process a negative input signal Vin-. Each signal path includes a corresponding first transistor M1 and a corresponding cascode transistor M2, which are coupled between a power supply node VDD and a reference node in a cascode configuration. The differential cascode amplifier 800 also includes a corresponding input matching network coupled to each of Vin+ and Vin-, a corresponding source degradation network coupled to each corresponding first transistor M1, and matching circuitry coupled between differential intermediate nodes of the two signal paths.

[0083] In the cascode amplifier 800, in response to one or more control signals, the corresponding cascode transistor M2 is selectively biased into mode 1 or mode 2, respectively. For example, a first control signal can be used to select the operating mode of the first cascode transistor M2 in a first signal path, and a second control signal can be used to select the operating mode of the second cascode transistor M2 in a second signal path. In some embodiments, the control signals can be the same signal, causing the two cascode transistors M2 to switch operating modes in a cooperative manner. Additionally or alternatively, the control signals can be independent, allowing the operating mode of the respective cascode transistor M2 to be adjusted individually (e.g., considering mismatch or asymmetrical loads). The differential cascode amplifier 800 also includes corresponding output circuitry coupled to each output node to generate differential output signals Vout+ and Vout-.

[0084] Figure 9 An exemplary differential cascode amplifier 900 is shown, which is generally similar to... Figure 8 The differential cascode amplifier 800 also includes a capacitor neutralization network 980 coupled between the differential nodes. In the illustrated example, the capacitor neutralization network 980 is coupled between the differential intermediate nodes associated with the two signal paths. In various implementations, the capacitor neutralization network 980 can be configured to reduce the equivalent coupling associated with parasitic capacitances (e.g., parasitic gate-to-drain coupling) by providing neutralization capacitance between the differential nodes. By reducing this coupling, the capacitor neutralization network 980 can support stability, reverse isolation, and frequency response targets in practical differential implementations, including implementations that selectively bias the corresponding cascode transistor M2 between Mode 1 and Mode 2 using the techniques of this disclosure.

[0085] Although for clarity, the capacitor neutralization network 980 is shown as a capacitor network coupled between differential intermediate nodes, other neutralization layouts and implementations can be used. For example, in some implementations, the capacitor neutralization network 980 can be implemented using one or more adjustable capacitors and / or switched capacitor banks, allowing the degree of neutralization to be adjusted for selected operating frequency bands, selected load conditions, or selected operating modes of the respective cascode transistor M2.

[0086] In short, Figure 8 and Figure 9 The mode decoupling and mode selection techniques for the cascode transistor M2 disclosed herein can be applied to a differential cascode amplifier, including an implementation in which the operating mode of each respective cascode transistor M2 can be controlled using one or more control signals, and including an implementation that further incorporates capacitor neutralization (e.g., capacitor neutralization network 980) to support practical stability and coupling management in the differential signal path.

[0087] Figure 10 A block diagram of an exemplary power amplifier (PA) signal chain 1000 is shown, which can implement the cascode mode control technique of this disclosure in a transmission environment. As shown, the PA signal chain 1000 receives an RF input signal RF_IN and provides an amplified RF output signal RF_OUT. The PA signal chain 1000 includes a driver stage 1040, a multi-mode cascode stage 1050, an output matching network 1060 coupled to a power node VDD, and gain boosting and stabilization circuitry 1080 coupled between the driver stage 1040 and the multi-mode cascode stage 1050. As described above, the driver stage 1040 may include a cascode transistor stage, a common gate transistor stage, or a combination thereof, and the multi-mode cascode stage 1050 may include cascode transistors selectively biased to operate in different operating modes (e.g., modes with different conduction angles). In various implementations, the multi-mode cascode stage 1050 can support two or more operating modes (e.g., mode 1, mode 2, mode 3, or mode 4 (discussed in more detail below)), allowing the PA signal chain 1000 to be reconfigured among multiple gain, linearity, and efficiency curves for different operating conditions. The driver stage 1040 and the multi-mode cascode stage 1050 can be implemented in single-ended or differential configurations.

[0088] According to one or more embodiments, a gain boosting and stabilization circuit 1080 can be provided to address frequency-dependent gain reduction and potential instability that may be caused by inherent device feedback capacitance. As part of the inherent device geometry, parasitic capacitances (e.g., gate-drain capacitance Cgd and gate-source capacitance Cgs) may exist at the transistor terminals within the driver stage 1040 and / or the multi-mode cascode stage 1050. In PA operation at frequencies of several gigahertz and above, the feedback capacitance represented by Cgd becomes increasingly significant and may produce a Miller effect, increasing the equivalent input capacitance and coupling output variations back to the input node. This Miller coupling adversely affects gain and bandwidth and complicates stable operation. From a design perspective, the maximum stable gain (MSG) can be approximately inversely proportional to the equivalent gate-to-drain capacitance (i.e., MSG ∝ 1 / Cgd), thus Cgd becomes a bottleneck to achieving the desired broadband stable gain unless the equivalent feedback capacitance is reduced.

[0089] In the illustrated example, the gain boosting and stabilization circuit 1080 includes a capacitor neutralizing element 1084 (Cneu), configured to cancel at least a portion of the equivalent feedback capacitance. In a differential PA implementation, the capacitor neutralizing element 1084 can be implemented as a cross-coupled capacitor neutralizing network that provides a negative capacitance effect between differential nodes to reduce the equivalent feedback capacitance associated with the active device. This capacitor neutralization can improve gain and stability across the entire frequency range by reducing Miller-coupled feedback. However, in practical layouts, the accuracy of the Cneu may be limited by unwanted parasitic effects and process variations, and the Cneu may behave as a frequency-dependent element whose compensation effect is bandwidth-limited.

[0090] To address these limitations, the gain boosting and stabilization circuitry 1080 also includes a stabilization inductor 1082 coupled to a capacitive neutralizing element 1084. This additional inductor element mitigates the practical limitations of capacitive neutralization accuracy by providing supplemental compensation, which further reduces the equivalent feedback path associated with the Miller effect, thereby enhancing broadband stability and extending the PA's operating bandwidth. In some implementations, the stabilization inductor 1082 can be selected as a relatively small inductor that forms a loop impedance around the cascode junction to stabilize the gain over frequency. In some implementations, the stabilization inductor 1082 can be implemented as a compact transmission line segment. In addition to providing inductor behavior, the transmission line implementation can serve as an interconnect between nodes associated with the cascode junction, thereby supporting the integration of stability features with inter-stage routing in a layout-efficient manner.

[0091] The output matching network 1060 can be configured to present the desired load impedance to the multimode cascode stage 1050 and couple the amplified signal to the RF output RF_OUT. In various embodiments, the output matching network 1060 may include a transformer-based matching network (e.g., a narrowband matching network or a multi-resonant broadband network) selected to transform the optimal device load impedance to a system impedance such as approximately 50 ohms. In this way, the gain boost and stabilization circuitry 1080 can reduce the equivalent Miller-coupled feedback path associated with Cgd, which can support enhanced broadband stable gain and improved operating bandwidth of the PA signal chain 1000, while the multimode cascode stage 1050 can maintain mode-based on-angle control for linearity and efficiency tradeoffs without redesigning the core signal path.

[0092] Figure 11 An exemplary PA signal chain 1100 is illustrated, wherein an automatic mode selection network 1152 is configured to select the operating mode of a multi-mode cascode stage 1150. In the illustrated embodiment, an RF input signal RF_IN is provided to a driver stage 1140, and the driver stage 1140 provides a drive signal to the multi-mode cascode stage 1150. The multi-mode cascode stage 1150 can implement the cascode technology of this disclosure in a differential configuration, including selectable operating modes of the cascode device to provide different conduction angle behaviors and corresponding gain, linearity, and efficiency tradeoffs. In some embodiments, the multi-mode cascode stage 1150 is designed to operate in two or more different modes (e.g., mode 1, mode 2, mode 3, and mode 4), such that the PA can switch between the following modes: a high-gain, low-efficiency operating mode; a low-gain, high-efficiency, and linearity operating mode; a mode that focuses on improving gain flatness and backoff efficiency; and a switch-like mode with relatively small gain at low power but high gain at higher output levels.

[0093] Figure 11 Further illustrated is a gain boosting and stabilization circuitry 1180 coupled between the driver stage 1140 and the multi-mode cascode stage 1150. The gain boosting and stabilization circuitry 1180 can be configured to support broadband stable gain of the PA signal chain 1100, including by shaping the interstage response and reducing sensitivity to parasitic feedback effects along the interstage path, while maintaining a compact implementation suitable for integrated PA designs. In some embodiments, the gain boosting and stabilization circuitry 1180 can implement a reference... Figure 10 The differential form of the capacitor neutralization and stabilizing inductor technique is described to provide broadband gain enhancement and stability benefits in differential PA topologies.

[0094] The PA signal chain 1100 also includes a wideband output matching network 1160 coupled between the power node VDD and the RF output node RF_OUT. The wideband output matching network 1160 can be configured to transform the PA's optimal device load impedance to the system load impedance (e.g., approximately 50 ohms) over a selected operating bandwidth. In various implementations, the wideband output matching network 1160 can be implemented using one or more transformers, coupling lines, multimode balanced couplers, or other wideband impedance transformation structures. In some embodiments, the wideband output matching network 1160 may additionally include one or more coupling segments that provide a sample of the RF output power for monitoring purposes.

[0095] According to several embodiments, the automatic mode selection network 1152 is configured to select the operating mode of the multi-mode cascode stage 1150 based on the monitored signal level associated with the PA signal chain 1100. For example, the automatic mode selection network 1152 may use a coupling segment associated with a wideband output matching network 1160 to obtain output-related metrics, which couples out a portion of the RF output power. The coupled RF signal may be provided to an RF-DC converter (e.g., a power detector) that generates a DC signal representing the output level, including embodiments of the detected DC voltage varying with the square of the RF voltage. The automatic mode selection network 1152 may use analog circuitry, digital circuitry, or a combination thereof to process the DC signal and may responsively provide one or more control signals that adjust the bias of the cascode devices in the multi-mode cascode stage 1150 to select an appropriate operating mode for the current operating conditions. In this way, a specific intelligent PA automation chain can be implemented, in which the coupler samples the RF power, the RF-DC converter generates a level indication signal, and the control logic uses the signal to drive the mode selection control of the multi-mode cascode stage 1150.

[0096] By adapting the operating mode of the multi-mode cascode stage 1150 based on the monitored signal level, the PA signal chain 1100 can dynamically switch between operating conditions emphasizing linear amplification and those emphasizing power efficiency and output oscillation. This is achieved by maintaining wideband output matching through the wideband output matching network 1160 and maintaining stable wideband gain through the gain boosting and stabilization circuitry 1180. In summary, the automated mode selection network 1152 provides an intelligent control mechanism that dynamically (e.g., in real-time or near real-time) adjusts the operating mode of the multi-mode cascode stage 1150 to meet target performance requirements under varying signal conditions, while reusing a common multi-mode PA hardware platform.

[0097] Figure 12An exemplary graph is shown, illustrating how gain, efficiency, and frequency response vary in different operating modes of a multi-mode cascode PA. In the example shown, the four columns correspond to four example operating modes (modes 1 through 4). For each mode, the first row of the graph shows the relationship between power gain and output power, the second row shows the relationship between efficiency and output power, and the third row shows the relationship between power gain and frequency.

[0098] exist Figure 12 In the first row, the gain-output power graph shows exemplary gain envelopes labeled Gfmax and Gfmin. In Mode 1, this gain envelope provides relatively high gain at lower output power levels, but the gain is sharply compressed as the output power approaches saturation. The difference between Gfmax and Gfmin indicates that the gain varies relatively significantly with frequency at a given output level. In Mode 2, the exemplary gain curve can be lower than that of Mode 1 at low output power, but a higher effective gain can be maintained in the region from the 1dB compression point (P1dB) up to the saturation power Psat. Compared to Mode 1, P1dB can be shifted to be closer to Psat, which can improve the reflection of large-signal linearity. In Mode 3, the overall gain level can be further reduced, but the difference between Gfmax and Gfmin can be narrowed, indicating improved gain flatness across the entire frequency range. In mode 4, the gain characteristics can be similar to switching behavior, with relatively low gain at low output power and increasing gain as the output power increases to a higher power range, thus enabling the PA to effectively "turn on" under higher power conditions while maintaining low responsiveness at low power.

[0099] exist Figure 12 In the second row, the efficiency-output power graph shows an example efficiency curve that rises as output power increases from the backoff region towards Psat. In Mode 1, the efficiency curve increases gently relative to output power and remains relatively low at medium output levels, reflecting that the bias in Mode 1 is set for higher gain rather than peak efficiency. In Mode 2, efficiency can rise more significantly and higher efficiency can be achieved in the central region of interest (e.g., at the efficiency peak labeled ηcentre) while still maintaining acceptable gain. Mode 3 can further improve backoff efficiency, allowing efficiency to rise earlier with output power, while the PA operates at a lower total gain level, which is highly advantageous for applications operating in backoff mode for extended periods. In Mode 4, the efficiency curve can be shaped to keep efficiency low at very low output levels and to significantly increase efficiency once the PA enters the higher power region, consistent with the gain behavior of similar switches described above.

[0100] exist Figure 12 In the third row, the power gain-frequency plot shows example frequency response envelopes for different modes. In Mode 1, the example response may show relatively strong gain ripple in the expected frequency band, corresponding to gain variations across frequencies. In Mode 2, the response is relatively flatter, with reduced ripple while maintaining a suitable maximum gain. In Mode 3, the response can be even flatter, improving gain flatness across the entire frequency range at the cost of reduced peak gain. In Mode 4, the response can be shaped to focus on operation on a subset of frequency bands or to reallocate gain across frequency bands, such as to adapt to system-level constraints or optimize the efficiency of specific channels.

[0101] In general, Figure 12 This demonstrates that in a multi-mode cascode PA incorporating the gain boost, stability, and intelligent mode selection techniques of this disclosure, different operating modes can be designed to provide different combinations of gain levels, efficiency profiles, and gain flatness across the entire frequency range. (See references...) Figure 11 The described control architecture can be selected from these modes, or interpolated between them in an implementation with continuously adjustable bias, so that a single PA implementation can be adapted to meet different operating requirements and signal conditions with little or no change to the underlying hardware.

[0102] For purposes of illustration and description, the foregoing description of various embodiments of the claimed subject matter has been provided. It is not intended to be exhaustive or to limit the claimed subject matter to the precise forms of this disclosure. Many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described in order to best illustrate the principles of this disclosure and its practical application, thereby enabling those skilled in the art to understand the claimed subject matter, the various embodiments, and the various modifications suitable for the particular intended use.

[0103] While the detailed description depicts certain embodiments and the expected best mode, the technology can be implemented in a variety of ways, no matter how detailed the detailed description may appear. Embodiments can vary considerably in their implementation details while still being covered by the specification. Specific terms used in describing certain features or aspects of the various embodiments should not be construed as implying that the term is redefined herein as limited to any particular feature, characteristic, or aspect of the technology associated with that term. Generally, the terms used in the following claims should not be construed as limiting the technology to the specific embodiments disclosed in the specification, unless such terms are explicitly defined herein. Therefore, the actual scope of the technology includes not only the embodiments of this disclosure but also all equivalent ways of practicing or implementing those embodiments.

[0104] The language used in this specification has been chosen primarily for readability and instruction purposes. It may not have been chosen to define or limit the scope of the subject matter. Therefore, the scope of this technology is not defined by the specific embodiments, but by any claims made in the application based thereon. Thus, the disclosure of various embodiments is intended to illustrate, and not limit, the scope of the technology set forth in the appended claims. Furthermore, it should be noted that computer-aided design tools can be used to describe the various circuits disclosed herein and, based on their behavior, register transfers, logic components, transistors, layout geometry, and / or other characteristics, to express (or represent) them as data and / or instructions contained in various computer-readable media. Formats of files and other objects that can implement such circuit expressions include, but are not limited to: formats supporting behavioral-level languages ​​(such as C, Verilog, and VHDL); formats supporting register-level description languages ​​(such as RTL); formats supporting geometric description languages ​​(such as GDSII, GDSIII, GDSIV, CIF, MEBES); and any other suitable formats or languages. Computer-readable media in which such formatted data and / or instructions can be embodied include, but are not limited to, various forms of non-volatile storage media (e.g., optical, magnetic, or semiconductor storage media).

Claims

1. An amplifier circuit, comprising: The first transistor is configured to receive an input signal and generate an amplified signal; The second transistor is coupled to the first transistor in a common-source, common-gate configuration; as well as The bias control circuit is configured to bias the first transistor to operate in a first operating mode and the second transistor to operate in a second operating mode. Wherein, the first operating mode corresponds to the first conduction angle, and The second operating mode corresponds to the second conduction angle, which is smaller than the first conduction angle.

2. The amplifier circuit according to claim 1, wherein, The first conduction angle corresponds to the basic full-cycle conduction of the first transistor, and the second conduction angle corresponds to the non-full-cycle conduction of the second transistor.

3. The amplifier circuit according to claim 1, wherein, The bias control circuit is configured to maintain a substantially constant bias of the first transistor while biasing the second transistor in the second operating mode.

4. The amplifier circuit according to claim 1, wherein, The bias control circuit is configured to selectively operate the second transistor in a third operating mode, the third operating mode corresponding to a third conduction angle that is smaller than the second conduction angle.

5. The amplifier circuit according to claim 4, wherein, The third conduction angle corresponds to the basic full-cycle conduction of the second transistor.

6. The amplifier circuit according to claim 4, further comprising: The sensor circuit is configured to generate a control signal in response to a signal level associated with the amplifier circuit, wherein the bias control circuit is configured to select an appropriate operating mode based on the control signal.

7. The amplifier circuit according to claim 6, wherein, The bias control circuit is configured to select an appropriate operating mode for the second transistor based on whether the signal level meets threshold conditions associated with a 1dB compression point (P1dB) requirement and / or a third-order input intercept point (IIP3) requirement.

8. The amplifier circuit according to claim 6, wherein, The bias control circuit is configured to select between the second operating mode and the third operating mode based on the control signal.

9. The amplifier circuit according to claim 6, wherein, The sensor circuit is configured to sense the input power of the input signal.

10. The amplifier circuit according to claim 6, wherein, The sensor circuit is configured to sense the output power of the amplified signal.

11. The amplifier circuit according to claim 6, wherein, The sensor circuit is configured to sense both the input power of the input signal and the output power of the amplified signal.

12. The amplifier circuit according to claim 6, wherein, The bias control circuit includes a comparator configured to compare a control signal from the sensor circuit with a threshold and generate a mode selection signal accordingly.

13. The amplifier circuit according to claim 1, wherein, The bias control circuit is configured to enable the second transistor to operate in more than two operating modes.

14. The amplifier circuit according to claim 1, wherein, The bias control circuit is configured to continuously adjust the bias of the second transistor within a range of bias values.

15. The amplifier circuit according to claim 1, further comprising: An output matching network is coupled to the output node of the amplifier circuit, wherein the output matching network includes a transformer.

16. The amplifier circuit according to claim 15, wherein, The output matching network is configured to attenuate out-of-band frequency components relative to the in-band frequency range.

17. The amplifier circuit according to claim 1, wherein, The first transistor, the second transistor, and the bias control circuit are integrated on the same semiconductor die.

18. An amplifier circuit, comprising: A first input node and a second input node, wherein the first input node is configured to receive a first component of a differential input signal, and the second input node is configured to receive a second component of a differential input signal; A first transistor and a second transistor, the first transistor being coupled to the first input node and the second transistor being coupled to the second input node, the first transistor and the second transistor forming a differential input pair, the differential input pair being configured to generate a differential amplified signal at a pair of intermediate nodes; A third transistor and a fourth transistor, wherein the third transistor is coupled in series with the first transistor between a power node and a reference node, and the fourth transistor is coupled in series with the second transistor between the power node and the reference node, wherein the third transistor and the fourth transistor are coupled to the first transistor and the second transistor respectively in a common-source, common-gate configuration; as well as The bias control circuit is configured to bias the first transistor and the second transistor in a first operating mode, and to bias the third transistor and the fourth transistor in a second operating mode. Wherein, the first operating mode corresponds to the first conduction angle of the first transistor and the second transistor, and The second operating mode corresponds to the second conduction angle of the third transistor and the fourth transistor, and the second conduction angle is smaller than the first conduction angle.

19. The amplifier circuit according to claim 18, further comprising: A capacitor neutralization network is coupled between the differential nodes of the amplifier circuit to reduce the equivalent feedback capacitance associated with at least one of the differential input pairs or cascode transistors.

20. The amplifier circuit of claim 19, further comprising a control circuit configured to provide one or more control signals to the bias control circuit to adjust the bias applied to the third transistor and the fourth transistor based on a signal level associated with the amplifier circuit.

21. The amplifier circuit according to claim 20, wherein, The control circuit is configured to adjust the bias applied to the third transistor and the fourth transistor based on a signal derived from the differential input signal of the amplifier circuit and / or a signal derived from the differential output signal of the amplifier circuit.

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