Transceiver for back channel communication

Abstract

A transceiver is provided. The transceiver includes a voltage divider, a switch circuit, a voltage pull-up circuit, and a rise time circuit. The voltage divider couples an output line terminal to a receive terminal and reduces an input voltage of an input signal received by the output line terminal. The switch circuit provides an output signal to the output line terminal and is controlled by a transmit signal received at a transmit terminal. The voltage pull-up circuit is coupled to a supply voltage and the output line terminal and controls an output voltage of the output signal. The rise time circuit is coupled to the supply voltage, the transmit terminal, and the output line terminal and controls a rise time of the output signal. A network device can include a pair of transceivers to communicate with an adjacent network device in a point-to-point network configuration.

Description

Technical Field

[0001] This disclosure generally relates to a transceiver, and more specifically to a transceiver for facilitating serial reverse channel communication between network devices. Background Technology

[0002] Commercial environments (such as offices or schools) typically include a network of devices for monitoring the environment and controlling lighting systems or other systems within it. These devices are often coupled together via a parallel-configured Controller Area Network (CAN) bus. However, in this configuration, diagnosing network faults (such as lost terminals and / or faulty network devices) is difficult. U.S. Patent Publication No. 2019 / 0116480 discloses a low-power control and monitoring network with devices having a CPU in a minimum power consumption state, a CPU and transceiver for waking up the device, and wake-up circuitry for waking up the CPU of another device. Summary of the Invention

[0003] This disclosure generally relates to transceivers for facilitating serial reverse channel communication between network devices. Network devices (such as relay switches, lighting controllers, motion sensors, etc.) may already be connected in parallel via a Controller Area Network (CAN) bus. Each network device includes at least one transceiver for series connection to another device via a wired connection. The transceivers are bidirectional, enabling bidirectional point-to-point communication networks to diagnose network faults. Furthermore, the transceivers compensate for series resistance and wire capacitance up to one thousand feet. In point-to-point networks, most network devices will include two transceivers for series connection to other network devices.

[0004] The transceiver includes transmit terminals, receive terminals, and output terminals. Additionally, it includes a voltage divider, switching circuitry, pull-up voltage circuitry, and rise time circuitry. In transmit mode, the network device's microcontroller provides a transmit signal to the transmit terminals. The transmit signal can be a 3.3V high-level signal. The transmit signal is then provided to the switching circuitry. The switching circuitry includes a switching transistor with a base configured to receive the transmit signal. The switching circuitry provides an output signal to the output terminals for transmission to another network device. The output voltage and rise time of the output signal are controlled by the rise time circuitry and the pull-up voltage circuitry. The output signal can be a 24V high-level signal.

[0005] In receive mode, the output terminal receives an input signal from another network device. The input signal can be a 24-volt high-level signal. A voltage divider generates the received signal by reducing the input voltage of the input signal, making the received signal processable by the microcontroller. The received signal can also be a reduced 3.3-volt high-level signal. The receive terminal receives the received signal from the voltage divider and provides the input signal to an analog-to-digital converter (ADC). The ADC processes the received signal into a converted signal and provides the converted signal to the microcontroller for further processing.

[0006] Generally, in one aspect, a transceiver is provided. The transceiver includes a voltage divider configured to couple an output line terminal to a receiving terminal. The voltage divider reduces the input voltage of the input signal received by the output line terminal.

[0007] The transceiver also includes a switching circuit. The switching circuit is configured to provide an output signal to the output line terminals. The switching circuit is controlled by a transmit signal received at the transmit terminal.

[0008] The transceiver also includes a voltage pull-up circuit. The voltage pull-up circuit is coupled to the power supply voltage and the output line terminals. The voltage pull-up circuit is configured to control the output voltage of the output signal.

[0009] The transceiver also includes a rise time circuit. The rise time circuit is coupled to the power supply voltage, the transmit terminal, and the output line terminal. The rise time circuit is configured to control the rise time of the output signal.

[0010] As an example, a switching circuit includes a switching transistor.

[0011] As an example, a voltage pull-up circuit includes a pull-up resistor.

[0012] According to one example, the rise-time circuit includes a rise-time transistor. The base of the rise-time transistor is coupled to the emitter terminal via a rise-time capacitor and a first rise-time resistor. A second rise-time resistor couples the base of the rise-time transistor to the emitter of the rise-time transistor. The collector of the rise-time transistor is coupled to the output line terminal.

[0013] According to one example, the input signal received at the output line terminal is a 24-volt high-level signal.

[0014] As one example, the input signal is a 3.3-volt high-level signal after being reduced by the voltage divider.

[0015] According to one example, the transmitted signal is a 3.3-volt high-level signal.

[0016] According to one example, the output signal is a 24-volt high-level signal.

[0017] Generally speaking, in another aspect, a network device is provided. This network device includes a transceiver.

[0018] In one example, the microcontroller provides a transmit signal to the transmit terminal of the transceiver.

[0019] In one example, the input signal is provided to the microcontroller via an ADC.

[0020] According to one example, the output line terminal is coupled to a second network device via a first wired connection.

[0021] According to one example, the network device also includes a second transceiver that is communicatively coupled to the third network device via a second wired connection.

[0022] According to one example, the first wired connection is a Category 5 (CAT5) connection.

[0023] According to one example, the length of the first wired connection is less than or equal to one thousand feet.

[0024] It should be understood that all combinations of the foregoing concepts and the additional concepts discussed in more detail below (assuming these concepts are not contradictory) are considered part of the inventive subject matter disclosed herein. In particular, all combinations of the claimed subject matter appearing at the end of this disclosure are considered part of the inventive subject matter disclosed herein. It should also be understood that terms expressly used herein and that may also appear in any disclosure incorporated by reference should be given the meaning most consistent with the specific concepts disclosed herein.

[0025] In various implementations, the processor or controller may be associated with one or more storage media (generally referred to herein as "memory," such as volatile and non-volatile computer memories, including RAM, PROM, EPROM, EEPROM, floppy disk, compact disk, optical disk, magnetic tape, SSD, etc.). In some implementations, the storage media may be encoded with one or more programs that, when executed on one or more processors and / or controllers, perform at least some of the functions discussed herein. Various storage media may be fixed within the processor or controller or may be removable, such that one or more programs stored thereon can be loaded into the processor or controller to implement the various aspects discussed herein. The terms "program" or "computer program" are used herein in a general sense to refer to any type of computer code (e.g., software or microcode) that can be used to program one or more processors or controllers.

[0026] These and other aspects of the various embodiments will become apparent and will be explained with reference to the embodiments described below. Attached Figure Description

[0027] In the accompanying drawings, the same reference numerals typically refer to the same parts in different views. Furthermore, the drawings are not necessarily drawn to scale; instead, the emphasis is usually on illustrating the principles of various embodiments.

[0028] Figure 1 This is a schematic diagram of a communication system for multiple network devices, based on an example.

[0029] Figure 2A This is a schematic diagram of a communication system for multiple network devices, based on an example, where reverse channel data is transmitted from left to right.

[0030] Figure 2B This is a schematic diagram of a reverse channel communication system for multiple network devices, based on an example, where reverse channel data is transmitted from right to left.

[0031] Figure 3 It is a functional block diagram of network devices based on an example communication system.

[0032] Figure 4A This is a circuit diagram based on an example transceiver.

[0033] Figure 4B It is based on an example Figure 4A Another circuit diagram of the transceiver.

[0034] Figure 5 It is based on the voltage diagram of the output signal and the transmitted signal of an example.

[0035] Figure 6 This is another voltage diagram based on an example of the output signal and the transmitted signal.

[0036] Figure 7 It is based on the voltage diagram of the input and received signals of an example. Detailed Implementation

[0037] This disclosure generally relates to transceivers for facilitating serial reverse channel communication between network devices. Network devices (such as relay switches, lighting controllers, motion sensors, etc.) may be connected in parallel via a Controller Area Network (CAN) bus. Each network device includes at least one transceiver for series connection to another device via a wired connection. The transceivers are bidirectional, enabling bidirectional point-to-point communication networks to diagnose network faults. Furthermore, the transceivers compensate for series resistance and wire capacitance up to one thousand feet. In point-to-point networks, most network devices will include two transceivers for series connection to other network devices.

[0038] Now turn to the attached diagram. Figure 1This is a schematic diagram illustrating a communication system 1 comprising multiple network devices 10 according to various embodiments of the present disclosure. In some examples, the network devices 10 are installed in commercial buildings, such as office buildings or schools. Each network device 10 can be one of various different types of devices, such as relay switches, lighting controllers, motion sensors, etc. In some examples, the network devices 10 are integrated into a connected lighting system. In the connected lighting system, the lighting attributes of one or more luminaires can be controlled by a controller. The controller can control the luminaires based on information collected from various input sources, such as sensors or user interfaces. Furthermore, in some examples, the lighting attributes of the luminaires can be directly controlled by input sources.

[0039] exist Figure 1 In the example, network device 10 is connected in parallel via a Controller Area Network (CAN) bus 3. The CAN bus 3 is terminated at each end by terminals 5a and 5b coupled to ground. However, in this configuration, network faults are difficult to diagnose. These faults may include missing or damaged terminals 5a and 5b and / or faulty network device 10.

[0040] To provide information for diagnosing these network faults, a serial reverse channel network was employed, such as... Figure 1 As shown. In this reverse channel network, network devices 10 are connected in series via wired connections 20. These wired connections 20 are formed by a pair of transceivers 100 in each network device 10 (e.g., ...). Figure 3 (As shown in more detail below) to promote. For example... Figure 1 As shown, a first network device 10a is connected to a second network device 10b via a first wired connection 20a having a first length 16a; the second network device 10b is connected to a third network device 10c via a second wired connection 20b having a second length 16b; the third network device 10c is connected to a fourth network device 10d via a third wired connection 20c having a third length 16c; and so on. In total, all wired connections 20 can have a total length of up to one thousand feet, because the series resistance and wire capacitance of cables exceeding one hundred feet can increase the rise time and reduce the pulse width of the signal transmitted by transceiver 100 to an undesirable degree. In some non-limiting examples, the wired connection 20 is implemented as a Category 5 (CAT5) cable that inserts into the registration jack (RJ) 45 connector of network device 10. However, in other examples, the wired connection 20 can be implemented as any suitable type of cable coupled to network device 10 via any suitable type of connector. In some examples, the signal transmitted by the wired connection 20 is a 24-volt high-level signal.

[0041] Figure 2A An example of communication system 1 is shown. Figure 2AIn the example, the reverse channel data transmitted by network device 10 propagates from left to right. For example... Figure 2A As shown, a first network device 10a transmits signals to a second network device 10b via a first wired connection 20a. The second network device 10b transmits signals to a third network device 10c via a second wired connection 20b. The third network device 10c transmits signals to a fourth network device 10c via a second wired connection 20c, and so on. Therefore, in some examples, a failure of the second network device 10b can be partially detected by data received (or not received) by the third network device 10c.

[0042] Figure 2B It shows Figure 2A Variations. In Figure 2B In the example, the reverse channel data transmitted by network device 10 propagates from right to left. For example... Figure 2A As shown, the fourth network device 10d transmits signals to the third network device 10c via the third wired connection 20c. The third network device 10c transmits signals to the second network device 10b via the second wired connection 20b. The second network device 10b transmits signals to the first network device 10a via the first wired connection 20a, and so on. Therefore, in some examples, a failure of the second network device 10b can be detected in part by data received (or not received) by the first network device 10a.

[0043] Figure 3 A functional block diagram of a non-limiting example of a network device 10 according to various embodiments of the present disclosure is shown. Figure 3 As shown, network device 10 includes a microcontroller 12, two analog-to-digital converters (ADCs) 14a and 14b, and two transceivers 100a and 100b. In some examples, the two ADCs 14a and 14b may be integrated into a single component. In some non-limiting examples, one or both of the two ADCs 14a and 14b may be functional peripheral components integrated into the microcontroller 12. In other non-limiting examples, one or both of the two ADCs 14a and 14b may be separate components disposed outside the microcontroller 12. Similarly, aspects of the two transceivers 100a and 100b may also be integrated into one or more common components. Furthermore, in some examples, the functionality of the microcontroller 12 may be divided into multiple components. Each transceiver 100a and 100b is configured to be bidirectional. However, during operation, one of the transceivers 100a and 100b will act as a transmitter, while the other will act as a receiver. For example, the first transceiver 100a may act as a transmitter, and the second transceiver 100b may act as a receiver. Alternatively, the first transceiver 100a can be used as a receiver, while the second transceiver 100b can be used as a transmitter.

[0044] like Figure 3 As shown, in transmit mode, the first transceiver 100a receives a first transmit signal 120a from the microcontroller 12. In some examples, the first transmit signal 120a is a 3.3-volt high-level signal. The first transceiver 100a then transmits a first output signal 118a to another network device 10 via a first wired connection 20a. The first output signal 118a is generated based on the first transmit signal 120a. In some examples, the first output signal is a 24-volt high-level signal. In receive mode, the first transceiver 100a receives a first input signal 116a from another network device 10 via the first wired connection 20a. In some examples, the first input signal 116a is a 24-volt high-level signal. The first transceiver 100a then transmits a first receive signal 148a to a first ADC 14a. The first receive signal 148a is generated based on the first input signal 116a. In some examples, the first receive signal 148a is a 3.3-volt high-level signal. ADC 14a then generates a first converted signal 150a based on the first received signal 148a and transmits the first converted signal 150a to microcontroller 12. ADC 14a is used to set the ground of the signal provided to microcontroller 12 and may be particularly useful when the signal is received over a very long wired connection.

[0045] Similarly, in transmit mode, the second transceiver 100b receives a second transmit signal 120b from the microcontroller 12. In some examples, the second transmit signal 120b is a 3.3-volt high-level signal. The second transceiver 100b then transmits a second output signal 118b to another network device 10 via a second wired connection 20b. The second output signal 118b is generated based on the second transmit signal 120b. In some examples, the second output signal is a 24-volt high-level signal. In receive mode, the second transceiver 100b receives a second input signal 116b from another network device 10 via a second wired connection 20. In some examples, the second input signal 116b is a 24-volt high-level signal. The second transceiver 100b then transmits a second receive signal 148b to a second ADC 14b. The second receive signal 148b is generated based on the second input signal 116b. In some examples, the second receive signal 148b is a 3.3-volt high-level signal. The second ADC 14b then generates a second conversion signal 150b based on the second received signal 148b, and transmits the second conversion signal 150b to the microcontroller 12.

[0046] In some examples, a first output signal 118a transmitted by a first transceiver 100a may be at least partially based on a second input signal 116b received by a second transceiver 100b. Similarly, a second output signal 118b transmitted by a second transceiver 100b may be at least partially based on a first input signal 116a received by a first transceiver 100a. For example, output signals 118a and 118b may indicate the state (e.g., a fault) of the network device 10 that provides input signals 116a and 116b.

[0047] Figure 4A and 4B A circuit diagram of transceiver 100 is shown. Figure 4A The various sub-circuits of transceiver 100 are labeled, and Figure 4B The labels indicate numerous components, including sub-circuits. Generally, transceiver 100 is defined by output line terminal 102, receive terminal 104, and transmit terminal 106. Output line terminal 102 is coupled to wired connection 20 to connect transceiver 100 to another network device 10. (See also...) Figure 4A and 4B As shown, output terminal 102 is configured to receive input signal 116 and transmit output signal 118. Receive terminal 104 is configured to provide receive signal 148 to ADC 14. Transmit terminal 106 is configured to receive transmit signal 120 from microcontroller 12.

[0048] In addition, such as Figure 4A As shown, transceiver 100 can also be defined by a series of sub-circuits, including voltage divider 108, switching circuit 110, voltage pull-up circuit 112, and rise time circuit 114. Voltage divider 108 is used for the receiving aspect of the transceiver, while switching circuit 110, voltage pull-up circuit 112, and rise time circuit 114 are used for the transmitting aspect.

[0049] like Figure 4B As shown, voltage divider 108 includes a first voltage-dividing resistor 156 (R2) and a second voltage-dividing resistor 158 (R3). The first voltage-dividing resistor 156 is coupled between the output terminal 102 and the receive terminal 104. The second voltage-dividing resistor 158 is coupled between the receive terminal 104 and ground. Therefore, voltage divider 108 is arranged to reduce the input voltage 122 of input signal 116 to generate a receive signal 148 having a receive voltage 154 acceptable to ADC 14 and microcontroller 12. In some examples, input signal 116 is a 24-volt high-level signal, while receive signal 148 is a 3.3-volt high-level signal.

[0050] like Figure 4AAs shown, the switching circuit 110 is coupled to the transmitter terminal 120, the power supply voltage 124, and the output line terminal 102 (via diode 162 (D2)). In some examples, the power supply voltage is 24 volts. Figure 4B As shown, the switching circuit 114 includes a switching transistor 130 (Q2) and a switching resistor 160 (R6). Figure 4A In this example, the switching transistor 130 is implemented as a PNP bipolar junction transistor (BJT). Generally, the emitter terminal 106 provides an emit signal 120 to the base of the switching transistor 130. Therefore, the switching transistor 130 generates a digital output signal 118 that switches high when the emitter signal 120 is low and vice versa. In some examples, the emitter signal 120 is a 3.3-volt high-level signal, while the output signal 118 is a 24-volt high-level signal.

[0051] The output voltage 126 of output signal 124 is controlled by voltage pull-up circuit 112 and rise time circuit 114. For example... Figure 4B As shown, the voltage pull-up circuit 112 includes a pull-up resistor 132. The pull-up resistor 132 is coupled between the power supply voltage 124 and the output terminal 102. Therefore, the pull-up resistor 132 is configured to increase the output voltage 126 of the output signal 118 to a voltage level closer to the power supply voltage 124, in this case, 24 volts.

[0052] Similarly, Figure 4A As shown, the rise time circuit 114 is coupled to the transmit terminal 120, the power supply voltage 124, and the output line terminal 102. Generally, the rise time circuit 114 is configured to significantly reduce the rise time 128 of the output signal 118. Without the rise time circuit 114, the capacitance of the wired connection 20 between the network devices 10 would result in a long rise time from low voltage to high voltage. Figure 4BAs shown, the rise time circuit 114 includes a rise time transistor 134 (Q1), a rise time capacitor 142 (C1), a first rise time resistor 144 (R5), and a second rise time resistor 146 (R4). The base 136 of the rise time transistor 134 is coupled to the emitter terminal 120 via the rise time capacitor 142 and the first rise time resistor 144. The second rise time resistor 146 is coupled between the power supply voltage 124 and the base 136 of the rise time transistor 134. The emitter 138 of the rise time transistor 134 is coupled to the power supply voltage 124, while the collector 140 of the rise time transistor 134 is coupled to the output terminal 118. During the low-to-high transition of the switching circuit 110, the rise time transistor 134 is turned on, and as the rise time capacitor 142 charges, the output voltage 126 of the output signal 118 is pulled up. When the emitter signal 120 charges the rise time capacitor 142, the pull-up resistor 132 is bypassed. Once the rise time capacitor 142 is fully charged, the rise time transistor 134 is turned off, and the output voltage 126 of the output signal 118 remains pulled up towards the power supply voltage 124 by the pull-up resistor 132.

[0053] The advantages of rise time circuits are as follows: Figure 5 and Figure 6 As shown. Figure 5 This is a voltage diagram of the output signal 116 and the transmitted signal 120 without implementing the rise time circuit 114. (Example) Figure 5 As shown, the transmit voltage 152 of the transmit signal 120 ranges between 0 and 3.3 volts, while the output voltage 126 of the output signal 118 ranges between approximately 0.5 volts and 18 volts. When the transmit signal 120 switches low, the output signal 118 switches high, and vice versa. Notably, the rise time 128 of the output signal 118 significantly reduces the pulse width of the output signal 118. Figure 6 The output signal 116 and the transmit signal 120 are shown when the rise time circuit 114 is implemented, which greatly reduces the rise time.

[0054] Figure 7 This is a voltage diagram of input signal 116 and received signal 148. (For example...) Figure 7 As shown, the input voltage 122 of the input signal 122 ranges between 0 and 18 volts, while the receiving voltage 154 of the receiving signal 148 ranges between approximately 0.2 volts and 2.4 volts. When the transmitting signal 120 switches low, the output signal 118 switches high, and vice versa.

[0055] All definitions used herein should be understood as controls over dictionary definitions, definitions in references incorporated herein by reference, and / or the general meaning of the defined terms.

[0056] The indefinite articles “a” and “an” used herein in the specification and claims should be understood to mean “at least one” unless the opposite is explicitly stated.

[0057] The phrase “and / or” as used herein in the specification and claims should be understood to mean “any one or two” of the elements so combined, that is, elements that exist together in some cases and separately in others. Multiple elements listed with “and / or” should be interpreted in the same way, that is, “one or more” of the elements so combined. In addition to the elements specifically identified by the “and / or” clause, other elements may optionally exist, whether or not they are related to those specifically identified.

[0058] As used herein in the specification and claims, “or” should be understood to have the same meaning as “and / or” as defined above. For example, when separating items in a list, “or” or “and / or” should be interpreted as inclusive, i.e., including at least one, but also including multiple elements or more than one element in a list of elements, and optionally, additional unlisted items. Only terms that explicitly indicate the opposite, such as “only one” or “exactly one”, or when used in the claims, “consisting of…”, will refer to including multiple elements or exactly one element in a list of elements. In general, the term “or” as used herein should only be interpreted as an alternative to exclusivity when preceded by exclusive terms such as “any,” “one of,” “only one,” or “exactly one” (i.e., “one or the other, but not both”).

[0059] As used herein in the specification and claims, the phrase "at least one" in relation to a list of one or more elements should be understood to mean at least one element selected from any one or more elements in the list, but does not necessarily include at least one of every element specifically listed in the list, and does not exclude any combination of elements in the list. This definition also allows for the optional presence of elements other than those specifically identified in the list referred to by the phrase "at least one," regardless of their relation to those specifically identified elements.

[0060] It should also be understood that, unless the contrary is explicitly stated, in any method claimed herein that includes more than one step or action, the order of the steps or actions of the method is not necessarily limited to the order in which the steps or actions of the method are stated.

[0061] In the claims and the foregoing description, all transitional phrases such as “comprising,” “including,” “carrying,” “having,” “containing,” “involving,” “holding,” “constituting,” etc., should be understood as open-ended, meaning including but not limited to. Only the transitional phrases “constituting of” and “constituting substantially of” should be closed or semi-closed transitional phrases, respectively.

[0062] The examples of the subject described above can be implemented in any of a variety of ways. For example, some aspects can be implemented using hardware, software, or a combination thereof. When any aspect is implemented at least partially in software, the software code can execute on any suitable processor or set of processors, whether it is provided in a single device or computer or distributed across multiple devices / computers.

[0063] This disclosure can be implemented as a system, method, and / or a computer program product at any possible level of integration technical detail. The computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions thereon for causing a processor to execute aspects of this disclosure.

[0064] Computer-readable storage media can be tangible devices capable of retaining and storing instructions for use by an instruction execution device. Computer-readable storage media can be, for example, but not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital versatile disc (DVD), memory sticks, floppy disks, mechanical encoding devices (such as punched cards or raised structures in grooves on which instructions are recorded), and any suitable combination of the foregoing. As used herein, computer-readable storage media should not be construed as being itself a transient signal, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0065] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a corresponding computing / processing device, or downloaded via a network to an external computer or external storage device, such as the Internet, a local area network (LAN), a wide area network (WAN), and / or a wireless network. The network may include copper cables, optical fibers, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them for storage in a computer-readable storage medium within the corresponding computing / processing device.

[0066] Computer-readable program instructions used to perform the operations of this disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, integrated circuit configuration data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, and procedural programming languages ​​such as the "C" programming language or similar programming languages. The computer-readable program instructions may be executed entirely on a user's computer, partially on a user's computer, partially on a user's computer and partially on a remote computer as a standalone software package, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet provided by an Internet service provider). In some examples, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs) may execute computer-readable program instructions by personalizing the electronic circuitry with state information from the computer-readable program instructions in order to perform aspects of this disclosure.

[0067] This document describes aspects of the disclosure with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to examples of the disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0068] Computer-readable program instructions may be provided to a processor of a special-purpose computer or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / actions specified in one or more blocks of a flowchart and / or block diagram. These computer-readable program instructions may also be stored in a computer-readable storage medium that can instruct a computer, programmable data processing apparatus, and / or other devices to operate in a particular manner, such that the computer-readable storage medium storing the instructions comprises an article of manufacture including instructions for implementing aspects of the functions / actions specified in the flowchart and / or block diagram or blocks.

[0069] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer-implemented process, such that the instructions, which execute on the computer, other programmable apparatus or other device, perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0070] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various examples of this disclosure. In this regard, each box in a flowchart or block diagram may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing a specified logical function(s). In some alternative implementations, the functions marked in the boxes may occur in a non-linear order. For example, two boxes shown consecutively may actually be executed substantially simultaneously, or these boxes may sometimes be executed in reverse order, depending on the functions involved. It will also be noted that each box in the block diagrams and / or flowcharts, and combinations of boxes in the block diagrams and / or flowcharts, may be implemented by a system based on dedicated hardware that performs the specified function or action or executes a combination of dedicated hardware and computer instructions.

[0071] Other embodiments are within the scope of the following claims and other claims to which the applicant is entitled.

[0072] While various examples have been described and illustrated herein, those skilled in the art will readily conceive of various other means and / or structures for performing functions and / or obtaining results and / or one or more advantages described herein, and each of these variations and / or modifications is considered to be within the scope of the examples described herein. More generally, those skilled in the art will readily understand that all parameters, dimensions, materials, and configurations described herein are meant to be exemplary, and actual parameters, dimensions, materials, and / or configurations will depend on one or more specific applications using the teachings. Those skilled in the art will recognize, or be able to determine, by conventional experimentation alone, many equivalents of the specific examples described herein. Therefore, it should be understood that the foregoing examples are given by way of example only, and that the examples may be implemented in ways different from the specific descriptions and claims within the scope of the appended claims and their equivalents. The examples of this disclosure pertain to each individual feature, system, article, material, kit, and / or method described herein. Furthermore, any combination of two or more such features, systems, articles, materials, kits, and / or methods is included within the scope of this disclosure if such features, systems, articles, materials, kits, and / or methods are not contradictory.

Claims

1. A transceiver (100), comprising: A voltage divider (108) is configured to couple an output line terminal (102) to a receiving terminal (104), wherein the voltage divider (108) reduces the input voltage (122) of the input signal (116) received by the output line terminal (102). A switching circuit (110) is configured to provide an output signal (118) to an output line terminal (102), wherein the switching circuit (110) is controlled by a transmission signal (120) received at a transmission terminal (106); A voltage pull-up circuit (112) coupled to a power supply voltage (124) and an output line terminal (102) is provided, wherein the voltage pull-up circuit (112) is configured to control the output voltage (126) of an output signal (118); and Rise time circuit (114) coupled to power supply voltage (124), transmit terminal (106) and output line terminal (102), wherein rise time circuit (114) is configured to control the rise time (128) of output signal (118).

2. The transceiver (100) according to claim 1, wherein the switching circuit (110) includes a switching transistor (130).

3. The transceiver (100) according to claim 1, wherein the voltage pull-up circuit (112) includes a pull-up resistor (132).

4. The transceiver (100) of claim 1, wherein the rise time circuit (114) includes a rise time transistor (134), wherein the base (136) of the rise time transistor (134) is coupled to the emitter terminal (106) via a rise time capacitor (142) and a first rise time resistor (144), wherein a second rise time resistor (146) couples the base (136) of the rise time transistor (134) to the emitter (138) of the rise time transistor (134), and wherein the collector (140) of the rise time transistor (134) is coupled to the output line terminal (102).

5. The transceiver (100) according to claim 1, wherein the input signal (116) received at the output line terminal is a 24-volt high-level signal.

6. The transceiver (100) according to claim 1, wherein the input signal (116) is a 3.3-volt high-level signal after being reduced by the voltage divider.

7. The transceiver (100) according to claim 1, wherein the transmitted signal (120) is a 3.3-volt high-level signal.

8. The transceiver (100) according to claim 1, wherein the output signal (118) is a 24-volt high-level signal.

9. A network device (10), wherein the network device (10) includes the transceiver (100) according to claim 1.

10. The network device (10) according to claim 9, wherein the microcontroller (12) provides a transmit signal (120) to the transmit terminal (106) of the transceiver (100).

11. The network device (10) according to claim 9, wherein the input signal (116) is provided to the microcontroller (12) via an analog-to-digital converter (ADC) (14).

12. The network device (10) according to claim 11, wherein the output line terminal (102) is coupled to the second network device (10b) via a first wired connection (20).

13. The network device (10) according to claim 12 further includes a second transceiver (100b) communicatively coupled to the third network device (10c) via a second wired connection (20b).

14. The network device (10) according to claim 12, wherein the first wired connection (20) is a Category 5 (CAT5) connection.

15. The network device (10) of claim 12, wherein the length (16) of the first wired connection (20) is less than or equal to one thousand feet.

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