Physical layer register access

Abstract

An apparatus comprising: a physical layer device (PHY); a PHY management interface; and a multi-port Ethernet device coupled with the PHY via the PHY management interface. The multi-port Ethernet device can comprise: a processor; a set of registers accessible by the processor via an internal bus of the multi-port Ethernet device; a management interface controller to construct management frames at the PHY management interface; and a logic circuit to initiate copying of data from registers of the PHY via the management interface controller and store the copied PHY register data at the registers of the multi-port Ethernet device.

Description

Cross-references to related applications

[0001] This application is based on 35 USC 119(e) claims the benefit of U.S. Provisional Patent Application Serial No. 63 / 575,248, filed April 5, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] One or more examples generally relate to an apparatus including a physical layer device (PHY), a management data input / output bus, and an Ethernet switch. The Ethernet switch includes registers, a media-independent interface controller, and logic circuitry that facilitates reading data from the PHY's registers, and that copies data from the PHY's registers via the media-independent interface controller and stores the copied data in the registers. Background Technology

[0003] The controller can utilize the standard data interface between the physical layer device (PHY) and the media access control device (MAC) or Ethernet switch, and manage the PHY via a bus connection. Attached Figure Description

[0004] To facilitate the identification of any particular element or action in the discussion, the most important number in the figure labels refers to the figure number of the element when it was first introduced.

[0005] Figure 1 It is a block diagram depicting an apparatus, according to one or more examples, capable of autonomous register access at one or more Ethernet physical layer devices (PHYs).

[0006] Figure 2 It is a block diagram depicting an apparatus, according to one or more examples, capable of autonomous register access at one or more PHYs via an external register connected to an Ethernet switch (or a device including an Ethernet switch).

[0007] Figure 3 It is a block diagram depicting the eMIIM scanning functionality based on one or more examples.

[0008] Figure 4 It is a block diagram depicting the logical association between the PHY registers and the shadow registers via memory mapping, according to one or more examples.

[0009] Figure 5 It is a sequence diagram of communication protocols depicting the process of scheduling reads of multiple PHYs (in this particular example, PHY counters) involving a processor, an eMIIM controller, and one or more PHYs, according to one or more examples.

[0010] Figure 6 It is a communication protocol sequence diagram depicting a process 600 involving an event-driven read of one or more PHY registers, based on one or more examples, of a processor, an eMIIM controller, and one or more PHY registers.

[0011] Figure 7 It is a block diagram of a circuit that can be used in some examples to implement the various functions, operations, actions, processes or methods disclosed herein. Detailed Implementation

[0012] In the following detailed description, reference is made to the accompanying drawings, which form part of this disclosure, and specific examples of embodiments in which this disclosure may be practiced are shown by way of example. These embodiments have been described in sufficient detail to enable those skilled in the art to practice this disclosure. However, other embodiments may be utilized, and changes in structure, materials, and processes may be made without departing from the scope of this disclosure.

[0013] The illustrations presented herein are not intended to be actual views of any particular method, system, apparatus, device, or structure, but are merely idealized representations used to describe embodiments of this disclosure. The accompanying drawings are not necessarily drawn to scale. For the reader's convenience, similar structures or components in the drawings may retain the same or similar designations; however, similar designations do not imply that the structure or component must be identical in size, composition, configuration, or any other attribute.

[0014] The following description may include examples to assist those skilled in the art in practicing the embodiments disclosed herein. The use of the terms “exemplary,” “by example,” and “for example” indicates that the related descriptions are illustrative, and while the scope of this disclosure is intended to cover examples and legal equivalents, the use of such terms is not intended to limit the embodiments or the scope of this disclosure to the specified parts, steps, features, or functions, etc.

[0015] It should be readily understood that the components of the embodiments generally described herein and illustrated in the accompanying drawings can be arranged and designed in a variety of different configurations. Therefore, the following description of various embodiments is not intended to limit the scope of this disclosure, but merely to illustrate various embodiments. While various aspects of the embodiments may be presented in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated otherwise.

[0016] Furthermore, the specific embodiments shown and described are merely examples and should not be construed as the only way to implement this disclosure unless otherwise specified herein. Components, circuits, and functions may be shown in block diagram form so as not to obscure this disclosure with unnecessary detail.

[0017] Conversely, the specific implementations shown and described are merely exemplary and should not be construed as the only way to implement this disclosure unless otherwise specified herein. Additionally, the block definitions and logical partitioning between the blocks are examples of specific implementations. It will be apparent to those skilled in the art that this disclosure can be practiced with many other partitioning solutions. In most cases, details regarding timing considerations, etc., have been omitted, as such details are not necessary for obtaining a full understanding of this disclosure and are within the capabilities of those skilled in the art.

[0018] Those skilled in the art will understand that information and signals can be represented using any of a variety of different techniques and methods. For clarity of presentation and description, some figures may illustrate a signal as a single signal. It should be understood by those skilled in the art that a signal may represent a signal bus, wherein the bus may have multiple bit widths, and this disclosure can be implemented on any number of data signals, including a single data signal.

[0019] The various exemplary logic blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed using a general-purpose processor, a special-purpose processor, a digital signal processor (DSP), an integrated circuit (IC), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic components, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor (also referred to herein as a host processor or simply a host) may be a microprocessor, but in alternative embodiments, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration. When a general-purpose computer including a processor executes computational instructions (e.g., software code) related to embodiments of this disclosure, the general-purpose computer is considered a special-purpose computer.

[0020] The implementation scheme can be described based on a process depicted as a flowchart, schematic diagram, structural diagram, or block diagram. While a flowchart can describe operable actions as a continuous process, many of these actions can be performed in another sequence, in parallel, or substantially concurrently. Furthermore, the order of actions can be rearranged. A process can correspond to, but is not limited to, methods, threads, functions, procedures, subroutines, and subroutines. Moreover, the methods disclosed herein can be implemented in hardware, software, or both. If implemented in software, functions can be stored or transmitted as one or more instructions or code onto a computer-readable medium. Computer-readable media includes both computer storage media and communication media, which includes any medium that facilitates the transfer of a computer program from one location to another.

[0021] Any reference to elements in this document using names such as “first”, “second”, etc., does not limit the number or order of those elements unless such limitation is explicitly stated. Rather, these names may be used herein as a convenient way to distinguish between two or more elements or instances of elements. Thus, referring to a first element and a second element does not imply that only two elements can be used there, or that the first element must somehow precede the second element. Furthermore, unless otherwise stated, a group of elements may include one or more elements.

[0022] As used herein, the term “substantially” means, and includes, the degree to which a given parameter, attribute, or condition is satisfied with a small degree of variance, such as, for example, within acceptable manufacturing tolerances, as would be understood by one of ordinary skill in the art. By way of example, depending on the particular parameter, attribute, or condition that is substantially satisfied, the parameter, attribute, or condition may be satisfied at least 90%, at least 95%, or even at least 99%.

[0023] As used herein, any relational terms (such as "above", "below", "on", "under", "upper", "lower", etc., but not limited thereto) are used for clarity and convenience in understanding this disclosure and the accompanying drawings, and such relational terms do not imply or depend on any particular preference, orientation or order unless the context clearly indicates otherwise.

[0024] In this description, the term "coupled" and its derivatives may be used to indicate that two elements cooperate or interact with each other. When an element is described as "coupled" to another element, then the element may be in direct physical or electrical contact, or an intermediary element or layer may be present. In contrast, when an element is described as "directly coupled" to another element, then no intermediary element or layer is present. The term "connection" may be used interchangeably with the term "coupled" in this specification and has the same meaning unless otherwise expressly indicated or the context will otherwise indicate to a person skilled in the art.

[0025] As used herein, the terms “assert,” “deassert,” and their derivatives used with respect to the pin and the component are referred to respectively to assert or deassert the signal associated with the pin (e.g., a signal specifically assigned to or to the pin, but not limited thereto).

[0026] Typically, Ethernet physical layer devices (PHYs) can be accessed by a processor via an IEEE 802.3 MDIO (Management Data Input / Output) / MDC (Management Data Clock) interface (e.g., control, reading, but not limited to this), where the processor issues synchronous commands (e.g., IEEE 802.3 multipoint MDIO / MDC Rd / Wr (read / write) @ 2.5MHz to 25MHz, where 2.5MHz is the highest common MDIO speed, but not limited to this). Synchronous reads of the PHY's registers via the MDIO / MDC interface (“synchronous register reads”) are typically slow and prevent (e.g., for a certain number of processing cycles, but not limited to this) the processor from performing other tasks while the read operation is in progress. A “synchronous read” is a data transfer method in which the processor must wait for the read to complete before it can continue performing other tasks.

[0027] Some register reads are time-critical, such as retrieving timestamps from transmitted IEEE 1588 PTP (Precision Time Protocol) frames. Other register reads used for diagnostic data (e.g., MACsec counters, functional safety, but not limited to) involve regular transmissions of large amounts of data. The internal main processor of an Ethernet switch operates at clock rates ranging from hundreds of MHz to several GHz. In synchronous register reads, the processor waits while performing a read on a slow MDIO / MDC interface and thus pauses during that period. When performed at a 2.5 MHz MDC clock speed, a 100-bit timestamp read takes 200+ microseconds (ps). In switches with many external PHYs and high PTP transmission rates, this blocking time places a heavy load on the processor, to the point where only a few ports can be served.

[0028] In one or more examples, the scanning function is integrated into the enhanced MIIM (eMIIM) controller. The scanning function offloads MDIO read operations from the processor by autonomously reading data (including diagnostic counters and timestamps) and caching it in a shadow register, as described below. This reduces the effective processor blocking time to below 700 nanoseconds.

[0029] The scanning function is configured by the processor. During configuration, the processor can program the scanning function with predetermined parameters, including one or more of the following: register selection, read scheduling, or event triggers. In some examples, the processor can configure the scanning function with one or more sets of predetermined parameters. Multiple different sets of parameters can be associated with different data types (e.g., operational data, diagnostic data, timestamps, regularly occurring data, or other types of data, but not limited to these).

[0030] A counter is a dedicated register that counts the number of applicable events, and this count can be used to track statistics. Within the Ethernet PHY, counters (PHY counters) are used to track statistics such as the number of packets sent or received, error events, or other metrics, and more generally, in conjunction with logging operational or diagnostic information related to link performance and activity. These counters help higher-level system functions (e.g., CPU or network management software) monitor network health, diagnose problems, and optimize overall performance.

[0031] Once configured by the processor, the scan function automatically (without processor intervention or supervision) performs scheduled and event-triggered MDIO read operations. By schedule (e.g., fixed scheduling, but not limited to) or in response to a specific event, the scan function accesses the PHY registers (via the MDIO / MDC interface) and passes the retrieved data (e.g., register data, but not limited to) to the corresponding shadow register. The scan function then interrupts the processor only when the data is ready to be retrieved, thus avoiding the need for continuous processor intervention. This autonomous operation significantly reduces processor blocking time and allows for concurrent execution of other processor tasks. This results in reduced blocking time at the processor compared to the synchronous reads discussed above.

[0032] In this manner, the autonomous scanning function can hide the MDIO read time or the MDIO read time of specific types of data from the processor.

[0033] The Media Independent Interface (MII) is a standard interface used to connect an Ethernet PHY to an Ethernet MAC layer. MII allows data to be sent and received between the PHY and the MAC layer of an Ethernet device. MII is designed to be media independent, meaning it can be used with a variety of physical media (e.g., copper, fiber optic, twisted-pair, coaxial, but not limited to) without requiring changes to the MAC hardware.

[0034] Figure 1 This is a block diagram depicting an apparatus 100 capable of autonomous register access at one or more Ethernet physical layer devices (PHYs) according to one or more examples.

[0035] Apparatus 100 includes a multi-port Ethernet device 114 and one or more PHY devices communicatively coupled via an MDIO / MDC 122 interface, referred to herein as a first PHY 102 and an Nth PHY 108. The multi-port Ethernet device 114 is a device that includes or is capable of supporting more than one Ethernet port, such as, but not limited to, an Ethernet switch, an Ethernet hub, a router with multiple Ethernet ports, a network interface card with multiple Ethernet ports, or a network device with multiple Ethernet ports. The multi-port Ethernet device 114 includes a processor 118, one to N interrupt handlers 130, and an enhanced MII management (eMIIM) controller 128 including a MIIM controller 116 and scanning functionality 124. The processor 118 communicates with these internal controller blocks of the eMIIM controller 128 via an internal bus 120. Interrupt signals (INT 1, INT 2) from the respective PHY in one or more PHYs may optionally be received by one to N interrupt handlers 130 of the multi-port Ethernet device 114. The multiport Ethernet device 114 may include one to N interrupt handlers 130 for implementing event-triggered readings, as discussed herein.

[0036] Device 100 can autonomously collect PHY register data and deliver it to processor 118 without incurring the conventional overhead (e.g., blocking time, but not limited thereto) associated with synchronous reads via the MDIO / MDC interface.

[0037] exist Figure 1 The first to Nth PHYs, denoted as PHY 102 and PHY 108, are physical layer devices that convert digital signals into appropriate analog waveforms (and vice versa) for transmission and reception over a physical medium (e.g., twisted pair or other cables, but not limited to). The corresponding PHYs include registers 104 / 110 and MDIO-manageable devices (MMDs) 106 / 112. Registers 104 / 110 can be used to store information such as link status, error counters, timestamps (for time-sensitive protocols such as IEEE 1588, but not limited to), and other PHY-specific data, but not limited to. The MMD implements the MDIO management interface portion defined by IEEE 802.3 for MDIO / MDC122. The MMD decodes MDIO commands (e.g., commands for read / write transactions, but not limited to), retrieves the corresponding register data from registers 104 / 110, and responds to a control entity, in this case, the eMIIM controller 128.

[0038] The MDIO / MDC 122 is a management interface defined by IEEE 802.3 for reading from and writing to PHY registers. MDC is the clock line, and MDIO is the data line. Read and write operations are serialized; each bit is clocked into or out of the PHY via MDIO, synchronized with the MDC clock. The MDIO / MDC 122 interface supports multiple PHYs, each with a unique address, enabling centralized control from a single controller (in this case, the eMIIM controller 128).

[0039] The Enhanced Media Independent Interface (MII) Management Controller 128 (eMIIM Controller 128) is a management interface controller. The eMIIM Controller 128 implements the management portion of the MII interface, which manages PHY register access operations (e.g., read, write, but not limited to) via MDIO / MDC 122. The eMIIM Controller 128 enhances the standard MIIM controller (here, the standard MIIM controller is MIIM Controller 116) with additional logic (specifically, scan function 124).

[0040] The MIIM controller 116 of the eMIIM controller 128 is a management interface controller that implements standard MII management operations as defined by 802.3, including but not limited to MDIO register reads or writes. The MIIM controller 116 generates bit-level signaling on the MDIO lines of the MDIO / MDC 122 to construct MDIO management frames for standard MII management operations (i.e., having a management frame structure as defined in clause 22.2.4 of 802.3), such as reading or writing the contents of configuration or status registers used by higher-level management functions, but not limited to this. The MIIM controller 116 constructs the MDIO management frame format and orchestrates their transmission at the clock rate of the MDC clock of the MDIO / MDC 122.

[0041] For example, when the MIIM controller 116 initiates an MDIO register read or write, it generates an MDIO management frame (sometimes referred to as an "MDIO transaction" or "MDIO command"). Specifically, the MIIM controller 116 transmits the command portion of the frame, which includes a preamble, frame start, opcode (an indication of the type of MDIO transaction, e.g., read or write, but not limited to), PHY address, and register address. The MDIO management frame may also optionally include other specific data fields depending on specific operating conditions. After transmitting this command portion, there is a turnaround period (as a non-limiting example, the duration measured in bit time or bit bits), during which the MIIM controller 116 releases control of the MDIO lines of MDIO / MDC 122. During the turnaround period and subsequent bits, the PHY's MMD (e.g., MMD 106 or MMD 112, but not limited to) decodes the command, accesses the specified register and register data, and drives the MDIO lines to transfer the register data to the MIIM controller 116.

[0042] In one or more examples, the MIIM controller 116 may construct and send MDIO management frames, including but not limited to those for MDIO register reads and writes, in response to a request or a command from higher-level logic such as scan function 124 or processor 118. By using such higher-level commands, the MIIM controller 116 may initiate MDIO register reads or MDIO register writes under the higher-level control of processor 118 or scan function 124.

[0043] Scan function 124 is logic circuitry integrated with eMIIM controller 128 (e.g., implemented in hardware, hardware, or both), and it serves as logic for autonomously managing PHY register access via MIIM controller 116 and MDIO / MDC 122, as discussed herein.

[0044] In one or more examples, once configured (e.g., programmed, but not limited to) by processor 118, scan function 124 can autonomously initiate the copying of register data from the corresponding PHY registers among one to N PHYs to register 126. More specifically, scan function 124 can issue a command to read data from a PHY register (“PHY register read”). More specifically, scan function 124 can issue a command in response to this. MIIM controller 116 initiates the MDIO register read. In one or more examples, scan function 124 can initiate the copying of register data at predetermined intervals (e.g., based on an internal timer or 1PPS reference, but not limited to) in response to the detection of a specific event or interrupt (e.g., a timestamp ready signal, but not limited to) or both. After receiving PHY register data from MIIM controller 116, scan function 124 stores the data in register 126 or a buffer (referred to herein as a “shadow register”) accessible by processor 118 via internal bus 120. In the case of scheduled reads, scan function 124 can initiate the copying at set (e.g., preset, but not limited to) time intervals. In the event of a triggered copy, scan function 124 may initiate a copy of the PHY register data associated with the trigger in response to a predetermined trigger.

[0045] Register 126 of scan function 124 stores a copy (“copied PHY register data”) of register data retrieved from one to N PHYs for the corresponding PHY (e.g., but not limited to, registers 104 and 110). In one or more examples, the copied register data at the corresponding PHY may include some or all of the register data at the corresponding PHY register. As a non-limiting example, the copied PHY register data may include timestamp data or status report data. In one or more examples, the shadow register data stored at register 126 may be updated in response to an event, according to a schedule, or both.

[0046] In one or more examples, the trigger for the scan function 124 to copy data from the PHY's registers in response can be an assertion of an interrupt (INT) associated with the PHY (in this particular example, INT 1 of the first PHY 102 or INT N of the Nth PHY 108). In one or more examples, the corresponding INT of the PHY can be coupled to the multiport Ethernet device 114, the eMIIM controller 128, or the scan function 124. One to N interrupt handlers 130 at the multiport Ethernet device 114 can be pre-associated with the corresponding PHY among one to N PHYs to identify which PHY should have its registers read.

[0047] Scheduled reads aligned with timing reference

[0048] In one or more examples, scan function 124 can be configured to initiate the copying of register data based on a predetermined scheduling and timing reference, such as, but not limited to, a 1PPS (one pulse per second) signal. A 1PPS signal is a highly accurate timing signal that generates one pulse per second. It is important to note that the use of a 1PPS signal in this specification is merely a non-limiting example to illustrate a highly accurate timing reference. It is explicitly contemplated that the timing reference can be derived from a variety of sources, including but not limited to external GPS receivers, atomic clocks, or via protocols such as PTP, gPTP, or NTP, or even from an internal system time scale. Furthermore, the timing reference does not need to generate one pulse per second; any periodic or non-periodic timing signal exhibiting any pulse frequency, whether regular or irregular, can be used within reasonable limits. This disclosure is not limited to a 1PPS signal or any particular periodic or pulse frequency.

[0049] In the case of scheduled reads, scan function 124 is programmed with a desired read interval (e.g., every microsecond, or a fraction or multiple thereof, but not limited to) and PHY information (e.g., the address of the register to be copied, but not limited to). At each pulse of the timing reference, scan function 124 commands MIIM controller 116 to perform an MDIO read of the selected PHY register (such as a counter, diagnostic information, or other status data). The resulting data is passed to eMIIM controller 128 and scan function 124 via MDIO / MDC 122 and made available to processor 118 via internal bus 120. As a non-limiting example, data can be made available to processor 118 by storing it in register 126, which processor 118 can access via internal bus 120. Because scan function 124 autonomously manages the timing and read operations, processor 118 is not blocked during these scheduled reads, thereby reducing overhead while ensuring periodic updates (e.g., for statistical collection or diagnostic monitoring).

[0050] Reads triggered by events via interrupt handlers

[0051] In addition to scheduled reads or as an alternative, device 100 supports an event-driven mechanism that utilizes one to N interrupt handlers 130 within the multi-port Ethernet device 114. Each PHY (e.g., the first PHY 102 or the Nth PHY 108) can assert a dedicated interrupt signal (INT 1…INTN) to indicate the occurrence of a time-critical event, such as the availability of a newly captured timestamp. The one to N interrupt handlers 130 receive the corresponding interrupt from the PHY, identify the source PHY, and forward an interrupt notification 132 to the scan function 124. The interrupt notification 132 identifies the type of interrupt and the source PHY. In response, the scan function 124 commands the MIIM controller 116 to perform an MDIO read of the relevant PHY registers to retrieve event-specific data (e.g., timestamps). The retrieved PHY register data is stored in register 126, which can trigger a notification to the processor 118 (e.g., an interrupt, but not limited to) indicating that the PHY register data is available for reading from register 126.

[0052] As a non-limiting example, the autonomous register reads discussed herein can be used to read various register data for a variety of purposes, and this disclosure is not limited to any particular one. For example, autonomous register reads can be used to read operational or diagnostic data about the state of a PHY or Ethernet link for timestamp retrieval (2-step, IEEE 802.IAS) or both.

[0053] In some cases (as a non-limiting example, in high-density systems using many PHYs, but not limited thereto), providing a dedicated interrupt line for each PHY can significantly increase hardware complexity and consume valuable pin resources.

[0054] In one or more examples, interrupt signals are aggregated into one or more external registers and connected to a single connection (or in some cases, the number of connections is less than the number of interrupts), and a serial controller (e.g., a single GPIO connection and a serial GPIO controller, but not limited to this) reads their status. This design reduces the number of interrupt pins required, thereby simplifying the interconnection between the PHY and the switch, and streamlining the initiation of target MDIO transactions based on detected events.

[0055] Figure 2 It is a block diagram depicting an apparatus 200, according to one or more examples, capable of autonomous register access at one or more PHYs via an external register connected to an Ethernet switch (or a device or system including an Ethernet switch).

[0056] Figure 2 Depicting based on Figure 1The illustrated example demonstrates the establishment of the concept and further introduces one to N external registers 226 and a serial controller 236. Unless otherwise stated, Figure 2 It has such Figure 1 The component names in the text can be understood as components related to... Figure 1 The corresponding part in it works in a basically similar way.

[0057] exist Figure 2 In the illustrated example, the status of the corresponding PHY's INT is transmitted to the Ethernet switch 216 via an external register and a connection to the serial controller. The scan function 228 reads the status information of the interrupts for various PHYs and copies the PHY registers as indicated by the status information.

[0058] exist Figure 2 In this configuration, the first PHY 202 and the Nth PHY 208 each include registers and MMD, as shown below. Figure 1 The PHY is the same as in the example. However, in this example, the INT 1...INT N signals are routed to one to N external registers 226, instead of being directly input to a dedicated interrupt handler within the Ethernet switch 216. External registers 226 aggregate or latch these interrupt signals from multiple PHYs, and the serial controller 236 communicates them via a serial interface (e.g., SPI or I / O). 2 (C, but not limited to) periodically reads or polls these external registers 226, the serial controller being part of or communicatively coupled to the eMIIM controller 232. When an indication in the external registers 226 indicates that the PHY has asserted an interrupt, the scan function 228 is notified via the INT vector 238, and the scan function may, in response, initiate an MDIO read of the relevant PHY registers.

[0059] This design allows device 200 to handle event-based triggering with minimal pin usage and eliminates the need for a dedicated interrupt input on each PHY on the Ethernet switch. Therefore, external register 226 acts as a centralized repository for interrupt status information, while serial controller 236 ensures that scan function 228 can quickly detect and respond to new events. Once scan function 228 retrieves data (e.g., timestamps or diagnostic counters) via MIIM controller 218, it stores the data in a local shadow register (register 230) and optionally notifies processor 220 via internal bus 222. Thus, similar to... Figure 1 The device 200 achieves scheduling and event-driven data collection with reduced CPU blocking time, but with increased flexibility through interrupt aggregation based on external registers.

[0060] Figure 3This is a block diagram depicting an eMIIM scan function 300 according to one or more examples. The scan function is suitable for use within an enhanced MII management controller that autonomously performs register reads, and is a non-limiting example of scan functions 124 and 228.

[0061] The illustrated arrangement can be operated in a scheduled, event-driven, or combined manner, depending on the specific operational context. Although the following description refers to reading, those skilled in the art will understand that write operations can be similarly implemented, subject to the requirements of a given design.

[0062] The eMIIM scanning function 300 includes an MDIO command generator 306, a shadow register 308, a notification generator 334, an event detector 304, and a configuration register 326.

[0063] Configuration register 326 stores parameters (collectively referred to as configuration data 302) that define how and when the scan function initiates MDIO transactions. These parameters may include the address of the PHY register to be accessed, the timing interval, or the event triggering criterion. In one or more examples, the Ethernet switch processor writes configuration data 302 into configuration register 326 to program the eMIIM scan function 300. The stored configuration data 302 can then be used by event detector 304 and MDIO command generator 306, and optionally by other blocks as command configuration data 328 or trigger configuration data 318, as discussed below.

[0064] Event detector 304 monitors external signals (such as external signals collectively denoted as event 316) to determine whether an MDIO access operation should be initiated. These signals may include pulses from a timing reference used for scheduling reads (e.g., from a 1PPS source, but not limited to this), interrupt lines or interrupt notifications indicating interrupts to one or more PHY devices, or other system-level triggers.

[0065] Event detector 304 uses trigger configuration data 318 received from configuration register 326 to interpret and filter incoming events 316. Upon detecting a valid trigger condition (e.g., a rising / falling edge of a timing pulse, an interrupt assertion, or another specified event, but not limited to these), event detector 304 issues an MDIO command trigger 314 to MDIO command generator 306. Depending on the configuration parameters of eMIIM timing scan function 300, this mechanism supports scan-only, event-driven operation only, or a mixture of both.

[0066] The MDIO command generator 306 generates commands based on the trigger and configuration data it receives for the MIIM controller to initiate MDIO access operations, and more specifically, generates low-level MDIO read or write commands to one or more PHYs by the MUM controller.

[0067] The MDIO command generator 306 retrieves command configuration data 328 from the configuration register 326. This command configuration data specifies which PHY registers to access and how to format the MDIO transaction. The MDIO command generator 306 outputs command 312 to the standard MIIM controller block, which initiates the transfer of PHY register data from the PHY to the shadow register 308.

[0068] Shadow register 308 receives and stores PHY register data 310 passed from the PHY. This local storage allows the Ethernet switch's processor to retrieve updated data at high speed, thereby avoiding duplicate or blocking MDIO operations.

[0069] In response to instruction 338, notification generator 334 signals to the processor (or another controller or host logic) via notification 336 that PHY register data is available at shadow register 308.

[0070] Figure 4 This is a block diagram depicting the logical association between PHY registers and shadow registers via memory mapping 400 according to one or more examples. In this specific example, the address of one or more PHY registers (PHY register address 406) is associated with the address of one or more shadow registers (shadow register address 404). The shadow registers, the set of PHY addresses, or both can be associated with a specific PHY via memory mapping 400, and the scan function 124 can determine which PHYs are associated with copied register data at the shadow registers.

[0071] Figure 4 The dashed line or arrow 402 in the diagram represents the logical association between a specific PHY register address and its corresponding shadow register. The processor can use the same or similar address references that it would use for direct PHY access to read from these shadow registers at high speed. However, because the shadow registers reside on the internal bus or in local memory, the processor avoids the long wait times typically associated with MDIO transactions.

[0072] Figure 5 It is a communication protocol sequence diagram depicting a process 500 for scheduled reading of multiple PHYs (in this particular example, PHY counters) involving processor 502, eMIIM controller 504 and one or more PHYs 506, according to one or more examples.

[0073] At operation 508, at predefined scheduled intervals, the eMIIM controller 504 initiates an operation to read register data (in this particular non-limiting example, a counter value) from one or more PHYs 506. Because each register in one or more PHYs 506 is accessed via a relatively slow MDIO bus, the read operation at operation 510 may take tens or hundreds of microseconds. During this time interval, the processor 502 remains unblocked, allowing it to perform other tasks. Once the eMIIM controller 504 receives PHY register data from one or more PHYs 506, it writes the retrieved PHY register data to a local shadow register at operation 512 and notifies the processor 502 at operation 514 that PHY register data is available in the shadow register. At operation 516, the processor 502 then reads from these shadow registers. Because these shadow registers reside on the high-speed internal bus coupling processor 502 and eMIIM controller 504, processor 502 can retrieve updated data in several orders of magnitude less time than the interval between read operations, as shown in reference numeral 516. At operation 518, data is made available to processor 502, thus completing the scheduled read cycle. Offloading slow MDIO transactions to eMIIM controller 504 reduces blocking time while ensuring that processor 502 can quickly access updated PHY counters once the read operation is complete.

[0074] Figure 6 It is a communication protocol sequence diagram depicting a process 600 involving an event-driven read of one or more PHY registers of a processor 602, an eMIIM controller 604, and one or more PHY registers 606, according to one or more examples.

[0075] exist Figure 6In the depicted event-driven register read procedure 600, processor 602, eMIIM controller 604, and PHY interact to retrieve PHY registers in response to an event (here, an interrupt signal). At operation 608, new or updated data is in one or more registers 606 of the PHY (“one or more PHY registers 606”). At operation 610, the PHY asserts an interrupt (INT) line to indicate that new or updated data, such as a timestamp or diagnostic counter value, is available in its register. At operation 612, eMIIM controller 604 issues an MDIO read command to the PHY to initiate a data transfer, which may take approximately twenty microseconds for each 32-bit register at the standard MDIO clock rate. At operation 614, the PHY sends the requested PHY register data in response to the MDIO read command. At operation 616, eMIIM controller 604 receives the PHY register data from the PHY and writes the received PHY register data to one or more shadow registers. In operation 616, eMIIM controller 604… At operation 618, the eMIIM controller 604 notifies the processor 602 that PHY register data is available in the shadow register. At operation 620, the processor 602 performs a high-speed read of the shadow register (via the high-speed internal bus) to retrieve the PHY register data. At operation 622, the newly acquired data becomes available for further processing or system-level tasks.

[0076] By limiting slower MDIO transactions to the eMIIM controller 604, the processor 602 remains unblocked until the data has been fully retrieved, thereby reducing latency and improving efficiency in time-sensitive applications.

[0077] Those skilled in the art will understand that the functional elements (e.g., functions, operations, actions, processes, or methods) of the examples disclosed herein can be implemented in any suitable hardware, software, firmware, or a combination thereof. Figure 7 Non-limiting examples of specific implementations of the functional elements disclosed herein are illustrated. In some examples, some or all portions of the functional elements disclosed herein may be executed by hardware capable of performing the functional elements.

[0078] Figure 7This is a block diagram of circuitry 700 that, in some examples, can be used to implement the various functions, operations, actions, processes, or methods disclosed herein. Circuitry 700 includes one or more processors 702 (sometimes referred to herein as "processor 702") operatively coupled to one or more data storage devices 704 (sometimes referred to herein as "storage device 704"). Storage device 704 includes machine-executable code 706 stored thereon, and processor 702 includes logic circuitry 708. Machine-executable code 706 includes information describing functional elements that can be implemented (e.g., executed) by logic circuitry 708. Logic circuitry 708 is adapted to implement (e.g., execute) the functional elements described by machine-executable code 706. When executing the functional elements described by machine-executable code 706, circuitry 700 should be considered as dedicated hardware for executing the functional elements disclosed herein. In one or more examples, processor 702 may execute the functional elements described by machine-executable code 706 sequentially, concurrently (e.g., on one or more different hardware platforms), or in one or more parallel process flows.

[0079] When implemented by the logic circuitry 708 of the processor 702, the machine-executable code 706 adapts the processor 702 to perform the operations of the examples disclosed herein. In a non-limiting manner, the machine-executable code 706 can adapt the processor 702 to perform some or all of one or more of the following operations: process 500 or process 600.

[0080] Similarly, as a non-limiting example, machine-executable code 706 may adapt processor 702 to perform some or all of the features, functions, or operations disclosed herein for one or more of device 100, device 200, eMUM scan function 300, or memory mapping 400. More specifically, Figure 1 The first PHY 102, register 104, MMD 106, the Nth PHY 108, register 110, MMD 112, MDIO / MDC 122, multi-port Ethernet device 114, eMIIM controller 128, MIIM controller 116, scan function 124, register 126, internal bus 120, processor 118, one to N interrupt handlers 130 or a source of timing reference IPPS; or Figure 2 The first PHY 202, register 204, MMD 206, the Nth PHY 208, register 210, MMD 212, external register 226, MDIO / MDC 224, Ethernet switch 216, eMIIM controller 232, MIIM controller 218, scan function 228, register 230, internal bus 222, processor 220, serial controller 236 or timing reference IPPS source.

[0081] Processor 702 may include a general-purpose processor, special-purpose processor, central processing unit (CPU), microcontroller, programmable logic controller (PLC), digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic unit, discrete hardware unit, other programmable device, or any combination thereof, designed to perform the functions disclosed herein. A general-purpose computer is considered a special-purpose computer at least when it includes one or more processors 702 (including the general-purpose processor) executing functional elements corresponding to machine-executable code 706 (e.g., software code, firmware code, configuration data, hardware description, but not limited thereto) associated with the examples of this disclosure. It should be noted that the general-purpose processor (also referred to herein as a host processor or simply host) may be a microprocessor, but in alternatives, the general-purpose processor of processor 702 may include any conventional processor, controller, microcontroller, or state machine. The FPGA or other PLD of processor 702 can be configured (e.g., programmed, but not limited to) using configuration data to perform the functions disclosed herein, or additionally or alternatively, can be configured or reconfigured (e.g., programmable or reprogrammable, but not limited to) using configuration data to perform the functions disclosed herein. Processor 702 can also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0082] In one or more examples, storage device 704 includes volatile data storage devices (e.g., random access memory (RAM), static RAM (SRAM), but not limited thereto) and non-volatile data storage devices (e.g., flash memory, hard disk drive, solid-state drive, erasable programmable read-only memory (EPROM), but not limited thereto). In some examples, processor 702 and storage device 704 may be implemented as a single device (e.g., semiconductor device product, system-on-a-chip (SoC), but not limited thereto). In some examples, processor 702 and storage device 704 may be implemented as separate devices.

[0083] In one or more examples, machine-executable code 706 may include computer-readable instructions (e.g., software code, firmware code). As a non-limiting example, the computer-readable instructions may be stored in storage device 704, directly accessed by processor 702, and executed by processor 702 using at least logic circuitry 708. Also by a non-limiting example, the computer-readable instructions may be stored on storage device 704, passed to a memory device (not shown) for execution, and executed by processor 702 using at least logic circuitry 708. Processor 702 or its logic circuitry 708 may be coupled to or include such memory device (e.g., configuring memory cells, but not limited thereto). Thus, in some examples, logic circuitry 708 includes electrically configurable logic circuitry 708.

[0084] In one or more examples, machine-executable code 706 may describe hardware (e.g., circuitry) to be implemented in logic circuitry 708 to perform functional elements. This hardware may be described at any of a range of abstraction levels, from low-level transistor layout to high-level description languages. At high-level abstractions, hardware description languages ​​(HDLs), such as the IEEE standard hardware description language (HDL), may be used. By way of non-limiting examples, Verilog, SystemVerilog, or VLSI hardware description language (VHDL) may be used.

[0085] HDL descriptions can be transformed into descriptions at any of many other levels of abstraction as needed. As a non-limiting example, a high-level description can be transformed into a logic-level description such as Register Pass Language (RTL), Gate-level (GL) description, Placement-level description, or Mask-level description. As a non-limiting example, micro-operations to be performed by the hardware logic circuitry of logic circuitry 708 (e.g., gates, flip-flops, registers, but not limited thereto) can be described in RTL, then transformed into a GL description using a synthesis tool, and the GL description can be transformed into a placement-level description using placement and routing tools, which corresponds to the physical layout of an integrated circuit of programmable logic devices, discrete gate or transistor logic components, discrete hardware components, or combinations thereof. Therefore, in some examples, machine-executable code 706 may include HDL, RTL, GL descriptions, Mask-level descriptions, other hardware descriptions, or any combination thereof.

[0086] In an example where machine-executable code 706 includes a hardware description (at any level of abstraction), the system (not shown, but including storage device 704) implements the hardware description described by machine-executable code 706. As a non-limiting example, processor 702 may include a programmable logic device (e.g., an FPGA or PLC, but not limited thereto), and logic circuitry 708 may be electrically controlled (e.g., via configuration data, but not limited thereto) to implement circuitry corresponding to the hardware description into logic circuitry 708. Similarly, by a non-limiting example, logic circuitry 708 may include hardwired logic components manufactured by a manufacturing system (not shown, but including storage device 704) according to the hardware description of machine-executable code 706.

[0087] Regardless of whether the machine-executable code 706 includes computer-readable instructions or a hardware description, the logic circuit 708 is adapted to execute the functional elements described by the machine-executable code 706 when the functional elements of the machine-executable code 706 are implemented. It should be noted that although the hardware description may not directly describe the functional elements, it indirectly describes the functional elements that the hardware elements described by the hardware description can execute.

[0088] As used in this disclosure, the terms "module" or "component" can refer to a specific hardware implementation that performs actions of a module or component and / or software object or software routine that can be stored on and / or executed by general-purpose hardware (e.g., computer-readable media, processing devices, but not limited thereto) of a computing system. In some examples, the different components, modules, engines, and services described in this disclosure may be implemented as objects or processes (e.g., as separate threads) that execute on a computing system. While some of the systems and methods described in this disclosure are generally described as being implemented in software (stored on and / or executed by general-purpose hardware), specific hardware implementations or combinations of software and specific hardware implementations are also possible and conceivable.

[0089] As used in this disclosure, the term "combination" referring to multiple elements can include a combination of all elements or any one of various different sub-combinations of certain elements. For example, the phrase "A, B, C, D or combinations thereof" can refer to any one of A, B, C, or D; a combination of each of A, B, C, and D; and any sub-combination of A, B, C, or D, such as A, B, and C; A, B, and D; A, C, and D; B, C, and D; A and B; A and C; A and D; B and C; B and D; or C and D.

[0090] The terminology used in this disclosure, and particularly in the appended claims (e.g., in the body of the appended claims, but not limited thereto), is generally intended to be “open-ended” terms (e.g., the term “comprising” should be interpreted as “including but not limited to”, and the term “having” should be interpreted as “at least having, but not limited to”). As used herein, the term “each” means “some or all”. As used herein, the term “each and every” means “all”.

[0091] Additionally, if the introduced claim statements are intended to have a specific number, such intent will be explicitly stated in the claims, and without such a statement, such intent does not exist. For example, as an aid to understanding, the appended claims may contain the use of the introductory phrases “at least one” and “one or more” to introduce claim statements. However, the use of such phrases should not be construed as implying that a claim statement introduced by the indefinite article “a” or “an” limits any particular claim containing such an introduced claim statement to an example containing only one such statement, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an” (e.g., “a” and / or “an” can be interpreted as referring to “at least one” or “one or more”, but is not limited thereto); the same applies to the use of definite articles to introduce claim statements.

[0092] Furthermore, even when a specific number of the introduced claim statements are explicitly stated, those skilled in the art will recognize that such statements should be interpreted as meaning at least the number stated (e.g., the unmodified statement "two statements" means, in the absence of other modifying elements, at least two statements, or two or more statements, but not limited thereto). Additionally, in instances where conventions such as "at least one of A, B, and C, but not limited thereto" or "one or more of A, B, and C, but not limited thereto" are used, such constructions are generally intended to include, but are not limited to, a single A, a single B, a single C, A and B together, A and C together, B and C together, or A, B, and C together.

[0093] Furthermore, any separate word or phrase presenting two or more alternative terms in the specification, claims, or drawings should be understood to contemplate the possibility of including one term, any one term, or both terms. For example, the phrase "A or B" should be understood to include the possibility of including "A" or "B" or "A and B".

[0094] Additional non-limiting embodiments include:

[0095] Example 1: An apparatus comprising: a physical layer device (PHY); a PHY management interface supporting sequential transactions; and a multiport Ethernet device coupled to the PHY via the PHY management interface, the multiport Ethernet device comprising: a processor; a set of registers accessible by the processor via the internal bus of the multiport Ethernet device; a management interface controller configured to construct management frames at the PHY management interface; and logic circuitry configured to initiate data copying from the PHY registers via the management interface controller and store the copied PHY register data in the register set of the multiport Ethernet device.

[0096] Example 2: The apparatus according to Example 1, wherein the logic circuitry is configured to initiate data copying from the registers of the PHY without intervention or supervision of the processor of the multi-port Ethernet device.

[0097] Example 3: The apparatus according to any one of Examples 1 and 2, wherein copying data from the register of the PHY is a non-blocking, asynchronous copy relative to the operation of the processor.

[0098] Example 4: The apparatus according to any one of Examples 1 to 3, wherein the logic circuit is used to initiate data copying in response to a predetermined trigger.

[0099] Example 5: The apparatus according to any one of Examples 1 to 4, wherein the predetermined trigger is an interruption from the PHY.

[0100] Example 6: The apparatus according to any one of Examples 1 to 5, wherein the logic circuitry is used to initiate data copying in response to an event-driven trigger.

[0101] Example 7: The apparatus according to any one of Examples 1 to 6, wherein the predetermined trigger occurs at regular intervals indicated by a timing reference signal.

[0102] Example 8: The apparatus according to any one of Examples 1 to 7, wherein the timing reference signal comprises a pulse per second (1PPS) signal received from an external timing source.

[0103] Example 9: An apparatus according to any one of Examples 1 to 8, wherein the multi-port Ethernet device is coupled to an interrupt of the PHY, and the logic circuitry is configured to initiate data copying from the PHY in at least part of response to an assertion of the interrupt of the PHY.

[0104] Example 10: An apparatus according to any one of Examples 1 to 9, the apparatus comprising: one or more registers coupled to a single input of the multiport Ethernet device, the one or more registers being coupled to receive and store interrupts of one or more PHYs of the apparatus; wherein the serial controller of the multiport Ethernet device identifies a corresponding PHY associated with a drive interrupt in response to a drive interrupt at the connection and provides interrupt information to the logic circuitry, the interrupt information including the identified PHY and the state of the drive interrupt.

[0105] Example 11: A method comprising: initiating a read of a register of a PHY coupled to a multiport Ethernet device in response at least in part to a command generated without intervention or supervision by a processor of the multiport Ethernet device, the read being initiated via a PHY management interface supporting sequential transactions; and storing the register data of the PHY in a set of registers of the multiport Ethernet device, the register data being passed to the multiport Ethernet device via the read via the PHY management interface, the registers being accessible by the processor of the multiport Ethernet device.

[0106] Example 12: The method according to Example 11, the method includes generating the command in at least part of response to a predetermined trigger.

[0107] Example 13: The method according to any one of Examples 11 and 12, the method comprising generating the command in at least part of response to an event-driven trigger.

[0108] Example 14: The method according to any one of Examples 11 to 13, wherein the predetermined trigger is an interruption from the PHY.

[0109] Example 15: The method according to any one of Examples 11 to 14, the method comprising generating the command in at least part of response to a predetermined scheduling and timing reference signal.

[0110] Example 16: The method according to any one of Examples 11 to 15, wherein the timing reference signal comprises a pulse per second (1PPS) signal received from an external timing source.

[0111] Example 17: The method according to any one of Examples 11 to 16, the method comprising: detecting a driver interrupt at the connection of the multi-port Ethernet device; identifying the PHY as associated with the driver interrupt; and generating the command, and in response to the command, at least in part in response to the identified PHY, initiating an MDIO read.

[0112] While this disclosure has been described with respect to certain exemplary embodiments, those skilled in the art will recognize and understand that the invention is not limited thereto. Rather, many additions, deletions, and modifications may be made to the exemplary and described embodiments without departing from the scope of the invention as claimed below and its legal equivalents. Furthermore, features from one embodiment may be combined with features from another embodiment while still being covered within the scope of the invention as contemplated by the inventors.

Claims

1. An apparatus, the apparatus comprising: Physical layer device (PHY), the PHY includes: A PHY management interface, which supports sequential transactions; and A multi-port Ethernet device, wherein the multi-port Ethernet device is coupled to the PHY via the PHY management interface, the multi-port Ethernet device comprising: processor; A set of registers that can be accessed by the processor via the internal bus of the multiport Ethernet device; Management interface controller, the management interface controller being configured to construct management frames at the PHY management interface; and A logic circuit is configured to initiate the copying of data from the registers of the PHY via the management interface controller, and store the copied PHY register data in the register group of the multiport Ethernet device.

2. The apparatus of claim 1, wherein the logic circuitry is configured to initiate data copying from the registers of the PHY without intervention or supervision by the processor of the multiport Ethernet device.

3. The apparatus of claim 1, wherein copying data from the register of the PHY is a non-blocking, asynchronous copy relative to the operation of the processor.

4. The apparatus of claim 1, wherein the logic circuitry is configured to initiate data copying in response to a predetermined trigger.

5. The apparatus of claim 4, wherein the predetermined trigger is an interrupt from the PHY.

6. The apparatus of claim 1, wherein the logic circuitry is configured to initiate data copying in response to an event-driven trigger.

7. The apparatus of claim 4, wherein the predetermined trigger occurs at regular intervals as indicated by the timing reference signal.

8. The apparatus of claim 6, wherein the timing reference signal comprises a pulse-per-second (1PPS) signal received from an external timing source.

9. The apparatus of claim 1, wherein the multi-port Ethernet device is coupled to an interrupt of the PHY, and the logic circuitry is configured to initiate data copying from the PHY in at least part of response to an assertion of the interrupt of the PHY.

10. The apparatus of claim 1, wherein the apparatus comprises: One or more registers coupled to a single input of the multiport Ethernet device, the one or more registers being coupled to receive and store interrupts from one or more PHYs of the device; The serial controller of the multi-port Ethernet device responds to a drive interrupt at the connection to identify the corresponding PHY associated with the drive interrupt and provides interrupt information to the logic circuit, the interrupt information including the identified PHY and the status of the drive interrupt.

11. A method, the method comprising: At least in part, in response to a command generated without intervention or supervision by the processor of the multiport Ethernet device, a read of the registers of the PHY coupled to the multiport Ethernet device is initiated, the read being initiated via a PHY management interface that supports sequential transactions; as well as The PHY register data is stored in a set of registers of the multiport Ethernet device. The register data is transferred to the multiport Ethernet device via a read from the PHY management interface. The registers can be accessed by the processor of the multiport Ethernet device.

12. The method of claim 11, wherein the method includes generating the command in at least a partial response to a predetermined trigger.

13. The method of claim 11, wherein the method includes generating the command in at least a portion of response to an event-driven trigger.

14. The method of claim 12, wherein the predetermined trigger is an interrupt from the PHY.

15. The method of claim 11, wherein the method includes generating the command in at least a partial response to a predetermined scheduling and timing reference signal.

16. The method of claim 15, wherein the timing reference signal comprises a pulse-per-second (1PPS) signal received from an external timing source.

17. The method of claim 11, wherein the method comprises: Detect a driver interrupt at the connection point of the multi-port Ethernet device; The PHY is identified as being associated with the drive interrupt; as well as The command is generated, and in response to the command, at least in part, the identified PHY is used to initiate an MDIO read.

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