High speed reconfiguration of radio frequency units in a system on a chip

Abstract

The present disclosure provides various techniques for distributing radio frequency (RF) configuration information across scalable multi-channel and multi-SoC systems using high-speed serial command streams. A master device encodes RF control words into framed command streams that are serialized and transmitted over a SerDes-style interface. Each destination system-on-a-chip (SoC) includes a mixed-signal receiver, a digital controller, and a configuration memory organized into pending and active states, and optionally has a load signal for updating each-channel RF signal cells in a synchronized manner. An integrated repeater circuit can re-drive the same serial bit stream toward downstream SoCs, with each device selectively responding based on an embedded device identifier. These arrangements can reduce wiring complexity, increase command bandwidth, and support large RF arrays without external fan-out buffers.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 766,985, filed March 5, 2025, entitled “High-Speed ​​Generic Master IO for Multi-Channel RF in Wireless Communication Systems,” the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure generally relates to analog circuit design, and more specifically to the control of radio frequency (RF) components in integrated circuits and wireless communication systems. Background Technology

[0004] Radio frequency (RF) systems and their applications have become an indispensable part of modern society, including, for example, sixth-generation (6G) telecommunications networks and beyond, Wi-Fi systems, satellite and non-terrestrial networks (NTN), sensor-interconnected communication (ISAC), vehicle-to-everything (V2X) systems, Internet of Things (IoT) applications, industrial and private networks, defense and aerospace systems, and medical and wearable devices.

[0005] These RF systems typically rely on complex RF front-ends and multi-channel RF signal processing architectures to support high data rates, wide bandwidth, beamforming, and other advanced capabilities. RF subsystems can include multiple RF signal elements, such as multiple transmit chains, multiple receive chains, multiple phase shifter paths, multiple gain control stages, or other per-channel RF signal processing blocks. For example, phased arrays and other multi-channel architectures can include a large number of RF signal elements, each configured on an element-by-element basis to set phase, gain, frequency state, or other operating parameters. These parameters are frequently reconfigured over time, such as during calibration, beam switching, channel changes, power control, interference mitigation, or other operational scenarios.

[0006] In conventional systems, relatively low-speed sideband interfaces are often used to perform configuration and control of RF signal units. For example, the controller may use a Serial Peripheral Interface (SPI), General Purpose Input / Output (GPIO) pins, or another serial control bus to write configuration values ​​to registers or memory locations on the RF integrated circuit. In such approaches, configuration is transmitted as a series of bus transactions, each including a command or opcode and one or more address and data fields. When the system includes multiple RF channels, conventional controllers may need to perform a large number of serial transactions to update phase, gain, or other parameters across RF channels, which can increase the time required to complete a full configuration update.

[0007] Furthermore, conventional methods may present challenges in supporting configuration updates intended for synchronous application across multiple RF signaling units. For example, when writing and applying configuration values ​​on a transaction-by-transaction basis, different RF signaling units may receive and apply configuration values ​​at different times, potentially introducing timing skew on the RF channel. Additionally, as the complexity of RF systems increases, control plane routing and interface management for distributing configuration information can add to the overall implementation complexity. Therefore, scaling conventional RF control architectures to a large number of RF signaling units may present challenges in terms of update latency, synchronization, and implementation complexity.

[0008] Therefore, there is still a need for technologies that enable scalable, efficient, and robust reconfiguration of RF signal units in modern multichannel RF systems. Attached Figure Description

[0009] In the accompanying drawings, one or more embodiments of the present disclosure are shown by way of example and not limitation, wherein the same reference numerals denote similar elements. These drawings are not necessarily drawn to scale.

[0010] Figure 1 An example radio frequency (RF) communication environment in which this embodiment can be implemented is shown.

[0011] Figure 2 An example phased array system is shown, in which the controller configures phase shifters coupled to the antenna elements to form equal-phase wavefronts.

[0012] Figure 3 An example functional block diagram is shown in which a master device provides control signaling to a target system-on-chip (SoC) that implements one or more of the technologies disclosed herein.

[0013] Figure 4 It shows Figure 3 An example SoC architecture with some implementation details in an embodiment of the SoC.

[0014] Figure 5 It shows what can be used as Figure 4An example of a channel-addressable static random access memory (SRAM) structure as part of a digital control circuit.

[0015] Figure 6 It shows what can be used as with Figure 5 An example register structure that is part of a two-level latch arrangement associated with an SRAM structure.

[0016] Figure 7 An example signaling setup is shown, in which the master device sends data and clock signals along with chip select signals to the destination SoC.

[0017] Figure 8 An example signaling setup is shown, in which the destination SoC uses a data enable signal to send data signals.

[0018] Figure 9 An example functional diagram is shown, illustrating a receiver configured to capture an incoming command stream and a repeater configured to output the command stream to one or more repeater ports, the repeater having a separate enable control for switching its function.

[0019] Figure 10 An example system arrangement is shown, in which a master device provides a command stream to a SoC, and the SoC distributes the command stream to multiple downstream SoCs, with each repeater port driving one downstream SoC.

[0020] Figure 11 Another example system arrangement is shown, in which the master device provides a command stream to the SoC, and the SoC distributes the command stream to multiple downstream SoCs through one or more intermediate SoCs, with each repeater port driving multiple downstream SoCs.

[0021] Figure 12 An example method is shown in which a device receives a command stream, determines whether a device identifier in the command stream matches an identifier associated with the device, and selectively controls an RF signal unit or forwards RF configuration information to a downstream device.

[0022] Figure 13 An example method is shown in which a device transmits data in response to a readback request from a master device.

[0023] Figure 14 An example method is shown that is executed by the master device to encode RF configuration information and send it in a command stream. Detailed Implementation

[0024] Modern wireless communication systems increasingly rely on highly integrated System-on-Chip (SoC) solutions, which combine digital processing circuitry, mixed-signal blocks, and multiple radio frequency (RF) signal units. For example, SoCs in phased array transceivers, massive MIMO base stations, or satellite communication terminals can integrate numerous transmit and receive paths, each with independently controllable phase, gain, and other configuration states. As system requirements evolve towards wider bandwidth, more antennas, and more dynamic beam and link management, there is an increasing need to update these RF configuration states more frequently and across more RF signal units. This places increasingly higher demands on how to transmit and apply configuration information within the SoC and across multiple integrated circuits.

[0025] As mentioned above, conventional control architectures for RF systems typically rely on relatively low-speed sideband interfaces, such as Serial Peripheral Interface (SPI) links or General Purpose Input / Output (GPIO) pins, to configure an increasing number of RF signal units. With the increasing number of channels and configuration points, the controller may need to issue numerous discrete bus transactions to update phase, gain, and other operating parameters on the channels. This transaction-by-transaction model can lead to longer update times, make coordinating configuration changes across multiple channels or devices more difficult, and potentially increase the complexity of the control plane as the system scales in size and functionality.

[0026] Therefore, this section introduces techniques for transmitting configuration information for RF signaling units in the form of a high-speed serial command stream that is parsed and applied on-chip. In various embodiments, the master device can encode a device identifier and RF configuration information into a field data structure defined in the command stream, and the destination SoC can extract the device identifier and configuration information from the command stream. The destination SoC can determine whether the device identifier matches the SoC, and when a match is detected, it can use the RF configuration information to control multiple RF signaling units. Furthermore, the destination SoC can support burst configuration updates, phased pending and valid configuration states, and conditionally forwarding at least a portion of the command stream to downstream devices in a cascaded arrangement.

[0027] In summary, embodiments of this disclosure enable faster, more scalable, and more flexible reconfiguration of RF signal elements in complex RF systems. By using structured command streams carrying device identification information and RF configuration fields, the disclosed techniques reduce reliance on large numbers of low-speed sideband transactions, facilitate the coordination of configuration updates across multiple channels or devices, and simplify the routing of control signals in systems comprising multiple integrated circuits.

[0028] Furthermore, the disclosed techniques provide a unified framework compatible with different physical signaling arrangements and system topologies. For example, a given implementation can use a clock data interface with a chip select signal or a data interface with a data enable indication, while still relying on the same command stream field structure and on-chip parsing behavior. Similarly, system designers can choose between a fan-out configuration where each repeater port drives a single downstream device and a configuration where repeater ports feed multiple downstream devices, without changing the basic command format or device identifier-based routing behavior. This flexibility facilitates the reuse of digital and analog design resources across product families, allows for easy migration to higher channel numbers or different array geometries, and supports the deployment of RF systems in a wide range of application environments.

[0029] Numerous specific details are set forth below to provide a thorough understanding of the currently disclosed techniques. In other embodiments, the techniques described herein may be practiced without these specific details. In other instances, well-known features such as particular manufacturing techniques have not been described in detail to avoid unnecessarily obscuring this disclosure. References to “embodiment,” “one embodiment,” etc., in this specification mean that a particular feature, structure, material, or property described is included in at least one embodiment of this disclosure. Therefore, the appearance of these phrases in this specification does not necessarily refer to the same embodiment. Furthermore, such references are not necessarily mutually exclusive. Moreover, particular features, structures, materials, or properties may be combined in any suitable manner in one or more embodiments. And it should be understood that the various embodiments shown in the accompanying drawings are merely illustrative representations and are not necessarily drawn to scale.

[0030] Certain details concerning the structures or processes typically associated with integrated circuit design, including the physical layout of typical passive components (e.g., inductors, capacitors, resistors, filters, and related sub-components), may not be set forth in the following description, as including such well-known details could obscure important aspects of the disclosed technology. Furthermore, while the following disclosure illustrates several embodiments of different aspects of this disclosure, several other embodiments may have different configurations or different components than those described in this section. Therefore, the presented technology may have other embodiments with or without the several elements described below.

[0031] For the purposes of this discussion, the terms “coupled” and “connected” and their derivatives may be used to describe structural relationships between components. It should be understood that these terms are not intended to be synonyms for each other. Rather, in certain embodiments, “connected” may be used to indicate that two or more elements are in direct contact with each other. Unless otherwise stated in the context, the term “coupled” may be used to indicate that two or more elements are in direct or indirect contact with each other (with other intermediate elements between them), or that two or more elements cooperate or interact with each other (e.g., as in a causal relationship), or both. Notwithstanding the foregoing, and unless otherwise stated or explicitly stated in the context, references to “series connection” or “parallel connection” of components refer to their functional electrical relationship, not to the requirement of uninterrupted physical conductors.

[0032] For the purposes of this discussion, an "upstream" device refers to a device that is located earlier in the daisy chain command distribution path than one or more "downstream" devices, where "upstream" and "downstream" describe relative positions in the chain, rather than any specific upload or download operation.

[0033] Figure 1 An example radio frequency (RF) communication environment 100 in which this embodiment can be implemented is shown. The RF communication environment 100 includes a user terminal 110, a low Earth orbit (LEO) communication satellite 120, a gateway or ground station 130, and a network such as the Internet 160. In the illustrated example, the user terminal 110 represents one or more terminals that can wirelessly communicate with the LEO communication satellite 120 via a first RF link 140. For example, the user terminal 110 may be a fixed or mobile terminal that includes an electronically controllable antenna array or other multi-channel RF front-end capable of forming and controlling a communication beam toward the LEO communication satellite 120.

[0034] The RF communication environment 100 also illustrates LEO communication satellite 120 communicating with gateway or ground station 130 via a second RF link 150. LEO communication satellite 120 can provide bendable or regenerative payloads that relay services between user terminal 110 and gateway or ground station 130. Gateway or ground station 130 may include one or more high-gain antenna structures coupled to RF transceiver equipment and to routing or switching equipment providing connectivity to Internet 160 or another core network. In various embodiments, gateway or ground station 130 may serve multiple LEO communication satellites 120 and multiple user terminals 110.

[0035] In many embodiments, one or more of the user terminal 110, LEO communication satellite 120, and gateway or ground station 130 may include a system-on-a-chip (SoC) device that integrates digital processing circuitry, mixed-signal circuitry, and multiple RF signal units for implementing RF links 140 and 150. For example, the SoC within the user terminal 110 may include multiple RF signal units supporting beamforming, beam tracking, or polarization control for RF link 140, while the SoC within the gateway or ground station 130 may include RF signal units supporting a high-throughput feeder link for RF link 150. In such embodiments, the techniques disclosed herein can be used to configure and reconfigure the RF operating parameters of the RF signal units within the SoC, thereby supporting dynamic link management, beam steering, and other RF control operations in the RF communication environment 100. Although for ease of explanation, Figure 1 The LEO satellite communication scenario is shown, but RF communication environment 100 is just an example, and the techniques disclosed herein can also be applied to other terrestrial or non-terrestrial RF systems.

[0036] As previously noted in this disclosure, environments of the type illustrated in RF communication environment 100 are experiencing a growing need for faster and more scalable reconfiguration of RF signal elements. For example, LEO satellite systems may involve rapidly moving satellites, frequent handovers between satellites, and time-varying propagation conditions, potentially requiring frequent adjustments to beam orientation, beam shape, and transmit and receive power at user terminal 110 and gateway or ground station 130. With increasing antenna array size and support for multiple simultaneous beams, a single user terminal 110 or gateway or ground station 130 can include dozens or hundreds of RF signal elements whose phase, gain, and other operating parameters are updated on fine time scales. Furthermore, LEO satellites at altitudes of approximately 500 to 1,200 kilometers can traverse the visible sky of a given user terminal within minutes, which could correspond to a change of several degrees per second in the apparent position of the satellite as seen from user terminal 110 or gateway or ground station 130.

[0037] Therefore, conventional control methods that rely on a large number of slow configuration transactions may become increasingly inadequate in such cases, prompting the use of the techniques disclosed herein to deliver and apply configuration information to RF signaling units in a more efficient and coordinated manner.

[0038] Figure 2An example phased array system 200 is shown, in which a controller configures phase shifters coupled to antenna elements to form equiphase wavefronts. The phased array system 200 includes a radio frequency (RF) source 210, a plurality of phase shifters 220, corresponding plurality of antenna elements 230, and an RF unit controller 240. In the illustrated embodiment, the RF source 210 provides RF signals allocated to the phase shifters 220. Each phase shifter 220 is coupled to a corresponding one of the antenna elements 230 and is configured to apply controllable phase shifts Φ0, Φ1, Φ2, Φ3, ..., Φ(N-2), Φ(N-1) to the RF signals provided to the corresponding antenna element 230. The RF unit controller 240 is coupled to the phase shifters 220 and is configured to set or adjust the respective phase shifts for the antenna elements 230.

[0039] By appropriately selecting the phase shift Φ0 to Φ(N-1), the phased array system 200 can form a composite radiation field that approximates an equal-phase wavefront 250 in the desired direction. Figure 2 In the example shown, the phased array system 200 forms a scanning beam in a scanning beam direction 260 offset by an angle θ from the wide side direction 270 of the antenna aperture. Constructive interference from the RF signal radiated by the antenna element 230 along the scanning beam direction 260 is caused by a phase shift selected by the controller, such that the effective phases of signals arriving along the equal-phase wavefront 250 are substantially equal. Due to the phase difference, signals radiated in other directions are difficult to superimpose effectively, thus forming a sidelobe pattern. In various embodiments, the RF unit controller 240 can update the phase shift Φ0 to Φ(N-1) over time to manipulate the scanning beam direction 260, track moving targets or satellites, or form different beam patterns.

[0040] The phased array system 200 provides an example of an RF subsystem that can benefit from effective control of multiple RF signal paths. In particular, each combination of the phase shifter 220 and the corresponding antenna element 230 can be considered as an RF signal unit whose operating parameters (such as phase, gain, or polarization) can be adjusted in coordination with other RF signal units.

[0041] However, as array size increases and beams are manipulated or reconfigured more frequently, the complexity of managing the configuration of RF signal elements can increase significantly. In conventional implementations, the controller can program the phase shifter 220 using a sideband control interface, such as a Serial Peripheral Interface (SPI) bus or General Purpose Input / Output (GPIO) pins, by issuing register-write transaction sequences to each RF signal element. As the number of RF signal elements increases, for example to tens or even hundreds of elements in a phased array (e.g., 64, 128, 256 elements or more), full beam updates can involve a large number of low-speed SPI or GPIO transactions to update the phase control word throughout the array. For example, in a phased array with 256 RF signal elements and a 16-bit phase control word, updating all phase settings via an SPI interface operating at clock rates on the order of megahertz may require transmitting thousands of bits per update, and each full array beam adjustment may consume several milliseconds, which can be significant when tens or hundreds of beam updates are performed per second. In such cases, aggregated transaction time and bus bandwidth can become bottlenecks for the rapid configuration and reconfiguration of RF signal units, especially when beam manipulation, beam skipping, or calibration operations are performed on fine time scales.

[0042] Therefore, the technology disclosed herein can be used in conjunction with systems such as phased array system 200 to transmit configuration information to RF signal units in a scalable manner and support rapid, coordinated updates of phase settings for generating the equal-phase wavefront 250 and the scanning beam direction 260. However, it should be noted here that although Figure 1 and Figure 2 The LEO communication and phased array control scenarios are shown as example application environments, but the disclosed techniques are not limited to these specific use cases and can be applied to a variety of other RF systems and deployment environments.

[0043] Figure 3 An example functional block diagram of system 300 is shown, in which a master device 310 provides control signaling to a destination system-on-chip (SoC) 320 that implements one or more of the technologies disclosed herein. The master device 310 can be implemented using various platforms, such as a field-programmable gate array (FPGA), a microcontroller (MCU), a processor-based control board, a personal computer (PC), or another suitable controller. According to this embodiment, the master device 310 can send commands and configuration information to the SoC 320, and in several embodiments, can also receive status or read back data from the SoC 320. In some examples, the master device 310 may also include an interface to an AI-based processing or other control function 318 that generates configuration information for a plurality of radio frequency (RF) signaling units 350 implemented on the destination SoC 320.

[0044] The master device 310 may include different types of input / output ports, including general purpose input / output (GPIO) interfaces and high-speed serializer / deserializer (SerDes) interfaces, and the SoC 320 may similarly include GPIO ports and SerDes-based ports. In the illustrated embodiment, the master device 310 and the destination SoC 320 are coupled via a SerDes-style interface including a high-speed data path 332 and associated control signal ports 314. The data path 332, depicted on the master side as DATA_in and DATA_out 312, carries a serial bitstream containing RF configuration commands and associated configuration data. The control signal ports 314 transmit one or more control signals from the master device 310 to the mixed-signal transmit / receive (TX / RX) unit 330, such as clock, chip select, framing, or enable signals, which define the timing and transaction boundaries of the serial bitstream on the data path 332. The mixed-signal TX / RX unit 330 includes a high-speed input / output (I / O) receiver 334, which operates as an on-chip SerDes receiver, receiving serial data on data path 332 and any associated control signaling 314, and providing corresponding clock and data signals to the digital unit 340. In some implementations, the SoC 320 may also support one or more additional interfaces dedicated to user payload traffic, while the DATA_in / DATA_out path 332 is reserved for RF configuration commands and related configuration data. Other signal lines (such as power connection, ground reference, reset signal, reference clock signal, and device select or mode select signal) may also exist between the host device 310 and the SoC 320 (even if, for simplicity, they are not explicitly stated in the original text). Figure 3 (As shown in the image).

[0045] Digital unit 340 can implement control circuitry that parses the command stream provided by high-speed I / O receiver 334 and controls RF signal unit 350 accordingly. Figure 3In the example, the serial bitstream carried via high-speed data path 332 (DATA_in / DATA_out) constitutes a command stream that encodes both command fields and RF configuration data, and in at least some embodiments, differs from any payload data stream that can be used in the system to carry user data. In some embodiments, the command stream encoded by master device 310 may include multiple identifiers (e.g., device identifier, channel identifier, etc.) and RF configuration information for one or more RF signaling units 350 in a defined field data structure. Furthermore, in some embodiments, the clock circuitry associated with high-speed I / O receiver 334 may include a phase-locked loop (PLL) that generates a sampling clock for capturing the serial bitstream at a fast (e.g., nanosecond-level) timing resolution, thereby reducing command-to-application latency.

[0046] The control circuitry in digital unit 340 can extract a device identifier field and an RF configuration information field for the destination SoC 320 from the command stream. The device identifier can be compared with a predetermined identifier stored for the destination SoC 320 to determine if a given command in the command stream is for that device. When the device identifier matches a predetermined identifier for the destination SoC 320, digital unit 340 interprets the RF configuration information and controls RF signal unit 350 based on that RF configuration information. The RF configuration information may include, for example, gain control fields, phase control fields, and frequency status fields for various RF channels, as well as operation identifiers (e.g., specifying read, write, or load operations), burst mode identifiers, and memory address fields specifying locations within the on-chip memory structure.

[0047] In several embodiments, digital unit 340 includes one or more first memory circuits storing RF configuration information to be processed and one or more second memory circuits storing valid RF configuration information. In several examples, the first memory circuits may include one or more addressable memory arrays, such as static random access memory (SRAM) structures, holding each channel configuration word, and the second memory circuits may include output storage elements, such as registers, latches, or flip-flops, that directly drive the control inputs of RF signal units 350. For each RF channel of RF signal units 350, the destination SoC 320 may allocate corresponding memory locations in the first and second memory circuits such that each RF signal unit 350(0) to 350(N-1) has associated storage for both pending and valid configuration states. In this way, each SoC device may have its own device identifier, and each RF channel on that device may have corresponding memory for receiving channel-specific configuration information carried in the command stream.

[0048] The control circuitry in digital unit 340 can also support burst access operations, where a portion of the command stream encodes a sequence of burst commands that update RF configuration information across multiple RF signaling units 350. For example, the command stream can specify a starting memory address and a burst length, and digital unit 340 can automatically execute multiple burst access commands sequentially, writing phase and gain settings for consecutive channels to the corresponding memory locations. In some embodiments, memory addresses assigned to RF signaling units are assigned sequentially, such that stepping through consecutive addresses in a burst naturally steps through the corresponding RF signaling units along the array. In such an example, a single command frame in the command stream can update phase and gain information for many RF signaling units 350. For example, a burst write can program a corresponding phase control word and gain control word for each RF signaling unit, where the phase and gain value pairs for a given RF signaling unit can differ from the phase and gain value pairs for other RF signaling units in the burst. In this way, burst access operations can reduce the number of discrete control transactions compared to conventional serial peripheral interfaces or general input / output control schemes.

[0049] In several implementations, digital unit 340 responds to a load signal by transferring RF configuration information to be processed from a first memory circuit to a second memory circuit. The load signal may be supplied as a dedicated RF load (Fast_LOAD) input pin on the destination SoC 320, or it may be encoded within the command stream itself as a specific operation identifier or load flag. When digital unit 340 detects a load condition (via an external load signal or via an in-band load command in the command stream), digital unit 340 can replace the valid RF configuration information in the second memory circuit with the RF configuration information to be processed in the first memory circuit. Because load operations can be performed using on-chip transmission, and because the SerDes command stream can exhibit very low latency (e.g., in nanoseconds), the downtime delay of each RF signaling unit 350 during configuration updates can remain very short, while still allowing a large number of channels to be updated synchronously.

[0050] RF signal unit 350 represents each channel RF path, such as a transmit chain, receive chain, or other RF front-end elements associated with an antenna array or multi-channel RF subsystem. Figure 3In the example depicted, RF signal unit 350 includes multiple RF paths 350(0), 350(1), 350(2) to 350(N-1), each RF path being controllable by digital configuration data derived from digital unit 340. For example, each RF signal unit 350(i) may receive control inputs corresponding to phase control words, gain settings, frequency bands, or other operating parameters stored in the effective memory circuitry of digital unit 340. Because the pending configuration states for all channels can be preloaded and then simultaneously transmitted to the effective memory circuitry in response to a load signal, RF signal unit 350 can transition to a new beamforming or gain state with minimal interruption to RF operation.

[0051] The mixed-signal TX / RX unit 330 of the destination SoC 320 also includes an on-chip repeater 336, which in Figure 3 This is illustrated as a daisy-chain repeater. The on-chip repeater 336 can receive a command stream output from a high-speed I / O receiver 334 and generate one or more forwarded versions of the command stream at one or more repeater ports (e.g., Repeater_port_0 and Repeater_port_N-1). In a typical implementation, the on-chip repeater 336 can redrive the entire command stream without reinterpreting individual commands, thereby repeating the complete serial bit stream towards downstream devices in the daisy chain. By repeating the entire bit stream instead of reissuing individual register writes, the repeater 336 can rapidly propagate commands to additional SoCs and can support very large-scale RF arrays. The on-chip repeater 336 may include a transmit driver, SerDes output circuitry, or other output stage that re-establishes signal amplitude, timing, and equalization characteristics suitable for transmission over high-speed links to downstream SoCs.

[0052] Furthermore, in some embodiments, digital unit 340 can generate a repeater enable signal to determine whether on-chip repeater 336 is valid. Control circuitry can monitor the repeater enable signal, and when the repeater enable signal indicates that the repeater is enabled, the control circuitry can forward a serial bit stream from the on-chip receiver in high-speed I / O receiver 334 to on-chip repeater 336 to provide a cascading command path to downstream electronic devices. When the repeater enable signal indicates that the repeater is disabled, such as for the last device in the chain without other downstream SoCs, on-chip repeater 336 can be turned off to reduce power consumption and prevent unnecessary signaling on unused links. In various embodiments, the repeater port of on-chip repeater 336 can drive downstream SoCs using a SerDes interface, and in some embodiments, the repeater can interface between different signaling formats, such as SerDes-in with GPIO or serial peripheral interface outputs, although SerDes-in and SerDes-out implementations are generally preferred in high-speed RF systems. This daisy-chain cascading technology allows many SoCs (potentially on the order of hundreds or even thousands of RF channels across multiple integrated circuits) to be connected in series without requiring off-chip SerDes fan-out buffers on the printed circuit board (PCB). Therefore, the daisy-chain cascading technology disclosed herein can reduce PCB routing complexity and component count, and can help reduce the cost and design effort associated with distributing control information from the master device 310 to a large number of SoCs.

[0053] In view of the above, Figure 3 The architecture shown offers substantial improvements in how RF configuration information is transmitted from the master device 310 to the RF signaling unit 350. The master device 310 encapsulates RF commands into a high-speed serial bitstream, which is transmitted along with associated control signaling on the control signal port 314 on the DATA_in / DATA_out path 332. The destination SoC 320 deserializes the command stream at a gigabits per second data rate using integrated SerDes circuitry in the high-speed I / O receiver 334. Because the SerDes clock can operate several orders of magnitude faster than GPIO switching rates or conventional Serial Peripheral Interface (SPI) clocks, the effective command bandwidth between the master device 310 and the SoC 320 can be increased by tens of times compared to conventional GPIO or SPI-based control schemes. Therefore, the “command-to-action” time measured from issuing a command at the master device 310 to applying the corresponding configuration at the RF signal unit 350 can be transformed from microsecond-level latency associated with low-speed GPIO or SPI transmissions to nanosecond-level latency dominated by SerDes pipeline latency and on-chip payload transfer operations.

[0054] Although not in Figure 3As detailed in the diagram, the destination SoC 320 can also support an uplink or readback path for transmitting status information from the RF signaling unit 350 and the digital unit 340 back to the master device 310. For example, the digital unit 340 can provide readback data in response to a read command in the command stream and can output status information through an uplink interface with a data rate lower than that of the high-speed I / O receiver 334. The uplink interface can be implemented using a GPIO interface or another suitable signaling format, and the master device 310 also acts as an upstream device in this reporting path. In this way, the system 300 combines a high-speed downstream command stream for fast and scalable RF configuration with flexible low-rate upstream reporting and readback, while supporting daisy-chain connections to additional SoCs via the on-chip repeater 336.

[0055] Figure 4 An example system-on-chip (SoC) architecture 400 is shown, illustrating some implementation details of one embodiment of the destination SoC 320 described above. The SoC architecture 400 is divided into a mixed-signal transmit / receive (TX / RX) unit 430, a digital unit 440, and an RF signaling unit 450. (As...) Figure 4 As shown, the TX / RX unit 430 sends signals to the host device (e.g., Figure 3 The master device 310 provides a high-speed interface, the digital unit 440 implements command decoding and configuration storage circuitry, and the RF signal unit 450 implements the per-channel RF path, whose operating parameters are controlled based on the configuration information stored in the digital unit 440. The SoC architecture 400 can represent an N-channel RF SoC suitable for multi-channel RF applications such as multi-beam beamforming and beam acquisition, satellite communications, phased array radar, multi-carrier communication systems, or broadband spectrum analysis.

[0056] In the example SoC architecture 400, the mixed-signal TX / RX unit 430 includes a TX / RX block that receives a clock signal, a chip select signal (CSB), and serial data signals (DATA_in and DATA_out) from the master device. (See also: ...) Figure 3The discussed DATA_in signal can carry a serial command stream, which encodes device identifiers and RF configuration information, etc., in a defined field data structure, while the DATA_out signal can be used to carry readback information or other upstream data. The TX / RX block can use a clock signal provided by the master device to deserialize the incoming command stream, and in one or more embodiments, the corresponding clock and data signals can be forwarded to the digital controller within the digital unit 440. In some embodiments, the TX / RX block may also include clock recovery or clock conditioning circuitry (e.g., a phase-locked loop (PLL)) to regenerate or clear the sampled clock from the received signaling, while in other embodiments, an externally provided clock signal is used directly as a timing reference. Additional signals, such as a reset (CDN) signal and other bias or reference signals, may also be provided to the mixed-signal TX / RX unit 430.

[0057] exist Figure 4 In the illustrated embodiment, digital unit 440 includes a digital controller that receives a deserialized serial command stream from TX / RX unit 430 and interprets the commands and configuration fields contained in the stream. Based on the decoded commands, the digital controller generates internal control signals and memory access signals to update the configuration storage for RF signal unit 450. The digital controller may also interface to auxiliary digital or mixed-signal functions, such as successive approximation register analog-to-digital converters (SARADCs) and temperature sensors (T sensors), which may be implemented in a SARADC / T sensor block. In some embodiments, the SARADC / T sensor block may monitor on-chip operating conditions (e.g., supply voltage, die temperature) and may provide corresponding digital readings to the digital controller, which may then adjust configuration settings or bias conditions accordingly.

[0058] Digital unit 440 may also include a static random access memory (SRAM) array (SRAM 16×16) and a register array (register 16×16). In one or more embodiments, the SRAM 16×16 and register 16×16 together may form part of one or more memory circuits that store pending RF configuration information for multiple RF signal units 450. More specifically, the SRAM 16×16 may be organized, for example, 16 rows by 16 columns, where each row may correspond to a channel identifier for a corresponding RF signal unit, and each column corresponds to a bit position in a configuration word (e.g., a 16-bit phase or gain control word). Then, for example, the digital controller may write the configuration word into selected rows of the SRAM 16×16 based on the channel identifier and memory address parsed from the command stream, thereby establishing a set of pending configuration states for multiple RF channels. In various implementations, the configuration words stored in the SRAM 16×16 can collectively represent the RF signal status for the channel, such as signal control bits, amplitude settings, phase control values, frequency status bits, or other channel-specific parameters that can manage the behavior of the RF signal unit 450.

[0059] In some embodiments, the SRAM structure can be channel-addressable, for example, by using channel identifier bits carried in the command stream and comparing these bits with locally stored channel tags. When a match is detected, shared signals such as address [6:0], data input [7:0], write enable, read enable, and clock can be passed to the control unit for the SRAM array, thereby waking up the corresponding SRAM and generating internal pulses for the row decoder, column decoder, sense amplifier, and latch circuitry. By allowing multiple SRAM arrays to share a common set of external address, data, and control lines and relying on channel identifier matching to select the appropriate array, the total number of wires that must be routed across the SoC can be reduced, even in the presence of many RF channels.

[0060] The 16×16 register block can be used to implement, for example, different types of addressable configuration storage. In some implementations, the 16×16 register can hold configuration information, calibration coefficients, or other control parameters for global or block-level settings, which are not strictly per-channel but are written to and read under the control of the same command flow targeting RF signal unit 450. The digital controller can use the 16×16 register for settings that benefit from direct register access rather than SRAM access via channel indexes, while still employing a similar write and read mechanism based on decoded command fields. In such embodiments, the 16×16 register can facilitate memory circuitry storing RF configuration information to be processed, the difference being that the stored values ​​can correspond to global or block-level parameters rather than per-channel words. Furthermore, registers can be organized using register identifier bits that are compared with register address bits on shared address and control lines, allowing a common set of address, data, write enable, read enable, and clock signals to be broadcast to many registers, while only the register whose identifier matches the address participates in a given transaction, which can further help reduce wiring complexity.

[0061] Furthermore, according to one or more embodiments, a set of RS flip-flop (RS FF) stages is provided between the digital unit 440 and the RF signal unit 450, which provides per-channel output storage. In some embodiments, these RS FF stages can implement memory circuitry for storing valid RF configuration information. For each RF channel, the RS FF block can receive configuration bits from SRAM 16×16 and / or register 16×16, and can store these bits as valid states applicable to the corresponding RF signal unit 450. The RS FF stages can be arranged using two stages of latches or flip-flops (e.g., as shown below). Figure 5 and Figure 6 This is achieved through the Level 1 and Level 2 architectures discussed in the text, to separate the processing and efficient storage and support the transmission of configuration information.

[0062] The load signal (Fast_LOAD) can be provided to the RSFF stage from the digital controller or, in some embodiments, from an off-chip signal. In operation, the digital controller can assert the Fast_LOAD signal in response to a decoded load command in the command stream, or an external device can assert Fast_LOAD via a dedicated input pin. When Fast_LOAD is asserted, the first-stage storage element holding the configuration value to be processed can transfer its contents to the second-stage RSFF driving the RF signal unit 450, thereby replacing the previously valid configuration information with the newly loaded configuration word. In this way, the SRAM 16×16 and register 16×16 in the digital unit 440 serve as memory circuitry for accumulating the RF configuration information to be processed, and the RSFF stage serves as memory circuitry for holding the valid RF configuration information, with Fast_LOAD providing synchronous transfer between the two. Because the transfer controlled by Fast_LOAD updates the second-stage output for all channels substantially simultaneously, the RF signal unit 450 can undergo phase and amplitude coherent changes in configuration while minimizing interruptions to ongoing RF operations.

[0063] According to implementation methods, in many multi-SoC arrangements, Fast_LOAD can be provided by the master SoC or the root SoC, where devices with Fast_LOAD set are connected to the Fast_LOAD control of all downstream SoCs in a fan-out manner. However, in other multi-SoC arrangements, SoC devices may also include dedicated Fast_LOAD output terminals that forward load signals to downstream SoCs, enabling multiple devices to perform pending-to-valid conversions synchronously across daisy-chains and / or fan-outs.

[0064] Digital unit 440 may also include additional control logic, such as an 8-bit register bank (8-bit register × 12) and associated low-dropout (LDO) regulators, bandgap (BG) references, and switch control blocks. These elements demonstrate that the digital controller can manage not only the RF channel configuration word but also other on-chip control points, such as bias voltages, reference generation, and analog switch states. Configuration information for these auxiliary circuits can also be passed via the same high-speed command stream and stored in appropriate register or memory locations under the control of the digital controller. In some embodiments, the corresponding outputs for such auxiliary control points can also be organized into pending and active states coordinated using the Fast_LOAD signal, enabling bias and control changes to be applied in a controlled and synchronous manner.

[0065] In the SoC architecture 400, the RF signaling unit 450 is shown as an RF path with channel indices (channel_0, channel_1, ..., channel_(N-1)). Each RF signaling unit 450(i) may correspond to a transmit or receive chain, a phase shifter path, a gain stage, or another RF front-end element, as described above regarding... Figure 3 As described, the control input of each RF signaling unit 450(i) is driven by valid configuration bits stored in the RS FF level, which represent the current RF configuration information for that channel selection. Because the configuration value to be processed can be written to SRAM 16×16 and register 16×16 over time, and then simultaneously transferred to the RS FF level in response to Fast_LOAD, the SoC architecture 400 can support coordinated updates of all RF signaling units 450 with minimal downtime and without requiring separate low-speed register write transactions for each individual channel.

[0066] Overall, the SoC Architecture 400 is an example of a system that can use digital controller logic, SRAM arrays, register arrays, and RS flip-flop stages to implement pending and active state memory structures and their interactions via load signals on a SoC that controls multiple RF signal units.

[0067] Figure 5 An example channel-addressable static random access memory (SRAM) structure 500 is shown, which can be used as part of the digital control circuitry of a SoC architecture 400, for example, as an SRAM-based configuration memory slice that facilitates the storage of pending configurations for the digital unit 440. SRAM structure 500 represents one way to implement memory circuitry that holds pending RF configuration information for multiple RF channels while reusing a common set of address, data, and control lines across many such memories.

[0068] SRAM structure 500 may include a channel identifier comparator that receives a set of channel identifier bits Channel_ID[3:0] from a command stream and compares these bits with locally stored channel labels channel[3:0]. Each bit of Channel_ID[3:0] can be compared with the corresponding bit of Channel[3:0] using, for example, a comparison gate, and the comparison results are combined to generate a match signal. When all bits match, the match signal is set, indicating that the incoming command is intended for a specific SRAM structure 500 (and, by extension, the RF channel associated with that structure). When the match signal is not set, SRAM structure 500 remains idle for that command.

[0069] A set of shared access signals can be provided to SRAM structure 500, including, for example, an address bus (Address[6:0]), a data input bus (Data_In[7:0]), a write enable signal, a read enable signal, and a clock signal. These signals can be shared across multiple SRAM structures. In the illustrated embodiment, the shared access signals are gated by a match signal such that when a match occurs, the gated Address[6:0], Data_In[7:0], write enable, read enable, and clock signals are delivered to the control unit associated with SRAM structure 500. The control unit responds by waking up one or more associated SRAM banks and generating internal pulses for the row decoder, column decoder, sense amplifier, and latch circuitry. By allowing many SRAM structures to share the same external address, data, and control lines, and relying on Channel_ID[3:0] / Channel[3:0] comparisons to determine which structure is valid in a given transaction, the total number of wires required to support a large number of RF channels can be reduced, as multiple channel-specific SRAM slices can reuse the same Channel[3:0], Address[6:0], Data_In[7:0], write enable, read enable, and clock signals throughout the chip.

[0070] exist Figure 5 In the example, SRAM structure 500 includes two SRAM banks (SRAM-B and SRAM-A). Each bank includes a bit cell storage bank operating under the control of a corresponding control unit, associated row decoder, and column decoder / sensor amplifier circuitry. For a given match access, the control unit receives strobed address, data, and control signals and performs a read or write operation on the selected row of the bit cell storage bank. In one embodiment, the two SRAM banks are used together to store different bit portions of a wide RF configuration word. For example, SRAM-A may hold the low byte of a 16-bit configuration word, and SRAM-B may hold the high byte of the same configuration word, allowing a 16-bit channel configuration to be assembled across the banks when data is read.

[0071] Each SRAM bank is coupled to a two-stage output-memory arrangement implemented using reset-set latch flip-flops (RS FFs). In the illustrated embodiment, each bank includes a first-stage RS FF (stage 1 RS-FF) and a second-stage RS FF (stage 2 RS-FF). The first-stage RS-FF receives data read from the column decoder / sensor amplifier circuitry and acts as the output register to be processed, while the second-stage RS-FF acts as the valid output register driving the corresponding Data_Out bus. A load signal Fast_LOAD is applied between the first-stage RS-FF and the second-stage RS-FF. When Fast_LOAD is set, the contents of the first-stage RS-FF are synchronously transferred to the second-stage RS-FF, thereby replacing the previously valid configuration bits with the newly read values. In the specific example shown, the 2-stage RS-FF of SRAM-A drives the Data_Out[7:0] bus, and the 2-stage RS-FF of SRAM-B drives the Data_Out[15:8] bus, so that the two output buses together can provide a 16-bit RF configuration word to downstream circuitry such as the per-channel RS-FF stage and RF signal unit of the SoC architecture 400.

[0072] Therefore, SRAM structure 500 shows an example of a two-level pending / valid arrangement driven by Fast_LOAD, which can be used to apply new per-channel configuration words in a coordinated manner.

[0073] Figure 6 An example register structure 600 is shown, which can be used as part of a two-stage latch arrangement associated with the configuration memory described above, including SRAM structure 500. Register structure 600 provides globally addressable or bank-specific configuration registers that employ a two-stage storage arrangement and a load signal Fast_LOAD to separate the value to be processed from the valid output, while reusing a common set of data and control lines on many registers in a manner similar to a channel-addressable SRAM structure.

[0074] Register structure 600 may include a register identifier comparator that receives a set of register identifier bits (Register_ID[6:0]) and compares these bits with the corresponding register address bits (Reg_Address[6:0]) derived from the command stream or from the shared address lines. Comparison gates can be used to compare each pair of bits, and the comparison results can be combined to generate a match signal. When all bits match, the match signal is set, indicating that the current command targets the specific register instance represented by register structure 600. When the match signal is deasserted, register structure 600 ignores the current command, thus allowing many such register structures to share common control lines without contention.

[0075] Shared control signals can be broadcast to multiple register structures, including the data input bus Data_In[7:0], write enable signal, read enable signal, and clock signal. In register structure 600, these shared signals can be gated by a match signal, causing only the addressed register to respond to a given transaction. When a match occurs and a write enable condition is present, the gated Data_In[7:0] and clock signals are applied to the memory bank of the first-stage flip-flop (Level 1 DFF), which serves as the eight-bit unprocessed storage element of the register. When a match occurs and a read enable condition is present, the shared bus structure can again be used to present the data held in the register to upstream circuitry (e.g., for reading back via the shared DATA_out path). In some embodiments, multiple configuration-memory blocks corresponding to respective RF signal units share a common data bus carrying configuration or read-back values. Each memory block may include, for example, a tri-state output circuit coupled to a shared bus, and when the memory block is selected, the tri-state circuit drives the bus with the stored data; when no memory block is selected, the tri-state circuit places its connection to the bus in a high-impedance state, allowing other memory blocks or circuits to drive the bus without contention. By employing register identification tags and match gating similar to the channel identification scheme used in SRAM architecture 500, register architecture 600 can reduce wiring complexity while still allowing individually addressable registers to be distributed across the die.

[0076] Register structure 600 also includes a storage bank for a second-stage flip-flop (stage 2 DFF), which in one implementation is implemented as a reset-set flip-flop (RS-FF0 to RS-FF7). Stage 1 DFF provides the contents of the register to be processed, while Stage 2 DFF holds the corresponding valid configuration output that ultimately drives the downstream circuitry. The load signal Fast_LOAD is coupled between the two stages of flip-flops. When Fast_LOAD is set, the value stored in Stage 1 DFF is transferred to Stage 2 DFF in a substantially simultaneous manner, thereby replacing the previously valid register value with the new configuration data. The outputs of Stage 2 DFF collectively form an 8-bit output bus Data_Out[7:0], which can provide bias control settings, calibration coefficients, mode selection bits, or other non-per-channel control information to analog and digital blocks elsewhere on the SoC.

[0077] In this way, register structure 600 can implement two levels of pending / valid register slices, which, along with... Figure 5 The SRAM-based slice coordination operation uses Fast_LOAD as a common mechanism for coordinating updates, while leveraging a shared bus and tag-based addressing.

[0078] Figure 7An example signaling arrangement 700 is illustrated, in which a master device (e.g., device 310) uses data signals, clock signals, and chip select signals to transmit serial control information to a destination SoC (e.g., SoC 320). See also... Figure 3 The following section further explains the example signaling deployment 700.

[0079] According to this embodiment, the master device 310 can generate a clock signal CLOCK, a chip select signal CSB, and a data signal DATA_in, and the destination SoC 320 can receive these signals at the corresponding input pins. In one or more embodiments, CSB is set during the effective interval, wherein the master device 310 initiates a bit sequence of a command stream timed relative to the clock signal on DATA_in. When CSB is reset, the command interval ends, and the destination SoC 320 can stop interpreting the incoming bits for that transaction.

[0080] Within the SoC 320, the high-speed I / O receiver and associated digital controller (e.g., the aforementioned high-speed I / O receiver 334 and digital unit 340) can sample DATA_in on a valid transition (such as a rising edge) of CLOCK when the CSB is set. In several embodiments, the bits of the serial command stream are transmitted in most significant bit-first order, where the least significant bit of a field or word appears last in time. Aligning the DATA_in sampling with the defined edge of the CLOCK signal and using a consistent bit order simplifies the timing closure and deserialization logic within the SoC 320. This approach also provides a more predictable set-up and hold relationship at the interface between the master device 310 and the SoC 320.

[0081] In some implementations, the CSB signal defines a coarse transaction boundary, and the SoC 320 can apply additional timing rules around the setting and holding of the CSB to improve robustness. For example, the SoC 320 can ignore a predetermined number of clock cycles immediately following the CSB being set and immediately before the CSB being reset, thereby providing a timing margin for any skew between the CSB and DATA_in. The remaining clock cycles (where DATA_in is stable near the sampling edge of the defined CLOCK) can be considered as the effective bit time constituting the serial command stream. More specifically, in some implementations, the control circuitry can exclude a predetermined number of initial bit times (T_setup) after the set chip select signal and a predetermined number of final bit times (T_hold) before the reset chip select signal from command parsing, thereby providing explicit set and hold margins around the command frame.

[0082] In signaling arrangement 700, the serial bit stream transmitted on DATA_in can be logically organized into command frames 710. Each command frame may sequentially include a synchronization mode, one or more identification and addressing fields, an operation field, and associated payload information. For example, in a representative implementation, a command frame may begin with a synchronization mode that presents a known bit sequence (e.g., an alternating mode), which the digital controller uses to align bit boundaries and acknowledge the start of a new frame. Once the synchronization mode is detected and the sampling clock is aligned, the same timing reference can be used to drive the on-chip repeater, ensuring that the forwarded serial bit stream remains aligned with the frame and bit boundaries established by the synchronization mode. Following the synchronization mode, the frame may include a value carrying the integrated circuit selection (ICSEL). <n:0>The device selection field, one or more channel or register identification fields, operation identifier (e.g., read, write, or load), address field, optional burst length or mode field, and for write operations, a data payload field containing configuration or control bits.

[0083] The device selection field can be used in multi-SoC daisy-chain deployments, where many N-channel SoCs share the same downstream command stream. In such embodiments, each SoC can store a local identifier, and the digital controller can interpret the ICSEL in the command frame. <n:0>The value is compared with a local identifier. When the device selects a value that matches the local identifier, the SoC 320 accepts and executes the command and associated data; when the value does not match, the SoC 320 can ignore commands regarding its own configuration while still forwarding the serial bit stream to downstream devices via the on-chip repeater mentioned above. In this way, a single master device 310 can address individual SoCs or groups of SoCs without changing the physical wiring topology.

[0084] From a command semantics perspective, commands processed by a digital controller can typically be grouped into read commands and write commands, with additional command types (e.g., load or mode change commands) defined according to the needs of a given application. Each command can be issued as a single-step access or as part of a continuous sequence designed to reduce control overhead. For example, a write command can specify a start address, channel or register identifier, and a burst length field. In response, the digital controller can automatically execute a sequence of write operations across consecutive address or channel entries using consecutive payload words following in the same command frame, without requiring a separate full command header for each access. Similarly, a read command can specify a start address and burst length, and the SoC 320 can use a sequence of read commands with a start address and burst length. Figure 8 The described signaling arrangement executes a sequence of read operations and returns the requested data bits via DATA_out. The use of this continuous operation can reduce the number of serial transactions required to refresh or query configuration data on many RF channels.

[0085] Figure 7 The synchronization and framing behavior can also be coordinated with chip-selected timing. In some embodiments, the master device 310 sets the CSB, transmits the synchronization mode and the remainder of the command frame while the CSB is set, and then resets the CSB after the last bit of the frame has been transmitted. The SoC 320 can be configured to begin parsing the frame only after detecting the synchronization mode while the CSB is active. In some embodiments, the SoC 320 can exclude one or more initial and final bit cycles after the CSB is set and before the CSB is reset from the frame parsing window, which can help absorb timing skew or jitter between the CSB and DATA_in, thereby increasing the robustness of command decoding at high data rates.

[0086] Note that, although Figure 7 The focus is on downstream signaling from the master device 310 to the destination SoC 320, but the same CLOCK and CSB framework can be reused when the SoC 320 initiates a readback transaction. In this case, the master device 310 can continue to drive the CLOCK and CSB, while the SoC 320 drives the CLOCK and CSB according to the specified parameters. Figure 8 The described protocol uses the same or similar bit ordering and sampling rules to drive DATA_out. By unifying timing, framing, and command semantics across write and read operations, Signaling Arrangement 700 can support scalable, high-speed configuration and monitoring of large RF arrays using a compact set of serial interface signals.

[0087] Figure 8 An example signaling arrangement 800 is illustrated, in which a destination system-on-chip (SoC) 820 sends a data signal along with a data enable signal to a master device 810. The master device 810 includes a receive interface 814 with one or more data input ports configured to accept an upstream data signal DATA_out and an associated data enable signal DATAE_out. The destination SoC 820 includes a corresponding transmit interface 834 with an output driver that sends DATA_out and DATAE_out to the master device 810 as part of a readback or status reporting operation.

[0088] During the example readback transaction, the master device 810 uses the above-mentioned... Figure 7 The described downstream signaling arrangement initiates a command sequence (e.g., setting a chip select signal, issuing a read-type command in the command stream, and providing clock transitions for bit timing). In response to a decoded read command, the destination SoC 820 retrieves the requested register or memory contents from its digital unit and presents the obtained information on DATA_out. The SoC 820 sets DATA_out when valid readback information is driven on DATA_out and resets DATA_out when the transaction is complete. Figure 8 As shown, the "Sync" part indicates the synchronization interval for DATAE_out to transition from an invalid state to a valid state; the "Command / Data" part indicates the interval for transmitting read-back bits on DATA_out while DATA_out remains valid.

[0089] In several embodiments, the master device 810 samples DATA_out when DATAE_out is set and can ignore DATA_out when DATAE_out is invalid. This behavior, when DATAE_out is set, allows DATA_out to be placed in a tri-state or multiplexed for other purposes and helps avoid contention in systems where multiple SoCs share one or more upstream data lines. In some implementations, the read-back bits on DATA_out follow the same bit ordering and clocking conventions described for the downstream command stream (e.g., most significant bit first, sampled on the valid edge of the shared clock), even if for simplicity... Figure 8 The clock and chip select signals are omitted. The readback information provided via DATA_out can include, for example, configuration values ​​read from the pending or active memory circuitry, status flags from the RF signal unit, temperature or power measurements from the SARADC / T sensor block, or other diagnostic data that allows the master device 810 to monitor and verify the operation of the target SoC 820. In this way, the command stream interface disclosed herein can support reliable high-speed operation without requiring complex timing margins or protocol overhead.

[0090] Figure 9 Example functional diagram 900 is shown, illustrating how a received command stream can be captured locally by the SoC under the control of a single enable signal, and simultaneously relayed to one or more downstream devices. For example... Figure 9 As shown, receiver 934 is coupled to an input port that carries an incoming serial command stream from an upstream master device or SoC. Receiver 934 can perform front-end analog functions, such as level shifting, termination, equalization, or signal conditioning, and can output a conditioned serial data signal suitable for on-chip digital processing.

[0091] Receiver 934 can output an incoming command stream to digital unit 940, which operates synchronously with a clock signal (CLK). In one or more embodiments, digital unit 940 processes incoming serial data synchronously with CLK and, in some embodiments, provides corresponding commands and configuration information to local control circuitry controlling RF signal units. Furthermore, the command stream from receiver 934 can be coupled to repeater control and buffer 960 (and associated driver circuitry) so that the same command stream is also used as a downstream repeating input. In some embodiments, repeater control and buffer 960 can apply transmit-side buffering and signal conditioning to the repeater port. In this way, the same incoming command stream can be interpreted and executed locally while also serving as a source for cascading command paths.

[0092] According to several implementations, the data output and clock signal can be further provided to a repeater circuit, which includes multiple driver circuits 936 (Driver_0 to Driver_n-1) and an associated repeater control and buffer block 960. More specifically, the repeater control and buffer block 960 can receive data and CLK and generate a set of appropriately timed internal drive signals for the driver 936. Each driver circuit 936 can then drive a corresponding repeater port (Repeater_port_0 to Repeater_port_n-1) connected to one or more downstream SoCs or other electronic devices. In several implementations, the driver 936 can redrive an incoming stream of serial commands without decoding individual commands, thereby providing regenerated amplitude and timing characteristics suitable for continued transmission along a daisy-chain or fan-out topology.

[0093] Furthermore, the enable input 970 can be coupled to repeater circuitry (e.g., to repeater control and buffer block 960) to control whether repeater functionality is enabled. When the enable signal is set (e.g., to logic high), the repeater control and buffer block 960 causes the driver circuitry 936 to transmit a command stream synchronized with CLK on the repeater port, causing downstream devices to receive the same serial bit sequence as the local controller. When the enable signal is reset (e.g., to logic low), the repeater control and buffer block 960 can disable the driver 936, for example, by placing the repeater port in a high-impedance or inactive state, thereby preventing unnecessary signaling and reducing power consumption when the SoC is at the end of a chain or when repetition is not required.

[0094] Therefore, functional diagram 900 illustrates how a single incoming serial command stream can be consumed locally or selectively redriven to multiple downstream devices, wherein enable input 970 provides independent control over the repeater's behavior without affecting receiver 934 or the local controller interface.

[0095] Figure 10 An example multi-level system layout 1000 is illustrated, in which the master device 1010 uses the aforementioned repeater technology to drive command streams into the hierarchy of system-on-chip (SoC) devices. Figure 10 In the example, the master device 1010 communicates with the first SoC, which operates as the root device in the hierarchy, via a data port (Data_Port_out). This root SoC can correspond to... Figure 3 The described destination SoC 320, and may include, for example Figure 9 The local RF signal unit, configuration memory, and on-chip repeater circuit are shown.

[0096] The root SoC can expose multiple repeater ports (e.g., DP_0, DP_1, ..., DP_n-1), each of which carries the command stream to the corresponding SoC in the first-layer downstream devices, denoted as SoC[0], SoC[1], ..., SoC[n-1]. Each of these first-layer SoCs can have the same internal architecture as the root SoC, including a local RF channel and repeaters that forward serial command streams, while optionally consuming commands addressed to that particular device. In this way, the first-layer SoCs operate as intermediate fan-out nodes that both control their own RF front-end resources and further distribute the command streams into the array.

[0097] For each first-layer SoC[i], the corresponding additional SoC group 1020 can be cascaded to one of its repeater ports, forming a daisy chain of second-layer SoCs labeled SoC[i]_0, SoC[i]_1, ..., SoC[i]_{n-1}. Each SoC in this chain receives the same serial bit stream at its input port, uses its local comparison logic to determine whether a given command is targeted at that device (e.g., based on the device identifier in the ICSEL field of the command stream), and, where appropriate, applies the associated RF configuration data to its own RF signaling unit. Commands not addressed to a particular SoC can be passed by its on-chip repeater to the next device in the chain, as per the relevant information. Figure 9 The repeater structure discussed here.

[0098] SoC group 1020 therefore represents multiple daisy-chain branches, each anchored by an intermediate SoC in the first layer and extending through several second-layer SoCs. Although in Figure 10 The diagram schematically illustrates the number of SoCs per branch and the number of branches, but in practice, these values ​​can be chosen to match the desired total RF channel count or array size. Because each SoC contains both local configuration memory and repeater functionality, a single master device 1010 and a single command port can be scaled to control a large number of SoCs distributed across many branches without requiring external SerDes fan-out buffers or complex printed circuit board wiring.

[0099] Therefore, system layout 1000 illustrates how the disclosed repeater-based command distribution scheme can be applied in a hierarchical manner: the master device 1010 transmits a serial command stream to the root SoC, the root SoC uses its repeater port to forward the stream to multiple intermediate SoCs, and each intermediate SoC then forwards the same stream to a chain of additional SoCs, thereby achieving extensive scalability of RF configuration control within a multi-SoC system.

[0100] Figure 11 Another example of a multi-level system arrangement 1100 is shown, in which a master device 1110 uses both daisy-chain cascading and per-port fan-out to distribute command streams to a large number of system-on-chip (SoC) devices. The master device 1110 outputs a serial command stream on a data port (Data_Port_out) to the SoC, which again serves as the root device in the hierarchy. (See also...) Figure 10 In this arrangement, the root SoC can achieve Figure 9 The local RF signal unit, configuration memory, and repeater circuitry of the type shown can consume commands addressed to its own device identifier while forwarding command streams to the attached SoC.

[0101] In arrangement 1100, the root SoC uses its repeater port to drive one or more intermediate SoCs. Each intermediate SoC may be structurally similar to the root SoC and may, in turn, provide its own repeater port to distribute the same command stream to SoC group 1120. SoC group 1120 represents a collection of multiple downstream SoCs, all fed from a single repeater port of an intermediate SoC. In an example implementation, a single repeater output channel from an intermediate SoC may be routed on a printed circuit board to m different SoCs within SoC group 1120, such that each of those SoCs receives the same serial bit stream.

[0102] Each SoC within SoC group 1120 may include local comparison logic that examines a device selection field (e.g., an ICSEL field) in the command stream and determines whether a given command is targeted at that device. When the field matches a locally stored identifier, the addressed SoC interprets the accompanying command and updates its own configuration memory and RF signaling units accordingly. When the field does not match, the SoC may treat the frame as being related to another device, while the remaining SoCs in the group continue to observe the same serial bit stream. In this way, a single repeater port can efficiently address multiple SoCs without the need for additional off-chip fanout buffers.

[0103] and Figure 10 Compared to the previous arrangement, where each repeater port effectively feeds a single daisy-chain branch, System 1100 demonstrates how the same command allocation scheme can be scaled to allow each repeater port to drive multiple SoCs in parallel. Because the underlying serial link can operate at high data rates, the presence of additional fan-outs and numerous cascaded devices can introduce only modest latency, while avoiding the need for discrete fan-out devices and the associated routing complexity.

[0104] Figure 12 An example method 1200 is shown that can be implemented by a system-on-a-chip (SoC) or other electronic devices participating in the high-speed command allocation scheme described above. Method 1200 can, for example, be implemented by the digital unit and mixed-signal interface circuitry of the destination SoC 320 along with reference... Figure 3 , Figure 4 and Figure 9 The described on-chip repeater circuit works together. Although Figure 12 The specific sequence of operations is depicted in the form of a flowchart, but operations can be combined, subdivided, or reordered in various ways, and some operations may be omitted or performed in parallel in other embodiments.

[0105] At step 1210, the device receives a serial bit stream. This bit stream may correspond to a command stream initiated by the master device via a high-speed serializer / deserializer (SerDes) interface, such as the DATA_out / clock / chip select signaling combination discussed above. In various embodiments, the receiver front-end and deserializer in the mixed-signal TX / RX unit may capture the incoming bit stream, perform equalization or other adjustments, and present the deserialized command stream to the digital controller.

[0106] At step 1220, the device extracts the device identifier and radio frequency (RF) configuration information from the bit stream. In one embodiment, the command stream follows a defined frame structure that includes an Integrated Circuit Select (ICSEL) field and one or more fields encoding RF configuration data (e.g., phase control words, gain settings, frequency status bits, or combined fields for multiple RF channels), as well as other fields. The digital controller can parse the command frame according to this format, recover the ICSEL field and configuration fields, and temporarily store the recovered configuration information in a pending state memory structure, such as information about... Figures 4-6 Described SRAM and register slices.

[0107] At determination step 1230, the device determines whether the extracted device identifier matches an identifier associated with that device. For example, the SoC can store a locally programmed device ID in a configuration register and compare the received ICSEL value with that local ID. If the values ​​match, method 1200 proceeds along the "yes" branch to step 1240; however, if the values ​​do not match, the method follows the "no" branch to step 1250. In this way, multiple SoCs connected in a chained or fan-out topology can observe the same serial bit stream while selectively responding only to commands addressed to them.

[0108] When the identifier matching condition is met, the method proceeds to step 1240, where the device controls its RF signal unit according to RF configuration information. This control operation may include writing configuration information to a first-level (e.g., pending) memory circuit, transmitting information to a second-level (e.g., valid) memory circuit in response to a load signal such as Fast_LOAD, thereby updating the phase, gain, or other operating parameters of the RF signal path. In some embodiments, the control operation may further include executing a read command, returning status information via the uplink path, or performing calibration-related updates based on the received configuration fields. After step 1240, the method proceeds to step 1250.

[0109] At step 1250, the method further determines whether the repeater is enabled, and if so, forwards the bit stream to the downstream device. In one implementation, the command stream recovered at the receiver is accompanied by a repeater enable signal (such as regarding...). Figure 9 The described enable input 970 is provided together with the on-chip repeater circuitry. In various embodiments, repeater determination and forwarding can be implemented by separate hardware and can operate in parallel. When the repeater enable signal indicates that forwarding is active, the repeater drives one or more repeater ports with a serial bit stream, causing additional SoCs in a daisy-chain or fan-out configuration to receive the same sequence of commands. When the repeater enable signal indicates that forwarding is disabled, the device can suppress or tri-state its repeater outputs while still receiving and processing commands locally, which is useful for the last device in the chain or for power reduction.

[0110] Overall, Method 1200 illustrates how each SoC in the disclosed system can receive a shared high-speed command stream, determine whether to update its own RF configuration based on the embedded device identifier, and propagate the same command stream to additional downstream devices when appropriate using integrated repeater functionality.

[0111] Figure 13 Example method 1300 is shown, in which an electronic device, such as a destination SoC 320, transmits data in response to a readback request from a master device. Operation of method 1300 can be performed by control circuitry within the digital unit 340 in conjunction with the aforementioned mixed-signal TX / RX interface. Although Figure 13 The specific sequence of operations is depicted in the form of a flowchart, but operations can be combined, subdivided, or reordered in various ways, and some operations may be omitted or performed in parallel in other embodiments.

[0112] At step 1310, the device receives a command stream from the master device that includes a readback request. The readback request may be encoded as one or more command frames within a serial bit stream, wherein each frame includes a command type field indicating a read operation, one or more addressing fields identifying a target internal storage element or state source, and, in some implementations, a device identifier field specifying the intended destination SoC.

[0113] At determination step 1320, the device determines whether the device identifier extracted from the received command stream matches the device identifier associated with that device. The digital controller may compare the received identifier (e.g., an ICSEL field value) with a locally stored identifier. If the identifiers do not match, method 1300 may terminate for that device regarding the current readback request, meaning that the device with the mismatched identifier does not respond to the request and generate readback data. Readbacks for devices further downstream in the daisy chain may be handled by their own instances of method 1300.

[0114] If the device identifier matches, the method proceeds to step 1330. In this step, the digital controller parses the command field of the readback request and determines which internal storage element or status source is being queried. Depending on the encoded address and command type, the controller can select, for example, a specific location in an SRAM slice of the channel index, a global configuration register, or a status register associated with an RF signal unit, analog-to-digital converter, temperature sensor, or other on-chip circuitry.

[0115] At step 1340, the device retrieves response information from a selected internal source and assembles a response frame for transmission. The controller may read the requested data from an identified memory location or status register, place the read values ​​into a readback buffer, and construct a response frame including, for example, framing or synchronization information and payload bits representing one or more retrieved values. In implementations supporting burst readback, the controller may iterate through internal reads across address sequences and aggregate multiple data words into a single response frame.

[0116] At step 1350, the device sends a response frame to the master device. Buffered response bits can be provided to the serializer driving the DATA_out signal, and in some embodiments, data enable or framing signals such as DATA_out can be set to indicate the interval where valid response data exists. Outgoing bits can be started synchronously with the transmit clock, allowing the master device to reliably capture the response frame and associate the returned data with the initiated readback request. After the response frame has been sent, the device can resume monitoring the command stream for additional commands, including further readback requests, configuration writes, or load operations.

[0117] Figure 14 An example method 1400, which can be executed by a master device, is shown to encode radio frequency (RF) configuration information and transmit that information as a command stream to one or more destination system-on-chip (SoC) devices. Method 1400 can be executed, for example, by a master device (such as regarding...) Figure 3 The control logic and serializer / deserializer (SerDes) interface circuitry in the described master device 310 are used to execute this. Although Figure 14 A specific ordering of operations is described, but operations can be combined, subdivided, or reordered, and some operations may be omitted or performed in parallel in other implementations.

[0118] At step 1410, the master device determines RF configuration information to be applied to one or more RF signaling elements. The RF configuration information can be derived from higher-level system objectives such as desired beam direction, target gain level, or calibration adjustment, and can specify per-channel parameters, including, for example, phase control values, amplitude control values, and frequency status indicators for RF signaling elements implemented across multiple SoCs.

[0119] At step 1420, the master device assembles the RF configuration information into one or more configuration words suitable for transmission via a command stream. In one embodiment, the master device encodes the configuration state of each channel into a numeric word of a defined width (e.g., 16 bits) and associates the word with a specific device identifier, channel identifier, and memory address within the destination SoC. For burst operations, the master device may generate a sequence of configuration words corresponding to consecutive memory addresses or consecutive channels.

[0120] At step 1430, the master device constructs one or more command frames that embed a configuration word into a defined field structure. For example, each command frame may include a synchronization mode or preamble, a device selection field (such as an Integrated Circuit Select (ICSEL) field identifying the target SoC), a command type field indicating a write or load operation, an addressing field specifying a target memory circuitry or register (e.g., an SRAM slice for a channel index or a global configuration register), an optional burst length or sequence control field, and a payload field carrying the configuration word assembled at step 1420. In this way, a single command frame can carry both addressing information and RF configuration data for one or more RF channels.

[0121] At step 1440, the master device serializes the framed information into a bit stream. Command frames can be loaded into a transmit buffer or shift register and converted into a serial DATA_out signal under the control of the transmit clock (CLK_out). In some implementations, the most significant bit within each frame is transmitted first, and the least significant bit is transmitted last, and the DATA_out timing is aligned with a selected edge of CLK_out, allowing the destination SoC to reliably sample the serial stream. A chip select or framing signal (CSB_out) can depict the interval at which valid command data exists on DATA_out.

[0122] At step 1450, the master device sends a serialized command stream to the SoC. The master device's SerDes output driver emits DATA_out and CLK_out (and, if used, CSB_out) to one or more high-speed links connected to the root SoC in the hierarchy, such as regarding... Figure 10 and Figure 11 The described layout. Then, the same serialized command stream can be consumed by the root SoC and forwarded to downstream additional SoCs via repeater functionality.

[0123] In optional step 1460, the master device issues a command or otherwise induces a synchronous loading of the RF configuration at the destination SoC. In one example, once the relevant configuration frame has been sent, the master device appends a dedicated LOAD command frame to the command stream. In another example, the master device sets an external load control signal, such as the Fast_LOAD pin, after a defined timing interval. In either case, the destination SoC can respond by transferring the configuration value to be processed from the first-level memory circuitry to the second-level valid memory circuitry, thereby applying the new RF configuration information to the RF signaling units in a coordinated manner.

[0124] Overall, Method 1400 illustrates how a master device can participate in the disclosed command allocation architecture by translating high-level RF control targets into framed digital command streams compatible with the SoC's on-chip configuration memory and repeater architecture. Method 1400 can be used with... Figure 12 and Figure 13 The device-side approach collaborates to provide end-to-end control flow that supports scalable, low-latency RF configurations across large multi-SoC arrays.

[0125] For illustrative and descriptive purposes, the foregoing description of various embodiments of the claimed subject matter has been provided. It is not intended to be exhaustive or to limit the claimed subject matter to the precise forms disclosed. Many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described in order to best illustrate the principles of the invention and its practical application, thereby enabling those skilled in the art to understand the claimed subject matter, the various embodiments, and the various modifications suitable for the particular intended use.

[0126] While the detailed description depicts certain embodiments and the expected best mode, the technology can be practiced in many ways, no matter how detailed the detailed description may appear. Embodiments can vary significantly in their implementation details while still being covered by the specification. Specific terms used in describing certain features or aspects of the various embodiments should not be construed as implying that the term is redefined herein as limited to any particular characteristic, feature, or aspect of the technology associated with that term. Generally, the terms used in the following claims should not be construed as limiting the technology to the specific embodiments disclosed in the specification, unless such terms are expressly defined herein. Therefore, the actual scope of this technology includes not only the disclosed embodiments but also all equivalent ways of practicing or implementing the embodiments.

[0127] The language used in this specification has been chosen primarily for readability and guidance purposes. It may not have been chosen to depict or limit the subject matter. Therefore, it is intended that the scope of this technology is not limited to specific embodiments, but rather to any claims published in the application based thereon. Thus, the disclosure of various embodiments is intended to illustrate, and not limit, the scope of the technology as set forth in the appended claims. Furthermore, it should be noted that the various circuits disclosed herein can be described using computer-aided design tools and expressed (or represented) as data and / or instructions embodied in various computer-readable media in terms of their behavior, register transfers, logic components, transistors, layout geometry, and / or other characteristics. Formats of documents and other objects that can implement such circuit expressions include, but are not limited to, formats supporting behavioral languages ​​such as C, Verilog, and VHDL; formats supporting register-level description languages ​​such as RTL; formats supporting geometric description languages ​​such as GDSII, GDSIII, GDSIV, CIF, MEBES; and any other suitable formats or languages. Computer-readable media that can embody such formatted data and / or instructions include, but are not limited to, various forms of non-volatile storage media (e.g., optical, magnetic, or semiconductor storage media).

Claims

1. An electronic device, comprising: Multiple radio frequency (RF) signal units; The on-chip serializer / deserializer SerDes receiver is configured to receive a serial bit stream from an upstream device; as well as A control circuit, coupled to the SerDes receiver and the plurality of RF signal units, is configured to: Extract (1) device identifier and (2) radio frequency (RF) configuration information from the serial bit stream; Determine whether the device identifier matches a predetermined identifier of the electronic device; as well as In response to determining that the device identifier matches the predetermined identifier of the electronic device, the plurality of RF signal units are controlled according to the RF configuration information. The serial bit stream is a command stream in which the device identifier and the RF configuration information are encoded in a defined field data structure, and The command stream is different from the payload data stream used to transmit user data.

2. The electronic device according to claim 1, wherein, The RF configuration information includes one or more of the following: gain control field, phase control field, or frequency status field.

3. The electronic device according to claim 2, wherein, The RF configuration information also includes one or more of the following: operation identifier, burst mode identifier, or memory address.

4. The electronic device according to claim 1, in, A portion of the command stream encodes multiple burst access commands, and The control circuit is configured to automatically execute the plurality of burst access commands in sequence.

5. The electronic device according to claim 4, wherein, The memory addresses allocated to the RF signal units to be accessed by the plurality of burst access commands are contiguous.

6. The electronic device according to claim 4, wherein, The multiple burst access commands update the phase information and gain information of the corresponding number of RF signal units respectively, and each RF signal unit has a different pair of phase information and gain information.

7. The electronic device according to claim 1, in, The RF configuration information includes a channel identifier that identifies a selected RF signal element among the plurality of RF signal elements, and Controlling the plurality of RF signal units includes storing corresponding RF configuration information in an on-chip memory circuit and at a location assigned to the selected RF signal unit, such that the RF configuration information is applied to the selected RF signal unit.

8. The electronic device according to claim 1, further comprising: The first memory circuit is configured to store RF configuration information to be processed. The second memory circuit is configured to store valid RF configuration information; The control circuit is further configured as follows: In response to a load signal, the valid RF configuration information in the second memory circuit is replaced with the RF configuration information to be processed in the first memory circuit.

9. The electronic device according to claim 8, wherein, The control circuit is also configured to: The plurality of RF signal units update the valid RF configuration information synchronously based on the load signal.

10. The electronic device according to claim 8, wherein, The electronic device includes a dedicated input terminal configured to receive the load signal from an upstream electronic device.

11. The electronic device according to claim 8, wherein, The electronic device includes a dedicated output terminal configured to output the load signal to one or more downstream electronic devices.

12. The electronic device according to claim 8, wherein, The load signal is provided within the command stream.

13. The electronic device according to claim 1, further comprising: On-chip repeater The control circuitry is configured to forward the serial bit stream from the on-chip receiver to the on-chip repeater in response to determining that the on-chip repeater is enabled, so as to provide a cascading command path to downstream electronic devices.

14. The electronic device according to claim 13, wherein, The control circuit is configured as follows: Whether to enable the on-chip repeater is determined based on the repeater enable signal.

15. The electronic device according to claim 13, wherein, The control circuit is configured as follows: The serial bit stream is redriven by generating a forwarded serial bit stream with a signal level defined by the on-chip repeater.

16. The electronic device according to claim 13, wherein, The serial bit stream includes a synchronous mode, and wherein the control circuit is configured to: Detect the synchronization mode; and The serial bit stream is forwarded with timing alignment based on the synchronization mode.

17. The electronic device according to claim 1, wherein, The serial bit stream includes a synchronous mode, and wherein the control circuit is configured to: Detect the synchronization mode; and The synchronization mode is used to align the parsing of the device identifier and / or the RF configuration information.

18. The electronic device according to claim 17, wherein, The synchronization mode includes the alternating bit mode.

19. The electronic device according to claim 1, wherein, The electronic device includes: A control input is configured to receive a chip select signal, and wherein the control circuitry is configured to parse the command stream in response to a set state of the chip select signal.

20. The electronic device according to claim 19, wherein, The control circuit is configured as follows: After setting the chip select signal, the synchronization mode in the bitstream is detected; and In response to the detection of the synchronization mode, the defined field data structure is parsed.

21. The electronic device according to claim 19, wherein, The control circuit is configured as follows: The defined field data structure is parsed using bits from the command stream received during the set interval of the chip select signal.

22. The electronic device according to claim 21, wherein, The control circuit is configured as follows: Exclude a predetermined number of bit times of preamble received after the chip select signal has been set; and Excludes a predetermined number of subsequent bit times received before the chip select signal is reset.

23. The electronic device according to claim 1, further comprising: A clock circuit is configured to provide a sampling clock for capturing the serial bit stream, wherein the clock circuit includes a phase-locked loop (PLL).

24. The electronic device according to claim 1, wherein, The control circuit is configured as follows: Status information is provided to the upstream device via an uplink interface, the data rate of which is lower than the data rate of the on-chip SerDes receiver.

25. The electronic device according to claim 1, wherein, The control circuit is configured as follows: A read operation is performed in response to a read command in the command stream, and readback data representing the stored RF configuration information is output.

26. The electronic device according to claim 1, further comprising: Multiple storage blocks, corresponding to the multiple RF signal units; as well as A shared bus is coupled to the multiple memory blocks. Each memory block includes a tri-state output circuit configured to selectively drive the shared bus when the memory block is selected, and to float the shared bus when the memory block is not selected.

Images