Parallel distribution matching method, device and system for probabilistic amplitude shaping

Abstract

The present application relates to a communication method and a communication apparatus. An exemplary method includes demultiplexing information bits from a code block into two bit streams, the two bit streams corresponding to a real dimension and an imaginary dimension, respectively; splitting each of the two bit streams into sub-blocks; performing bit labeling on each of the sub-blocks in parallel to obtain a shaped amplitude bit sequence; and transmitting a signal including the shaped amplitude bits.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 573,877, filed April 3, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application generally relates to wireless communication, and more particularly to a parallel distributed matching method, apparatus and system for probability amplitude shaping. Background Technology

[0004] Wireless communication systems such as fourth-generation (4G) systems (e.g., long-term evolution (LTE) systems) and fifth-generation (5G) systems (e.g., new radio (NR) systems) have been deployed to provide various types of applications, such as messaging, voice, video, and other data.

[0005] Current wireless standards (e.g., 5G NR) support modulation constellations with different modulation orders (i.e., different constellation sizes) and forward error correction (FEC) at various code rates (CR). For example, the 5G NR standard uses quadrature amplitude modulation (QAM) as its modulation scheme and low-density parity check (LDPC) codes as its FEC scheme. When transmitting and receiving data, the modulation order and CR form a transmission pattern corresponding to a specific spectral efficiency or transmission rate within a given time and bandwidth, which can be measured in bits per second per Hertz (bps). This combination of modulation order and CR is called a modulation and coding scheme (MCS). The MCS is selected to best match the channel conditions.

[0006] Typically, a wireless channel can be characterized by its channel capacity, which represents the maximum amount of information that can be transmitted "error-free" through the channel in the presence of noise, measured in bits per channel. The transmission rate obtained with the chosen MCS cannot exceed the channel capacity. The difference between the transmission rate and the channel capacity can be represented by the difference in signal-to-noise ratio (SNR). In 5G NR, for higher-order MCSs, a significant gap between the transmission rate and channel capacity can be observed with QAM and LDPC codes. In some cases, higher-order MCSs such as 1024-QAM or 4096-QAM can be used, which requires a high SNR. However, due to the high frequency reuse density in modern cellular systems, achieving a high SNR may be difficult due to noise and inter-cell interference. Summary of the Invention

[0007] One or more implementations of this application provide a communication method and a communication apparatus. The techniques described in this application can realize parallel distribution matching for probability amplitude shaping.

[0008] According to a first aspect, a method is provided. The method includes: demultiplexing information bits from a code block into two bit streams, the two bit streams corresponding to a real dimension and an imaginary dimension, respectively; dividing each bit stream into sub-blocks; performing bit tagging on each sub-block in parallel to obtain an integer amplitude bit sequence; and transmitting a signal including the integer amplitude bits.

[0009] Referring to the first aspect, in some implementations, the number of sub-blocks is determined as follows: ,in This represents the number of information bits from the code block used for each of the real and imaginary dimensions. This represents the floor operation on the real number x, and Ksb represents the predefined maximum size of the sub-block.

[0010] Referring to the first aspect, in some implementations, each sub-block within a sub-block comprises the same number of bits, the number being expressed as... , where Kp represents the number of padding bits appended to the end of the code block such that Ka+Kp is divisible by M, and where Kp is a non-negative integer.

[0011] Referring to the first aspect, in some implementations, for M sub-blocks, the size of sub-block i is Ksb, where i = 1, ..., M-1, and the size of sub-block M is... .

[0012] Referring to the first aspect, in some implementations, performing bit marking includes: mapping information bits in each sub-block of the sub-block to an integer amplitude; performing bit marking on the integer amplitude to generate a bit sequence for each sub-block of the sub-block; and multiplexing the bit sequence for each sub-block of the sub-block to obtain an integer amplitude bit sequence.

[0013] Referring to the first aspect, in some implementations, performing bit marking includes: mapping information bits in each sub-block to an integer amplitude; multiplexing the integer amplitudes of each sub-block to obtain an integer amplitude sequence; and performing bit marking on the integer amplitudes to obtain an integer amplitude bit sequence.

[0014] Referring to the first aspect, in some implementations, performing bit marking on the shaped amplitude includes performing bit marking on the shaped amplitude with Qm-2 bits, where Qm is the modulation order of the complex symbol to be transmitted on the signal.

[0015] Referring to the first aspect, in some implementations, the shaping amplitude is non-uniformly distributed.

[0016] According to a second aspect, a method is provided. The method includes: receiving a signal including shaped amplitude bits. The shaped amplitude bits are generated by: demultiplexing information bits from a code block into two bit streams, the two bit streams corresponding to the real and imaginary dimensions, respectively; dividing each of the two bit streams into sub-blocks; and performing bit marking on each sub-block in parallel to obtain a sequence of shaped amplitude bits. The method further includes: acquiring the shaped amplitude bits.

[0017] According to a third aspect, a communication apparatus is provided. The communication apparatus includes: an encoder for performing operations including: generating bit groups corresponding to complex-valued symbols, wherein each group includes Qm bits corresponding to one of the complex-valued symbols, where Qm is the modulation order of the complex-valued symbol, and the Qm bits include shaping amplitude bits and parity bits, wherein the Qm bits have bit markers corresponding to the sign and amplitude of the corresponding complex-valued symbol; reordering the bit markers to generate reordered bit markers, such that at least a portion of the shaping amplitude bits have reordered bit markers corresponding to the sign of the corresponding complex-valued symbol, and the parity bits have reordered bit markers corresponding to the amplitude of the corresponding complex-valued symbol; and mapping the bit groups to the complex-valued symbols based on the reordered bit markers. The communication apparatus further includes: an interface coupled to the encoder for transmitting a signal including the complex-valued symbols.

[0018] According to a fourth aspect, a communication apparatus is provided. The communication apparatus includes: an interface for receiving a signal including shaped amplitude bits, wherein the shaped amplitude bits are generated by: demultiplexing information bits from a code block into two bit streams, the two bit streams corresponding to a real dimension and an imaginary dimension, respectively; dividing each of the two bit streams into sub-blocks; and performing bit tagging on each sub-block in parallel to obtain a sequence of shaped amplitude bits. The communication apparatus further includes: a decoder for obtaining the shaped amplitude bits.

[0019] According to a fifth aspect, an apparatus is provided. The apparatus includes one or more processors and one or more memories. The one or more memories store instructions that, when executed by the one or more processors, cause the apparatus to perform the method according to the first aspect or one or more implementations of the first aspect, or the second aspect or one or more implementations of the second aspect.

[0020] According to a sixth aspect, a communication system is provided. The communication system includes: a first communication device for performing the method according to the first aspect or one or more implementations of the first aspect. The communication system further includes: a second communication device for performing the method according to the second aspect or one or more implementations of the second aspect.

[0021] According to a seventh aspect, a communication system is provided. The communication system includes a first communication device according to a third aspect or one or more implementations of the third aspect. The communication system also includes a second communication device according to a fourth aspect or one or more implementations of the fourth aspect.

[0022] According to an eighth aspect, a non-transitory computer-readable storage medium is provided. The non-transitory computer-readable storage medium stores instructions that, when executed by a device, cause the device to perform the method according to the first aspect or one or more implementations of the first aspect, or the second aspect or one or more implementations of the second aspect. Attached Figure Description

[0023] Figure 1 A schematic diagram of an exemplary communication system is shown;

[0024] Figure 2 Another exemplary communication system is shown;

[0025] Figure 3 An example is shown of a device communicating wirelessly with at least one of two devices in a communication system;

[0026] Figure 4 Examples of units or modules in a device or apparatus are shown;

[0027] Figure 5 An example of a coding and modulation chain for probabilistic amplitude shaping (PAS) is shown;

[0028] Figure 6 An example of a DM processing chain for the distribution matching (DM) module is shown;

[0029] Figure 7 An example of parallel DM processing for each I / Q dimension is shown;

[0030] Figure 8 Another example of parallel DM processing for each I / Q dimension is shown;

[0031] Figure 9 Another example of parallel DM processing for each I / Q dimension is shown, where each distribution matcher is a bit-level distribution matcher;

[0032] Figure 10 An example of a parallel DM process according to this disclosure is shown. Detailed Implementation

[0033] To reduce the gap between achievable transmission rates and channel capacity, probabilistic amplitude shaping (PAS) has been proposed in recent years. For additive white Gaussian channels (AWGNs), which can be used to model wireless channels using available channel information at the transmitter, Gaussian input distributions have been shown to achieve sufficient channel capacity. However, for practical wireless systems, constructing such Gaussian input distributions is difficult due to finite transmission lengths, and flexible transmission lengths corresponding to variable transmission resources should be supported by well-performing input distributions.

[0034] In 5G NR, First, FEC is performed to add redundancy to the data via LDPC coding, followed by Rate Matching to select the amount of coded bits that matches the allocated transmission resources. The rate-matched selected coded bits are then uniformly mapped to QAM symbols, which are subsequently transmitted over the radio channel. This MCS scheme is called Bit-Interleaved Coded Modulation (BICM) in 5G NR, where the amplitude of the QAM symbols is uniformly distributed. BICM is easy to implement because the modulation module and FEC module are used separately. Furthermore, at low modulation orders and average modulation orders (e.g., ≤256-QAM), the gap between this scheme and channel capacity is small. However, for higher-order MCSs such as 1024-QAM or 4096-QAM, a significant gap can be observed. To address this challenge in selecting higher-order MCSs, PAS can be applied to reduce the gap with channel capacity. Under PAS, information bits are mapped to the amplitude of QAM symbols according to a non-uniform amplitude distribution. More specifically, such amplitudes can follow a Maxwell-Boltzmann (MB) distribution, which approximates a Gaussian distribution. FEC can then be performed on the bits representing the shaped amplitude to generate a uniformly distributed set of parity bits. The parity bits and a subset of optional information bits are then mapped to the sign of QAM symbols. The amplitude and sign form QAM symbols in both the in-phase (I) and quadrature (Q) dimensions, which are then transmitted together via the wireless channel. By jointly performing modulation and FEC by shaping the amplitude of QAM symbols to an MB distribution and using FEC to generate the signs of QAM symbols, the gap between transmission rate and channel capacity can be reduced. Therefore, the benefit of PAS is increased transmission rate for a given SNR (i.e., under given channel conditions). Furthermore, PAS requires a lower SNR to achieve a given transmission rate, thus saving transmit power.

[0035] Various aspects of this disclosure relate to coding and modulation chains for PAS (Programmable Array of Signals and Modulations). The coding chain may include multiple modules with inputs of information bits and outputs of QAM symbols. The proposed coding can be flexibly used for switching between PAS and non-PAS schemes.

[0036] Figure 1A schematic diagram of an exemplary communication system 100 is shown. The communication system 100 (which may be a wireless system) includes a radio access network (RAN) 120. The RAN 120 may be a next-generation radio access network or a traditional (e.g., 5G, 4G, 3G, or 2nd generation, 2G) radio access network. One or more electronic devices (EDs) 110a, 110b, 110c, 110d, 110e, 110f, 110g, 110h, 110i, 110j (collectively referred to as 110) may interconnect with each other or be connected to one or more network nodes (170a, 170b, collectively referred to as 170) in the RAN 120. A core network 130 may be part of the communication system and may depend on or be independent of the radio access technology used in the communication system 100. The communication system 100 may also include a public switched telephone network (PSTN) 140, the Internet 150, and other networks 160.

[0037] Figure 2 An exemplary communication system 100 is illustrated. Typically, the communication system 100 enables multiple wireless or wired components to transmit data and other content. The purpose of the communication system 100 may be to provide content such as voice, data, video, and / or text via broadcast, multicast, unicast, etc. The communication system 100 can operate by sharing resources such as carrier spectrum bandwidth among its constituent components. The communication system 100 may include terrestrial communication systems and / or non-terrestrial communication systems. The communication system 100 can provide a wide range of communication services and applications (e.g., earth monitoring, remote sensing, passive sensing and positioning, navigation and tracking, autonomous delivery and mobility, etc.). The communication system 100 can provide high availability and robustness through the joint operation of terrestrial and non-terrestrial communication systems. For example, integrating a non-terrestrial communication system (or components thereof) into a terrestrial communication system can create a heterogeneous network that can be considered as comprising multiple layers. Compared to traditional communication networks, heterogeneous networks can achieve better overall performance through efficient multi-link joint operation, more flexible function sharing, and faster physical layer link switching between terrestrial and non-terrestrial networks.

[0038] Terrestrial communication systems and non-terrestrial communication systems can be subsystems of a communication system. Figure 2In the example shown, communication system 100 includes electronic devices (EDs) 110a, 110b, 110c, and 110d (collectively referred to as ED110), radio access networks (RANs) 120a and 120b, a non-terrestrial communication network 120c, a core network 130, a public switched telephone network (PSTN) 140, the Internet 150, and other networks 160. RANs 120a and 120b include corresponding base stations (BSs) 170a and 170b, which can be collectively referred to as terrestrial transmit and receive points (T-TRPs) 170a and 170b. The non-terrestrial communication network 120c includes access nodes 172, which can be collectively referred to as non-terrestrial transmit and receive points (NT-TRPs) 172.

[0039] Any ED 110 can be used alternatively or additionally to connect to, access, or communicate with any T-TRP 170a, T-TRP 170b, and NT-TRP 172, Internet 150, core network 130, PSTN 140, other network 160, or any combination thereof. In some examples, ED 110a can communicate with T-TRP 170a via terrestrial air interface 190a for uplink and / or downlink transmission. In some examples, ED 110a, 110b, 110c, and 110d can also communicate directly with each other via one or more sidelink air interfaces 190b. In some examples, ED 110d can communicate with NT-TRP 172 via non-terrestrial air interface 190c for uplink and / or downlink transmission.

[0040] Air interfaces 190a and 190b can employ similar communication technologies, such as any suitable wireless access technology. For example, communication system 100 can implement one or more channel access methods in air interfaces 190a and 190b, such as code division multiple access (CDMA), space division multiple access (SDMA), time division multiple access (TDMA), frequency division multiple access (FDMA), orthogonal FDMA (OFDMA), or single-carrier FDMA (SC-FDMA) (also known as discrete Fourier transform spread OFDMA (DFT-s-OFDMA)). Air interfaces 190a and 190b can employ other higher-dimensional signal spaces, which may involve combinations of orthogonal and / or non-orthogonal dimensions.

[0041] The non-terrestrial air interface 190c enables communication between the ED 110d and one or more NT-TRP 172s via a wireless link (or simply a link). For some examples, the link is a dedicated connection for unicast transmission, a connection for broadcast transmission, or a connection between a group of ED 110s and one or more NT-TRP 172s for multicast transmission.

[0042] RANs 120a and 120b communicate with core network 130 to provide various services, such as voice, data, and other services, to EDs 110a, 110b, and 110c. RANs 120a and 120b and / or core network 130 may communicate directly or indirectly with one or more other RANs (not shown), which may or may not be directly served by core network 130, and may or may not use the same radio access technology as RANs 120a, RAN 120b, or both. Core network 130 may also serve as a gateway access between (i) RANs 120a and 120b or EDs 110a, 110b, and 110c, or both, and (ii) other networks (e.g., PSTN 140, Internet 150, and other networks 160). Furthermore, some or all of EDs 110a, 110b, and 110c may include the ability to communicate with different wireless networks via different radio links using different radio technologies and / or protocols. Instead of wireless communication (or other than wireless communication), ED 110a, 110b, and 110c can also communicate with service providers or exchanges (not shown) via wired communication channels and with the Internet 150. PSTN 140 may include a circuit-switched telephone network for providing plain old telephone service (POTS). The Internet 150 may include a network of computers and / or subnets (internal networks) and incorporate protocols such as Internet Protocol (IP), Transmission Control Protocol (TCP), and User Datagram Protocol (UDP). ED 110a, 110b, and 110c may be multimode devices capable of operating under various wireless access technologies and include multiple transceivers required to support these wireless access technologies.

[0043] Figure 3Another example of ED 110 and base stations 170a, 170b, and / or 170c is shown. ED 110 is used to connect people, objects, machines, etc. ED 110 can be widely used in a variety of scenarios, including, for example, cellular communication, device-to-device (D2D), vehicle-to-everything (V2X), peer-to-peer (P2P), machine-to-machine (M2M), machine-type communication (MTC), Internet of Things (IoT), virtual reality (VR), augmented reality (AR), mixed reality (MR), metaverse, digital twins, industrial control, autonomous driving, telemedicine, smart grids, smart furniture, smart offices, smart wearable devices, smart transportation, smart cities, drones, robots, remote sensing, passive sensing, positioning, navigation and tracking, autonomous delivery, and mobility, etc.

[0044] Each ED 110 represents any suitable end-user equipment for wireless operation and may include (or be referred to as): user equipment / device (UE), wireless transmit / receive unit (WTRU), mobile station, fixed or mobile subscriber unit, cellular phone, station (STA), machine-type communication (MTC) device, personal digital assistant (PDA), smartphone, laptop, computer, tablet, wireless sensor, consumer electronics, smartbook, vehicle, automobile, truck, bus, train, or IoT device, wearable device (e.g., watch, glasses, head-mounted device, etc.), industrial equipment, or a device comprising or including the aforementioned devices (e.g., communication module, modem, or chip), etc. Next-generation Ed 110 may be referred to using other terms. Base stations 170a and 170b are T-TRPs and will be referred to hereinafter as T-TRP 170. Similarly, Figure 3As shown, NT-TRP will be referred to as NT-TRP 172 below. Each ED 110 connected to T-TRP 170 and / or NT-TRP 172 can be dynamically or semi-statically started (i.e., established, activated, or enabled), shut down (i.e., released, deactivated, or disabled), and / or configured in response to one or more of connectivity availability and connectivity necessity.

[0045] ED 110 includes a transmitter 201 and a receiver 203 coupled to one or more antennas 204. Only one antenna 204 is shown in the figures to avoid congestion. Alternatively, one, part, or all of the antennas 204 may be panels. For example, the transmitter 201 and receiver 203 may be integrated as a transceiver. The transceiver is used to modulate data or other content for transmission by at least one antenna 204 or a network interface controller (NIC). The transceiver may also be used to demodulate data or other content received through at least one antenna 204. Each transceiver includes any suitable structure for generating signals for wireless or wired transmission and / or processing signals received wirelessly or wiredly. Each antenna 204 includes any suitable structure for transmitting and / or receiving wireless or wired signals.

[0046] ED 110 includes at least one memory 208. Memory 208 stores instructions and data used, generated, or acquired by ED 110. For example, memory 208 may store software instructions or modules for implementing some or all of the functions and / or embodiments described herein and executed by one or more processing units (e.g., processor 210). Each memory 208 includes any suitable one or more volatile and / or non-volatile storage and retrieval devices. Any suitable type of memory can be used, such as random-access memory (RAM), read-only memory (ROM), hard disk, optical disk, subscriber identity module (SIM) card, memory stick, secure digital (SD) memory card, on-processor cache, etc.

[0047] ED 110 may also include one or more input / output devices (not shown) or interfaces (e.g., connected to...). Figure 1(Wired interface of Internet 150 in the network). Input / output devices or interfaces support interaction with users or other devices in the network. Each input / output device or interface includes any suitable structure for providing or receiving information from the user and / or for network interface communication. Suitable structures include, for example, speakers, microphones, numeric keypads, keyboards, displays, touch screens, etc.

[0048] ED 110 includes a processor 210 for performing operations, including operations related to: preparing uplink transmissions to be transmitted to NT-TRP 172 and / or T-TRP 170; processing downlink transmissions received from NT-TRP 172 and / or T-TRP 170; and processing sidelink transmissions transmitted to and from another ED 110. Processing operations related to preparing uplink transmissions may include operations such as encoding, modulation, transmit beamforming, and generating symbols for transmission. Processing operations related to processing downlink transmissions may include operations such as receive beamforming, demodulation, and decoding of received symbols. According to an embodiment, the downlink transmissions may be received by receiver 203 possibly using receive beamforming, and processor 210 may extract signaling from the downlink transmissions (e.g., by detecting and / or decoding signaling). For example, an example of signaling may be a reference signal transmitted by NT-TRP 172 and / or T-TRP 170. In some embodiments, processor 210 performs transmit beamforming and / or receive beamforming based on beam direction indications (e.g., beam angle information (BAI)) received from T-TRP 170. In some embodiments, processor 210 may perform operations related to network access (e.g., initial access) and / or downlink synchronization, such as operations related to detecting synchronization sequences, decoding, and acquiring system information. In some embodiments, processor 210 may perform channel estimation, for example, using reference signals received from NT-TRP 172 and / or from T-TRP 170.

[0049] Although not shown, processor 210 may be part of transmitter 201 and / or receiver 203. Although not shown, memory 208 may be part of processor 210.

[0050] The processing components of processor 210, transmitter 201, and receiver 203 may each be implemented by the same or different one or more processors for executing instructions stored in memory (e.g., memory 208). Alternatively, some or all of the processing components of processor 210, transmitter 201, and receiver 203 may each be implemented using dedicated circuitry, such as a programmable field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), graphics processing unit (GPU), or hardware accelerators such as artificial intelligence (AI) accelerators.

[0051] In some implementations, the T-TRP 170 can also have other names, such as base station, basetransceiver station (BTS), wireless base station, network node, network device, network-side device, transmit / receive node, NodeB, evolved NodeB (eNodeB or eNB), home eNodeB, next-generation NodeB (gNB), transmission point (TP), site controller, access point (AP), wireless router, relay station, ground node, ground network device, ground base station, base band unit (BBU), remote radio unit (RRU), active antenna unit (AAU), remote radio head (RRH), central unit (CU), distributed unit (DU), positioning node, etc. The T-TRP 170 can be a macro BS, pico BS, relay node, or host node, or a combination thereof. T-TRP 170 may refer to the aforementioned device or a component within the aforementioned device (e.g., a communication module, modem, or chip).

[0052] In some embodiments, the various parts of T-TRP 170 may be distributed. For example, some modules of T-TRP 170 may be located remotely from the device housing the antenna 256 for T-TRP 170 and may be coupled to the device housing the antenna 256 via a communication link (not shown) sometimes referred to as a fronthaul (e.g., a common public radio interface (CPRI)). Therefore, in some embodiments, the term "T-TRP 170" may also refer to network-side modules that perform processing operations such as determining the location of ED 110, resource allocation (scheduling), message generation, and encoding / decoding, and are not necessarily part of the device housing the antenna 256 of T-TRP 170. These modules may also be coupled to other T-TRPs. In some embodiments, T-TRP 170 may actually be multiple T-TRPs that operate together, for example, by using coordinated multicast transmissions to serve ED 110.

[0053] T-TRP 170 includes at least one transmitter 252 and at least one receiver 254 coupled to one or more antennas 256. Only one antenna 256 is shown in the figures to avoid congestion. Alternatively, one, some, or all of the antennas 256 may be panels. The transmitter 252 and receiver 254 may be integrated as a transceiver. T-TRP 170 also includes a processor 260 for performing operations including operations related to: preparing downlink transmissions to ED 110, processing uplink transmissions received from ED 110, preparing backhaul transmissions to NT-TRP 172, and processing transmissions received from NT-TRP 172 via backhaul. Processing operations related to preparing downlink or backhaul transmissions may include operations such as encoding, modulation, precoding (e.g., multiple-input multiple-output (MIMO) precoding), transmit beamforming, and generating symbols for transmission. Processing operations related to transmissions received in the uplink or received via backhaul may include receive beamforming, demodulation of received symbols, and decoding of received symbols. Processor 260 may also perform operations related to network access (e.g., initial access) and / or downlink synchronization, such as generating the contents of a synchronization signal block (SSB) and generating system information. In some embodiments, processor 260 also generates an indication of beam direction (e.g., BAI), which scheduler 253 may schedule for transmission. Processor 260 performs other network-side processing operations described herein, such as determining the location of ED 110 and the location for deploying NT-TRP 172. In some embodiments, processor 260 may generate signaling, for example, to configure one or more parameters of ED 110 and / or one or more parameters of NT-TRP 172. Any signaling generated by processor 260 is transmitted by transmitter 252. It should be noted that “signaling” as used herein may alternatively be referred to as control signaling. Signaling can be transmitted in physical layer control channels such as the physical downlink control channel (PDCCH). In this case, the signaling can be called dynamic signaling. Signaling transmitted in the downlink physical layer control channel is called downlink control information (DCI). Signaling transmitted in the uplink physical layer control channel is called uplink control information (UCI). Signaling transmitted in the sidelink physical layer control channel is called sidelink control information (SCI).Signaling can be included in higher-layer (e.g., above the physical layer) data packets transmitted on physical layer data channels such as the Physical Downlink Shared Channel (PDSCH). In this case, the signaling can be referred to as higher-layer signaling, static signaling, or semi-static signaling. Higher-layer signaling can also refer to radio resource control (RRC) protocol signaling or media access control-control element (MAC-CE) signaling.

[0054] Scheduler 253 may be coupled to processor 260. Scheduler 253 may be included within T-TRP 170 or may operate separately therefrom. Scheduler 253 may schedule uplink, downlink, lateral, and / or backlink transmissions, including issuing scheduling authorizations and / or configuring scheduling-free (e.g., "configuration authorization") resources. T-TRP 170 also includes memory 258 for storing information and data. Memory 258 stores instructions and data used, generated, or collected by T-TRP 170. For example, memory 258 may store software instructions or modules for implementing some or all of the functions and / or embodiments described herein and executed by processor 260.

[0055] Although not shown, processor 260 may constitute part of transmitter 252 and / or receiver 254. Furthermore, although not shown, processor 260 may implement scheduler 253. Although not shown, memory 258 may constitute part of processor 260.

[0056] The processing components of processor 260, scheduler 253, transmitter 252, and receiver 254 may each be implemented by the same or different one or more processors for executing instructions stored in memory (e.g., memory 258). Alternatively, some or all of the processing components of processor 260, scheduler 253, transmitter 252, and receiver 254 may be implemented using dedicated circuitry, such as a programmed FPGA, hardware accelerator (e.g., GPU or AI accelerator), or ASIC.

[0057] Although the NT-TRP 172 is shown as an example of a drone only, it can be implemented in any suitable non-terrestrial form, such as satellites and high-altitude platforms including international mobile telecommunications base stations and unmanned aerial vehicles. Furthermore, in some implementations, the NT-TRP 172 may use other names, such as a non-terrestrial node, a non-terrestrial network device, or a non-terrestrial base station. The NT-TRP 172 includes a transmitter 272 and a receiver 274 coupled to one or more antennas 280. Only one antenna 280 is shown in the figures to avoid congestion. One, some, or all of the antennas may alternatively be panels. The transmitter 272 and receiver 274 may be integrated as a transceiver. The NT-TRP 172 also includes a processor 276 for performing operations related to: preparing downlink transmissions to ED 110, processing uplink transmissions received from ED 110, preparing return transmissions to T-TRP 170, and processing transmissions received from T-TRP 170 via return. Processing operations related to preparing to transmit downlink or backhaul transmissions may include operations such as encoding, modulation, precoding (e.g., MIMO precoding), transmit beamforming, and generating symbols for transmission. Processing operations related to processing transmissions received in the uplink or received via backhaul may include operations such as receive beamforming, demodulating received symbols, and decoding received symbols. In some embodiments, processor 276 implements transmit beamforming and / or receive beamforming based on beam direction information (e.g., BAI) received from T-TRP 170. In some embodiments, processor 276 may generate signaling, for example, for configuring one or more parameters of ED110. In some embodiments, NT-TRP 172 implements physical layer processing but does not implement higher-layer functions, such as those at the medium access control (MAC) layer or radio link control (RLC) layer. Since this is only an example, NT-TRP 172 may more generally implement higher-layer functions in addition to physical layer processing.

[0058] The NT-TRP 172 also includes a memory 278 for storing information and data. Although not shown, a processor 276 may form part of the transmitter 272 and / or the receiver 274. Although not shown, the memory 278 may form part of the processor 276.

[0059] The processing components of processor 276, transmitter 272, and receiver 274 can each be implemented using one or more processors, which may be the same or different, to execute instructions stored in memory (e.g., memory 278). Alternatively, some or all of the processing components of processor 276, transmitter 272, and receiver 274 can be implemented using dedicated circuitry, such as a programmed FPGA, hardware accelerator (e.g., GPU or AI accelerator), or ASIC. In some embodiments, NT-TRP 172 may actually be multiple NT-TRPs operating together to serve ED 110, for example, through cooperative multicasting.

[0060] T-TRP 170, NT-TRP 172 and / or ED 110 may include other components, but these components have been omitted for clarity.

[0061] according to Figure 4 One or more steps of the methods in the embodiments provided herein may be performed by the corresponding units or modules. Figure 4 Units or modules in devices such as ED 110, T-TRP 170, or NT-TRP 172 are illustrated. For example, signals may be transmitted or output by a transmitting unit or transmitting module. Signals may be received or input by a receiving unit or receiving module. Signals may be processed by a processing unit or processing module. Other steps may be performed by an artificial intelligence (AI) module or a machine learning (ML) module. The corresponding units or modules may be implemented using hardware, one or more components or devices executing software, or a combination thereof. For example, one or more of these units or modules may be circuits such as integrated circuits. Examples of integrated circuits include programmed FPGAs, GPUs, or ASICs. For example, one or more of these units or modules may be logical, such as logical functions executed by software instructions executed by a circuit, a portion of an integrated circuit, or a processor. It should be understood that if these modules are implemented using software executed by a processor, etc., then these modules may be retrieved by the processor, in whole or in part, individually or collectively, for processing, in single or multiple instances, and these modules themselves may include instructions for further deployment and instantiation.

[0062] Although not shown, the transmitting module and the receiving module can be part of a transceiver module, or they can be combined to form a transceiver module. The transceiver module can also be called an interface module, or simply an interface, and is used for input and output operations.

[0063] Further details regarding ED 110, T-TRP 170, and NT-TRP 172 are known to those skilled in the art. Therefore, these details are omitted herein.

[0064] Some aspects of this disclosure relate to distribution matching (DM) for QAM modulation in a PAS. In a PAS employing QAM modulation, each complex-valued QAM symbol corresponds to a signal point with two dimensions: in-phase (I) and quadrature (Q). DM can be performed separately for each I / Q dimension to map information bits to symbol amplitudes according to a desired distribution (e.g., a Maxwell-Boltzmann (MB) distribution). Furthermore, DM for the I and Q dimensions can be performed in parallel to improve system throughput (in bits per second).

[0065] Since DM is a serial process, performing DM on a large number of information bits as input may reduce system throughput due to increased processing latency, making it unsuitable for high-throughput applications.

[0066] This disclosure includes embodiments of a method for performing parallel DM for a PAS to improve system throughput and reduce processing latency. To this end, information bits from a code block (CB) can be divided into multiple subblocks (SBs), and then DM can be performed in parallel for all SBs. The parallel DM process can be performed only once, i.e., only one round of DM is performed to obtain the shaped amplitude bits. The method may also include detailed parameter settings for the SBs to be specified.

[0067] Various aspects of this disclosure relate to coding and modulation chains for PAS. Figure 5 The general coding and modulation chain for PAS 500 is shown. More specifically, the coding and modulation process of PAS can be given as follows:

[0068] (1) First, the information bits from each CB are demultiplexed into two bit streams. One bit stream, called the first bit stream, is used as the input to the distribution matcher 502, while the other bit stream, called the second bit stream, remains unchanged. The DM encodes the first bit stream according to a non-uniform distribution (e.g., an MB distribution) to generate an output bit stream. This output bit stream of the DM is called the shaped amplitude bit, which is mapped to the amplitude of the QAM symbol. Since QAM has two dimensions, I and Q, distribution matching is performed separately and in parallel for each I / Q dimension. Furthermore, QAM amplitudes can be mapped to shaped amplitude bits using Gray notation or rules based on nature.

[0069] (2) The shaping amplitude bits and a second bitstream called the uniform information bits are used as inputs to the forward error correction (FEC) coding module 504. The FEC can be a systematic code such as an LDPC code or a Turbo code. The FEC encodes the input bits according to the code rate (CR) to generate parity bits (called uniform parity bits). The shaping amplitude bits and the uniform information bits are the systematic bits of the FEC codeword. In some FEC codes (e.g., the LDPC codes used in 5G NR), some systematic bits are punctured to enhance decoding performance; that is, the codeword may not include punctured systematic bits. In this case, puncturing can be performed on the uniform information bits to maintain the shaping gain provided by the shaping amplitude bits. Therefore, in the input of FEC encoding, the uniform information bits can be placed before the shaping amplitude bits.

[0070] (3) The shaped amplitude bits, (punctured) uniform information bits, and uniform parity bits are multiplexed to form the FEC mother codeword. After the rate matching process, the transmitted coded bits can then be mapped to QAM symbols by the constellation mapper 506.

[0071] When using QAM modulation Figure 6 An exemplary process 600 for DM processing of a DM module is illustrated, for example... Figure 5 The DM module 502 is shown. An exemplary process 600 is as follows:

[0072] (1) The information bits in each code block (CB) are first demultiplexed into two bit streams by the DEMUX module 602, and each bit stream can enter the corresponding DM for I / Q dimensions 604a and 604b. Therefore, there are two parallel DM processing chains, each for one of I / Q dimensions 604a or 604b. In some implementations, a portion of the information bits in the CB (i.e., not all bits of the CB) can enter the DM.

[0073] (2) For I / Q dimensions 604a or 604b, the information bits are mapped to an amplitude sequence (called shaped amplitude). The amplitudes in this sequence can follow a non-uniform distribution, such as the MB distribution.

[0074] (3) Subsequently, at 606a or 606b, each amplitude in the shaped amplitude of the I / Q dimension is labeled with (Qm-2) bits, where Qm represents the modulation order. The shaped amplitude can be labeled using a Gray map or a natural-based map.

[0075] (4) The bit markers of the I-dimensional and Q-dimensional integer amplitudes are multiplexed by the MUX module 608 to obtain the integer amplitude bit sequence.

[0076] exist Figure 6 In this context, for each I / Q dimension, the DM 604 and bit-marking 606 processes, which map information bits to integer amplitudes and integer amplitudes to integer amplitude bits, can be further parallelized to improve system throughput. To this end, the information bits for each I / Q dimension (i.e., after demultiplexing) can be divided into multiple subblocks (SBs). Then, the information bits of each SB are mapped to an integer amplitude sequence via DM, and all SBs can be processed in parallel. Therefore, system throughput can be significantly improved. Here, a single round of parallel DM is performed to obtain integer amplitude bits, thus meeting the high throughput requirements.

[0077] The parameter setting process for the proposed parallel DM processing is described below:

[0078] (1) Let Ka represent the number of information bits from CB used in each I / Q dimension. Therefore, the number of information bits from CB used in the I and Q dimensions is: .

[0079] (2) Then, the Ka information bits are demultiplexed into M SBs. The number of SBs (M) is determined as follows: Here, This represents the floor function of a real number x, i.e., the smallest integer greater than or equal to x. Furthermore, Ksb represents the maximum size of SB, and Ksb can be defined in the standard. In some examples, Ka can be chosen as a multiple of Ksb to make M an integer.

[0080] (3) The size of SB can be determined by either of the following two methods:

[0081] (i) Method 1: The size S(i) of each SB-i can be the same, and is determined by... Given i = 1, ..., M, where As defined above. For example, when Ka=2000 and Ksb=256, we get... The size of each SB is In some cases, if Ka is not divisible by M, Kp padding bits (e.g., "0" bits) can be appended to the end of CB, where This ensures that Ka+Kp is divisible by M. In this case, the size S(i) of each SB-i can be the same, and is determined by... Given, among which .

[0082] (ii) Method 2: The size S(i) of each SB-i (where i=1,…,M-1) can be the same and equal to Ksb, i.e.: S(1)=S(2)=…=S(M-1)=Ksb. Meanwhile, the size S(M) of SB-M is determined by… Given. For example, if Ka = 2000, Ksb = 256 and Then S(1) = S(2) = ... = S(7) = 256 and .

[0083] Figure 7 The parallel DM processing for each I / Q dimension is shown as 700. Figure 7 As shown, in this example, for each of the three SBs obtained after demultiplexing at 702 points, first in DM processing is performed at the SB, and the DM output of each SB is a shaped amplitude sequence. In this sequence, each shaped amplitude is then represented by a bit marker at 706a-c, which is defined in the standard. The output of the bit marker module is the bit sequence for each SB. Subsequently, the bit sequences of all SBs are multiplexed at 708 to obtain the shaped amplitude bit sequence.

[0084] Figure 8 An alternative method 800 for parallel DM processing per I / Q dimension is shown. For example... Figure 8 As shown, in this example, for each of the three SBs obtained after demultiplexing at position 802, first in The distribution matching process is performed at the SB, and the DM output of each SB is a shaped amplitude sequence. Subsequently, the shaped amplitude sequences of all SBs are multiplexed by 806 to obtain a single-path shaped amplitude sequence. In this sequence, each shaped amplitude is then represented by a bit tag 808, which is defined in the standard. The output of the bit tag module is the bit sequence of all SBs.

[0085] exist Figure 7 and Figure 8 Examples of distribution matching methods performed in the code can be constant distribution matcher (CCDM), shell mapping (SM), prefix-free code distribution matcher (PCDM), or enumerative sphereshaping (ESS). In these methods, shaping is performed at the amplitude level, meaning the output of the DM is a sequence of shaped amplitudes.

[0086] Alternatively, some embodiments include a distribution matching method (e.g., bit-level distribution matching) where shaping is performed at the bit level rather than the amplitude level. Therefore, the output of DM is a bit sequence, i.e., no bit-marking process is required. Figure 9 The parallel DM process 900 is shown, where the DM for each SB is a bit-level distributed matcher between demultiplexing at 902 and multiplexing at 906. .therefore, Figure 9 There is no bit tag module in it.

[0087] Figure 10 An example of a parallel DM process 1000 according to this disclosure is shown. Process 1000 can be performed by an ED or a network node (e.g., Figure 1 The encoder of the device shown is executed.

[0088] At position 1002, the encoder demultiplexes the information bits from the code block into two bit streams, which correspond to the real dimension and the imaginary dimension (e.g., the I / Q dimension), respectively.

[0089] At position 1004, the encoder divides each of the two bitstreams into sub-blocks. In some implementations, the number of sub-blocks is determined to be... Ka represents the number of information bits from the code block used for each of the real and imaginary dimensions. This represents the floor operation on the real number x, and Ksb represents the predefined maximum size of the sub-block.

[0090] In some implementations, each sub-block within a sub-block comprises the same number of bits, represented as Where Kp represents the number of padding bits appended to the end of the code block such that Ka + Kp is divisible by M, and Kp is a non-negative integer. In some implementations, for M sub-blocks, the size of sub-block i is Ksb, where i = 1, ..., M-1, and the size of sub-block M is... .

[0091] At position 1006, the encoder performs bit tagging in parallel on each sub-block to obtain an integer amplitude bit sequence. In some implementations, performing bit tagging includes: mapping information bits in each sub-block to an integer amplitude; performing bit tagging on the integer amplitude to generate a bit sequence for each sub-block; and multiplexing the bit sequence for each sub-block to obtain the integer amplitude bit sequence.

[0092] In some implementations, performing bit marking includes: mapping information bits in each sub-block to an integer amplitude; multiplexing the integer amplitudes of each sub-block to obtain an integer amplitude sequence; and performing bit marking on the integer amplitudes to obtain an integer amplitude bit sequence.

[0093] In some implementations, bit-marking the shaped amplitude involves bit-marking the shaped amplitude with Qm-2 bits, where Qm is the modulation order of the complex symbol to be transmitted on the signal. In some implementations, the shaped amplitude is non-uniformly distributed.

[0094] At position 1008, the encoder sends a signal including amplitude-shaping bits for transmission over the air interface.

[0095] In some implementations, the reversal process corresponding to process 1000 can be performed by the decoder of the ED or network node. In an exemplary reversal process, the decoder receives a signal from the interface including shaped amplitude bits, which are generated by: demultiplexing the information bits from the code block into two bit streams, corresponding to the real and imaginary dimensions respectively; dividing each of the two bit streams into sub-blocks; and performing bit tagging on each sub-block in parallel to obtain the sequence of shaped amplitude bits. The decoder can then obtain the shaped amplitude bits.

[0096] This disclosure covers a variety of embodiments, including not only method embodiments but also other embodiments, such as apparatus embodiments and embodiments related to non-transitory computer-readable storage media. Embodiments may be incorporated individually or in combination with the features disclosed herein.

[0097] While this disclosure refers to illustrative embodiments, it is not intended to be construed as limiting. Those skilled in the art will recognize various modifications and combinations of the illustrative embodiments, as well as other embodiments of this disclosure, upon referring to this description.

[0098] Features disclosed herein in the context of any particular embodiment may be implemented additionally or alternatively in other embodiments. For example, method embodiments may be implemented additionally or alternatively in apparatus, system, and / or computer program product embodiments. Furthermore, although embodiments have been described primarily in the context of methods and apparatus, other implementations are contemplated, such as as instructions stored on one or more non-transitory computer-readable media. Such media may store programs or instructions to perform any of the various methods consistent with this disclosure.

[0099] In this disclosure, the terms “a” and “an” are defined to mean “at least one”, that is, unless otherwise stated, these terms do not exclude multiple items.

[0100] In this disclosure, terms such as “substantially,” “usually,” and “about” that modify the values, conditions, or characteristics of features of exemplary embodiments should be understood to indicate that the values, conditions, or characteristics are defined within acceptable tolerances to ensure that exemplary embodiments operate correctly in their intended applications.

[0101] In this disclosure, unless otherwise stated, the terms “connection” and “coupling” and their derivatives and variations herein refer to any direct or indirect structural or functional connection or coupling between two or more elements. For example, a connection or coupling between elements can be acoustic, mechanical, optical, electrical, thermal, logical, or any combination thereof.

[0102] In this disclosure, expressions such as “matched,” “matching,” and “matched” (including variations and derivatives thereof) are intended to refer to the state in which two or more elements are identical or within a predetermined tolerance of each other. That is, these terms not only cover matching two elements “completely” or “perfectly consistent,” but also matching two or more elements “substantially” or “subjectively,” and providing a higher or better match among multiple matching possibilities.

[0103] In this disclosure, the expression "based on" is intended to mean "at least partially based on," that is, the expression can mean "based on only" or "partially based on," and therefore should not be interpreted narrowly. More specifically, the expression "based on" can also be understood as "depends on," "represents," "indicates," "related to," or similar expressions.

[0104] In this disclosure, the terms "system" and "network" are used interchangeably in different embodiments of this application. "At least one" means one or more, and "multiple" means two or more. The term "and / or" describes the association relationship between related objects and indicates that three possible relationships may exist. For example, A and / or B can indicate three cases: only A exists, both A and B exist, and only B exists, where A and B can be singular or plural. The character " / " indicates an "OR" relationship between related objects. "At least one of the following items" or similar expressions indicate any combination of these items, including a single item or any combination of multiple items. For example, "at least one of A, B, or C" includes: only A; only B; only C; A and B; A and C; B and C; or A, B, and C; "at least one of A, B, and C" can also be understood as: only A; only B; only C; A and B; A and C; B and C; or A, B, and C. In addition, unless otherwise stated, the ordinal numbers such as "first" and "second" in the embodiments of this application are used to distinguish multiple objects, and are not used to limit the order, time order, priority or importance of multiple objects.

[0105] Those skilled in the art will understand that embodiments of this application can be provided as a method, apparatus (or system), computer-readable storage medium, or computer program product. Therefore, this application can take the form of a purely hardware embodiment, a purely software embodiment, or an embodiment combining software and hardware. Furthermore, this application can take the form of a computer program product implemented on one or more computer-readable storage media (including, but not limited to, disk storage, optical storage, etc.) that include computer-readable program code.

[0106] This application is described in conjunction with flowcharts and / or block diagrams of the methods, apparatus (systems), and computer program products according to this application. It should be understood that computer program instructions can be used to implement each process and / or each block in the flowcharts and / or block diagrams, as well as combinations of processes and / or blocks in the flowcharts and / or block diagrams. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing apparatus, and enable the machine to execute these instructions. When executed by a processor of any computer or programmable data processing apparatus, these instructions cause the apparatus to implement the specific functions described in one or more processes in the flowcharts and / or one or more blocks in the block diagrams. Alternatively, the computer program instructions can be stored in a computer-readable storage medium capable of instructing a computer or another programmable data processing apparatus to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means. The instruction means implement the specific functions in one or more processes in the flowcharts and / or one or more blocks in the block diagrams.

[0107] These computer program instructions may alternatively be loaded onto a computer or another programmable data processing device to perform a series of operations and steps on that computer or other programmable device, thereby generating a computer-implemented process. Therefore, the instructions that execute on a computer or other programmable device provide steps for implementing one or more processes in a flowchart and / or one or more boxes in a block diagram that describe a specific function.

[0108] Obviously, those skilled in the art can make various modifications and variations to this disclosure without departing from the scope of this application. This disclosure is intended to cover such modifications and variations as long as they fall within the protection scope defined by the appended claims and their equivalents.

Claims

1. A method, characterized in that, include: The information bits from the code block are demultiplexed into two bit streams, which correspond to the real part dimension and the imaginary part dimension, respectively. Each of the two bitstreams is divided into sub-blocks; Bit tagging is performed on each sub-block in parallel to obtain an shaped amplitude bit sequence; Send a signal that includes shaped amplitude bits.

2. The method according to claim 1, characterized in that, The number of sub-blocks is determined to be: Ka represents the number of information bits from the code block used for each of the real and imaginary dimensions. This represents the floor operation on the real number x, and Ksb represents the predefined maximum size of the sub-block.

3. The method according to claim 2, characterized in that, Each sub-block in the sub-block comprises the same number of bits, the number being expressed as... , where Kp represents the number of padding bits appended to the end of the code block such that Ka+Kp is divisible by M, and where Kp is a non-negative integer.

4. The method according to claim 2, characterized in that, For M sub-blocks, the size of sub-block i is Ksb, where i = 1, ..., M-1, and the size of sub-block M is... .

5. The method according to any one of claims 1 to 4, characterized in that, Performing the bit tagging includes: Map the information bits in each sub-block of the sub-block to an integer amplitude; Bit tagging is performed on the shaped amplitude to generate a bit sequence for each sub-block in the sub-block; The bit sequence of each sub-block in the sub-block is multiplexed to obtain the shaped amplitude bit sequence.

6. The method according to any one of claims 1 to 4, characterized in that, Performing the bit tagging includes: Map the information bits in each sub-block of the sub-block to an integer amplitude; The shaping amplitude of each sub-block in the sub-block is multiplexed to obtain a shaping amplitude sequence; Bit tagging is performed on the shaped amplitude to obtain the shaped amplitude bit sequence.

7. The method according to claim 6, characterized in that, Performing bit marking on the shaped amplitude includes: performing bit marking on the shaped amplitude with Qm-2 bits, where Qm is the modulation order of the complex symbol to be transmitted on the signal.

8. The method according to any one of claims 5 to 7, characterized in that, The shaping amplitude is non-uniformly distributed.

9. A method, characterized in that, include: Receive a signal including shaped amplitude bits, wherein the shaped amplitude bits are generated in the following manner: The information bits from the code block are demultiplexed into two bit streams, which correspond to the real part dimension and the imaginary part dimension, respectively. Each of the two bitstreams is divided into sub-blocks; Bit tagging is performed on each sub-block in parallel to obtain an shaped amplitude bit sequence; Obtain the shaped amplitude bits.

10. The method according to claim 9, characterized in that, The number of sub-blocks is determined to be: Ka represents the number of information bits from the code block used for each of the real and imaginary dimensions. This represents the floor operation on the real number x, and Ksb represents the predefined maximum size of the sub-block.

11. The method according to claim 10, characterized in that, Each sub-block in the sub-block comprises the same number of bits, the number being expressed as... , where Kp represents the number of padding bits appended to the end of the code block such that Ka+Kp is divisible by M, and where Kp is a non-negative integer.

12. The method according to claim 10, characterized in that, For M sub-blocks, the size of sub-block i is Ksb, where i = 1, ..., M-1, and the size of sub-block M is... .

13. The method according to any one of claims 9 to 12, characterized in that, Performing the bit tagging includes: Map the information bits in each sub-block of the sub-block to an integer amplitude; Bit tagging is performed on the shaped amplitude to generate a bit sequence for each sub-block in the sub-block; The bit sequence of each sub-block in the sub-block is multiplexed to obtain the shaped amplitude bit sequence.

14. The method according to any one of claims 9 to 12, characterized in that, Performing the bit tagging includes: Map the information bits in each sub-block of the sub-block to an integer amplitude; The shaping amplitude of each sub-block in the sub-block is multiplexed to obtain a shaping amplitude sequence; Bit tagging is performed on the shaped amplitude to obtain the shaped amplitude bit sequence.

15. The method according to claim 14, characterized in that, Performing bit marking on the shaped amplitude includes: performing bit marking on the shaped amplitude with Qm-2 bits, where Qm is the modulation order of the complex symbol to be transmitted on the signal.

16. The method according to any one of claims 13 to 15, characterized in that, The shaping amplitude is non-uniformly distributed.

17. A communication device, characterized in that, include: An encoder is used to perform operations including the following: The information bits from the code block are demultiplexed into two bit streams, which correspond to the real part dimension and the imaginary part dimension, respectively. Each of the two bitstreams is divided into sub-blocks; Bit tagging is performed on each sub-block in parallel to obtain an shaped amplitude bit sequence; An interface, coupled to the encoder, is used to transmit signals including shaped amplitude bits.

18. The communication device according to claim 17, characterized in that, The number of sub-blocks is determined to be: Ka represents the number of information bits from the code block used for each of the real and imaginary dimensions. This represents the floor operation on the real number x, and Ksb represents the predefined maximum size of the sub-block.

19. The communication device according to claim 18, characterized in that, Each sub-block in the sub-block comprises the same number of bits, the number being expressed as... , where Kp represents the number of padding bits appended to the end of the code block such that Ka+Kp is divisible by M, and where Kp is a non-negative integer.

20. The communication device according to claim 18, characterized in that, For M sub-blocks, the size of sub-block i is Ksb, where i = 1, ..., M-1, and the size of sub-block M is... .

21. The communication device according to any one of claims 17 to 20, characterized in that, Performing the bit tagging includes: Map the information bits in each sub-block of the sub-block to an integer amplitude; Bit tagging is performed on the shaped amplitude to generate a bit sequence for each sub-block in the sub-block; The bit sequence of each sub-block in the sub-block is multiplexed to obtain the shaped amplitude bit sequence.

22. The communication device according to any one of claims 17 to 20, characterized in that, Performing the bit tagging includes: Map the information bits in each sub-block of the sub-block to an integer amplitude; The shaping amplitude of each sub-block in the sub-block is multiplexed to obtain a shaping amplitude sequence; Bit tagging is performed on the shaped amplitude to obtain the shaped amplitude bit sequence.

23. The communication device according to claim 22, characterized in that, Performing bit marking on the shaped amplitude includes: performing bit marking on the shaped amplitude with Qm-2 bits, where Qm is the modulation order of the complex symbol to be transmitted on the signal.

24. The communication device according to any one of claims 21 to 23, characterized in that, The shaping amplitude is non-uniformly distributed.

25. A communication device, characterized in that, include: An interface for receiving signals including shaped amplitude bits, wherein the shaped amplitude bits are generated in the following manner: The information bits from the code block are demultiplexed into two bit streams, which correspond to the real part dimension and the imaginary part dimension, respectively. Each of the two bitstreams is divided into sub-blocks; Bit tagging is performed on each sub-block in parallel to obtain an shaped amplitude bit sequence; A decoder is used to obtain the shaped amplitude bits.

26. An apparatus, characterized in that, include: A processor for causing the apparatus to perform the method according to any one of claims 1 to 16.

27. A communication system, characterized in that, The communication system includes: a first communication device for performing the method according to any one of claims 1 to 8; and a second communication device for performing the method according to any one of claims 9 to 16.

28. A non-transitory computer-readable storage medium, characterized in that, It stores instructions that, when executed by the device, cause the device to perform the method according to any one of claims 1 to 16.

29. A computer program, characterized in that, Includes a program for execution by a processor, the program including instructions for performing the method according to any one of claims 1 to 16.

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