Determining distance between reference node and measurement node of multipoint network

Abstract

A method can include generating, at one or more nodes of a multipoint network, round-trip pulses, a respective round-trip pulse of the round-trip pulses selectively passing through one or more of: internal circuitry of the one or more nodes, or a physical medium between a first node and a second node of the one or more nodes; determining, based at least in part on a measurement window error and a measured round-trip of the round-trip pulses within a predetermined measurement window, an overall delay of the one or more nodes and an internal delay; and determining, based at least in part on the measured round-trip of the round-trip pulses and the internal delay of at least one of the first node or the second node, a distance between the first node and the second node.

Description

Priority Statement

[0001] This application claims the benefit of U.S. Provisional Patent Application Serial No. 63 / 548,565, filed on February 1, 2024, entitled “DETERMINING DISTANCE BETWEEN AREFERENCE NODE AND A MEASURED NODE”, the disclosure of which is incorporated herein by reference in its entirety. Background Technology

[0002] Network topology discovery is the process of learning information about the topology of a network (e.g., distances, but not limited to this). Attached Figure Description

[0003] To facilitate the identification of any particular element or action in the discussion, the most important number in the figure labels refers to the figure number of the element when it was first introduced.

[0004] Figure 1 This is a schematic diagram of a device for determining internal delay based on one or more examples.

[0005] Figure 2 It is a schematic diagram depicting a system for measuring the distance between RN and MN according to one or more examples.

[0006] Figure 3 This is a timing diagram illustrating a method for determining round-trip time based on one or more examples.

[0007] Figure 4 It is a diagram depicting the changes to the TD control register and topology discovery register of the TC14 specification for OA according to one or more examples.

[0008] Figure 5 An example procedure for determining the distance between a first node and a second node, both located on a multipoint network / Ethernet segment, is illustrated based on one or more examples.

[0009] Figure 6 An example procedure for measuring the round trip pulses when a predetermined fixed measurement window is a fixed number of round trips (e.g., denoted as a fixed pulse count) is illustrated according to one or more examples.

[0010] Figure 7 An example process is illustrated, based on one or more examples, for enhancing measurement resolution by counting both the rising and falling edges of a clock signal during a fixed number of round trips.

[0011] Figure 8 An example procedure for detecting and processing partial or fractional round trips of a round trip pulse is illustrated, based on one or more examples.

[0012] Figure 9 An example process for detecting and processing partial or fractional round trips via round-trip pulses is illustrated according to one or more examples.

[0013] Figure 10 An example procedure for measuring the round trip of a pulse when a predetermined fixed measurement window is of fixed duration is illustrated according to one or more examples.

[0014] Figure 11 It is a block diagram of a circuit that can be used in some examples to implement the various functions, operations, actions, processes or methods disclosed herein. Detailed Implementation

[0015] In the following detailed description, reference is made to the accompanying drawings, which form part of this disclosure, and specific examples of embodiments in which this disclosure may be practiced are shown by way of example. These embodiments have been described in sufficient detail to enable those skilled in the art to practice this disclosure. However, other embodiments may be utilized, and changes in structure, materials, and processes may be made without departing from the scope of this disclosure.

[0016] The illustrations presented herein are not intended to be actual views of any particular method, system, device, or structure, but are merely idealized representations used to describe embodiments of this disclosure. The figures presented herein are not necessarily drawn to scale. For the reader's convenience, similar structures or components in the figures may retain the same or similar designations; however, similar designations do not imply that the structure or component must be identical in size, composition, configuration, or any other attribute.

[0017] The following description may include examples to assist those skilled in the art in practicing the embodiments disclosed herein. The use of the terms “exemplary,” “by example,” and “for example” indicates that the related descriptions are illustrative, and while the scope of this disclosure is intended to cover examples and legal equivalents, the use of such terms is not intended to limit the embodiments or the scope of this disclosure to the specified parts, steps, features, or functions, etc.

[0018] It should be readily understood that the components of the embodiments generally described herein and illustrated in the accompanying drawings can be arranged and designed in a variety of different configurations. Therefore, the following description of various embodiments is not intended to limit the scope of this disclosure, but rather to represent various embodiments only. While various aspects of the embodiments may be presented in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated otherwise.

[0019] Furthermore, the specific embodiments shown and described are merely examples and should not be construed as the only way to implement this disclosure unless otherwise indicated herein. Components, circuits, and functions may be shown in block diagram form so as not to obscure this disclosure with unnecessary detail. Rather, the specific embodiments shown and described are merely exemplary and should not be construed as the only way to implement this disclosure unless otherwise indicated herein. Additionally, block definitions and logical partitioning between blocks are examples of specific embodiments. It will be apparent to those skilled in the art that this disclosure can be practiced with many other partitioning solutions. In most cases, details regarding timing considerations, etc., have been omitted, as such details are not necessary for obtaining a full understanding of this disclosure and are within the capabilities of those skilled in the art.

[0020] Those skilled in the art will understand that information and signals can be represented using any of a variety of different techniques and methods. For clarity of presentation and description, some figures may illustrate a signal as a single signal. It should be understood by those skilled in the art that a signal may represent a signal bus, wherein the bus may have multiple bit widths, and this disclosure can be implemented on any number of data signals, including a single data signal.

[0021] The various exemplary logic blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed using a general-purpose processor, a special-purpose processor, a digital signal processor (DSP), an integrated circuit (IC), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic components, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor (which may also be referred to herein as a host processor or simply host) may be a microprocessor, but in alternative embodiments, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration. When a general-purpose computer including a processor executes computational instructions (e.g., software code) related to the embodiments of this disclosure, the general-purpose computer is considered a special-purpose computer.

[0022] The implementation scheme can be described based on a process depicted as a flowchart, schematic diagram, structural diagram, or block diagram. While a flowchart can describe operable actions as a continuous process, many of these actions can be performed in another sequence, in parallel, or substantially simultaneously. Furthermore, the order of actions can be rearranged. A process can correspond to a method, thread, function, procedure, subroutine, or subroutine, but is not limited thereto. Furthermore, the methods disclosed herein can be implemented in hardware, software, or both. If implemented in software, functions can be stored or transmitted as one or more instructions or code onto a computer-readable medium. Computer-readable media includes both computer storage media and communication media, including any medium that facilitates the transfer of a computer program from one location to another.

[0023] Any reference to elements in this document using names such as “first”, “second”, etc., does not limit the number or order of those elements unless such limitation is explicitly stated. Rather, these names may be used herein as a convenient way to distinguish between two or more elements or instances of elements. Thus, referring to a first element and a second element does not imply that only two elements can be used there, or that the first element must somehow precede the second element. Furthermore, unless otherwise stated, a group of elements may include one or more elements.

[0024] As used herein, the term “substantially” means, and includes, the degree to which a given parameter, attribute, or condition is satisfied with a small degree of variance, such as, for example, within acceptable manufacturing tolerances, as would be understood by one of ordinary skill in the art. By way of example, depending on the particular parameter, attribute, or condition that is substantially satisfied, the parameter, attribute, or condition may be satisfied at least 90%, at least 95%, or even at least 99%.

[0025] As used herein, any relational terms (such as "above", "below", "on", "under", "upper", "lower", etc., but not limited thereto) are used for clarity and convenience in understanding this disclosure and the accompanying drawings, and such relational terms do not imply or depend on any particular preference, orientation or order unless the context clearly indicates otherwise.

[0026] In this description, the term "coupled" and its derivatives may be used to indicate that two elements cooperate or interact with each other. When an element is described as "coupled" to another element, then the element may be in direct physical or electrical contact, or there may be an intermediary element or layer. In contrast, when an element is described as "directly coupled" to another element, then there is no intermediary element or layer. The term "connection" is used interchangeably with the term "coupled" in this specification and has the same meaning unless otherwise expressly indicated or the context will otherwise indicate to a person skilled in the art.

[0027] As used herein, the terms “assert,” “deassert,” and their derivatives used with respect to the pin and the component are referred to respectively to assert or deassert the signal associated with the pin (e.g., a signal specifically assigned to or to the pin, but not limited thereto).

[0028] 10BASE-T1S is IEEE 802.3cg ™ The 802.3cg standard specifies the physical layer (PHY) behavior for physical layer collision avoidance (PLCA) on multipoint networks. A multipoint network is a communication network in which multiple devices are connected to and share a single physical medium, such as, but not limited to, twisted-pair or coaxial cable. The Open Alliance (OA) Technical Committee (TC) 14 supplements this with other specifications for PHYs used in automotive applications. For example, OA's TC14 has specifications for topology discovery (TD).

[0029] The specification for TD begins with a single pulse transmitted from the reference node (RN) to the measurement node (MN). Upon reception, the MN sends a pulse to the RN after a fixed internal delay. Upon reception, the RN sends another pulse to the MN after a fixed internal delay. This completes one round trip (RT). The number of RTs over a predetermined duration depends on the set duration, the distance between the MN and RN, and their respective internal delays. Using these parameters, the distance between the RN and MN (e.g., the length of the cable between the RN and MN) can be calculated. The internal delay can be similarly calculated using pulses and pulse echoes from pins that connect the MN or RN to the physical medium (rather than the remote node).

[0030] The inventors of this disclosure recognize that the predetermined duration is not necessarily divisible by the RT duration (i.e., the predetermined duration is not necessarily an integer multiple of the RT duration). The TC14 specification of the OA does not account for fractional RTs, and therefore the last RT may be lost if the duration ends before the last RT completes. Therefore, measurements based on RT counts may be inaccurate up to approximately the duration of the RT.

[0031] One or more examples generally involve a method for determining the distance between MN and RN (here, distance refers to the length of the physical medium). The duration of a predetermined number of RTs performed within the internal networks of MN and RN (from the TX to RX to TX pins) is determined. The determined duration divided by the predetermined number of RTs yields the internal delay. The duration of a predetermined number of RTs performed on the physical medium (MN to RN to MN) is determined. The determined duration divided by the predetermined number of RTs minus the corresponding internal delays of MN and RN yields the time required to travel the length of the physical medium.

[0032] One or both of RN and MN can determine the distance. The internal delays of both MN and RN are used in the distance formula. MN and RN can share their internal delay values. As a non-limiting example, the TC14 specification states that RN and MN can request internal delay values ​​via Ethernet frame exchange. As another non-limiting example, when MN uses pulses to measure its internal delay, the pulse stream is visible to either (including RN) on the bus, so RN and MN can coordinate their respective finite state machines (FSMs) so that RN can measure the time between a set count of MN pulses.

[0033] In either case, there are three levels: the internal delay of RN, the internal delay of MN, and the RN-MN measurement delay. There is symmetry here—the pulse flow of each level will be on the cable and visible to both nodes. Therefore, each node can be measured independently three (3) times. In some cases (e.g., when the stub is long, but not limited to this), comparing the two values ​​can provide better resolution.

[0034] By measuring the duration of a predetermined number of round trips instead of counting round trips within a fixed duration, the inaccuracy is reduced to a fraction of a clock cycle, an improvement over methods that rely on a fixed duration. Using this technique, the inaccuracy is limited to the clock period of the clock used to determine the duration of the predetermined number of round trips at the internal network or on the physical medium. As long as the corresponding number is known, different numbers of round trips can be used at the internal network compared to those on the physical medium.

[0035] The techniques discussed herein for determining distances can be used in place of the existing techniques in the TC14 specification of the OA. Alternatively or additionally, the techniques discussed herein for determining distances can be selectively used in conjunction with the existing techniques in the TC14 specification of the OA.

[0036] One or more embodiments generally relate to a method for determining the distance between MN and RN. A fractional RT time is determined, which is the duration from the start of the last pulse to the end of a predetermined duration. The fractional RT time can be measured by a clock with an appropriately high clock rate. The fractional RT time is subtracted from the predetermined duration, and the distance between MN and RN is determined using the adjusted predetermined duration.

[0037] Figure 1 This is a schematic diagram of an apparatus 100 for determining internal latency according to one or more examples. Apparatus 100 may include a physical layer device (PHY) in a topology discovery (TD) mode for determining internal latency. Apparatus 100 may be referred to herein as "node 100".

[0038] Node 100 includes internal circuitry 102, a transmitter 104, a receiver 106, and a connection 108. Node 100 also includes measurement circuitry 114, logic circuitry 116, and pulse generator circuitry 118, which are operable at least when node 100 is in topology discovery mode.

[0039] Pulse generator circuit 118 is a hardware and / or firmware-driven component that generates (e.g., generates or initiates (e.g., via transmitter 104, but not limited to)) pulses, including but not limited to round-trip pulses for measuring delays and distances in a multipoint network, as discussed below. In one or more examples, pulse generator circuit 118 may be responsible for generating pulses at specific intervals or in response to commands from logic circuit 116. In one or more examples, pulse generator circuit 118 creates signals (“round-trip pulses”) that traverse the physical medium depicted between the internal circuitry 102 of node 100 and the node (a portion 120 of the physical medium may be referred to as “physical medium portion 120”), as discussed below.

[0040] Measurement circuit 114 is a hardware and / or firmware-driven component that captures and quantifies measurement data, including information about the round trips of pulses generated by pulse generator circuit 118 within a specified measurement window, as discussed below. Generally, measurement circuit 114 measures how many pulses fit within a predetermined duration of the measurement window, or how much time has elapsed for a predetermined number of pulses. As discussed below, measurement circuit 114 can collect information about partial round trips across the boundaries of the measurement window (if applicable). In one or more examples, measurement circuit 114 may, depending on the design, provide measurement data indicating whether the number of measurement round trips should be increased or decreased, or whether the measurement window should be expanded or reduced (adjustable measurement window scenario), as discussed below.

[0041] The logic circuit 116 is a control or processing block—for example, implemented as digital logic, a microcontroller, or firmware—that analyzes the measurement data it utilizes to determine delays (delay of the physical medium, total delay, and internal delay of the node), as well as the measurement window error 122, as discussed below.

[0042] When in topology discovery mode, transmitter 104 transmits pulse 110, and receiver 106 receives pulse echo 112, which is a reflection of pulse 110 from connection 108. Internal circuitry 102 couples receiver 106 to transmitter 104. Pulse echo 112 propagates from receiver 106 to transmitter 104 via internal circuitry 102. The leading edge of the pulse is sampled via a local clock (not depicted), and when received at transmitter 104, the sample is used by an edge detector (not depicted) to detect the leading edge of pulse echo 112. Upon detection of the leading edge of pulse echo 112, the RT count is updated. Simultaneously, rising edge timers (or counters) and falling edge timers (or counters) are continuously incremented by the rising and falling edges of the clock, respectively. When the RT count equals a predetermined threshold (e.g., a predetermined number of RTs, but not limited to this), the timers stop, the average of the timer values ​​is taken (summed and divided by 2), and the average timer value divided by the predetermined number of RTs gives the internal delay of node 100.

[0043] In one or more examples, the internal system clock of node 100 is used as the timing source for a timer. In topology discovery, inaccuracy limits the resolution of the measured distance. As a non-limiting example, the inaccuracy can be reduced by half a clock cycle (if the duration is measured on both the rising and falling edges of a clock exhibiting an average 50% duty cycle). Resolution scales with clock frequency. Resolution is not a function of internal delay or cable length. Appropriate trade-offs between resolution and measurement time are design choices based on the specific operating conditions, as presented as a non-limiting example.

[0044] Figure 2 It is a schematic diagram depicting a system 200 for measuring the distance between RN and MN according to one or more examples.

[0045] In one or more examples, the corresponding node in reference node 202 and measurement node 204 may be node 100.

[0046] The corresponding internal delays of reference node 202 and measurement node 204 can be measured—either the node measures its own delay (e.g., using an internal loopback), or another node on the bus measures its delay by observing the pulse activity of that node. In one or more examples, as a non-limiting example, sharing or access to these internal delay values ​​can occur via direct frame exchange; here, since all pulses are visible on the bus, the delay of the measurement node or reference node is sent to another node via Ethernet messages or similar data protocols, or by monitoring the pulse stream on the shared medium. In the latter example, reference node 202 and measurement node 204 can coordinate their respective finite state machines (FSMs), so one node (e.g., RN) can precisely observe how many pulses (or how much time) the other node (MN) requires in its internal loopback. Once the two internal delays (MN and RN) are known to the node performing the distance calculation (reference node 202), that node subtracts the sum of these internal delays from the total measurement round-trip time, as discussed below. The result corresponds to the time traveled through physical medium 206.

[0047] In the hypothetical example, the measurement is performed with the RT count set to 1000. In this example, it is assumed that the actual time to the measurement time can deviate by 0.5 clock cycles, and the asynchronous pulse edge is sampled through any edge of a 25 MHz clock.

[0048] The determined distance error is 20 / 1000, or 20 picoseconds. The determined internal delay error is 20 / 1000, or 20 picoseconds. Inaccuracy = 20 + 20 + 20 = 60 picoseconds. Therefore, the distance error is 0.6 cm. This is a 20x or greater improvement over the existing distance measurement technology in the OA TC14 specification.

[0049] Figure 3 This is a signal timing diagram 300 illustrating a method for determining round-trip time according to one or more examples. The method incorporates a fine timer / counter into the measurement of the total round-trip duration of the transmitted pulses, specifically to capture a fraction of the remaining time, as discussed below. The remaining time and the number of completed round trips (which can be determined by...) Figure 3 Information (using an undepicted coarse or integer counter for counting) is used to adjust the predefined measurement time, and the adjusted measurement time can be used in distance calculations.

[0050] In this example, Figure 3 The first timer (coarse counter or integer counter), not explicitly marked, is used to count the number of round trips. In this particular non-limiting example, the first timer counts the round trip pulses from the leading edge of the pulse to the leading edge of the pulse (in... Figure 3The time-domain (TD) pulse 306 in s is counted. The second timer 308 (fine counter or fractional counter) operates with a finer resolution (i.e., compared to the first timer) to measure the remaining time 304, which is the portion of time between the start of the last pulse 302 (i.e., the leading edge of the last pulse) and the end of the predefined measurement time 310.

[0051] As a hypothetical operation, measurements are taken for a predefined duration (e.g., utilizing existing techniques in the Ethernet specification). During the predefined duration, a first timer (coarse or integer counter) is used to measure the completion of a round trip. A second timer 308 (fine or fractional counter of clock cycles) is used to measure the remaining time 304 from the start of the last pulse 302 to the end of the measurement time 310. The remaining time 304 represents the measurement window error, for example, the error of the predefined duration, i.e., the difference between the predefined duration for the corresponding RT count and the actual duration for the corresponding round trip count (i.e., the closest full integer count of the round trip time). The remaining time 304 is subtracted from the predefined duration to determine the adjusted measurement time (which is equal to the total round trip time of the completed round trip pulse). As discussed herein, the adjusted measurement time can be used to determine the average round trip time and / or distance.

[0052] As a specific, non-limiting example implementation, the leading edge detector monitors the received TD pulse 306 and generates an output signal in response to the detection of a leading edge. In response to the detector output indicating the detection of a leading edge, a coarse counter increments its count, and a fine counter is reset to zero and starts counting. When the total measurement timer signals the end of the measurement period, the corresponding counts in the coarse and fine counters are latched for further processing. Without exceeding the scope of this disclosure, other reference planes besides the leading / rising edge of the TD pulse 306 (e.g., trailing edge, falling edge, pulse center, but not limited thereto) may be utilized.

[0053] In one or more examples, the adjusted measurement time can be stored as a numerical value in a counter. The most significant bit (MSB) of the counter stores the integer count of the complete round trip (the integer part), and the least significant bit (LSB) of the counter stores the remaining time (the fractional part). This representation of the adjusted measurement time can be used to determine the average round trip time and / or distance.

[0054] Figure 4 It is a diagram depicting the changes to the TD control register and topology discovery register of the TC14 specification for OA according to one or more examples.

[0055] The TD control register includes fields for storing predetermined values ​​used to determine, but not limited to, internal delays and distances. The topology discovery register includes fields for storing count values ​​determined or measured during topology discovery, including distance determination.

[0056] The distance measurement duration (duration) field in the TD control register can be replaced with the RT count field. The low (back) and high (front) distance and measurement node delay measurement result fields used to store the count value can be replaced with rising (high) and falling (low) timer values ​​and rising / falling fractional timer values.

[0057] Figure 5 Example process 500 for determining the distance between a first node and a second node, both located on a multipoint network / Ethernet segment, is illustrated according to one or more examples. Although example process 500 depicts a particular sequence of operations, this sequence can be varied without departing from the scope of this disclosure. For example, some of the depicted operations may be performed in parallel or in different sequences that do not substantially affect the functionality of process 500. In other examples, different components of the example device or system implementing process 500 may perform functions substantially simultaneously or in a particular sequence.

[0058] According to one or more examples, at operation 502, the method may include generating (e.g., via pulse generator circuitry, but not limited to) round-trip pulses at one or more nodes in a multipoint network. A corresponding round-trip pulse in the round-trip pulse selectively traverses one or more of the following: the internal circuitry of one or more nodes (e.g., the internal circuitry of a first node, or the internal circuitry of a first node and the internal circuitry of a second node, but not limited to), or the physical medium between a first node and a second node (e.g., the corresponding internal circuitry of the first and second nodes, and cables and any intermediate devices along the signal path between the first and second nodes, but not limited to). Some pulses traverse only the internal circuitry of a node (selectively traversing the internal circuitry of a node), and some pulses may traverse the internal circuitry of a node, the physical medium (selectively traversing the corresponding internal circuitry of the first and second nodes, and the physical medium).

[0059] To measure the total round trip, one or more pulses in the round trip pulse can be transmitted from a node (the first or second node acting as a reference node) through an internal path traversing its internal circuitry, and then exit over a physical medium (e.g., a segment of physical medium, but not limited thereto) to a remote node (the other of the first or second nodes acting as a measurement node). Upon receiving these pulses, the remote node echoes the pulses back through its internal path traversing its internal circuitry and across the same physical medium (e.g., a segment of the same physical medium, but not limited thereto), ultimately returning them to the receiver interface of the reference node.

[0060] To measure the internal delay of a node (e.g., a first node or a second node, but not limited thereto), one or more round-trip pulses can be sent to the node's interface pins, and the node echoes these round-trip pulses back through a small internal loop inside the node, rather than sending these pulses across the physical medium to a remote node—that is, these round-trip pulses do not cross the cable.

[0061] According to one or more examples, at operation 504, the method may include determining the total delay and internal delay of at least one of a first node or a second node. Both the total delay and the internal delay may be determined at least in part based on the measurement round-trip pulse within a predetermined measurement window and the measurement window error (as discussed herein). In one or more examples, determining the internal delay of a node may include receiving a value indicating the internal delay from another node (e.g., a reference node as discussed above).

[0062] In one or more examples, a predetermined measurement window is set. As a non-limiting example, the measurement window can be a predetermined fixed measurement window, such as a fixed duration or a fixed number of pulses, as discussed below. Alternatively, the measurement window can be an adjustable measurement window, as discussed below.

[0063] Within a measurement window (e.g., during the measurement window, but not limited to this), process 500 specifically measures the number of pulses or the duration required when the pulse travels along a measurement path (such as the total path or internal path of a node, but not limited to this). Measuring the round trip of the internal path of a node allows isolation of the node's internal echo delay, which can then be removed from the total delay (internal delay) to determine the delay of the physical medium.

[0064] In one or more examples, the same or different predetermined measurement windows can be used to measure the round trips of the node's internal circuitry and to measure the total round trips. For example, a shorter measurement window can be used in conjunction with round trips used to measure internal delays, rather than with round trips used to measure the entire cable length.

[0065] According to one or more examples, at operation 506, the method may include determining the distance between the first node and the second node based at least in part on the measurement of the round-trip pulse and the internal delay of at least one of the first node or the second node.

[0066] The total delay (T) can be utilized 总 ), the internal delay of the reference node (T) 参考节点 ) and the internal delay of the measurement node (T 测量节点 The physical medium delay (T) is determined according to the following expression. 物理介质 ):

[0067]

[0068] In one or more examples, the distance can be determined based on the delay of the physical medium and the propagation delay per unit length using the following expression:

[0069]

[0070] Where Δ is the propagation delay per unit length in the physical medium.

[0071] Figure 6 An example process 600 is illustrated, according to one or more examples, for measuring round-trip pulses when a predetermined fixed measurement window is a fixed number of round trips (e.g., denoted as a fixed pulse count). Although example process 600 depicts a particular sequence of operations, this sequence can be varied without departing from the scope of this disclosure. For example, some of the operations depicted may be performed in parallel or in different sequences that do not substantially affect the functionality of process 600. In other examples, different components of the example device or system implementing process 600 may perform their functions substantially simultaneously or in a particular sequence.

[0072] Process 600 can be a subprocess or detailed method of process 500 to measure or “capture” round trips within a predetermined fixed measurement window defined by a fixed number of round trips (instead of a fixed duration).

[0073] According to one or more examples, at operation 602, the method may include counting the number of clock cycles within a fixed number of round trips within a measurement window. This count measures the total elapsed time (in clock cycles) for a predetermined number of round trips N (e.g., 1100 pulses, but not limited to). The total time of these N pulses is effectively captured because it is known how many clock cycles occur during these N round trips. A control register or firmware variable may hold the current count and the target number of round trips. A hardware or firmware counter starts counting clock cycles (e.g., a 25 MHz clock tick, but not limited to) in response to the start of the first round trip. Upon detection that the Nth round trip has been completed, process 600 stops the counter and latches the final clock cycle count. The original clock cycle value represents the total time for N round trips.

[0074] In one or more examples, a lower speed clock (e.g., 1 MHz vs. 25 MHz) can be used to save power compared to a higher frequency clock used for normal operation.

[0075] According to one or more examples, at operation 604, the method may include determining the total duration of the round-trip pulse based at least in part on the counted number of clock cycles and a fixed number of round trips. Procedure 600 may convert this clock cycle count (from operation 602) into a time measurement—which can then be used, depending on the specific circumstances, to derive the total delay, internal delay, or distance. In some examples, the average round-trip time may be utilized, which is the product of the clock cycle count multiplied by the clock cycle duration divided by the number of round trips N.

[0076] Figure 7 Example process 700, according to one or more examples, is illustrated for enhancing measurement resolution by counting both the rising and falling edges of a clock signal during a fixed number of round trips. Although example process 700 depicts a particular sequence of operations, this sequence can be varied without departing from the scope of this disclosure. For example, some of the depicted operations may be performed in parallel or in different sequences that do not substantially affect the functionality of process 700. In other examples, different components of the example device or system implementing process 700 may perform their functions substantially simultaneously or in a particular sequence.

[0077] By capturing two edges within a single clock cycle (the clock edges), this method achieves a finer-grained measurement of the total time. As a non-limiting example, this can significantly reduce the quantization error (the difference between the actual pulse edge and the most recent sample point) of the measurement window error.

[0078] According to one or more examples, at operation 702, the method may include counting the number of rising edges of a clock cycle within a fixed number of round trips in a measurement window. In one or more examples, a rising edge counter in response to a high-to-high transition (low to high) is initialized, for example, by a hardware register or firmware variable set to zero when the measurement window starts (which begins at the start of the first round trip in a fixed number of round trips). Each time the clock transitions from low to high, a comparator or edge-detection circuit may increment the counter. At the completion of the Nth round trip, the rising edge counter is stopped or latched into a register.

[0079] According to one or more examples, at operation 704, the method may include counting the number of falling edges within a fixed number of round trips in a measurement window. In one or more examples, a falling edge counter in response to a low-to-low transition (high to low) is initialized, for example, by another hardware register or another firmware variable being set to zero when the measurement window starts (which begins at the start of the first round trip in a fixed number of round trips). Another edge-detecting circuitry (or alternatively, the same edge-detecting circuitry configured with two flip-flops: one for rising edges and one for falling edges) increments a second counter for each falling edge. At the completion of the Nth round trip, the falling edge counter is stopped or latched into a register.

[0080] According to one or more examples, at operation 706, the method may include determining the total duration of the round-trip pulse based at least in part on the number of rising edges counted and the number of falling edges counted. The total time can be determined by summing the rising edge counts and falling edge counts and multiplying that sum by the bilateral edge resolution (e.g., 20 nanoseconds in the case of a 25 MHz clock with a clock cycle length of 40 nanoseconds, but not limited thereto).

[0081] If the round trip begins just before the end of the time window, it may only complete the portion of its journey that falls within the window. Counting such pulses completely (i.e., counting them as if they were entirely within the measurement window) or ignoring / discarding this fraction can introduce errors in the final calculation of the average round trip time or the total pulse count. The procedure 800 discussed below ensures that those partial pulses are not lost, thereby producing a more accurate measurement by adjusting the total measurement duration of the round trip pulses.

[0082] Figure 8An example process 800 for detecting and processing portions or fractions of a round trip pulse is illustrated according to one or more examples. Although example process 800 depicts a particular sequence of operations, this sequence can be varied without departing from the scope of this disclosure. For example, some of the operations depicted may be performed in parallel or in different sequences that do not substantially affect the functionality of process 800. In other examples, different components of the example device or system implementing process 800 may perform their functions substantially simultaneously or in a particular sequence.

[0083] By detecting round trips across the boundaries of the measurement window and adding or subtracting portions of those round trips according to the system's counting logic, process 800 ensures a more accurate total—for example, for distance or internal delay calculations.

[0084] According to one or more examples, at operation 802, the method may include measuring the round trip of a pulse within a predetermined fixed measurement window to obtain a measured round trip of the pulse within the predetermined fixed measurement window. A measured round trip (or preliminary count / time) of all pulses at least partially contained within the measurement window is obtained. For example, when the window starts (or at the first round trip), a timer, clock cycle counter, or pulse counter begins, counts or measures fully completed pulses, and notes partially completed pulses, which may require special handling (which occurs in a later step), and at the end of the measurement window, all or part of the data in a register / variable is stored for further processing.

[0085] According to one or more examples, at operation 804, the method may include detecting round trips extending beyond the boundary of the measurement window. Process 800 may identify any pulses overlapping the boundary of the measurement window (i.e., those that start within the window but end after the window closes, or vice versa). For example, checking whether the completion time of the final pulse extends beyond the boundary of the measurement window (e.g., measuring the stop time, but not limited to this), if the final pulse completes after the boundary of the measurement window, marking it (e.g., applying a label to indicate it as a round trip extending beyond the boundary, but not limited to this), and measuring or recording the fraction of round trips occurring inside and outside the window (e.g., via a secondary or fraction counter, but not limited to this).

[0086] According to one or more examples, at operation 806, the method may include determining the measured round trip of the round trip pulse based at least in part on the portion of the detected round trip within the measurement window. The fraction of this portion of the round trip is incorporated (as discussed below with respect to operations 808 and 810) into the overall measurement. The round trip of the final pulse is neither completely ignored nor fully included—only the fraction belonging to the measurement window is included.

[0087] According to one or more examples, at operation 808, process 800 may optionally include: if the measurement logic only counts completed round trips if the round trip is completely within the measurement window, then the portion of the detected round trip that falls within the measurement window is added to the measurement of the round trip pulse. In one or more examples, some systems may increment the "complete pulse" count only in response to a round trip being completely within the measurement window. If the pulse is partially within the measurement window, it initially receives "0". In this scenario, the portion of the round trip that is within the measurement window is added back to refine the measurement.

[0088] According to one or more examples, at operation 810, process 800 may optionally include: if the measurement logic only counts completed round trips if initiated within the measurement window, subtracting the portion of the detected round trips falling outside the measurement window from the measurement of the round trips of the round trip pulses. In one or more examples, some systems may increment the "complete pulse" count in response to any pulse that will initiate within the window as a "fully counted" pulse. In this case, the counter may overcount if the final pulse partially extends beyond the boundary of the measurement window. In this scenario, the portion of the final pulse's round trips outside the measurement window is subtracted.

[0089] If the round trip begins just before the end of the time window, it may only complete the portion of its journey that falls within the window. Counting such pulses completely (i.e., counting them as if they were entirely within the measurement window) or ignoring / discarding this fraction can introduce errors in the final calculation of the average round trip time or the total pulse count. The procedure 900 discussed below ensures that those partial pulses are not lost, thereby producing a more accurate measurement by adjusting the duration of the adjustable measurement window.

[0090] Figure 9 An example process 900 for detecting and processing portions or fractions of round trips via round-trip pulses is illustrated according to one or more examples. Although example process 900 depicts a particular sequence of operations, this sequence can be varied without departing from the scope of this disclosure. For example, some of the depicted operations may be performed in parallel or in different sequences that do not substantially affect the functionality of process 900. In other examples, different components of the example device or system implementing process 900 may perform their functions substantially simultaneously or in a particular sequence.

[0091] By detecting round trips across the boundary of the measurement window and increasing or decreasing the measurement window according to the system's counting logic—increases being hangover time and decreases being remaining time—process 900 ensures a more accurate total—for example, for distance or internal delay calculations.

[0092] According to one or more examples, at operation 902, the method may include measuring the round trip of a pulse within a predetermined fixed measurement window to obtain a measured round trip of the pulse within the predetermined fixed measurement window. A measured round trip (or preliminary count / time) of all pulses at least partially contained within the measurement window is obtained. For example, when the window starts (or at the first round trip), a timer, clock cycle counter, or pulse counter begins, counts or measures fully completed pulses, and notes partially completed pulses, which may require special handling (which occurs in a later step), and at the end of the measurement window, all or part of the data in a register / variable is stored for further processing.

[0093] According to one or more examples, at operation 904, the method may include detecting round trips extending beyond the boundary of the measurement window. Process 900 may identify any pulses overlapping the boundary of the measurement window (i.e., those that start within the window but end after the window closes, or vice versa). For example, checking whether the completion time of the final pulse exceeds the boundary of the measurement window (e.g., measuring the stop time, but not limited to this), if the final pulse completes after the boundary of the measurement window, marking it (e.g., applying a label to indicate it as a round trip extending beyond the boundary, but not limited to this), and measuring or recording the fraction of round trips occurring inside and outside the window (e.g., via a secondary or fraction counter, but not limited to this).

[0094] According to one or more examples, at operation 906, the method may include determining the measured round trip of a round trip pulse based at least in part on an adjusted measurement window. The adjustment of the measurement window may be proportional to the portion of the final round trip that is within or outside the boundaries of the measurement window. The measurement window is adjusted to account for this portion of the round trip (as discussed below with respect to operations 908 and 910). The pulse count remains unchanged. As disclosed herein, the adjusted measurement window can be used to determine the measured round trip and the average round trip.

[0095] According to one or more examples, at operation 908, the method may include: if the measurement logic only counts completed round trips if the round trip is completely within the measurement window, then the measurement window is reduced proportionally to the portion of the detected round trip that falls within the measurement window to obtain an adjusted measurement window. In one or more examples, some systems may increment the "complete pulse" count only in response to a round trip being completely within the measurement window. If the pulse is partially within the measurement window, it initially receives "0". In this scenario, the measurement window is reduced so that it ends at the last completely completed round trip, thereby excluding any partially completed pulses.

[0096] According to one or more examples, at operation 910, the method may include: if the measurement logic only counts completed round trips if initiated within the measurement window, then the measurement window is increased proportionally to the portion of the detected round trip that falls outside the measurement window to obtain an adjusted measurement window. In one or more examples, some systems may increment the "complete pulse" count in response to any pulse that will initiate within the window as a "fully counted" pulse. In this case, the counter may overcount if the final pulse partially extends beyond the boundary of the measurement window. In this scenario, the measurement window is extended to the end when the final partial pulse is fully completed, thereby ensuring that the entire pulse is included.

[0097] If a round trip begins just before the end of the time window, it may only complete the portion of its journey within the window. Ignoring this fraction can introduce errors into the final calculation of the average round trip time or the total pulse count. The procedure discussed below ensures that those partial round trips are not lost, resulting in a more accurate measurement.

[0098] Figure 10 An example process 1000 for measuring a round trip pulse when a predetermined fixed measurement window is of fixed duration is illustrated according to one or more examples. Although example process 1000 depicts a particular sequence of operations, this sequence can be varied without departing from the scope of this disclosure. For example, some operations in the depicted operations may be performed in parallel or in different sequences that do not substantially affect the functionality of process 1000. In other examples, different components of the example device or system implementing process 1000 may perform their functions substantially simultaneously or in a particular sequence.

[0099] By counting both fully completed round trips and fractional (partial) round trips, Process 1000 can improve distance or delay accuracy instead of ignoring or rounding off partial pulses.

[0100] According to one or more examples, at operation 1002, the method may include counting the number of complete round trips occurring within a fixed duration of a measurement window. During the fixed duration (measurement window), a master counter or integer counter measures (counts) how many round trips are started and completed entirely within that time window. This provides an integer count of the completion pulses. For example, a timer or reference clock starts at the beginning of the fixed duration. Whenever the system detects the end of a round trip (i.e., the echo pulse returns), it checks whether the clock is still within the fixed duration. At the end of the fixed duration, the final integer count N of the completely completed round trips can be stored.

[0101] According to one or more examples, at operation 1004, the method may include counting the fractional occurrences of partial round trips within a fixed duration of a measurement window. Some round trips may not be fully completed before the fixed duration expires. Instead of discarding these partial pulses, the method is implemented according to the design to measure how much of them actually occurred within or outside the window (e.g., 40% or 0.4% of the round trip, but not limited to this).

[0102] For example, when the time window ends, the pulse might be "in flight" (it starts before the window ends but doesn't finish until after the window ends). The system sees the "end" of the pulse arrive after the window boundary, so it is only partially within the time window. A secondary or fractional counter can measure (e.g., by fractional increments of the main counter, but not limited to) how many clock cycles (or how many ns) of that last pulse were within the fixed duration of the measurement window. The fractional value can be stored (e.g., 0, 0.2, 0.4, 0.5, 0.7, but not limited to) in a register or variable that indicates the partial round trip.

[0103] According to one or more examples, at operation 1006, the method may include determining the measured round trips of a round trip pulse based at least in part on a combination of the counted number of completed round trips and the counted fraction of partially completed round trips. If N is the number of fully completed round trips and F is the fraction of partially completed pulses (e.g., 0.4), your final "valid" count is N + F. In one or more examples, this final valid pulse count is counted as the total count per unit time of the average round trip or fixed-duration measurement window.

[0104] Those skilled in the art will understand that the functional elements (e.g., functions, operations, actions, processes, or methods) of the examples disclosed herein can be implemented in any suitable hardware, software, firmware, or a combination thereof. Figure 11 Non-limiting examples of specific implementations of the functional elements disclosed herein are illustrated. In some examples, some or all portions of the functional elements disclosed herein may be executed by hardware capable of performing the functional elements.

[0105] Figure 11This is a block diagram of circuitry 1100 that, in some examples, can be used to implement the various functions, operations, actions, processes, or methods disclosed herein. Circuitry 1100 includes one or more processors 1102 (sometimes referred to herein as "processor 1102") operatively coupled to one or more data storage devices 1104 (sometimes referred to herein as "storage device 1104"). Storage device 1104 includes machine-executable code 1106 stored thereon, and processor 1102 includes logic circuitry 1108. Machine-executable code 1106 includes information describing functional elements that can be implemented (e.g., executed) by logic circuitry 1108. Logic circuitry 1108 is adapted to implement (e.g., execute) the functional elements described by machine-executable code 1106. When executing the functional elements described by machine-executable code 1106, circuitry 1100 should be considered as dedicated hardware for implementing the functional elements disclosed herein. In one or more examples, processor 1102 may execute the functional elements described by machine-executable code 1106 sequentially, simultaneously (e.g., on one or more different hardware platforms), or in one or more parallel process flows.

[0106] When implemented by the logic circuitry 1108 of processor 1102, machine-executable code 1106 adapts processor 1102 to perform the operations of the examples disclosed herein. As a non-limiting example, machine-executable code 1106 may adapt processor 1102 to perform some or all of the operations of one or more processes for measuring the distance between nodes in the multipoint network discussed herein, including processes 500, 600, 700, 800, 900, and 1000, as well as the process of signal diagram 300.

[0107] Also by way of non-limiting example, machine-executable code 1106 may enable processor 1102 to perform some or all of the features, functions, or operations disclosed herein for one or more of the following: internal circuitry 102, transmitter 104, receiver 106, connection 108, measurement circuitry 114, logic circuitry 116, pulse generator circuitry 118, and physical medium portion 120 of node 100; reference node 202, measurement node 204, and physical medium 206 of system 200; and device 400.

[0108] Processor 1102 may include a general-purpose processor, special-purpose processor, central processing unit (CPU), microcontroller, programmable logic controller (PLC), digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic unit, discrete hardware unit, other programmable device, or any combination thereof, designed to perform the functions disclosed herein. A general-purpose computer is considered a special-purpose computer at least when it includes one or more processors 1102 (including general-purpose processors) executing functional elements corresponding to machine-executable code 1106 (e.g., software code, firmware code, configuration data, hardware description, but not limited thereto) relevant to the examples of this disclosure. It should be noted that a general-purpose processor (which may also be referred to herein as a host processor or simply a host) may be a microprocessor, but in alternatives, the general-purpose processor of processor 1102 may include any conventional processor, controller, microcontroller, or state machine. The FPGA or other PLD of processor 1102 can be configured (e.g., programmed, but not limited thereto) with configuration data to perform the functions disclosed herein, or additionally or alternatively, can be configured or reconfigured (e.g., programmable or reprogrammable, but not limited thereto) with configuration data to perform the functions disclosed herein. Processor 1102 can also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0109] In one or more examples, storage device 1104 includes volatile data storage devices (e.g., random access memory (RAM), static RAM (SRAM), but not limited thereto) and non-volatile data storage devices (e.g., flash memory, hard disk drive, solid-state drive, erasable programmable read-only memory (EPROM), but not limited thereto). In some examples, processor 1102 and storage device 1104 may be implemented in a single device (e.g., semiconductor device product, system-on-a-chip (SoC), but not limited thereto). In some examples, processor 1102 and storage device 1104 may be implemented in separate devices.

[0110] In one or more examples, machine-executable code 1106 may include computer-readable instructions (e.g., software code, firmware code). As a non-limiting example, the computer-readable instructions may be stored in storage device 1104, directly accessed by processor 1102, and executed by processor 1102 using at least logic circuitry 1108. Also as a non-limiting example, the computer-readable instructions may be stored on storage device 1104, passed to a memory device (not shown) for execution, and executed by processor 1102 using at least logic circuitry 1108. Processor 1102 or its logic circuitry 1108 may be coupled to or include such a memory device (e.g., configuring memory cells, but not limited thereto). Thus, in some examples, logic circuitry 1108 includes electrically configurable logic circuitry 1108.

[0111] In one or more examples, machine-executable code 1106 may describe the hardware (e.g., circuitry) to be implemented in logic circuitry 1108 to perform functional elements. This hardware may be described at any of a range of abstraction levels, from low-level transistor layout to high-level description languages. At high-level abstraction, hardware description languages ​​(HDLs), such as the IEEE standard hardware description language (HDL), may be used. As a non-limiting example, Verilog may be used. ® SystemVerilog ™ Or, the Very Large Scale Integration (VLSI) Hardware Description Language (VHDL).

[0112] HDL descriptions can be transformed into descriptions at any of a variety of other levels of abstraction as needed. As a non-limiting example, a high-level description can be transformed into a logic-level description such as Register Pass Language (RTL), Gate-level (GL) description, layout-level description, or mask-level description. As a non-limiting example, micro-operations to be performed by the hardware logic circuitry of logic circuitry 1108 (e.g., gates, flip-flops, registers, but not limited thereto) can be described in RTL, then transformed into a GL description using a synthesis tool, and the GL description can be transformed into a layout-level description using a placement and routing tool, which corresponds to the physical layout of an integrated circuit of programmable logic devices, discrete gate or transistor logic components, discrete hardware components, or combinations thereof. Therefore, in some examples, machine-executable code 1106 may include HDL, RTL, GL descriptions, mask-level descriptions, other hardware descriptions, or any combination thereof.

[0113] In an example where machine-executable code 1106 includes a hardware description (at any level of abstraction), the system (not shown, but including storage device 1104) implements the hardware description described by machine-executable code 1106. As a non-limiting example, processor 1102 may include a programmable logic device (e.g., an FPGA or PLC, but not limited thereto), and logic circuitry 1108 may be electrically controlled (e.g., via configuration data, but not limited thereto) to implement circuitry corresponding to the hardware description into logic circuitry 1108. Again, as a non-limiting example, logic circuitry 1108 may include hardwired logic components manufactured by a manufacturing system (not shown, but including storage device 1104) according to the hardware description of machine-executable code 1106.

[0114] Regardless of whether the machine-executable code 1106 includes computer-readable instructions or a hardware description, the logic circuit 1108 is adapted to execute the functional elements described by the machine-executable code 1106 when implementing the functional elements of the machine-executable code 1106. It should be noted that although the hardware description may not directly describe the functional elements, it indirectly describes the functional elements that the hardware elements described by the hardware description can execute.

[0115] As used in this disclosure, the terms "module" or "component" can refer to a specific hardware implementation that performs actions of a module or component and / or software object or software routine that can be stored on and / or executed by general-purpose hardware (e.g., computer-readable media, processing devices, but not limited thereto) of a computing system. In some examples, the different components, modules, engines, and services described in this disclosure may be implemented as objects or processes (e.g., as separate threads) that execute on a computing system. While some of the systems and methods described in this disclosure are generally described as being implemented in software (stored on and / or executed by general-purpose hardware), specific hardware implementations or combinations of software and specific hardware implementations are also possible and conceivable.

[0116] As used in this disclosure, the term "combination" referring to multiple elements can include a combination of all elements or any one of various different sub-combinations of certain elements. For example, the phrase "A, B, C, D or combinations thereof" can refer to any one of A, B, C, or D; a combination of each of A, B, C, and D; and any sub-combination of A, B, C, or D, such as A, B, and C; A, B, and D; A, C, and D; B, C, and D; A and B; A and C; A and D; B and C; B and D; or C and D.

[0117] The terminology used in this disclosure, and particularly in the appended claims (e.g., in the body of the appended claims, but not limited thereto), is generally intended to be “open-ended” terms (e.g., the term “comprising” should be interpreted as “including but not limited to”, and the term “having” should be interpreted as “at least having, but not limited to”). As used herein, the term “each” means “some or all”. As used herein, the term “each and every” means “all”.

[0118] Additionally, if a specific number of introduced claim statements are anticipated, such an intent will be explicitly stated in the claims, and without such statements, no such intent exists. For example, as an aid to understanding, the appended claims may contain the use of the introductory phrases “at least one” and “one or more” to introduce claim statements. However, the use of such phrases should not be construed as implying that a claim statement introduced by the indefinite article “a” or “an” limits any particular claim containing such an introduced claim statement to an example containing only one such statement, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an” (e.g., “a” and / or “an” can be interpreted as referring to “at least one” or “one or more”, but is not limited thereto); the same applies to the use of definite articles to introduce claim statements.

[0119] Furthermore, even when a specific number of the introduced claim statements are explicitly stated, those skilled in the art will recognize that such statements should be interpreted as meaning at least the number stated (e.g., the unmodified statement "two statements" means, in the absence of other modifying elements, at least two statements, or two or more statements, but not limited thereto). Additionally, in those conventional instances where phrases such as "at least one of A, B, and C, but not limited thereto" or "one or more of A, B, and C, but not limited thereto" are used, such constructions are generally intended to include, but are not limited to, a single A, a single B, a single C, A and B together, A and C together, B and C together, or A, B, and C together.

[0120] Furthermore, any separate word or phrase presenting two or more alternative terms in the specification, claims, or drawings should be understood to contemplate the possibility of including one term, any one term, or both terms. For example, the phrase "A or B" should be understood to include the possibility of including "A" or "B" or "A and B".

[0121] Additional non-limiting embodiments include:

[0122] Example 1: A method comprising: generating round-trip pulses at one or more nodes of a multipoint network, wherein a corresponding round-trip pulse in the round-trip pulse selectively traverses one or more of: the internal circuitry of the one or more nodes, or the physical medium between a first node and a second node of the one or more nodes; determining, at least in part, the total delay and internal delay of the one or more nodes based on: the measurement round-trip of the round-trip pulse within a predetermined measurement window; and a measurement window error; and determining, at least in part, the distance between the first node and the second node based on the measurement round-trip of the round-trip pulse and the internal delay of at least one of the first node or the second node.

[0123] Example 2: The method according to Example 1, wherein the predetermined measurement window indicates either a fixed duration or a fixed number of round trips.

[0124] Example 3: According to the method described in Examples 1 and 2, the method includes measuring the round trip of the round trip pulse within a predetermined fixed measurement window to obtain the measured round trip of the round trip pulse within the predetermined measurement window.

[0125] Example 4: The method according to any one of Examples 1 to 3, wherein measuring the round trip of the round trip pulse within a predetermined fixed measurement window includes: counting the number of clock cycles within a fixed number of round trips in the measurement window; and determining the measurement round trip of the round trip pulse based at least in part on the counted number of clock cycles.

[0126] Example 5: The method according to any one of Examples 1 to 4, wherein measuring the round trip of a round trip pulse within a predetermined fixed measurement window includes: counting the number of rising edges of a clock cycle within a fixed number of round trips in the measurement window; counting the number of falling edges of a clock cycle within a fixed number of round trips in the measurement window; and determining the measurement round trip of the round trip pulse based at least in part on the counted number of rising edges and the counted number of falling edges.

[0127] Example 6: The method according to any one of Examples 1 to 5, wherein measuring the round trip of a round trip pulse within a predetermined fixed measurement window includes: counting the number of completed round trips occurring within a fixed duration of the measurement window; counting the fractional occurrences of partial round trips occurring within the fixed duration of the measurement window; and determining the measured round trip of the round trip pulse based at least in part on a combination of the counted number of completed round trips and the counted fractional occurrences of partial round trips.

[0128] Example 7: The method according to any one of Examples 1 to 6, wherein measuring the round trip of a round trip pulse within a predetermined fixed measurement window comprises: counting the number of round trip pulses, wherein the corresponding count of the counted number of round trip pulses is triggered at least in part in response to the leading edge of the round trip pulse; counting the number of clock cycles up to the counted number of round trip pulses being equal to a predetermined fixed number of round trips in the measurement window; counting the number of clock cycles up to the completion of the final round trip pulse in the counted number of round trip pulses; and determining the measured round trip of the round trip pulse based at least in part on a combination of the counted number of clock cycles up to the counted number of round trip pulses being equal to the predetermined fixed number of round trips and the counted number of clock cycles up to the completion of the final round trip pulse in the counted number of round trip pulses.

[0129] Example 8: The method according to any one of Examples 1 to 7, wherein measuring the round trip of the round trip pulse within a predetermined fixed measurement window includes: detecting round trips extending beyond the boundary of the measurement window; and determining the measured round trip of the round trip pulse based at least in part on the portion of the detected round trip within the measurement window.

[0130] Example 9: The method according to any one of Examples 1 to 8, wherein determining the measurement round trip of the round trip pulse based at least in part on the portion of the detected round trip within the measurement window comprises: adding the portion of the detected round trip falling within the measurement window to the measurement of the round trip pulse.

[0131] Example 10: The method according to any one of Examples 1 to 9, wherein determining the measurement round trip of the round trip pulse based at least in part on the portion of the detected round trip within the measurement window includes: subtracting the portion of the detected round trip falling outside the measurement window from the measurement of the round trip of the round trip pulse.

[0132] Example 11: The method according to any one of Examples 1 to 10, the method includes: measuring the round trip of a round trip pulse within a predetermined adjustable measurement window to obtain a measured round trip of the round trip pulse within the predetermined measurement window.

[0133] Example 12: The method according to any one of Examples 1 to 11, wherein measuring the round trip of the round trip pulse within a predetermined adjustable measurement window includes: detecting round trips extending beyond the boundary of the measurement window; and determining the measured round trip of the round trip pulse based at least in part on the adjusted measurement window, the adjustment being proportional to the portion of the final round trip within or outside the boundary of the measurement window.

[0134] Example 13: An apparatus comprising: a pulse generator circuit for generating round-trip pulses at one or more nodes of a multipoint network, wherein corresponding round-trip pulses selectively pass through one or more of: internal circuitry of the one or more nodes, or a physical medium between a first node and a second node of the one or more nodes; a measurement circuit for measuring the round-trip of the round-trip pulses generated by the pulse generator circuit within a predetermined measurement window, and providing measurement data indicating the measured round-trip of the round-trip pulses; and a logic circuit for determining, at least in part, the total delay and internal delay of at least one of the one or more nodes based on: the measurement data; and a measurement window error; and determining, at least in part, the distance between the first node and the second node based on the measurement data and the determined internal delay of at least one of the first node or the second node.

[0135] Example 14: The apparatus according to Example 13, wherein a predetermined measurement window is associated with either a fixed duration or a fixed number of round trips.

[0136] Example 15: The apparatus according to Examples 13 and 14, wherein the measurement circuit is used to obtain the measurement round trip of the round trip pulse within a predetermined measurement window by capturing at least one timing or counting signal indicating the round trip pulse.

[0137] Example 16: An apparatus according to any one of Examples 13 to 15, wherein the measurement circuit is used to count the number of clock cycles within a fixed number of round trips of a measurement window, and wherein the logic circuit is configured to determine the measurement round trip of the round trip pulse based at least in part on the counted number of clock cycles.

[0138] Example 17: An apparatus according to any one of Examples 13 to 16, wherein the measurement circuit is configured to: count the number of rising edges of a clock cycle within a fixed number of round trips; count the number of falling edges of a clock cycle within a fixed number of round trips; and determine the measurement round trip of the round trip pulse based at least in part on the counted rising and falling edges.

[0139] Example 18: An apparatus according to any one of Examples 13 to 17, wherein the measurement circuit is configured to: count the occurrences of completed round trips within a fixed duration; count the fractional occurrences of partial round trips within a fixed duration; and determine the measured round trip of the round trip pulse based at least in part on the combination of the counted completed round trip occurrences and the fractional occurrences of partial round trips.

[0140] Example 19: An apparatus according to any one of Examples 13 to 18, wherein the measurement circuit is configured to: count the number of round-trip pulses in response to the leading edge of a pulse until the counted number of round-trip pulses equals a predetermined fixed number; count the number of clock cycles until the final round-trip pulse of the counted number is completed; and determine the measured round-trip of the round-trip pulse based at least in part on the counted number of clock cycles until the predetermined number of pulses arrive and the counted number of clock cycles until the final round-trip pulse is completed.

[0141] Example 20: An apparatus according to any one of Examples 13 to 19, wherein the measurement circuit is used to detect at least one round trip extending beyond the boundary of the measurement window, and wherein the measurement circuit is used to adjust the measurement data to take into account the portion of the round trip located within the measurement window.

[0142] Example 21: The apparatus according to any one of Examples 13 to 20, wherein the processing circuitry is used to add the detected round trip portion falling within the measurement window to the measurement data.

[0143] Example 22: The apparatus according to any one of Examples 13 to 21, wherein the processing circuitry is used to subtract the detected round trip portion falling outside the measurement window from the measurement data.

[0144] Example 23: An apparatus according to any one of Examples 13 to 22, wherein the measurement circuit is used to measure the round trip of the round trip pulse within a predetermined adjustable measurement window, and wherein the measurement circuit is used to detect at least one round trip extending beyond the boundary of the measurement window, and to provide adjusted measurement data based on at least a portion of the detected round trip.

[0145] Example 24: The apparatus according to any one of Examples 13 to 23, wherein the logic circuitry is used to reduce the measurement window proportionally to the portion of the final round trip that falls within the boundary, such that the adjusted measurement window ends at the time corresponding to the last complete round trip.

[0146] Example 25: An apparatus according to any one of Examples 13 to 24, wherein the logic circuitry is configured to increase the measurement window proportionally to the portion of the final round trip that extends beyond the boundary, such that the adjusted measurement window ends when the detected round trip is completed.

[0147] While this disclosure has been described with respect to certain exemplary embodiments, those skilled in the art will recognize and understand that the invention is not limited thereto. Rather, many additions, deletions, and modifications may be made to the exemplary and described embodiments without departing from the scope of the invention as claimed below and its legal equivalents. Furthermore, features from one embodiment may be combined with features from another embodiment while still being included within the scope of the invention as contemplated by the inventors.

Claims

1. A method, the method comprising: A round-trip pulse is generated at one or more nodes of a multipoint network, wherein a corresponding round-trip pulse in the round-trip pulse selectively passes through one or more of the following: the internal circuitry of the one or more nodes, or the physical medium between a first node and a second node of the one or more nodes; The total latency and internal latency of the one or more nodes are determined based at least in part on the following: The round-trip pulse is measured within a predetermined measurement window; and Measurement window error; and The distance between the first node and the second node is determined at least in part based on the measured round-trip pulses and the internal delay of at least one of the first node or the second node.

2. The method of claim 1, wherein the predetermined measurement window indicates either a fixed duration or a fixed number of round trips.

3. The method according to claim 1, wherein the method includes measuring the round trip of the round trip pulse within a predetermined fixed measurement window to obtain the measured round trip of the round trip pulse within the predetermined measurement window.

4. The method of claim 3, wherein measuring the round-trip pulse within the predetermined fixed measurement window comprises: The number of clock cycles within a fixed number of round trips in the measurement window is counted; as well as The measured round trip of the round trip pulse is determined at least in part based on the number of clock cycles counted.

5. The method of claim 3, wherein measuring the round-trip pulse within the predetermined fixed measurement window comprises: The number of rising edges of the clock cycle within a fixed number of round trips within the measurement window is counted; The number of falling edges of the clock cycle within the fixed number of round trips in the measurement window is counted; as well as The measured round trip of the round trip pulse is determined at least in part based on the number of rising edges counted and the number of falling edges counted.

6. The method of claim 3, wherein measuring the round-trip pulse within the predetermined fixed measurement window comprises: The number of round trips completed within a fixed duration of the measurement window is counted; The fractional occurrences of partial round trips within the fixed duration of the measurement window are counted; as well as The measured round trip of the round trip pulse is determined at least in part based on a combination of the counted number of completed round trips and the counted fractional occurrences of the partial round trips.

7. The method of claim 4, wherein measuring the round-trip pulse within the predetermined fixed measurement window comprises: The number of round-trip pulses is counted, wherein the corresponding count of the counted number of round-trip pulses is triggered at least in part in response to the leading edge of the round-trip pulse; The number of clock cycles is counted until the number of round-trip pulses counted is equal to the predetermined fixed number of round trips of the measurement window; Count the number of clock cycles until the final round-trip pulse of the counted round-trip pulses is completed; as well as The measured round trip of the round trip pulse is determined at least in part based on a combination of the number of clock cycles counted until the number of counted round trip pulses equals a predetermined fixed number of round trips and the number of clock cycles counted until the final round trip pulse of the counted number of round trip pulses is completed.

8. The method of claim 3, wherein measuring the round-trip pulse within the predetermined fixed measurement window comprises: Detect round trips extending beyond the boundary of the measurement window; as well as The measured round trip of the round trip pulse is determined at least in part based on the portion of the detected round trip within the measurement window.

9. The method of claim 8, wherein determining the measurement round trip of the round trip pulse based at least in part on the portion of the detected round trip within the measurement window comprises: The portion of the detected round trip that falls within the measurement window is added to the measurement of the round trip of the round trip pulse.

10. The method of claim 8, wherein determining the measurement round trip of the round trip pulse based at least in part on the portion of the detected round trip within the measurement window comprises: Subtract the portion of the detected round trip that falls outside the measurement window from the measurement of the round trip of the round trip pulse.

11. The method of claim 1, the method comprising measuring the round trip of the round trip pulse within a predetermined adjustable measurement window to obtain the measured round trip of the round trip pulse within the predetermined measurement window.

12. The method of claim 11, wherein measuring the round-trip pulse within the predetermined adjustable measurement window comprises: Detect round trips extending beyond the boundary of the measurement window; as well as The measurement round trip of the round trip pulse is determined at least in part based on an adjusted measurement window, the adjustment being proportional to the portion of the final round trip within or outside the boundaries of the measurement window.

13. An apparatus comprising: A pulse generator circuit for generating round-trip pulses at one or more nodes of a multipoint network, wherein a corresponding round-trip pulse selectively passes through one or more of the following: the internal circuitry of the one or more nodes, or the physical medium between a first node and a second node of the one or more nodes; A measurement circuit is configured to measure the round trip of the round trip pulse generated by the pulse generator circuit within a predetermined measurement window, and to provide measurement data indicating the measured round trip of the round trip pulse; and Logic circuit, the logic circuit being used for: The total latency and internal latency of at least one of the one or more nodes are determined based at least in part on the following: The measurement data; and Measurement window error; and The distance between the first node and the second node is determined at least in part based on the measurement data and the determined internal delay of at least one of the first node or the second node.

14. The apparatus of claim 13, wherein the predetermined measurement window is associated with either a fixed duration or a fixed number of round trips.

15. The apparatus of claim 13, wherein the measuring circuit is configured to obtain the measurement round trip of the round trip pulse within the predetermined measuring window by capturing at least one timing or counting signal indicating the round trip pulse.

16. The apparatus of claim 15, wherein the measurement circuitry is configured to count the number of clock cycles within a fixed number of round trips of the measurement window, and wherein the logic circuitry is configured to determine the measurement round trip of the round trip pulse based at least in part on the counted number of clock cycles.

17. The apparatus of claim 15, wherein the measuring circuit is used for: Count the number of rising edges in a clock cycle within a fixed number of round trips; Count the number of falling edges of the clock cycle within the fixed number of round trips; and The measured round trip of the round trip pulse is determined at least in part based on the counted rising and falling edges.

18. The apparatus of claim 15, wherein the measuring circuit is used for: Count the number of round trips completed within a fixed duration; The fractional occurrences of partial round trips within the fixed duration are counted; and The measured round trip of the round trip pulse is determined at least in part based on the combination of the counted completed round trips and the fractional occurrences of the partial round trips.

19. The apparatus of claim 15, wherein the measuring circuit is used for: The number of round-trip pulses in response to the leading edge of the pulse is counted until the counted number of round-trip pulses equals a predetermined fixed number. The number of clock cycles until the final round-trip pulse of the counted quantity is completed is counted; and The measured round trip of the round trip pulse is determined at least in part based on the number of clock cycles counted up to the arrival of a predetermined number of pulses and the number of clock cycles counted up to the completion of the final round trip pulse.

20. The apparatus of claim 15, wherein the measuring circuit is configured to detect at least one round trip extending beyond the boundary of the measuring window, and wherein the measuring circuit is configured to adjust the measuring data to take into account the portion of the round trip located within the measuring window.

21. The apparatus of claim 20, wherein the processing circuitry is configured to add the detected round-trip portion falling within the measurement window to the measurement data.

22. The apparatus of claim 20, wherein the processing circuitry is used to subtract from the measurement data the detected round-trip portion falling outside the measurement window.

23. The apparatus of claim 13, wherein the measuring circuit is configured to measure the round-trip pulse within a predetermined adjustable measuring window, and wherein the measuring circuit is configured to detect at least one round-trip extending beyond the boundary of the measuring window, and to provide adjusted measurement data based on at least a portion of the detected round-trip.

24. The apparatus of claim 23, wherein the logic circuitry is configured to reduce the measurement window proportionally to the portion of the final round trip falling within the boundary, such that the adjusted measurement window ends at the time corresponding to the last fully completed round trip.

25. The apparatus of claim 23, wherein the logic circuitry is configured to increase the measurement window proportionally to the portion of the final round trip that extends beyond the boundary, such that the adjusted measurement window ends when the detected round trip is completed.

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