Imaging sensor with gate-controlled isolation between shared pixels and imaging apparatus

Abstract

An imaging device includes a plurality of recta shared pixels, wherein a potential barrier between photoelectric conversion sections of the recta shared pixels is controlled by a control gate. In a default mode, a first voltage is provided to the control gate to cause a separation established between the photoelectric conversion sections of the recta shared pixels to be less than, equal to, or only slightly greater than a separation established by an intra-pixel separation structure. In another mode, a second voltage is provided to the control gate to cause a separation established between the photoelectric conversion sections of the recta shared pixels to be greater than the separation in the default mode. The default mode is maintained during image acquisition, while the other mode is applied only during a process in which charge is generated by the photoelectric conversion sections during a phase detection autofocus operation.

Description

Technical Field

[0001] This disclosure relates to imaging elements and imaging devices that include phase detection autofocus capability. Background Technology

[0002] Digital image sensors are commonly used in various electronic devices such as handheld cameras, security systems, telephones, computers, tablets, and machine vision systems to capture images. To ensure that the captured images are in focus, various autofocus systems and technologies have been developed. For example, contrast detection methods and phase detection methods have been developed. Each method has its advantages and disadvantages. For instance, contrast detection autofocus is generally slower than phase detection autofocus, but it can be more accurate. Therefore, many cameras and other electronic devices employ both contrast detection and phase detection methods.

[0003] In mirrorless imaging devices and in single-lens reflex cameras operating in live view or movie mode, autofocus must be performed using pixels arranged on the image sensor itself. However, phase-detection autofocus requires dedicated phase-detection pixels. Since the trend has been towards providing an increasing number of autofocus points to enable autofocus on image features across virtually all areas of an image frame, phase-detection pixels that can contribute image information in addition to the information used for focusing have become increasingly desirable.

[0004] Phase-detection autofocus systems typically include pairs of photosensitive elements. In some phase-detection arrangements, a physical mask ensures that individual pixels within a pair receive light from opposite sides of the imaging lens. However, this system suffers from poor low-light performance and cannot be used in imaging modes. In other phase-detection arrangements, each phase-detection pixel includes a pair of photoelectric conversion units positioned below a common microlens. In this arrangement, isolation between the photoelectric conversion units within the pixel is crucial for enabling phase-detection autofocus operation. Furthermore, the signal from the pixel pair can be used in imaging modes. However, when the isolation between pixels is large, charge in one pixel may overflow into a floating diffuser instead of into the other pixel in the pair, leading to degraded signal linearity. Summary of the Invention

[0005] Embodiments of this disclosure provide imaging elements and imaging apparatuses comprising phase detection autofocus pixels, which are presented in the form of multiple photodiodes, single microlens pixels, also referred to as recta shared pixels or recta phase detection (PD) pixels. Each recta shared pixel may include first and second (e.g., left and right, or top and bottom) sub-pixels or photodiodes. In phase detection autofocus (PDAF) mode, signals from the first and second photodiodes of the recta shared pixel are read out individually. In viewing or imaging mode, signals from the photodiodes of the recta shared pixel are read out as a combined signal. In PDAF mode, it is desirable to maintain a high degree of separation between the first and second photodiodes. In imaging mode, it is desirable to allow charge transfer from one of the first and second photodiodes to the other to improve the linearity of the output signal. According to embodiments of this disclosure, the amount of signal isolation between the first and second photodiodes within the recta phase detection pixel can be controlled. As a result, when the recta phase detection pixel is operating in autofocus mode, it can provide a high degree of isolation between the individual photodiodes of the recta phase detection pixel to promote accurate PDAF capability; and when the recta PD pixel is operating in imaging mode, it can provide a reduced degree of isolation to promote signal linearity.

[0006] According to embodiments of this disclosure, signal isolation between individual photodiodes of a Reta phase-detection pixel is controlled by creating a variable potential barrier. More specifically, a control gate is positioned adjacent to the potential barrier between the individual photodiodes. By selecting a first gate voltage, a high separation ratio can be achieved in phase-detection autofocus mode, and by selecting a second gate voltage, good linearity of the signal response across the entire Reta shared pixel can be achieved in imaging mode. Therefore, in embodiments of this disclosure, the control gate is operated to control the amount of separation between the individual photodiodes of the Reta shared pixel. More specifically, embodiments of this disclosure are configured such that: when the control gate is high or ON, the degree of signal isolation between sub-pixels is relatively low, and when the control gate is low or OFF, the degree of isolation between sub-pixels is relatively high. Furthermore, at least some embodiments of this disclosure maintain the control gate in a high or ON state in all operations except phase-difference autofocus operation. Under specific conditions for a particular application, the control gate can be applied with a reference voltage based on the application to allow for finer control of the isolation between the two shared photodiode pairs. Therefore, the control gate is kept in the ON state as the default mode.

[0007] The control gate can take any of a variety of configurations. For example, the control gate can be configured as a planar structure located on the surface of the substrate on which the first and second photodiodes are formed. As another example, the control gate can be configured as a vertical gate. As yet another example, the control gate can be configured as a double vertical gate. According to further embodiments of this disclosure, the control gate can have the same or similar elements or aspects as the transmission gate provided for the respective photodiodes. For example, at least some portions of the control gate can be located in the same plane and can have the same shape as the transmission gate. As another example, at least some portions of the control gate can be located in the same plane and can have the same shape and size as the transmission gate.

[0008] Other features and advantages of the various embodiments of this disclosure will be more readily understood from the following description, especially in conjunction with the accompanying drawings. Attached Figure Description

[0009] Figure 1 This is a diagram illustrating a schematic configuration example of a solid-state imaging apparatus according to various embodiments of the present disclosure. Figure 2A This is a vertical cross-sectional view of a prior art recta shared pixel photodiode where the potential barrier is fixed at a relatively high state. Figure 2B It shows Figure 2A The existing technology uses the photodiode potential of the shared pixel in the recta. Figure 3A This is a vertical cross-sectional view of a prior art recta shared pixel photodiode where the potential barrier is fixed at a relatively low state. Figure 3B It shows Figure 3A The existing technology uses the photodiode potential of the shared pixel in the recta. Figure 4 This is a plan view of a portion of an imaging apparatus according to various embodiments of this disclosure. Figure 5 It is along Figure 4 The vertical sectional view of the imaging device, taken from section line 5-5'. Figure 6A It is along Figure 4 The imaging device is shown in a vertical sectional view of the shared pixels of the recta, taken by the section lines 6A-6A', where the variable barrier is set at a relatively high level. Figure 6B It is along Figure 4 The imaging device is shown in a vertical cross-sectional view of the shared pixels of the recta, taken by the section lines 6B-6B', where the variable barrier is set at a relatively high level. Figure 6C It is along Figure 4 The imaging device is shown in a vertical cross-sectional view of the shared pixels of the recta, taken by the section lines 6A-6A', where the variable barrier is set at a relatively low state. Figure 6D It is along Figure 4 The imaging device is shown in a vertical cross-sectional view of the shared pixels of the recta, taken by the section lines 6B-6B', where the variable barrier is set at a relatively low state. Figure 7 yes Figures 6A to 6D The planar graph of the surface of the shared pixels of the rectangle. Figure 8A This is a barrel-shaped conceptual diagram of a photodiode with a common pixel according to various embodiments of the present disclosure, wherein the variable barrier is set at a relatively low state. Figure 8B This is a barrel-shaped conceptual diagram of a photodiode with a common pixel according to various embodiments of the present disclosure, wherein a variable barrier is set at a relatively high state. Figure 9A The potential of a photodiode of a common pixel according to various embodiments of the present disclosure is shown, wherein a variable barrier is set to a relatively low state. Figure 9B The potential of a photodiode of a common pixel according to various embodiments of the present disclosure is shown, wherein a variable barrier is set to a relatively high state. Figure 10 This is an example of the circuit configuration of shared pixels for recta according to various embodiments of this disclosure. Figure 11A This is a vertical sectional view of the common pixels of the recta according to various embodiments of this disclosure. Figure 11B It is a plan view of the common pixels of the rectangle according to various embodiments of this disclosure. Figure 12A This is a vertical sectional view of the common pixels of the recta according to other embodiments of this disclosure. Figure 12B It is a plan view of the common pixels of the rectangle according to other embodiments of this disclosure. Figure 13A This is a vertical sectional view of the common pixels of the recta according to other embodiments of this disclosure. Figure 13B It is a plan view of the common pixels of the rectangle according to other embodiments of this disclosure. Figure 14 This is a block diagram of an imaging system including an imaging device according to various embodiments of this disclosure. Figure 15 This is a flowchart illustrating various aspects of the operation of an imaging apparatus including shared recta pixels according to various embodiments of the present disclosure. Figure 16 This is a timing diagram illustrating the operation of the shared pixels of the recta according to various embodiments of this disclosure. Detailed Implementation

[0010] Figure 1This diagram illustrates various aspects of an imaging apparatus or imaging sensor 100 according to embodiments of the present disclosure, which includes multiple photodiodes and single microlens pixels (referred to herein as recta shared pixels 104). As described herein, embodiments of the present disclosure allow the potential barriers between subpixels of the recta shared pixels 104 to change depending on the operating mode of the recta shared pixels 104. Typically, the imaging sensor 100 includes a plurality of recta shared pixels 104 arranged in an array 108. As disclosed herein, the recta shared pixels 104 are capable of selectively operating in a phase-detection autofocus mode or an imaging mode. Therefore, all pixels of the imaging sensor 100 can be in the form of the recta shared pixels 104 disclosed herein. According to other embodiments, the imaging apparatus 100 may include conventional imaging pixels and / or conventional PDAF pixels in addition to the phase-detection autofocus and imaging recta shared pixels 104 disclosed herein. The recta shared pixels 104 may be arranged in an array 108 having multiple rows and columns of recta shared pixels 104. Furthermore, the common pixel 104 of recta is formed on or within the sensor substrate 112. Additionally, one or more peripheral circuits or other circuits may be formed in connection with the sensor substrate 112. Examples of such circuits include a vertical drive circuit 116, a column signal processing circuit 120, a horizontal drive circuit 124, an output circuit 128, and a control circuit 132. As described in more detail elsewhere herein, each common pixel 104 of recta in the imaging apparatus 100 according to an embodiment of this disclosure includes a pair of photosensitive regions or a pair of photoelectric conversion elements (referred to herein as subpixels or photodiodes).

[0011] For example, the vertical drive circuit 116 may include a shift register operable to select pixel drive lines 136 and to provide custom voltage pulses for driving sub-pixels of the recta common pixel 104 row by row via the selected drive lines 136. The vertical drive circuit 116 may also selectively scan the elements of the array 108 row by row in the vertical direction and provide signals generated within the recta common pixel 104 corresponding to the amount of light received to the column signal processing circuit 120 via vertical signal lines 140.

[0012] The column signal processing circuit 120 can be operated to perform signal processing such as noise removal on the signal output from the shared recta pixel 104. For example, the column signal processing circuit 120 can perform signal processing such as correlated double sampling (CDS) processing to remove the specific fixed-pattern noise of the selected shared recta pixel 104, and analog-to-digital (A / D) conversion processing of the signal.

[0013] The horizontal drive circuit 124 may include a shift register. The horizontal drive circuit 124 can sequentially select each of the column signal processing circuits 120 by sequentially outputting horizontal scan pulses, causing each of the column signal processing circuits 120 to output a pixel signal to the horizontal signal line 144. The output circuit 128 can perform predetermined signal processing on the signals sequentially provided from each of the column signal processing circuits 120 via the horizontal signal line 144. For example, the output circuit 128 can perform buffering, black level adjustment, column difference correction, various digital signal processing, and other signal processing procedures. The input / output terminals 148 exchange signals between the imaging device 100 and external components or systems.

[0014] The control circuit 132 can receive data indicating the input clock and operating mode, and can output data such as internal information related to the imaging device 100. Therefore, the control circuit 132 can generate clock and control signals based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock. This clock signal provides a reference for the operation of the vertical drive circuit 116, the column signal processing circuit 120, and the horizontal drive circuit 124. The control circuit 132 outputs the generated clock and control signals to various other circuits and components.

[0015] Therefore, according to at least some embodiments of the present disclosure, at least a portion of the imaging device 100 may be configured as a column A / D type CMOS image sensor capable of performing column signal processing.

[0016] Figure 2A It is a vertical cross-sectional view of photodiodes 204a and 204b of the prior art recta sharing pixel 208, wherein the barrier 212 is fixed in a relatively high state; and Figure 2B The prior art diagram shows the potential 216 of photodiodes 204a and 204b of shared pixel 208, where the barrier 212 is fixed in a relatively high state. (See diagram for reference.) Figure 2B As shown, when recta shares a photodiode 204 in pixel 208 (e.g., Figure 2BWhen the right photodiode 204b in the middle reaches saturation, charge 220 overflows into the floating diffuser 224, instead of overflowing into the other photodiode 204 (e.g., Figure 2B (The left photodiode 204a in the image). This loss of charge to the floating diffuser 224 results in linearity errors in the signal output by the recta shared pixel 208. Specifically, the charge lost to the floating diffuser 224 is not reflected in the signal output by pixel 208. Therefore, the performance of the recta shared pixel 208, where the barrier 212 is fixed at a relatively high state, is impaired in certain imaging operations.

[0017] Figure 3A It is a vertical cross-sectional view of photodiodes 304a and 304b of the prior art recta sharing pixel 308, in which the barrier 312 is fixed in a relatively low state; and Figure 3B The prior art diagram shows the potential 316 of photodiodes 304a and 304b of shared pixel 308, where the barrier 312 is fixed at a relatively low state. (See diagram for reference.) Figure 3B As shown, when recta shares a common pixel 308, one of the photodiodes 304 (e.g., Figure 3B When the right photodiode 304b in the middle reaches saturation, charge 320 will overflow into another photodiode 304 (e.g., Figure 3B (The left photodiode 304 in the image). In other words, the relatively low barrier 312 between photodiodes 304 leads to a reduced separation ratio between them. Because the isolation between photodiodes 304a and 304b is relatively weak, phase-detection autofocus becomes difficult.

[0018] The embodiments disclosed herein overcome the limitations of prior art recta shared pixels with fixed barriers by providing a variable barrier between the photoelectric conversion region diodes of the recta shared pixel. Figure 4 This is a plan view of a portion of the surface of an imaging apparatus 100 according to various embodiments of the present disclosure, the imaging apparatus 100 including an array 108 of shared rectangular pixels 104, and Figure 5 It is along Figure 4The vertical sectional view is taken from section line 5-5'. In this example, each of the two shared pixels 104 of the recta includes two photoelectric conversion regions or photodiodes 404, which are positioned below a single microlens 408. Also in this example, the light incident surface of each photodiode 404 is rectangular, and the light incident surface of each shared pixel 104 of the recta is square. However, other configurations are possible. For example, each of the two shared pixels 104 of the recta may have a rectangular light incident surface, and each of the two shared pixels 104 of the recta may contain two square photodiodes, both of which are positioned below a single microlens 408. Figure 4 As shown, all photodiodes 404 of the recta shared pixel 104 located below a microlens 408 can share a floating diffuser 412. Alternatively, a separate floating diffuser can be provided for each recta shared pixel 104 or each photodiode 404. Furthermore, according to embodiments of this disclosure, the recta shared pixel 104 includes a control gate 416 along or adjacent to the boundary between the photodiodes 404 of the recta shared pixel 104.

[0019] Figure 6A and Figure 6C It is along Figure 4 A vertical sectional view of a single rectangle sharing a pixel 104, taken by section lines 6A-6A' of the imaging device 100. Figure 6B and Figure 6D It is along Figure 4 The imaging device's profile line 6B-6B' cuts a vertical sectional view of recta with 104 shared pixels, and Figure 7 yes Figure 6A , Figure 6C , Figure 6B and Figure 6D The recta is a planar view of the surface opposite to the light incident surface, which has 104 shared pixels. Figure 6A and Figure 6B and Figure 6C and Figure 6D The difference is that, Figure 6A and Figure 6B This illustrates that control gate 416 is operated to form a relatively large gap or overflow path 638 between sub-pixels 404, while Figure 6C and Figure 6DThe control gate 416 is shown to be operated to form a relatively small gap or overflow path 638 between sub-pixels 404. According to another embodiment of this disclosure, the size of the overflow path 638 can be controlled to any value between a maximum and a minimum. The recta common pixel 104 is formed in the semiconductor substrate 604 and includes a wiring region 616, a color filter 620, and an on-chip lens 408.

[0020] An intra-pixel separation portion or intra-pixel separation structure 636 is disposed between the photodiodes 404 of the shared recta pixel 104. The intra-pixel separation structure 636 may be composed of a semiconductor region configured to have a relatively high P-type impurity concentration, and electrically separates the N-type semiconductor regions 624 of the adjacent photodiodes 404 of the shared recta pixel 104 from each other. Alternatively or additionally, the intra-pixel separation structure 636 may be formed as a trench or wall extending between photodiodes 404a and 404b. According to at least some embodiments of this disclosure, a gap or overflow path 638 may be established between the gate electrode 648 of the control gate 416 and the nearest extent of the intra-pixel separation structure 636. The overflow path 638 may exist in one or both of the cross-sectional and planar views of the shared recta pixel 104 (see...). Figure 6A and Figure 7 ).

[0021] A pixel separation section 640 is disposed at the boundary of adjacent shared pixels 104 of recta. The pixel separation section 640 may be composed of a semiconductor region configured to have a relatively high P-type impurity concentration and / or trenches or walls. The pixel separation section 640 electrically separates adjacent shared pixels 104 of recta from each other.

[0022] The transmission gate 632 includes a gate electrode 644 disposed on or adjacent to the surface of the photodiode 404 opposite to the light incident surface. The control gate 416 may also include a control gate electrode 648 disposed on or adjacent to the surface of the semiconductor substrate 604 opposite to the light incident surface. As illustrated in the example, both gate electrodes 644 and 648 may be disposed on the surface of the insulating film 608. The control gate 416 modulates a barrier 652 for controlling the range of the overflow path 638. By applying a voltage to the control gate 416, the height of the barrier 652 can be adjusted, thereby adjusting the range of the overflow path 638. Gate electrodes 644 and 648 may be disposed in the same layer or at the same horizontal plane in the rectangular pixel 104 structure. According to another embodiment, gate electrodes 644 and 648 may be identical in size, shape, or both. According to another embodiment, gate electrodes 644 and 648 may be made of the same material. As an example, this material may be polycrystalline silicon. The insulating film 608 between the gate electrodes 644 and 648 and the surface of the semiconductor substrate 604 may include a gate insulating film.

[0023] A wiring region 616 is disposed on the side of the semiconductor substrate 604 opposite to the light incident surface, and is a region therein containing wiring for the shared pixel 104 of the recta. The wiring region 616 includes one or more wirings 656 and an insulating layer 660. The wirings 656 can transmit signals, etc., related to the photodiode 404 of the shared pixel 104 of the recta. The wirings 656 can be made of conductors such as copper (Cu) or tungsten (W). The insulating layer 660 insulates the wirings 656 and can be made of, for example, silicon oxide.

[0024] An insulating film 608 is optional, used to provide an insulating layer on the light-incident surface of the semiconductor substrate 604. For example, the insulating film 608 may be disposed between the light-incident surface of the semiconductor substrate 604 and the color filter 620. The insulating film 608 may be made of silicon oxide or silicon nitride. The color filter 620 is an optical filter that allows light within a predetermined wavelength range to pass through. For example, the color filter 620 may be a filter that allows red, green, or blue light to pass through. The on-chip lens 408 is a lens used to focus incident light and guide it to the photodiode 404. Therefore, the on-chip lens 408 may have a generally hemispherical shape and is configured to focus light onto the photodiode 404.

[0025] Overflow path 638 is located between photodiodes 404 within the recta shared pixel 104. In this example, overflow path 638 is formed by N-type or P-type semiconductor regions 664. According to embodiments of the present disclosure, control gate 416 can be operated to control the configuration of overflow path 638. More specifically, embodiments of the present disclosure default to maintaining control gate 416 in an ON state or a relatively high voltage state, thereby reducing the height of the effective barrier 652 between photodiodes 404 within the recta shared pixel 104. For example, by providing a relatively high voltage to control gate 416, the barrier 652 between photodiodes 404 can be equal to, approximately equal to, or lower than the barrier established by the intra-pixel separation structure 636 between photodiodes 404 of the recta shared pixel 104. Utilizing the reduced barrier, the recta shared pixel 104 is advantageously configured for use in imaging operations performed by imaging device 100. Furthermore, embodiments of this disclosure can selectively change the control gate 416 to an OFF (off) state or a relatively low voltage state, thereby increasing the height of the effective barrier between the photodiodes 404 of the shared pixel 104. For example, by providing a relatively low voltage to the electrode control gate 416, the barrier between the photodiodes 404 can be extended beyond the height of the barrier 652 established solely by the intra-pixel separation structure 636.

[0026] Figures 8A to 8B The variable properties of the effective barrier 804 (i.e., the barrier established by the combination of the intra-pixel separation structure 636 and the barrier 652) between the photodiodes 404 of the rectangular shared pixel 104 according to various embodiments of the present disclosure are shown. In particular, in Figure 8A In this configuration, control gate 416 is in a default or high-level state, and control electrode 648 is in a relatively high-voltage state, resulting in a relatively low effective separation degree or effective barrier 804, and correspondingly, a relatively large overflow path 638 between photodiodes 404. For example, the level of effective barrier 804 may be equal to, approximately equal to, or lower than the separation degree 908 provided solely by the intra-pixel separation unit 636 (see [link to relevant documentation]). Figure 9A ).exist Figure 8B In this configuration, control gate 416 is controlled to a low level, resulting in a relatively low voltage state and thus a relatively high effective barrier 804. Consequently, this results in a relatively small overflow path 638 between photodiodes 404. Specifically, when control gate 416 is in the off state, the voltage supplied to control gate 648 is low, and the barrier 804 between photodiodes 404 causes the separation between photodiodes 404 to increase beyond the separation level 908 provided solely by the intra-pixel separation section 636 (see [link to relevant documentation]). Figure 9B ).

[0027] Figures 9A to 9B The effects of establishing an effective barrier 804 at different levels are shown. Specifically, in Figure 9A In this configuration, when the control gate 416 is in a high-level or ON state, and the control electrode 648 is in a default, relatively high-voltage state, the effective height of the effective barrier 804 between the photodiodes 404 is relatively low. According to at least some embodiments, the height of the effective barrier 804 is equal to, approximately equal to, or lower than the height of the barrier 908 established solely by the in-pixel separation structure 636. As a result, when one of the two photodiodes 404 saturates, charge 904 overflows along the overflow path 638 to the other photodiode 404 before reaching the potential 912 at which charge will overflow to the floating diffuser 658. By preventing charge overflow to the floating diffuser 658, linearity errors in the shared recta pixel 104 during imaging mode can be avoided. Figure 9A The diagram illustrates a situation where the right photodiode 404 is saturated and charge 904 overflows into the left photodiode 404, which receives the overflowed charge 904. However, those skilled in the art will understand upon reading this disclosure that the opposite is also possible, i.e., the left photodiode 404 is saturated and the right photodiode 404 receives the overflowed charge 904.

[0028] exist Figure 9B In this diagram, the control gate 416 is shown in a selected relatively low voltage state, resulting in a relatively high barrier 804 between the two photodiodes 404 of the recta shared pixel 104. Furthermore, regarding the barrier 804 established when the control gate 416 is in a low-level or OFF state and the control electrode 648 is in a relatively low voltage state, the effective height of the barrier 804 between the photodiodes can be significantly higher (e.g., 10% to 25% higher) than the height of the barrier 908 established solely by the intra-pixel separation portion 636 (i.e., without the influence of the voltage at the control gate 648). Accordingly, when the control gate 416 is in the OFF state, a relatively high degree of separation or isolation is maintained between the photodiodes 404. This higher degree of separation is preferred when the recta shared pixel 104 operates in phase-detection autofocus mode.

[0029] Figure 10This is an example of a circuit configuration for a shared recta pixel 104 according to various embodiments of the present disclosure. In this example, the shared recta pixel 104 includes: a first (e.g., left) photodiode 404a and a second (e.g., right) photodiode 404b; separate charge holding or floating diffuser sections 658a and 658b; transmission gates 632a and 632b; a reset transistor 1004; an amplifying transistor 1008; a selection transistor 1012; an overflow path 638; and a control gate 416. As an example, but not limited to this example, the transmission gate 632, reset transistor 1004, amplifying transistor 1008, and selection transistor 1012 may be constructed from n-channel MOS transistors. Although the circuit diagram shows a separate floating diffuser section 658 structure connected by conductors, those skilled in the art will understand that other configurations may also be used. For example, a shared floating diffuser section 658 structure may be provided. As another example, separate floating diffuser section 658 structures that can be selectively connected or separated from each other may be provided.

[0030] Each pixel 104 of the imaging device 100 is connected to a pixel drive wiring 136 and a vertical signal line 140. The pixel drive wiring 136 may include, for example, a signal line GATE for a control gate 416, a signal line TRG1 for a first transmission gate 632a, a signal line TRG2 for a second transmission gate 632b, a signal line RST for a reset transistor 1004, and a signal line SEL for a select transistor 1012. Pixel 104 is also connected to a power supply line Vdd. Each photodiode 404 has a grounded anode and a cathode connected to a corresponding transmission gate 632. The drain of each transmission gate 632 is connected to the source of the reset transistor 1004 and one end of a corresponding floating diffuser 658. The other end of each floating diffuser 658 may be grounded. The drain of the reset transistor 1004 is connected to the power supply line Vdd. The drain of the amplifying transistor 1008 is connected to the power supply line Vdd, and the source of the amplifying transistor 1008 is connected to the drain of the select transistor 1012. The source of the select transistor 1012 is connected to the signal line VO. The overflow path 638 extends between the cathodes of the photoelectric conversion unit 404.

[0031] A photodiode 404 performs photoelectric conversion on incident light. The photodiode 404 may be formed on or within a semiconductor substrate 604. More specifically, the photodiode 404 performs photoelectric conversion on incident light during exposure. The charge generated by exposing the photodiode 404 to incident light is transferred to a floating diffuser 658 via a transfer gate 632. The floating diffuser 658 is a semiconductor region formed in the semiconductor substrate 604. A reset transistor 1004 resets the floating diffuser 658 by turning it on and connecting it to the power supply line Vdd. An amplifying transistor 1008 amplifies the voltage of the floating diffuser 658. Therefore, an image signal with a voltage corresponding to the charge held in the floating diffuser 658 is generated at the source of the amplifying transistor 1008. This image signal can be output to the signal line VO by turning on the select transistor 1012.

[0032] The transmission gate 632, reset transistor 1004, amplification transistor 1008, and select transistor 1012 can be configured as n-channel MOS transistors. These transistors are turned on by applying a voltage exceeding a threshold voltage between the gate and source on their respective gates.

[0033] As described herein, overflow path 638 allows charge to overflow from one photodiode 404 to another. Overflow path 638 can be formed in a semiconductor region disposed between photodiodes 404. Control gate 416 allows the barrier of overflow path 638 to be modulated, and control gate 416 can be configured as an electrode 648 arranged adjacent to overflow path 638.

[0034] When the shared pixel 104 of the recta operates in phase detection autofocus mode, the transmission gates 632a and 632b are operated sequentially to individually transfer the charge generated by the corresponding photoelectric conversion units 404a and 404b to the floating diffuser 658 at their respective dedicated times. This charge transfer is called individual transfer. Therefore, a phase difference signal based on the charge individually transferred to the floating diffuser 658 can be output.

[0035] When the shared pixel 104 operates in imaging mode, transmission gates 632a and 632b are operated in unison to jointly transfer the charge generated by photoelectric conversion units 404a and 404b to the floating diffuser 658. In imaging mode, the floating diffuser 658 simultaneously retains the charge generated by photodiode 404. This charge transfer is called collective transfer. Therefore, an image signal based on the charge collectively transferred to the floating diffuser 658 can be output.

[0036] Figure 11AThis is a vertical sectional view of the common pixel 104 of the rectangle according to various embodiments of this disclosure, and Figure 11B yes Figure 11A The planar view of the surface of the common pixel 104 in the recta is shown. In this example, the control gate 416 has an electrode 648 disposed adjacent to the overflow path 638 and configured as a planar electrode 1104 disposed on the surface of the semiconductor substrate 604 on which the photodiode 404 is formed. This configuration is suitable for the overflow path within the recta pixel located near the silicon surface opposite to the microlens.

[0037] Figure 12A This is a vertical sectional view of the common pixel 104 of the rectangle according to other embodiments of this disclosure, and Figure 12B yes Figure 12A The planar view of the surface of the recta shared pixel 104 is shown. In this example, the control gate 416 has an electrode 648 disposed adjacent to the overflow path 638 and configured as a single T-shaped electrode 1204. The planar surface portion 1208 of the T-shaped electrode 1204 is disposed on the surface of the semiconductor substrate 604, and the vertical portion 1212 of the T-shaped electrode 1204 extends from the planar surface portion 1208 toward the light incident surface side of the semiconductor substrate 604. This configuration is suitable for overflow paths within the recta pixel that are away from the silicon surface opposite to the microlens. The vertical portion of the T-shaped electrode can be designed to adjust its length by modifying the manufacturing method to reach the overflow path.

[0038] Figure 13A This is a vertical sectional view of the common pixel 104 of the rectangle according to other embodiments of this disclosure, and Figure 13B yes Figure 13A The rectangles share a 104-pixel planar map or surface. In this example, the control gate 416 has an electrode 648 disposed adjacent to the overflow path 638 and configured as a T-shaped electrode 1304, the T-shaped electrode including: a planar surface portion 1308 disposed on the surface of the semiconductor substrate 604; and a pair of vertical portions 1312a and 1312b extending from the planar surface portion 1308 toward the light incident surface side of the semiconductor substrate 604. This configuration maintains Figure 12A The advantages of the depth reach described in the text are that it provides relatively better control over the potential manipulation by using two electrodes.

[0039] Figure 14This is a block diagram of an imaging system including an imaging device 100 according to various embodiments of the present disclosure. In this example, the imaging system takes the form of a camera 1400. As shown, the camera 1400 includes an optical system or lens 1401, an imaging device 100 having a plurality of shared pixels 104 as described herein, an imaging and autofocus control unit 1403, a lens drive unit 1404, an image processing unit 1405, an operation input unit 1406, a display unit 1408, and a recording unit 1409.

[0040] Optical system 1401 includes an objective lens of camera 1400. Optical system 1401 collects light from within the field of view of camera 1400, which can encompass a scene containing objects. Those skilled in the art will understand upon reading this disclosure that the field of view is determined by various parameters, including the focal length of the lens, the size of the effective area of ​​the array 108 of pixels 104 of imaging device 100, and the distance of the array 108 from the lens. In addition to the lens, optical system 1401 may also include other components such as a variable aperture and a mechanical shutter. Optical system 1401 guides the collected light to imaging device 100, thereby forming an image of the object on the light incident surface of imaging device 100.

[0041] As described elsewhere in this document, the imaging device 100 includes a plurality of shared rectangular pixels 104 arranged in an array 108. Furthermore, the imaging device 100 may include a semiconductor element or substrate 112, wherein each of the shared rectangular pixels 104 includes a plurality of photodiodes 404 formed as photosensitive regions within the substrate 112. Additionally, as described elsewhere in this document, each shared rectangular pixel 104 can selectively operate in an imaging mode as the default mode or in a phase-detection autofocus mode. The photodiodes 404 generate an amount of charge proportional to the amount of light incident upon them. These signals can be converted into digital signals, for example, in circuitry such as column signal processing circuitry 120, which is part of the imaging sensor 100, or in a separate circuit or processor. These signals can then be output.

[0042] The imaging control unit 1403 controls the imaging operation of the image imaging device 100 by generating a control signal and outputting the control signal to the imaging device 100. Furthermore, the imaging control unit 1403 can perform autofocus in the camera 1400 based on the image signal output from the imaging device 100. Here, "autofocus" refers to a system that detects the focal position of the optical system 504 and automatically adjusts the focal position. For example, a method can be used to detect image plane phase difference (image plane phase difference autofocus) by having a portion or all of the shared pixels 104 of the imaging device 100 operate in phase difference detection mode. Based on the detected focal position, the imaging control unit 1403 adjusts the position of the lens 1001 via the lens drive unit 1404, thereby achieving autofocus. Note that the imaging control unit 1403 may include, for example, a digital signal processor (DSP) equipped with firmware.

[0043] The lens drive unit 1404 drives the optical system 504 based on the control of the imaging control unit 1403. The lens drive unit 1404 can drive the optical system 1401 by changing the position of the included lens elements using a built-in motor.

[0044] The image processing unit 1405 processes the image signal generated by the imaging device 100. The image processing unit 1405 may include, for example, a microcomputer equipped with firmware and / or a processor executing an application program to implement the processing described herein for identifying color information in the acquired image information.

[0045] The operation input unit 1406 receives operation input from the user of the camera 1400. The operation input unit 1406 can be, for example, a button or a touch panel. The operation input received by the operation input unit 1406 is sent to the imaging control unit 1403 and the image processing unit 1405. Then, processing corresponding to the operation input begins, such as acquiring and processing an image of an object.

[0046] The display unit 1408 can display information processed by the image processing unit 1405. For example, a liquid crystal panel can be used as the display unit 1408.

[0047] The recording unit 1409 records the image data processed by the image processing unit 1405. For example, a memory card or a hard disk can be used as the recording unit 1409.

[0048] The foregoing has described an example of a camera 1400 to which various embodiments of the present disclosure may be applied. The imaging device 100 of the camera 1400 may be configured as described herein. Specifically, the imaging device 100 may include a plurality of shared recta pixels 104. Each shared recta pixel 104 may operate by default in an imaging mode, in which the included photodiodes 404 have a relatively low potential barrier; each shared recta pixel 104 may selectively operate in a phase difference detection autofocus mode, in which the included photodiodes 404 have a relatively high potential barrier.

[0049] Figure 15 This is a flowchart illustrating the operation of an imaging apparatus or imaging sensor 100 comprising a plurality of shared rectangular pixels according to various embodiments of the present disclosure. First, in step 1504, an operating mode of the imaging sensor 100 is selected. According to embodiments of the present disclosure, the default operating mode of the imaging sensor 100 is an imaging mode in which a relatively low potential barrier is maintained between some or all of the photodiodes 404 within the shared rectangular pixels 104. The operating mode of the imaging sensor 100 can be determined by the operation of, for example, a camera 1400 or a processor 1405 in another system containing the imaging sensor 100.

[0050] In step 1508, the selected operating mode is detected. When it is determined that a phase-detection autofocus mode has been selected, in response, the control gate 648 is placed in a relatively low voltage state, which has the effect of increasing the potential barrier between the photodiodes 404 within the recta shared pixel 104 (step 1512). Then, for each recta shared pixel 104 involved in the autofocus operation, the amount of charge generated in each photodiode 404 of the recta shared pixel 104 is read out individually (step 1516). Those skilled in the art will understand after reading this disclosure that the relative amount of charge generated by different photodiodes 404 within a given recta shared pixel 104 can indicate the focusing state of the optical system 1401. Specifically, when the amount of charge generated by each photodiode 404 within a given recta shared pixel 104 is equal, the recta shared pixel 104 indicates a "focused" state. When the amount of charge generated by each photodiode 404 within a given recta shared pixel 104 is different, the recta shared pixel 104 indicates a "disfocused" state. According to other embodiments of this disclosure, if one photodiode 404 within the shared pixel 104 of the recta has a larger relative charge than another photodiode 404, then it indicates that the lens drive unit 1404 should drive the optical system 1401 in a direction to achieve a focusing state.

[0051] When it is determined in step 1508 that an imaging mode has been selected, in response, the control gate 648 remains in the default state, that is, the control gate 648 remains in a relatively high voltage state or an "ON" state, thereby reducing the potential barrier between the photodiodes 404 of the shared recta pixel 104 (step 1520). Then, for each shared recta pixel 104 involved in the imaging operation, the amount of charge generated in each photodiode 404 of the shared recta pixel 104 is collectively read out (step 1524).

[0052] After reading the photodiode signal 404 individually from the shared recta pixel 104 at step 1516, or after reading the photodiode signal 404 collectively from the shared recta pixel 104 at step 1524, it can be determined whether the operation of the imaging sensor 100 should continue (step 1528). If operation is to continue, the process can return to step 1504. Otherwise, the process can end. Those skilled in the art will understand after reading this disclosure that, in phase detection autofocus mode, the operation of the shared recta pixel 104 may include operating these shared recta pixels 104 within a selected area or autofocus area of ​​the array 108 of shared recta pixels 104. Those skilled in the art will also understand after reading this disclosure that, in imaging mode, signals from all shared recta pixels 104 within the imaging sensor 100 are typically used to generate an image.

[0053] Figure 16 This is a timing diagram of the operation of the common pixel 104 of the imaging sensor 100 according to various embodiments of the present disclosure. More specifically, an example of the generation of image signals and phase difference autofocus signals according to various embodiments of the present disclosure is shown. In this figure, “RST”, “SEL”, “TRG1”, “TRG2”, and “GATE” represent the signals on signal lines RST, SEL, TRG1, TRG2, and GATE, respectively. More specifically, these signals are represented as waveforms of binarized control signals. In this figure, “FD” represents the potential of the floating diffuser 658. “VO” represents the output of signal line VO. The first half of the figure 1604 shows the operation of the imaging sensor 100 in phase detection autofocus mode, and the second half of the figure 1608 shows the operation of the imaging sensor 100 in imaging mode.

[0054] In the initial state, a value of "0" (i.e., low value) is applied to signal lines RST, SEL, TRG1, and TRG2. In the initial state, a value of "1" (i.e., high value) is applied to signal line GATE connected to control gate 416. Furthermore, control gate 416 is kept high, thus defaulting to the "ON" state. That is, except when the associated shared recta pixel 104 is operating in phase detection autofocus mode, control gate 416 is provided with a relatively high voltage, corresponding to the lower potential barrier between the photodiodes 404 of the shared recta pixel 104.

[0055] At time T1, an "ON" signal is applied to signal lines RST, TRG1, and TRG2. As a result, reset transistor 1004 and transmission gate 632a become ON, and photodiode 404 and floating diffuser 658 are reset. Additionally, signal line GATE, which has been applying a relatively high voltage to control gate 416, becomes a relatively low voltage state at time T1.

[0056] At T2, the "ON" signal is stopped being applied to signal lines RST and TRG1. For example, the voltage or signal applied to signal lines RST and TRG1 is changed from a high value to a low value. As a result, the exposure period begins, and the charge generated by the photoelectric conversion of the incident light is accumulated in the photodiodes 404 of the shared pixel 104. At T2, GATE remains in the "OFF" signal state. Since the potential barrier between photodiodes 404 is raised when a relatively low voltage is applied to the control gate 416 through the GATE signal line, the overflow path 638 between photodiodes 404 is relatively contracted. Therefore, when the exposure period of the phase detection autofocus process begins, the potential barrier is configured to enhance the separation between photodiodes 404, thereby establishing a good separation ratio between photodiodes 404.

[0057] At T3, an "ON" signal is applied to the signal line SEL. The "ON" signal is continuously applied to the signal line SEL until the phase difference signal of all pixels 104 in the selected pixel area is output.

[0058] At T4, an "ON" signal is applied to the signal line RST, and the floating diffuser 658 is reset.

[0059] At time T5, the "ON" signal is stopped being applied to the signal line RST. From time T5 to time T6, the reset signal "a" is output from the signal line VO.

[0060] At T6, an "ON" signal is applied to signal line TRG1. This turns the first transmission gate 632a on, thereby transferring the charge accumulated in the first photodiode 404a to the floating diffuser 658a, and ending the exposure period of the photodiode 404a.

[0061] At time T7, the "ON" signal is stopped being applied to signal line TRG1. From time T7 to time T8, an image signal "b" corresponding to the charge of photodiode 404a is output from signal line VO. Then, correlated double sampling is performed using image signal "a" and image signal "b" to generate the first phase difference signal of the shared pixel 104 of recta.

[0062] At T8, an "ON" signal is applied to the signal line RST, and each floating diffuser 658 is reset.

[0063] At time T9, the "ON" signal is stopped being applied to the signal line RST. From time T9 to time T10, the reset image signal "c" is output from the signal line VO.

[0064] At T10, an "ON" signal is applied to signal line TRG2. This turns the second transmission gate 632b on, thereby transferring the charge accumulated in the second photodiode 404b to the floating diffuser 658, and ending the exposure period of the photodiode 404b.

[0065] At T11, the "ON" signal applied to signal line TRG2 is stopped. An image signal "d" corresponding to the charge of photodiode 404a is output from signal line VO. Then, correlated double sampling is performed using image signal "c" and image signal "d" to generate a second phase difference signal for the shared pixel 104 of the recta. Subsequently, the first and second phase difference signals can be compared to determine the focus state of the light incident on the shared pixel 104 of the recta.

[0066] Next, imaging operation 1608 will be described. At T12, an "ON" signal is applied to signal lines RST, TRG1, TRG2, and GATE. As a result, reset transistor 1004 and each transmission gate 632 become switched on, and each photodiode 404 and each floating diffuser 658 are reset. In addition, since a relatively high voltage is applied to the control gate 648 through signal line GATE, the potential barrier between the photodiodes remains at a low level.

[0067] At T13, the "ON" signal is stopped being applied to signal lines RST, TRG1, and TRG2. As a result, the exposure period of imaging operation 1608 begins, and the charge generated by photoelectric conversion is accumulated in photodiode 404.

[0068] At T14, an "ON" signal is applied to the signal line SEL. The "ON" signal is continuously applied to the signal line SEL until the image signal of all rectangles sharing pixels 104 in the pixel area is output.

[0069] At T15, an "ON" signal is applied to the signal line RST, and each floating diffuser 658 is reset. At T15, the exposure period ends.

[0070] At T16, stop applying the "ON" signal to the RST signal line. Output the reset image signal "e" from the VO signal line until T17.

[0071] At T17, an "ON" signal is applied to signal lines TRG1 and TRG2. As a result, transmission gate 632 becomes switched on, and the charge accumulated in photodiode 404 is transferred to floating diffuser 658.

[0072] At T18, the application of the "ON" signal to signal lines TRG1 and TRG2 is stopped. Then, an image signal "f" corresponding to the charge of the two photodiodes 404 within pixel 104 shared with recta is output from signal line VO. Correlated double sampling is then performed using the image signal "e" and the image signal "f" to generate the image signal.

[0073] It is worth noting that the voltage supplied to the control gate 648 via the GATE signal line is maintained at a high voltage throughout the entire imaging operation 1608. Therefore, the potential barrier between the photodiodes 404 sharing the recta pixel 104 is relatively low, thereby reducing the likelihood of charge overflowing into the floating diffuser 658 during imaging operation 1608. Furthermore, maintaining a high voltage at the control gate 648 has the added advantage that the high positive voltage maintained throughout all periods except during phase-detection autofocus operation allows the photodiodes 404 to retain more charge than when the control gate 648 is at a lower or negative voltage. This, in turn, improves the dynamic range compared to other similar photodetectors that do not maintain a high positive voltage during most operational phases.

[0074] The foregoing description is provided for illustrative purposes only. Furthermore, this description is not intended to limit the disclosed systems and methods to the forms disclosed herein. Therefore, variations and modifications consistent with the foregoing teachings and within the scope of art or knowledge fall within the protection scope of this disclosure. The above embodiments are also intended to illustrate the best known modes for implementing the systems and methods disclosed herein, and to enable those skilled in the art to utilize the disclosed systems and methods in these or other embodiments, and to make various modifications as needed depending on the specific application or use. The appended claims are intended to be construed as including alternative embodiments permitted by the prior art.

Claims

1. An imaging device, comprising: Semiconductor substrate; and Multiple shared pixels of recta are disposed in the semiconductor substrate. Wherein, each of the recta shares pixels including: First photoelectric conversion region; Second photoelectric conversion region; An intra-pixel separation structure, wherein the intra-pixel separation structure establishes a separation barrier between the first photoelectric conversion region and the second photoelectric conversion region; Control gates; and The path between the separation structure and the control gate. In the default operating mode, a first voltage is provided to the control gate to increase the effective size of the path, thereby reducing the potential barrier between the first photoelectric conversion region and the second photoelectric conversion region. In another operating mode, a second voltage is provided to the control gate to decrease the effective size of the path, thereby increasing the potential barrier between the first photoelectric conversion region and the second photoelectric conversion region. The first voltage is higher than the second voltage.

2. The imaging apparatus as claimed in claim 1, wherein, The control gate includes control gate electrodes, and In the default operating mode, the first voltage is provided to the control gate electrode; in the other operating mode, the second voltage is provided to the control gate electrode.

3. The imaging apparatus as claimed in claim 2, wherein, There is a gap between the intra-pixel separation structure and the control gate electrode.

4. The imaging apparatus as claimed in claim 3, wherein, The control gate electrode includes a planar structure adjacent to a surface of the semiconductor substrate opposite to the light incident surface of the semiconductor substrate.

5. The imaging apparatus as claimed in claim 4, wherein, The control gate electrode further includes a vertical portion extending toward the light incident surface of the semiconductor substrate.

6. The imaging apparatus as claimed in claim 4, wherein, The control gate electrode further includes a first vertical portion and a second vertical portion extending toward the light incident surface of the semiconductor substrate.

7. The imaging apparatus as claimed in claim 2, wherein, Each of the shared pixels for the recta also includes: A first transmission gate selectively connects the first photoelectric conversion region to a first floating diffuser; and The second transmission gate selectively connects the second photoelectric conversion region to the second floating diffuser.

8. The imaging apparatus of claim 7, wherein, The first transmission gate includes a first transmission gate electrode. The second transfer gate includes a second transfer gate electrode, and The first transmission gate electrode and the second transmission gate electrode are located on the same plane as the control gate electrode.

9. The imaging apparatus of claim 8, wherein, The first transmission gate and the second transmission gate have the same size.

10. The imaging apparatus of claim 9, wherein, The first transmission gate and the second transmission gate have the same shape.

11. The imaging apparatus of claim 10, wherein, The control gate is made of the same material as the first transmission gate and the second transmission gate.

12. The imaging apparatus of claim 11, wherein, The control gate has the same shape as the first transmission gate and the second transmission gate.

13. The imaging apparatus of claim 1, wherein, The first photoelectric conversion region is a first photodiode, and The second photoelectric conversion region is a second photodiode.

14. A system comprising an imaging lens, an image sensor, and a processor, The image sensor includes multiple shared pixels arranged in an array. in, Each of the plurality of shared rectangular pixels includes: First photoelectric conversion region; Second photoelectric conversion region; An intra-pixel separation structure, wherein the intra-pixel separation structure establishes a separation barrier between the first photoelectric conversion region and the second photoelectric conversion region; and A control gate, which is positioned adjacent to the intra-pixel separation structure. Regarding the control gate, in the default operating mode, a first voltage is provided to the control gate to lower the effective potential barrier between the first photoelectric conversion region and the second photoelectric conversion region; in another operating mode, a second voltage is provided to the control gate to raise the effective potential barrier between the first photoelectric conversion region and the second photoelectric conversion region; and the first voltage is higher than the second voltage, and Regarding the processor, in the default mode, a first voltage is provided to the control gate of at least a portion of the shared recta pixels, and the effective potential barrier between the first photoelectric conversion region and the second photoelectric conversion region of the at least a portion of the shared recta pixels is equal to or less than the potential barrier established by the separate structure within the pixel alone; in another operating mode, a second voltage is provided to the control gate of the at least a portion of the shared recta pixels, and the effective potential barrier between the photoelectric conversion regions is greater than the effective potential barrier between the photoelectric conversion regions when the first voltage is provided to the control gate of the at least a portion of the shared recta pixels; and the first voltage is higher than the second voltage.

15. A method comprising: An image sensor is provided, the image sensor having a semiconductor substrate and a plurality of shared recta pixels disposed in the semiconductor substrate, wherein each of the shared recta pixels includes: First photoelectric conversion region; Second photoelectric conversion region; Intra-pixel separation structure, wherein the intra-pixel separation structure establishes a separation barrier between the first photoelectric conversion region and the second photoelectric conversion region; and A control gate, wherein the control gate is disposed adjacent to the intra-pixel separation structure; In the default operating mode, a first voltage is provided to the control gate of the plurality of shared recta pixels to reduce the effective potential barrier between the first photoelectric conversion region and the second photoelectric conversion region of each shared recta pixel; and In another operating mode, a second voltage is provided to the control gate of the plurality of shared recta pixels to increase the effective potential barrier between the first photoelectric conversion region and the second photoelectric conversion region of each shared recta pixel. The first voltage is higher than the second voltage. The default operating mode includes imaging mode, and The other operating mode includes phase detection autofocus mode.

16. The method of claim 15, wherein, The second voltage is provided to the control gate of the plurality of shared pixels only during the phase detection autofocus mode.

17. The method of claim 15, wherein, In the operating mode of the phase detection autofocus mode, the effective potential barrier is greater than the potential barrier established solely by the intra-pixel separation structure.

18. The method of claim 15, wherein, In the operating mode of the imaging mode, the effective potential barrier is equal to or less than the potential barrier established solely by the intra-pixel separation structure.

19. The method of claim 15, wherein, The intra-pixel separation structure is separated from the control gate by a gap.

20. The method of claim 15, wherein, The photoelectric conversion region is a photodiode.

Images