Circuit board and semiconductor package comprising the same

Abstract

An embodiment of the present application provides a circuit board including: a first build-up layer; and a first-1 wiring part and a first-2 wiring part having a larger line width / interval than the first-1 wiring part, which are provided on the first build-up layer, wherein the line width / interval of the first-1 wiring part is 1.7 μm to 3 μm.

Description

Technical Field

[0001] An embodiment of the present invention relates to a circuit board and a semiconductor package. Background Technology

[0002] As electrical / electronic products become increasingly high-performance, technologies for attaching mass packages to substrates of finite size have been proposed and researched. However, since typical packages are essentially based on mounting a single semiconductor chip, there are limitations in achieving the desired performance.

[0003] A typical circuit board or packaging substrate has the form in which a processor package, on which a processor chip is mounted, and a memory package, on which a memory chip is attached, are integrated into one unit. The advantage of this type of packaging substrate is that by manufacturing the processor chip and memory chip into a single integrated package, the chip mounting area is reduced, and high-speed signal processing can be achieved through short paths. Due to these advantages, this type of packaging substrate is widely used in mobile devices and other applications.

[0004] On the other hand, in recent years, package size has increased due to the higher specifications of electronic devices such as mobile devices and the adoption of High Bandwidth Memory (HBM). Furthermore, as the required functions of application processors increase, a circuit board is needed that can configure these functions individually as separate processor chips and mount these processor chips. In this case, even when the application processor is divided into two processor chips according to function, the number of terminals (input / output) set in each processor chip is increasing.

[0005] Furthermore, with recent trends such as 5G, the Internet of Things (IoT), improved image quality, and faster communication speeds leading to an increase in the number of power and signal lines, the number of terminals on processor chips is also gradually increasing. Consequently, the area and thickness of circuit boards, as well as the density of circuit patterns, are also increasing. When the area and thickness of circuit boards increase, issues arise such as difficulties in product miniaturization, reliability problems such as circuit board warpage, and increased product prices. Therefore, increasing the density of circuit patterns, rather than increasing the area and thickness of the circuit board, is more advantageous in terms of product price, reliability (such as minimizing warpage), and product miniaturization. Therefore, miniaturization of circuit patterns and via electrodes is necessary.

[0006] Furthermore, in order to connect bare dies on a substrate such as an interposer without embedding a bridging substrate, it is necessary to form fine patterns. However, when forming fine patterns, there are limitations such as reduced reliability of electrode portions or difficulty in manufacturing, depending on the linewidth and aspect ratio. Summary of the Invention

[0007] Technical issues

[0008] Embodiments of the present invention relate to implementing a circuit board and a semiconductor package including the circuit board, in which, as the semiconductor devices connected to the circuit board are miniaturized, the width and spacing of the circuit patterns in the circuit board are also reduced, and wherein the wiring density per unit area is increased by having a predetermined line width / spacing (L / S), thereby facilitating manufacturing and improving mechanical reliability.

[0009] Furthermore, embodiments can realize a circuit board and a semiconductor package including the circuit board, wherein fine patterns are densely arranged and the aspect ratio (thickness / width) is formed within a predetermined range, so that the required electrical characteristics such as high-density interposers are easily met and the number of inputs / outputs (I / O) generated by the fine patterns is increased.

[0010] Furthermore, the embodiments can realize a circuit board and a semiconductor package including the circuit board, in which miniaturization can be easily achieved by having a smaller thickness compared to other stacked layers.

[0011] The technical problems to be solved in the embodiments are not limited to those described above, and it should be understood that these problems also include the objectives or effects that can be understood from the technical solutions or embodiments described below.

[0012] Technical solution

[0013] The circuit board according to an embodiment of the present invention includes: a first stacked layer; and a first-1 wiring portion disposed on the first stacked layer and a first-2 wiring portion having a larger line width / spacing than the first-1 wiring portion, wherein the line width / spacing of the first-1 wiring portion is 1.7 μm to 3 μm.

[0014] The first-1 wiring section may include a lower region, a middle region on the lower region, and an upper region on the middle region along the stacking direction.

[0015] The length of each of the lower, middle, and upper regions in the stacking direction can be greater than 0.5 times the line width / spacing of the first-1 wiring section.

[0016] The lower region may include a first sub-region extending from the upper surface to a first surface having a minimum width or diameter, and a second sub-region extending from the first surface to the lower surface.

[0017] The angle formed by the outer surface of the first sub-region and the first surface can be different from the angle formed by the outer surface of the second sub-region and the first surface.

[0018] The lower region may have an upwardly raised surface on its lower surface.

[0019] The raised surface can be located below the first surface.

[0020] The lower region may have a width or diameter that decreases from the upper surface toward the lower surface.

[0021] The width or area of ​​the upper surface of the lower region can be greater than the width or area of ​​the lower surface of the lower region.

[0022] The thickness of each of the 1-1 wiring section and the 1-2 wiring section can be from 6 μm to 15 μm.

[0023] The aspect ratio (thickness / width) of the first-to-first wiring section can be from 2.3 to 8.9.

[0024] The aspect ratio (thickness / width) of the first-second wiring section can be smaller than that of the first-first wiring section.

[0025] The circuit board may also include a core layer, wherein a first stacked layer may be disposed on the upper surface of the core layer.

[0026] The circuit board may include: a lower stacked layer disposed below the core layer; and a second electrode portion, the second electrode portion including a second wiring portion and a second via electrode disposed in the lower stacked layer.

[0027] The line width / spacing of the second wiring section can be greater than that of the first wiring section.

[0028] Beneficial effects

[0029] Embodiments of the present invention provide a circuit board and a semiconductor package including the circuit board, wherein, as semiconductor devices and the like connected to the circuit board are miniaturized, the width and spacing of the circuit patterns in the circuit board are also reduced, and wherein, by having a predetermined line width / spacing (L / S), the wiring density per unit area is increased, thereby facilitating manufacturing and improving mechanical reliability.

[0030] Furthermore, embodiments may provide a circuit board and a semiconductor package including the circuit board, wherein fine patterns are densely arranged and the aspect ratio (thickness / width) is formed within a predetermined range, such that the required electrical characteristics, such as high-density interposers, are easily satisfied and the number of inputs / outputs (I / O) generated by the fine patterns is increased.

[0031] Furthermore, embodiments may provide a circuit board and a semiconductor package including the circuit board, in which miniaturization can be easily achieved by having a smaller thickness compared to other stacked layers.

[0032] The various advantages and effects of the present invention are not limited to those described above, and will be more readily understood in the process of describing specific embodiments of the present invention. Attached Figure Description

[0033] Figure 1 This is a cross-sectional view of a circuit board according to an embodiment of the present invention.

[0034] Figure 2 yes Figure 1 A magnified view of part K1 in the image.

[0035] Figure 3 This is a plan view of the first wiring portion and the first stacked layer in the circuit board according to the embodiment.

[0036] Figure 4 yes Figure 1 A magnified view of part K2 in the image.

[0037] Figure 5 This is a diagram illustrating the effect of the line width / spacing of the first wiring portion in the circuit board according to an embodiment.

[0038] Figure 6 This is a diagram showing a first example of the first wiring section 1-1 in a circuit board according to an embodiment.

[0039] Figure 7 This is a diagram showing a second example of the first wiring portion 1-1 in a circuit board according to an embodiment.

[0040] Figure 8 This is a diagram showing a third example of the first wiring portion 1-1 in a circuit board according to an embodiment.

[0041] Figure 9 and Figure 10 This is a photograph of the first wiring section in the circuit board according to the embodiment.

[0042] Figures 11 to 16 This is a diagram illustrating a method for manufacturing a circuit board according to an embodiment.

[0043] Figure 17 This is a view showing semiconductor devices stacked on a circuit board according to an embodiment of the present invention.

[0044] Figure 18 This is a diagram illustrating the configuration of semiconductor devices on a circuit board according to an embodiment. Detailed Implementation

[0045] Since the present invention can have various variations and several embodiments, specific embodiments will be shown and described in detail in the accompanying drawings.

[0046] However, this is not intended to limit the invention to the specific embodiments, and it should be understood that all modifications, equivalents, and substitutions are included within the spirit and technical scope of the invention.

[0047] Preferred embodiments of the invention will be described in detail below with reference to the accompanying drawings.

[0048] However, the spirit of the present invention is not limited to some of the described embodiments, but can be implemented in various different forms. Within the scope of the spirit of the present invention, one or more components in the embodiments can be selectively combined or substituted and used.

[0049] Furthermore, the terminology (including technical and scientific terms) used in the embodiments of this invention, unless explicitly and specifically defined, may be interpreted as having a meaning commonly understood by one of ordinary skill in the art to which this invention pertains. Commonly used terms, such as those defined in dictionaries, may be interpreted taking into account the contextual meaning of the relevant art.

[0050] Furthermore, the terminology used in the embodiments of the present invention is for the purpose of describing the embodiments and is not intended to limit the invention. In this specification, unless specifically stated otherwise in the context, the singular form may include the plural form, and when described as “at least one (or one or more) of A, B, and C,” it may include one or more of all combinations that can be formed by A, B, and C.

[0051] Ordinal terms (such as second, first, etc.) may be used to describe various components, but components are not limited by the terms. These terms are used only for the purpose of distinguishing one component from another. For example, a second component may be referred to as a first component without departing from the scope of the invention, and similarly, a first component may be referred to as a second component. The term "and / or" includes a plurality of related listed items or any combination of a plurality of related listed items. These terms are intended only to distinguish corresponding components from other components, and the nature, order, or sequence of corresponding components are not limited by these terms.

[0052] Furthermore, when a component is described as “connected,” “joined,” or “engaged” to another component, the component may not only be directly connected, joined, or engaged to the other component, but may also include cases where the “connection,” “joining,” or “engagement” occurs due to the insertion of another component between the component and the other component.

[0053] The terminology used in this application is for describing specific embodiments only and is not intended to limit the invention. Singular expressions include plural expressions unless the context clearly specifies otherwise. In this application, terms such as “comprising” or “having” are intended to indicate the presence of features, quantities, steps, operations, components, portions, or combinations thereof described in the specification, and should be understood to not exclude the possibility of pre-existing or added one or more other features, quantities, steps, operations, components, portions, or combinations thereof.

[0054] Furthermore, when a component is described as being formed or disposed "above" or "below" each component, "above" or "below" includes not only the case where two components are in direct contact with each other, but also the case where one or more other components are formed or disposed between the two components. Moreover, when expressed as "above" or "below," it can include not only the meaning of an upward direction based on a component, but also the meaning of a downward direction based on a component.

[0055] Furthermore, the statement that component A is positioned between component B and component C should be understood to include the meaning that component A is positioned such that at least a portion of it overlaps with component B and component C in the horizontal and / or vertical directions.

[0056] The expression indicating direction includes both horizontal and vertical directions, and the horizontal direction includes a first horizontal direction and a second horizontal direction perpendicular to the first horizontal direction. According to the Cartesian coordinate system, this is referred to as the first horizontal direction (X-axis), the second horizontal direction (Y-axis), and the vertical direction (Z-axis), and the meaning of overlapping along the horizontal direction should be understood to include the meaning of overlapping along the first horizontal direction and / or overlapping along the second horizontal direction.

[0057] Furthermore, the meaning of component A being exposed from component B should not be understood as component A being exposed from the entire product, but rather as component A being exposed from component B. In other words, when describing component A being exposed from component B, it should be understood that component A is at least partially covered by component C.

[0058] Furthermore, when describing component A as "in contact" with component B, this can include not only situations where component A is in direct contact with another component, but also situations where contact occurs because another component is inserted between component A and component B. Therefore, it should be understood that "direct contact" is described only when component A is in direct contact with component B.

[0059] Furthermore, when describing component A as being “covered” by component B, it should be understood that component A is covered by component B such that the portion used for the function and purpose to be solved is covered, and unless there are special circumstances, it should not be understood that the entirety of component A must be covered by component B.

[0060] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the context in the relevant field and should not be construed as having an ideal or overly formal meaning unless expressly defined in this application.

[0061] Before describing the embodiments, an electronic device using a circuit board and semiconductor package according to the embodiments will be briefly described. The electronic device includes a motherboard (not shown). The motherboard may be physically and / or electrically connected to various components. For example, the motherboard may be connected to a semiconductor package according to the embodiments. The semiconductor package may include a circuit board and semiconductor devices, and the semiconductor devices may be mounted on the circuit board.

[0062] Semiconductor devices can include active and / or passive devices. Active devices can be semiconductor chips in the form of integrated circuits (ICs) in which hundreds to millions or more devices are integrated into a single chip. Semiconductor chips can be logic chips, memory chips, etc. Logic chips can be non-memory chips, such as central processing units (CPUs), graphics processing units (GPUs), field-programmable gate arrays (FPGAs), etc. For example, a logic chip can be an application processor (AP) chip that includes at least one of a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor, a cryptographic processor, a microprocessor, and a microcontroller, or it can be an analog-to-digital converter, an application-specific integrated circuit (ASIC), etc., or a chipset that includes a specific combination of the above items listed above.

[0063] Memory chips can be stacked memories such as high-bandwidth memory (HBM). Furthermore, memory chips can include memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory.

[0064] On the other hand, the product family of semiconductor packaging using the embodiments can be any of, but is not limited to, chip-scale package (CSP), flip chip-scale package (FC-CSP), flip chip ball grid array (FC-BGA), package on package (POP), and system in package (SIP).

[0065] Furthermore, electronic devices can be smartphones, personal digital assistants, digital cameras, digital still cameras, vehicles, high-performance servers, network systems, computers, monitors, tablets, laptops, netbooks, televisions, video games, smartwatches, automotive equipment, etc. However, they are not limited to these, and it goes without saying that they can be any other electronic device that processes data.

[0066] Figure 1 This is a cross-sectional view of a circuit board according to an embodiment of the present invention. Figure 2 yes Figure 1 A magnified view of part of K1, Figure 3 This is a plan view of the first wiring portion and the first stacked layer in the circuit board according to an embodiment. Figure 4 yes Figure 1 A magnified view of part of K2, Figure 5 This is a view used to explain the effect of the line width / spacing of the first-1 wiring portion in the circuit board according to the embodiment. Figure 6 This is a view showing a first example of the first wiring portion 1-1 in a circuit board according to an embodiment. Figure 7 This is a view showing a second example of the first-1 wiring portion in a circuit board according to an embodiment. Figure 8 This is a view showing a third example of the first-1 wiring portion in a circuit board according to an embodiment, and Figure 9 and Figure 10 This is a photograph of the first wiring section in the circuit board according to the embodiment.

[0067] Reference Figure 1 The circuit board 100 according to an embodiment may include an insulating layer 110 and an electrode portion 120. In an embodiment, the insulating layer 110 may have a structure in which multiple insulating layers are stacked. The electrode portion 120 may be embedded and disposed in each of the multiple insulating layers 110, thereby serving to transmit signals and / or power from a motherboard (not shown) to a semiconductor device.

[0068] Furthermore, when the circuit board includes a core layer, it may include stacked insulating portions on the core layer. Specifically, as shown in the figures, the circuit board 100 may include a core layer 111, stacked insulating portions 112 and 113, a core electrode portion 121, and stacked electrode portions 122 and 123. Furthermore, in the embodiments of the present invention described below, the stacked insulating portions 112 and 113 may include multiple insulating layers and may be configured with a structure having multiple insulating layers stacked.

[0069] The stacked electrode portions 122 and 123 can be embedded and disposed in each layer (e.g., an insulating layer) of the stacked insulating portions 112 and 113, thereby serving to transmit signals and / or power from the motherboard (not shown) to the semiconductor device. Furthermore, when the circuit board includes a core layer, it can include a core layer disposed within the insulating layer 110.

[0070] As an example, the insulating layer 110 of the circuit board may include a core layer 111, an upper stacked layer 112, and a lower stacked layer 113. The upper stacked layer 112 may be located on the core layer 111. In addition, the lower stacked layer 113 may be located below the core layer 111.

[0071] Furthermore, as will be described later, the electrode portion 120 may be formed of a via electrode and a wiring portion.

[0072] First, the insulating layer 110 may include a core layer 111 as a core layer, and stacked insulating portions 112 and 113 formed by at least one insulating layer disposed above and below the core layer 111. Therefore, the stacked insulating portions 112 and 113 stacked on the core layer may include multiple vertically stacked insulating layers. The stacked insulating portion may include an upper stacked layer 112 and a lower stacked layer 113. As shown, the upper stacked layer 112 may be disposed above the core layer 111, and the lower stacked layer 113 may be disposed below the core layer 111. Each of the upper and / or lower stacked layers may be configured by stacking multiple insulating layers. Furthermore, the stacked layer (or stacked insulating portion) may be referred to as a stacked structure or a stacked insulating portion. The following description is based on this.

[0073] As another example, although the insulating layer 110 is described as including a core layer, the circuit board can be formed as a coreless type.

[0074] As an embodiment, the insulating layer 110 may include a core layer 111, an upper stacked layer 112, and a lower stacked layer 113. For example, the core layer 111 may be disposed at the central portion along the vertical direction of the insulating layer 110. When the stacked layers are stacked on both surfaces of the core layer 111, the core layer 111 may be located at the center of the insulating layer 110. That is, the upper stacked layer 112 may be disposed above the core layer 111, and the lower stacked layer 113 may be disposed below the core layer 111.

[0075] Furthermore, the insulating layer 110 of the circuit board 100 can be rigid or flexible. For example, the insulating layer 110 of the circuit board 100 can comprise glass or plastic. For example, the insulating layer 110 of the circuit board, or each insulating layer constituting the insulating layer 110, can comprise chemically tempered / semi-tempered glass, such as soda-lime glass or aluminosilicate glass. For example, the insulating layer 110 of the circuit board can comprise reinforced plastic or flexible plastic, such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), or polycarbonate (PC). For example, the insulating layer 110 of the circuit board can comprise sapphire. For example, the insulating layer 110 of the circuit board can comprise an optically isotropic film. For example, the insulating layer 110 of the circuit board can comprise a cyclic olefin copolymer (COC), a cyclic olefin polymer (COP), optically isotropic polycarbonate (PC), or optically isotropic polymethyl methacrylate (PMMA). For example, the insulating layer 110 of the circuit board can be formed of a material comprising fillers and insulating resins. For example, the insulating layer 110 of the circuit board may have a structure in which silica or alumina fillers are disposed in a thermosetting resin or a thermoplastic resin.

[0076] The insulating layer 110 may have a structure in which multiple different insulating materials are stacked, and exemplary arrangement structures will be described in more detail below.

[0077] In an embodiment, the insulating layer 110 may include a core layer 111, which includes reinforcing members. Here, the core layer 111 includes reinforcing members, and the thickness of the core layer 111 in the vertical direction (Y-axis direction or stacking direction) can range from tens of μm to hundreds of μm. Furthermore, the upper stacked layer 112 and the lower stacked layer 113 may include multiple layers disposed above and below the core layer 111, respectively, and do not include reinforcing members. The reinforcing members may also be referred to as reinforcing fibers or glass fibers embedded in the core layer. The reinforcing members may refer to glass fiber material extending along the horizontal direction (Y-axis direction) of the insulating layer and may have a different meaning than the fillers spaced apart from each other. For example, the insulating layer 110 may be formed of resin, fillers, and reinforcing members (e.g., glass fibers), or it may be formed of resin and fillers.

[0078] The core layer 111 can be formed of various insulating materials. For example, the core layer 111 can be part of a copper-clad laminate (CCL). Alternatively, the core layer can correspond to a copper-clad laminate. Furthermore, the core layer 111 can be formed of multiple layers, and the multiple layers can be formed of the same or different materials. In addition, the core layer 111 may include via electrodes penetrating the upper and lower surfaces of the core layer 111.

[0079] Furthermore, the upper stacked layer 112 or the lower stacked layer 113 can be provided with any insulating resin, such as thermosetting and / or photocurable resins. As a thermosetting resin, products released by Ajinomoto, such as Ajinomoto Build-up Film (ABF), can be used, and materials such as prepreg (PPG) including glass fibers can be used. As a photocurable resin, any insulating resin can be used, such as photo imageable dielectric (PID) resin. The aforementioned insulating resin can be exemplary epoxy resin, bismaleimide triazine resin (BT resin), phenolic resin, etc., and may contain inorganic fillers such as silica. When the insulating resin is used as a core, it can include reinforcing materials or reinforcing members provided with glass fibers, aramid fibers, etc. For example, when manufacturing the insulating layer 110, products released by Ajinomoto, such as Ajinomoto Build-up Film (ABF), can be used, as well as FR-4, Bismalleimide Triazine (BT), Photo Imageable Dielectric Resin (PID), BT, etc. For example, when the circuit board 100 is coreless, the insulating layer 110 can be formed by stacking ABF without a core layer.

[0080] Furthermore, the upper stacked layer 112 may include a first stacked layer 112a in contact with the core layer 111 and a second stacked layer 112b disposed on the first stacked layer 112a. In the stacking direction (Y-axis direction) or the vertical direction, the first stacked layer 112a may be located between the second stacked layer 112b and the core layer 111.

[0081] As another example, the first stacked layer 112a and the second stacked layer 112b can be formed of fillers with different sizes. For example, the second stacked layer 112b can have a smaller filler size than the first stacked layer 112a. For example, the second stacked layer 112b can contain nanofillers. Furthermore, the second stacked layer 112b can be a layer in which an upper electrode portion is disposed with a smaller width or spacing compared to the width or spacing of the first stacked layer 112a.

[0082] Furthermore, in the circuit board 100 according to the embodiment, the electrode portion 120 is provided for electrical connection between the motherboard and the chip (or semiconductor device or die), and the electrode portion 120 includes a wiring portion (circuit pattern, circuit pattern layer, pad or pattern portion) and a via portion (or via electrode).

[0083] For example, the wiring portion of electrode portion 120 may include patterns and pads on the upper surface of the insulating layer. Hereinafter, wiring portion will be described interchangeably with "circuit pattern" and "pattern portion". Furthermore, electrode portion 120 may include via portions or via electrodes penetrating the insulating layer. Therefore, in embodiments, electrode portion 120 will be described below as including wiring portions (circuit patterns) and via electrodes in each insulating layer. Furthermore, the wiring portions in electrode portion 120 may be designed in various forms for signal and / or power transmission with semiconductor devices and are disposed in each insulating layer of the stacked insulating portions 112 and 113.

[0084] The via electrodes (or via portions) in electrode portion 120 are configured to penetrate at least a portion of each insulating layer for vertical connections between circuit patterns disposed in each insulating layer of stacked insulating portions 112 and 113. Via electrodes can connect multiple circuit patterns (wiring portions) to each other. Like wiring portions, multiple via electrodes can be provided. That is, the insulating layer may include via holes for arranging the via electrodes. Furthermore, via electrodes may have a wider width than the circuit pattern for impedance optimization or heat dissipation, but are not limited to this, and can be freely designed.

[0085] In the electrode section 120, wiring sections (circuit patterns) can be provided in each insulating layer. Furthermore, the wiring sections (circuit patterns) can be electrically connected to each via electrode. The circuit patterns provided on the upper and lower surfaces of the insulating layers in the stacked insulating sections 112 and 113 can be electrically connected to the semiconductor device and / or the motherboard or substrate. For example, such electrode sections 120 can be located in each of the core layer 111, the upper stacked layer 112, and the lower stacked layer 113 (insulating layers).

[0086] In an embodiment, the electrode portion 120 may include a core electrode portion 121, an upper electrode portion 122, and a lower electrode portion 123. The upper electrode portion 122 and the lower electrode portion 123 may be stacked layer electrode portions. Furthermore, the upper electrode portion 122 is disposed in each insulating layer of the upper stacked layer 112 and may be an "upper stacked layer electrode portion". And the lower electrode portion 123 is disposed in each insulating layer of the lower stacked layer 113 and may be a "lower stacked wiring portion electrode".

[0087] The core electrode portion 121 may include core wiring portions 121a disposed on the upper and lower surfaces of the core layer 111 and core via electrodes 121b penetrating the core layer 111.

[0088] The upper electrode portion 122 may include a first wiring portion 122a and a first via electrode 122b. The first wiring portion 122a is a wiring portion disposed on the upper and lower surfaces of each insulating layer of the upper stacked layer 112, and the first via electrode 122b is a via electrode. The first via electrode 122b can penetrate each insulating layer of the upper stacked layer 112.

[0089] Furthermore, the lower electrode portion 123 may include: a second wiring portion 123a, which is a wiring portion disposed on the upper and lower surfaces of the lower stacked layer 113; and a second via electrode 123b, which is a via electrode. Furthermore, the second via electrode 123b may penetrate each insulating layer of the lower stacked layer 113.

[0090] Furthermore, in the embodiment, the first wiring portion 122a of the upper electrode portion (and / or lower electrode portion) may include a wiring portion with fine spacing (first-1 wiring portion 122aa) and a wiring portion with a larger spacing than the first wiring portion (first-2 wiring portion 122ab).

[0091] Wiring sections 1-2 can represent wiring with the same width and spacing as circuit patterns used in conventional circuit boards, while wiring section 1-1 can represent fine wiring with a narrower width and spacing than patterns used in conventional circuit boards, for interconnection between semiconductor devices, impedance matching, or inductor formation. For example, the line width and spacing of wiring section 1-1 can be a few micrometers (μm) or less. A detailed description will be provided later.

[0092] Furthermore, the circuit board 100 according to the embodiment may also include a protective layer (SR) and bump portions (not shown).

[0093] Furthermore, a protective layer (SR) can be disposed on the outside of the insulating layer 110. Specifically, the protective layer (SR) can protect the pads from external moisture or contaminants and prevent short circuits during the bonding process between the circuit board and the semiconductor device and / or motherboard. The protective layer (SR) can be exemplaryly configured as a solder resist layer. Specifically, the semiconductor device and / or motherboard, etc., have multiple terminals for connection to the circuit board. Furthermore, the multiple terminals can be arranged in a high density. For example, solder can be used when the multiple terminals and pads of the circuit board are bonded to each other. When solder is used, short circuits may occur between the high-density terminals. To solve this short circuit problem, a solder resist layer with poor wettability to solder can be provided. Furthermore, the protective layer (SR) can be formed of a material with insulating properties for electrical connection. The protective layer (SR) can contain resin, curing agent, photoinitiator, pigment, solvent, filler, additive, acrylic monomer, etc. Furthermore, the protective layer (SR) can include any of a photoresist layer, a capping layer, and a polymer material. The protective layer (SR) may have at least one or more openings for connection between the terminals of the semiconductor device and the pads of the circuit board. For example, in an embodiment, the protective layer (SR) may be formed of resin and filler as a reinforcing member.

[0094] A protective layer (SR) may be disposed on the insulating layer 110. The protective layer (SR) may contain various fillers. Specifically, the protective layer (SR) may include a first protective layer (SR1) disposed above the upper stacked layer 112 and a second protective layer (SR2) disposed below the lower stacked layer 113. The first protective layer (SR1) and the second protective layer (SR2) may be spaced apart from each other along the stacking direction and may have different thicknesses to account for the warpage of the circuit board. In the following description, the protective layer will be based on the first protective layer (SR1).

[0095] The bump portion may be provided on the protective layer (SR). For example, the bump portion may be provided on the upper surface of the protective layer (SR). The bump portion may be located outside the deposited electrode portions 122 and 123. For example, in the upper deposited layer 112, the bump portion may be located above the deposited electrode portions 122 and 123. Furthermore, the bump portion may include a protrusion (not shown) provided on the upper surface of the protective layer (SR) and a via portion (not shown) penetrating the protective layer (SR). In an embodiment, each of the via portion (not shown) and the protrusion (not shown) may include a plurality of protrusions or protrusions projecting toward an adjacent protective layer (SR). For example, on the first protective layer (SR1), the via portion (not shown) and the protrusion (not shown) may include a plurality of protrusions (or protrusions) projecting toward the first protective layer (SR1).

[0096] Furthermore, a metal layer can be additionally disposed on and electrically connected to the bump. This further improves the durability and reliability of the bump. For example, the metal layer can be formed of at least one metal layer. The metal layer can be formed of copper (Cu), gold (Au), nickel (Ni), palladium (Pd), tungsten (W), titanium (Ti), or a combination thereof. This increases the bonding strength between the metal layer and the bump, improves the corrosion resistance and durability of the bump, and minimizes the loss of electrical signals. The metal layer can be formed on the bump through deposition, electroplating, or other methods using various metals.

[0097] Furthermore, semiconductor devices can be disposed on the upper stacked layer 112. The semiconductor devices can be electrically connected to the aforementioned first-1 wiring portion, which is a fine pattern. The circuit board can be arranged with a high wiring density for signal connections to the semiconductor devices. Furthermore, the first-1 wiring portion, which is a fine pattern, can provide wiring for signal connections between semiconductor devices, or perform signal connections for each semiconductor device (e.g., to the lower substrate). Therefore, it can be configured to prevent semiconductor devices from becoming unnecessarily large, thereby improving the yield of the semiconductor devices.

[0098] Furthermore, circuit boards can be classified into packaging substrates and interposers based on their function. Packaging substrates serve to mount semiconductor devices and / or act as interposers. As the area of ​​a circuit board increases due to data expansion, or as the number of stacked insulating layers increases, the yield of the circuit board may decrease significantly. Therefore, to improve the yield of circuit boards with a large number of stacked layers, the yield can be improved by dividing the circuit board into interposers and packaging substrates. Additionally, as the density of semiconductor device terminals increases, it may be difficult to achieve pads on the packaging substrate with an area corresponding to the area of ​​the semiconductor device terminals. Therefore, interposers can serve as a buffer between the pad size of the packaging substrate and the fine pattern size of the semiconductor device terminals.

[0099] The aforementioned packaging substrate and interposer can be classified as core substrates and coreless substrates, respectively, based on the configuration of the insulating layers as described above. In the case of a core substrate, the insulating layer may include a core layer, which can refer to a layer comprising reinforcing members within stacked insulating layers. The reinforcing members may refer to glass fiber. Because the core layer is set to be thicker than other insulating layers, it can have the function of preventing circuit board warping during processing. However, the core layer may cause problems such as voltage drop and signal loss, or it may be difficult to thin it. Therefore, depending on the application, coreless substrates without a core layer can be used as the insulating layer of a circuit board.

[0100] Further reference Figures 2 to 4 In this embodiment, the first-1 wiring portion 122aa and the first-2 wiring portion 122ab may be disposed in the first stacking layer 112a. Furthermore, as described above, the first-2 wiring portion 122ab may have a larger linewidth / spacing than the first-1 wiring portion 122aa.

[0101] Prior to this, the first-1 wiring portion 122aa and the first-2 wiring portion 122aa may have inwardly recessed grooves at their lower portions. For example, the first-1 wiring portion 122aa may have a first groove G1, and the first-2 wiring portion 122ab may have a second groove G2. The first groove G1 and the second groove G2 may be adjacent to the upper surface of the first stacked layer 112a. Therefore, the width W3 (maximum width) of the first-1 wiring portion 122aa may be greater than the minimum width W4. In particular, the minimum width W4 may be the width of the first-1 wiring portion 122aa in the region closer to the lower surface than the upper surface. And, the width W1 (maximum width) of the first-2 wiring portion 122ab may be greater than the minimum width W2. And, the minimum width W4 of the first-2 wiring portion 122ab may be the width of the first-2 wiring portion 122ab in the region closer to the lower surface than the upper surface.

[0102] Furthermore, the interval SW2 between adjacent first-1 wiring sections 122aa can be smaller than the interval SW1 between adjacent first-2 wiring sections 122ab.

[0103] In an embodiment, on the upper surface of the first stacked layer 112a, the width W1 of the first-second wiring portion 122ab can be greater than the width W3 of the first-first wiring portion 122aa. This configuration facilitates the establishment of electrical connections between via pads and via electrodes. In other words, it prevents a decrease in electrical reliability due to electrical disconnection. Furthermore, the number of input / output (I / O) ports can be improved by using the first-first wiring portion 122aa as a fine pattern. This configuration can also be applied to the first-second wiring portion 122ab of each electrode layer.

[0104] [Table 1]

[0105] Table 1 shows the results of inspecting defects in multiple first-1 wiring portions with different linewidths / spacings (e.g., 108 samples inspected "after plating") and the dry films corresponding to the first-1 wiring portions (e.g., 30 samples inspected "after exposure"). As shown in the table, when the linewidth / spacing of the first-1 wiring portions is less than 1.7 μm, it can be seen that the dry films adhere to each other, causing a break between adjacent first-1 wiring portions during plating, or the ends of the first-1 wiring portions become sharp. More specifically, in the embodiment, the first-1 wiring portion 122aa can have a linewidth / spacing of 1.7 μm to 3 μm. That is, the first-1 wiring portion 122aa can be a fine pattern. Therefore, signal transmission efficiency can be improved. Furthermore, as described above in Table 1, since the linewidth / spacing of the first-1 wiring portions in the circuit board according to the embodiment is 1.7 μm to 3 μm, the problems of dry films adhering to each other or the ends of the first-1 wiring portions becoming sharp can be prevented. For example, when the linewidth / spacing is less than 1.7 μm, there is a problem: when forming the first-1 wiring section, when forming the dry film as a mask on the seed layer, adjacent dry films connect to each other (see reference). Figure 5 (a) and (b) of 5). For example, it can be seen that, due to Figure 5 In (a), 'A1' and Figure 5 In (b), the connection between adjacent dry films at 'A2' results in a short circuit between adjacent first-1 wiring portions 122aa. Furthermore, as... Figure 5 As shown in (c) and (d), in the extension direction, the width Wb at the end of the first-1 wiring portion 122aa can be smaller than the width Wa at the central portion. Furthermore, the spacing SWa at the ends of adjacent first-1 wiring portions 122aa can also be larger than the spacing SWb at the central portion. Thus, since the first-1 wiring portions 122aa do not have a uniform line (width) / spacing, electrical characteristics and electrical reliability may be reduced. Furthermore, when the line width / spacing is greater than 3 μm, the wiring density per unit area decreases, thereby reducing the multi-channel I / O (input / output) capacity, a critical requirement for high-density interposers. The increased volume ratio of the insulating material of the first and second stacked layers to the upper portion of the core layer amplifies the mechanical stress caused by the difference in thermal expansion coefficients, making electrical connections to the upper device difficult and leading to signal loss.

[0106] In general, when the linewidth / spacing of the first-1 wiring section is less than 1.7 μm, problems arise such as dry film adhesion causing short circuits or the wiring ends becoming sharp, making it impossible to maintain a uniform width. Therefore, this can lead to deterioration in electrical reliability (e.g., signal loss, disconnection) and an increase in manufacturing defect rate. Furthermore, when the linewidth / spacing of the first-1 wiring section exceeds 3 μm, the wiring density per unit area decreases, thereby potentially reducing the multi-channel I / O capacity of the high-density interposer. Additionally, increased mechanical stress due to differences in the thermal expansion coefficients of the insulating layers and weakened electrical connections to the upper device can also lead to signal loss.

[0107] In contrast, the first-second wiring portion 122ab can have a larger linewidth / spacing than the first-first wiring portion 122aa (e.g., 7 μm to 15 μm). For example, the first-second wiring portion 122ab can be connected to the lower substrate or a power or ground path.

[0108] Furthermore, when the linewidth / spacing of the first-second wiring section 122ab is less than 7 μm, it approaches a fine pattern, and precision is required in manufacturing processes (e.g., exposure, plating), which may increase the defect rate. Additionally, when used as a power or ground path, resistance increases, potentially leading to decreased stability. Moreover, when the linewidth / spacing of the first-second wiring section 122ab exceeds 15 μm, excessive wiring width reduces space utilization, making high-density design difficult, and creating space for weakened electrical connections with the upper fine pattern (first-first wiring section). Furthermore, increased material usage leads to higher costs.

[0109] Furthermore, in the embodiment, the first-2 wiring portion 122ab may have the same thickness as the first-1 wiring portion 122aa. The thickness (TT) of the first-1 wiring portion 122aa and the first-2 wiring portion 122ab may be approximately 6 μm to 15 μm (refer to...). Figure 10 ).

[0110] Furthermore, when the thickness is less than 6 μm, the cross-sectional area of ​​the wiring decreases, leading to increased resistance and reduced signal integrity. Additionally, mechanical strength is weakened, potentially increasing the risk of damage during processing. Moreover, when the thickness exceeds 15 μm, excessive thickness can cause interlayer height imbalance in the stacked structure, potentially weakening connectivity with via electrodes. Furthermore, increasing material costs may prevent the achievement of thinning requirements.

[0111] Furthermore, the aspect ratio (thickness / width ratio) of the first-1 wiring section 122aa can be from 2.3 to 8.9. The aspect ratio (thickness / width ratio) of the first-1 wiring section 122aa can be greater than that of the first-2 wiring section 122ab. That is, the first-1 wiring section 122aa can have a greater thickness compared to its width.

[0112] With this configuration, the first-1 wiring section 122aa ensures that the cross-sectional area of ​​the wiring is a fine pattern to reduce resistance and improve signal integrity at the same time. In addition, since the first-1 wiring section 122aa has the aspect ratio described above, the electrical characteristics required for high-density interposers can also be easily met.

[0113] Furthermore, since the first and second wiring sections 122ab have the aforementioned aspect ratio, low resistance and stability of the power lines can be guaranteed.

[0114] Specifically, when the aspect ratio is less than 2.3, the thickness-to-width ratio is small, resulting in insufficient cross-sectional area for the wiring, which increases resistance and reduces signal integrity. Furthermore, when the aspect ratio exceeds 8.9, if the thickness-to-width ratio is too large, uniform forming in manufacturing processes (e.g., electroplating, etching) becomes difficult, and the risk of short circuits between wirings increases. Additionally, the likelihood of wiring peeling off from the insulation layer due to mechanical stress may increase.

[0115] Further reference Figure 6 The first-1 wiring section 122aa may include a lower region (BA), a middle region (MA), and a upper region (UA) arranged sequentially along the stacking direction (Y-axis direction). The lower region (BA), middle region (MA), and upper region (UA) may have the same height along the stacking direction (Y-axis direction). That is, the lower region (BA), middle region (MA), and upper region (UA) may be regions divided into three equal parts along the stacking direction of the first-1 wiring section 122aa. This structure of the first-1 wiring section 122aa also... Figure 9 As shown in the image.

[0116] At this point, the lengths (Ta, Tb, Tc) of the lower region (BA), middle region (MA), and upper region (UA) can be greater than 0.5 times the linewidth / spacing of the first-1 wiring section 122aa. This configuration increases the mechanical strength of the wiring and easily prevents undercutting or over-etching that may occur during manufacturing.

[0117] Furthermore, the first wiring portion 122aa may have a first surface (S1) with the smallest width or diameter. The first surface (S1) may be located in the lower region (BA). Furthermore, the lower region (BA) may include a first sub-region (SA1) between the first surface (S1) and the upper surface (US) and a second sub-region (SA2) between the first surface (S1) and the lower surface (BS).

[0118] At this time, the outer surface (ES1) and the first surface (S1) of the first sub-region (SA1) can form a first angle (θ). And, a second angle (θ) can be formed by the outer surface (ES2) and the first surface (S1) of the second sub-region (SA2). The first angle (θ) can be different from the second angle (θ). For example, the first angle (θ) can be smaller than the second angle (θ).

[0119] Furthermore, the height of the first sub-region (SA1) in the stacking direction (Y-axis direction) can be greater than the height of the second sub-region (SA2) in the stacking direction (Y-axis direction).

[0120] In the first sub-region (SA1), the width (or diameter) can increase along the stacking direction (Y-axis direction). And in the second sub-region (SA2), the width (or diameter) can decrease along the stacking direction (Y-axis direction).

[0121] Furthermore, in the lower region (BA), the upper surface (US) can have a larger area or width than the lower surface (BS).

[0122] This configuration increases the bonding area between the stacked layer and the first-1 wiring portion. Therefore, the mechanical adhesion between the stacked layer and the first-1 wiring portion is improved, thereby enhancing the reliability of the circuit board. Furthermore, the increased space at the bottom between adjacent first-1 wiring portions reduces capacitance and other characteristics between adjacent wiring portions, improving specific electrical properties and preventing short circuits between adjacent wiring portions. Additionally, mask design can be simplified when forming the first-1 wiring portion.

[0123] Furthermore, in the first sub-region (SA1), the length of the outer surface perpendicular to the first surface (S1) in the stacking direction, rather than the first angle (θ), can be greater than the length of the outer surface (ES1) having the first angle (θ). This is also true in... Figure 9 This is shown in detail in the text.

[0124] Reference Figure 7As a second example, the first-1 wiring section 122aa may include a lower region (BA), a middle region (MA), and an upper region (UA) arranged sequentially in the stacking direction (Y-axis direction). Furthermore, the lower region (BA) may include a first sub-region (SA1) between the first surface (S1) and the upper surface (US) and a second sub-region (SA2) between the first surface (S1) and the lower surface (BS). In addition, the above-described content may be applied in addition to the content described below.

[0125] Furthermore, in the lower region (BA), the length (Tk) of the outer surface perpendicular to the first surface (S1) can be greater than the length (TL) of the region whose width decreases up to the first surface (S1) (outer surface, ES1). Also, in the lower region (BA), the length (TL) of the region whose width decreases up to the first surface (S1) (outer surface, ES1) can be greater than the length (Tm) from the first surface (S1) to the lower surface (BS). In the lower region (BA), the length (Tk) of the outer surface perpendicular to the first surface (S1) can be greater than the length (Tm) from the first surface (S1) to the lower surface (BS).

[0126] Furthermore, the lower region (BA) may have a raised surface (CS) that protrudes upward on the lower surface (BS). The raised surface (CS) may be located below the first surface (S1). That is, the raised surface (CS) may be located in the second sub-region (SA2). Moreover, the raised surface (CS) may not overlap with the first sub-region (SA1) in the horizontal direction.

[0127] This configuration increases the contact area between the first-1 wiring portion 122aa and the lower stacked layer. This configuration also improves the adhesion between the lower stacked layer and the first-1 wiring portion, thereby providing enhanced mechanical reliability for the circuit board according to the embodiment.

[0128] Furthermore, the raised surface (CS) may cause a gap between the lower surface of the first-1 wiring section 122aa and the lower stacked layer.

[0129] Reference Figure 8 In the third example, the first-1 wiring section 122aa may include a lower region (BA), a middle region (MA), and an upper region (UA) arranged sequentially in the stacking direction (Y-axis direction). Furthermore, in the lower region (BA), the width (or diameter, WL) may increase along the stacking direction (Y-axis direction). Alternatively, the lower region (BA) may have a width (or diameter) that decreases from the upper surface (US) towards the lower surface (BS).

[0130] Furthermore, the third angle (θ) formed by one side (ES3a) and the lower surface (BS) in the section in the lower region (BA) can be different from the fourth angle (θ) formed by the other side (ES3b) and the lower surface (BS) in the section.

[0131] This configuration ensures uniform adhesion between the first wiring portion and the stacked layer. Therefore, the adhesive area between the first wiring portion and the stacked layer increases, thereby improving peel strength. In other words, it enhances the mechanical reliability of the circuit board.

[0132] Furthermore, the line width / spacing of the second wiring section 123a can be greater than that of the first-1 wiring section 122aa. In particular, the line width / spacing of the wiring section in the lower stacking layer 113 can be greater than that of the first-1 wiring section 122aa.

[0133] Figures 11 to 16 This is a diagram illustrating a method for manufacturing a circuit board according to an embodiment.

[0134] Reference Figure 11 This can be used to prepare carrier substrates. For example, copper clad laminate (CCL) can be used as a carrier.

[0135] The carrier substrate may include a carrier insulating layer and a carrier metal layer disposed on at least one surface of the carrier insulating layer. In this case, as shown in the figure, the carrier metal layer may be disposed on both surfaces of the carrier insulating layer. However, the carrier substrate is not limited to this manufacturing method.

[0136] Furthermore, the manufacturing processes for the insulating layer, electrode layer, and via electrodes of the underlying circuit board can be performed separately on both surfaces of the carrier board. For example, in an embodiment, multiple substrate layers can be formed at once by performing the following processes separately on the upper and lower sides centered on the carrier board. Therefore, the quality and productivity of the circuit board can be improved. The following description will be based on one surface.

[0137] Reference Figure 12 The core electrode portion 121 can be formed by performing electroplating or the like on a carrier metal layer. In this case, the carrier metal layer can serve as a seed layer. To form the core electrode portion 121, dry film lamination, exposure and development, plating, dry film stripping, etching, etc., can be performed. For example, the dry film serving as a mask can be provided corresponding to via pads and pattern portions. Openings can be formed in the dry film through exposure and development processes. An electrode layer can be formed in the openings of the dry film. In other words, via pads and pattern portions can be formed in the openings of the dry film. At this time, a first electrode layer can be formed by electroplating or the like. The dry film serving as a mask can be removed by stripping or the like. Then, the area other than the area corresponding to the first electrode layer can be removed by etching or the like.

[0138] Reference Figure 13 The first deposited layer 112a can be formed on the first electrode layer. The first deposited layer 112a can be formed by various methods. The first deposited layer 112a can be formed by performing thermosetting (e.g., lamination) on the ABF.

[0139] Furthermore, a coating that functions as a seed layer can be formed on the first deposited layer 112a through plating or the like. Additionally, through-holes can be formed in the first deposited layer 112a, and a coating that functions as a seed layer can be additionally formed through plating or the like. Then, a second via electrode can be formed through plating.

[0140] Furthermore, as described above, in order to form the upper electrode portion 122 on the first deposited layer 112a, dry film lamination, exposure and development, plating, dry film stripping, etching, etc., can be performed. Therefore, the upper electrode portion can be formed on the upper surface of the first deposited layer 112a.

[0141] Furthermore, Figures 14A to 14J show the linewidth / spacing of the first-1 wiring section obtained by position offset (0, 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9 (μm)) when a pattern is formed by exposure in the dry film.

[0142] Table 2 shows the relationship between the line width / spacing of the first-1 wiring section obtained by position offset (0, 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9 (μm)) and the figures when the pattern is formed by exposure in the dry film.

[0143] [Table 2]

[0144] As can be seen in Figures 14A to 14J and Table 2, the change in linewidth / spacing relative to the offset is small during exposure. That is, the formation of the first-1 wiring portion can be more easily achieved in the circuit board according to the embodiment. (Refer to...) Figure 15 A second deposited layer 112b can be formed on the first deposited layer 112a. The second deposited layer 112b can be formed by thermosetting ABF or the like. Furthermore, in order to form the upper electrode portion 122, dry film lamination, exposure and development, electroplating, dry film stripping, etching, etc., can be performed. Therefore, the upper electrode portion 122 can also be formed on the second deposited layer 112b.

[0145] Reference Figure 16 A protective layer (SR) can be formed on the upper deposited layer 112 and the lower deposited layer 113. To form the protective layer (SR), dry film lamination, exposure and development, plating, dry film stripping, etching, etc., can be performed.

[0146] Figure 17 This is a view of semiconductor devices stacked on a circuit board according to an embodiment of the present invention, and Figure 18 This is a view showing the arrangement of semiconductor devices in a circuit board according to an embodiment.

[0147] Reference Figure 17 and Figure 18 In addition to semiconductor devices and circuit board 100, the packaging substrate of the circuit board according to the embodiment may also include a main substrate.

[0148] In this type of packaging substrate, the circuit board 100 according to the embodiment can be an interposer layer disposed between the main substrate and the semiconductor device. Furthermore, the circuit board 100 can be a substrate that performs a bridging function for the semiconductor device. Therefore, the circuit board can improve yield and serve as a buffer for fine pattern dimensions.

[0149] Specifically, multiple semiconductor devices (SD1, SD1', SD2) can be mounted on the upper electrode portion, which is the outer side of the circuit board 100. The circuit board 100 can be a circuit board of the various examples described above. Furthermore, the circuit board 100 can have a connection region (R) that connects the multiple semiconductor devices (DI1, DI1', DI2) to each other in adjacent portions. The connection region (R) can be formed by wiring portions of a finely patterned electrode layer as described above. In other words, multiple semiconductor devices can be connected to each other through wiring portions of the circuit board (e.g., wiring portion 1-1).

[0150] In addition, a bridge can be formed in the circuit board, a first wiring section can be formed on the bridge, and the first wiring section can connect the bridge and the semiconductor device.

[0151] Here, the multiple semiconductor devices may include logic chips or memory chips as described above. Furthermore, the first semiconductor device (DI1, DI1') and the second semiconductor device (DI2) may be heterogeneous semiconductor devices as described above.

[0152] Furthermore, in the circuit board 100, the pattern for connecting to the main substrate below the circuit board can be formed below the lower stacked layer. That is, the pattern portion, which is a fine pattern, may not be exposed at the bottom of the circuit board 100. In addition, a protective layer may be additionally provided on the upper surface of the uppermost insulating layer or the bottom surface of the lowermost insulating layer.

[0153] On the other hand, when a circuit board with the features of the above-described invention is used in IT equipment such as smartphones, server computers, and TVs or home appliances, functions such as signal transmission or power supply can be performed stably. For example, when a circuit board with the features of the present invention is used for semiconductor packaging, it can safely protect semiconductor chips from external moisture or contaminants, and can solve problems of leakage current or electrical short circuits between terminals, or problems of electrical open circuits at the terminals supplied to the semiconductor chip. Furthermore, when responsible for signal transmission functions, noise problems can be solved. Thus, by enabling a circuit board with the features of the above-described invention to maintain stable function in IT equipment or home appliances, the entire product and circuit board applying the present invention can achieve functional uniformity or technical interoperability.

[0154] When a circuit board having the features of the above invention is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, or safely protect the semiconductor chip controlling the transportation device from external influences, and solve the problems of leakage current or electrical short circuits between terminals, or electrical open circuits at the terminals supplied to the semiconductor chip, thereby further improving the stability of the transportation device. Therefore, the transportation device and circuit board to which this invention is applied can achieve functional unity or technical interoperability.

[0155] Furthermore, the circuit board according to embodiments of the present invention may include a first stacked layer and a second stacked layer disposed on the first stacked layer. Furthermore, the first and second stacked layers may each include multiple stacked insulating layers. That is, the circuit board may be formed from the insulating layers of the first and second stacked layers (or the first and / or the second stacked layers). The upper and lower stacked layers can be distinguished by a structure in which the diameter expansion directions of the vias in the layers are opposite to each other. For example, in the upper stacked layer, the width or area of ​​the vias may increase upwards. And in the lower stacked layer, the width or area of ​​the vias may decrease upwards. Furthermore, each stacked layer may correspond to an insulating layer other than the core layer. The circuit board may include a stacked structure, and when a core layer is present, the stacked structure may include an upper stacked layer, a core layer, and a lower stacked layer. Furthermore, when a core layer is absent, due to the aforementioned diameter expansion directions, the stacked structure may include an upper stacked layer and a lower stacked layer. In embodiments of the present invention, the stacked structure may include an upper stacked layer and a lower stacked layer. Furthermore, the stacked layer may be a layer different from the protective layer.

[0156] Furthermore, as mentioned above, each stacked layer includes an insulating layer. For example, when a core layer is present in the circuit board, the upper stacked layer can be disposed above the core layer, and the lower stacked layer can be disposed below the core layer. In this case, both the upper and lower stacked layers include multiple insulating layers. And when no core layer is present, the increasing directions of the via width can be different from each other. Therefore, the circuit board can be divided into upper and lower stacked layers.

[0157] Furthermore, as mentioned above, the stacked layer is a layer different from the protective layer described above, and the uppermost / lowermost surface of the stacked layer (or insulating layer) corresponds to the uppermost / lowermost surface of the stacked layer (insulating layer) located at the uppermost part, and does not imply the uppermost / lowermost surface of the protective layer. In other words, the uppermost surface of the insulating layer of the circuit board refers to the uppermost / lowermost surface of the stacked layer, not the protective layer.

[0158] The features, structures, effects, etc., described in the above embodiments are included in at least one embodiment, but are not necessarily limited to one embodiment. Furthermore, the features, structures, effects, etc., shown in each embodiment can be combined or modified by those skilled in the art relative to other embodiments. Therefore, content related to such combinations and modifications should be interpreted as being included within the scope of the embodiments.

[0159] Although the foregoing description has focused on embodiments, these are merely examples and not limiting of the embodiments, and those skilled in the art will understand that various modifications and applications not shown above are possible without departing from the essential characteristics of these embodiments. For example, each component specifically shown in the embodiments may be modified and practiced. Furthermore, differences associated with such modifications and applications should be interpreted as including within the scope of the embodiments defined in the appended claims.

Claims

1. A circuit board, comprising: First stacking layer; as well as Wiring section 1-1 and wiring section 1-2, wherein wiring section 1-1 is disposed on the first stack layer, and wiring section 1-2 has a larger line width / spacing than wiring section 1-1. The line width / spacing of the first-1 wiring section is 1.7 μm to 3 μm.

2. The circuit board according to claim 1, wherein, The first-1 wiring section includes a lower region, a middle region on the lower region, and an upper region on the middle region along the stacking direction.

3. The circuit board according to claim 2, wherein, The length of each of the lower region, the middle region, and the upper region in the stacking direction is greater than 0.5 times the line width / spacing of the first-1 wiring portion.

4. The circuit board according to claim 2, wherein, The lower region includes a first sub-region and a second sub-region, the first sub-region extending from the upper surface of the lower region to a first surface having a minimum width or diameter, and the second sub-region extending from the first surface to the lower surface of the lower region.

5. The circuit board according to claim 4, wherein, The angle formed by the outer surface of the first sub-region and the first surface is different from the angle formed by the outer surface of the second sub-region and the first surface.

6. The circuit board according to claim 4, wherein, The lower region has an upwardly convex protruding surface on its lower surface.

7. The circuit board according to claim 6, wherein, The raised surface is located below the first surface.

8. The circuit board according to claim 2, wherein, The lower region has a width or diameter that decreases from the upper surface of the lower region toward the lower surface of the lower region.

9. The circuit board according to claim 2, wherein, The width or area of ​​the upper surface of the lower region is greater than the width or area of ​​the lower surface of the lower region.

10. The circuit board according to claim 1, wherein, The thickness of each of the first-1 wiring portion and the first-2 wiring portion is 6 μm to 15 μm.

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