Circuit board and semiconductor package comprising the same

Abstract

A circuit board according to an embodiment includes: a build-up insulating layer including an upper surface and a lower surface, a plurality of insulating layers stacked between the upper surface and the lower surface, and an upper circuit layer provided on the upper surface; and a protective layer provided on the upper circuit layer of the build-up insulating layer, wherein the protective layer includes a via hole having a first depth in a vertical direction and a recess having a second depth different from the first depth in the vertical direction, and wherein the via hole and the recess are spaced apart from each other in a horizontal direction.

Description

Technical Field

[0001] One embodiment relates to a circuit board and a semiconductor packaging substrate including the circuit board. Background Technology

[0002] As the performance of electrical / electronic products increases, techniques for arranging a greater number of semiconductor devices on a semiconductor packaging substrate of limited size have been proposed and studied. However, since general semiconductor packaging is based on mounting a single semiconductor device, there are limitations in achieving the desired performance.

[0003] Therefore, recently, semiconductor packages have been provided that use multiple substrates to arrange multiple semiconductor devices therein. Such semiconductor packages have a structure in which multiple semiconductor devices are interconnected on the substrates in a horizontal and / or vertical direction. Therefore, the advantage of semiconductor packages is that they effectively utilize the mounting area of ​​the semiconductor devices and can transmit high-speed signals through short signal transmission paths between the semiconductor devices.

[0004] Furthermore, as the number of semiconductor devices and / or the size of each semiconductor device increases in line with the trend toward higher integration, or as the functional parts of semiconductor devices are divided, semiconductor packaging for products that provide Internet of Things (IoT), autonomous vehicles, high-performance servers, etc., is being expanded to the concept of semiconductor chiplets.

[0005] Meanwhile, the packaging substrate and / or interposer used in semiconductor packaging may include multiple bump portions configured to connect to semiconductor devices and / or semiconductor chiplets. Furthermore, as the number of pads on the connection members and the number of terminals on the semiconductor devices increases, fine spacing between the multiple bump portions is required. However, according to the prior art, there are limitations in reducing the size of vias overlapping with the bump portions in the vertical direction due to limitations in the exposure and / or development resolution of the solder resist. Therefore, in the prior art, there are limitations in reducing the spacing between multiple adjacent bump portions. Summary of the Invention

[0006] Technical issues

[0007] The embodiments provide a circuit board with a novel structure and a semiconductor package including the circuit board.

[0008] Additionally, this embodiment provides a circuit board capable of achieving fine pitch between bump portions configured to connect to a semiconductor device, and a semiconductor package including the circuit board.

[0009] The technical problems to be solved by the proposed embodiments are not limited to those described above, and those skilled in the art to which the embodiments described below pertain will clearly understand other technical problems not mentioned.

[0010] Technical solutions

[0011] The circuit board according to the embodiment includes: a multilayer insulating layer including an upper surface and a lower surface, a plurality of insulating layers stacked between the upper surface and the lower surface, and an upper circuit layer disposed on the upper surface; and a protective layer disposed on the upper circuit layer of the multilayer insulating layer, wherein the protective layer includes a through-hole having a first depth in a vertical direction and a recess having a second depth in a vertical direction different from the first depth, and wherein the through-hole and the recess are spaced apart from each other in a horizontal direction.

[0012] In addition, the first depth of the through hole is greater than the second depth of the recess.

[0013] Additionally, the upper circuit layer includes: a bump portion disposed in the recess and protruding from the bottom surface of the recess; and a pad portion disposed in a via, wherein at least a portion of the upper surface of the pad portion overlaps with the via in the vertical direction.

[0014] In addition, the upper circuit layer further includes a wiring portion connected to at least one of the pad portion and the bump portion, wherein the wiring portion is covered by a protective layer.

[0015] In addition, the bottom surface of the recess includes a concave surface that is recessed toward the laminated insulating layer.

[0016] Furthermore, the bump portion includes a plurality of bumps spaced apart from each other in the horizontal direction, wherein concave surfaces are disposed between the plurality of bumps.

[0017] In addition, the sidewalls of the recess include grooves that extend outward from the recess.

[0018] In addition, the groove is located at the boundary between the bottom surface of the recess and the sidewall of the recess.

[0019] In addition, the groove is provided along the circumferential direction of the bottom surface of the recess.

[0020] In addition, the thickness of the bump portion in the vertical direction is greater than the thickness of the pad portion in the vertical direction.

[0021] In addition, the thickness of the bump portion in the vertical direction is equal to the thickness of the wiring portion in the vertical direction.

[0022] In addition, the bump portion includes: a first portion disposed on the stack and having a first width in the horizontal direction; and a second portion disposed on the first portion and having a second width in the horizontal direction different from the first width.

[0023] In addition, the thickness of the first part of the bump in the vertical direction is equal to the thickness of the pad in the vertical direction.

[0024] In addition, the first width is greater than the second width, and the side surfaces of the first portion of the protrusion and the second portion of the protrusion form steps.

[0025] Furthermore, the central axes of the first part of the bump portion and the second part of the bump portion in the horizontal direction are offset from each other.

[0026] In addition, the bottom surface of the concave portion is positioned higher than the first part of the convex portion.

[0027] In addition, the circuit board also includes a connecting member embedded in the laminate and overlapping at least a portion of the recess in the vertical direction.

[0028] Furthermore, the slope of the sidewall of the through hole is different from the slope of the sidewall of the recess.

[0029] Meanwhile, the semiconductor package according to the embodiment includes: a multilayer insulating layer including an upper surface and a lower surface, a plurality of insulating layers stacked between the upper surface and the lower surface, and an upper circuit layer disposed on the upper surface; a protective layer disposed on the upper circuit layer of the multilayer insulating layer; and a semiconductor device disposed on the protective layer, wherein the protective layer includes vias having a first depth in a vertical direction and recesses having a second depth in a vertical direction different from the first depth, and wherein the vias and recesses are spaced apart from each other in a horizontal direction.

[0030] In addition, the semiconductor package also includes an embedded insulating layer for embedding semiconductor devices, wherein the embedded insulating layer fills at least a portion of the recess.

[0031] Beneficial effects

[0032] The circuit board according to the embodiment may include a multilayer and pad portions and bump portions disposed on the multilayer. The bump portions may include a first portion disposed on the multilayer and having a first width in the horizontal direction, and a second portion disposed on the first portion and having a second width in the horizontal direction that is less than the first width.

[0033] Therefore, this embodiment allows the bump portions to have a height equal to or greater than a predetermined level, and further enables fine spacing between multiple bump portions spaced apart from each other in the horizontal direction. Specifically, the bump portions can be disposed on the laminate at a predetermined height. In this case, the bump portions are formed by exposing and developing the dry film to form openings, and then filling the openings with a metallic material. As the height of the bump portions increases, the thickness of the dry film also increases, which may lead to a decrease in the exposure resolution of the dry film. For example, when performing an exposure process by irradiating the upper surface of the dry film with light, sufficient light may not reach the area adjacent to the lower surface of the dry film, so a portion of the dry film may not be adequately exposed and developed. Furthermore, as the thickness of the dry film increases, the resolution degradation due to light refraction can become more significant. Therefore, in the prior art, there are limitations in reducing the width of the bump portions in the horizontal direction and, furthermore, in reducing the spacing between multiple bump portions.

[0034] Conversely, according to the embodiment, multiple dry films stacked in the vertical direction can be used to form the bump portion. For example, in the prior art, when the bump portion has a height of 200 μm, a dry film with a thickness of 200 μm is used to form the bump portion, while according to the embodiment, the bump portion can be formed after stacking two dry films, each with a thickness of 100 μm. Therefore, depending on the thickness of the dry film, this embodiment can solve the problem of reduced exposure resolution caused by light refraction, thereby reducing the width of the bump portion in the horizontal direction. Furthermore, according to the embodiment, the width of the second portion of the bump portion in the horizontal direction can be smaller than the width of the first portion of the bump portion in the horizontal direction. Therefore, the spacing between adjacent bump portions can be increased while maintaining the spacing between adjacent bump portions, thereby preventing short circuits that may occur when adjacent bump portions are electrically connected to each other.

[0035] The implementation includes a protective layer disposed on the stacked layer. In this case, the protective layer includes vias that overlap with pad portions disposed on the stacked layer in the vertical direction, and recesses that overlap with bump portions in the vertical direction. The recesses may be disposed in the region where the bump portions are disposed, and the depth of the recesses in the vertical direction may be less than the depth of the vias in the vertical direction. In this case, according to the implementation, the thickness of the bump portions in the vertical direction may be greater than the thickness of the pad portions in the vertical direction, and the bump portions may overlap with the recesses disposed in the protective layer in the vertical and / or horizontal directions, such that the bump portions can be stably supported and / or protected by the protective layer. Therefore, compared to the comparative example, the implementation can increase the height of the bump portions (preferably, the thickness of the second portion of the bump portions), thereby ensuring that the semiconductor devices are stably disposed on the upper stacked layer.

[0036] Furthermore, the bottom surface of the recessed portion of the protective layer can be positioned higher than the first portion of the bump portion. Therefore, the interface between the first and second portions of the bump portion can be positioned lower than the recessed portion of the protective layer. That is, the interface between the first and second portions of the bump portion can be covered by the first protective layer. Therefore, this embodiment can prevent cracking at the interface between the first and second portions of the bump portion or prevent intermetallic compounds from penetrating into the interface, thereby further improving the mechanical and / or electrical reliability of the circuit board and the semiconductor package containing the circuit board.

[0037] Furthermore, the recesses in the protective layer may be spaced apart from the vias in the protective layer in the horizontal direction. For example, the protective layer may include a plurality of vias spaced apart from each other in the horizontal direction, and each of the plurality of vias may be spaced apart from the recesses without being connected to them. Therefore, mechanical and / or electrical reliability can be improved by preventing problems that may occur when the vias of the protective layer and the recesses of the first protective layer are connected to each other. For example, electrical reliability problems that may occur when the vias of the protective layer 104 and the recesses of the protective layer are connected to each other, such as short circuits caused by the flow of bonding members such as solder, can be prevented. In particular, the embodiment can prevent warping of the circuit board that may occur due to volume differences between the upper and lower insulating layers, thereby further improving the mechanical and / or electrical reliability of the circuit board and the semiconductor package.

[0038] Furthermore, the pad portion can be positioned around the bump portion. For example, the pad portion can be positioned closer to the outer surface of the upper stacked layer than the bump portion. In this case, the width of the pad portion in the horizontal direction can be greater than the width of the bump portion in the horizontal direction. That is, the pad portion with a relatively large width in the horizontal direction can be positioned adjacent to the outer surface of the upper stacked layer, thereby ensuring the rigidity around the periphery of the upper surface of the upper stacked layer and preventing excessive warping of the circuit board in a particular direction.

[0039] Compared to pad portions, bump portions can have a relatively fine width or relatively fine pitch. Bump portions can connect to terminals of semiconductor devices with relatively small linewidths and / or pitches, while pad portions can connect to terminals of semiconductor devices with relatively large linewidths and / or pitches and / or pads of external substrates. For example, pad portions can be used as power lines configured to supply power to semiconductor devices and / or connection members, and bump portions can be used as signal lines configured to send communication signals other than power signals to and from semiconductor devices and / or connection members. In this case, multiple pad portions can be arranged around the bump portions at locations spaced apart from them, thereby achieving stable power supply while preventing power signals transmitted through the pad portions from interfering with communication signals transmitted through the pad portions.

[0040] Additionally, the pad portion can serve as a shield to prevent interference signals (such as external noise) from being transmitted to the bump portion. Therefore, the loss of communication signals transmitted through the bump portion can be minimized to improve communication characteristics, thereby further enhancing the operational reliability of the circuit board and semiconductor package.

[0041] Furthermore, according to the embodiment, the slope of the sidewall of the through hole can be different from the slope of the sidewall of the recess. The sidewall of the through hole can have a predetermined slope relative to the upper or lower surface of the protective layer. For example, the sidewall of the through hole can be inclined such that the width of the through hole in the horizontal direction decreases from the upper part of the through hole toward the lower part of the through hole. Therefore, the volume of the joining member within the through hole, which has a relatively large volume, can be controlled, thereby reducing manufacturing costs. In addition, the sidewall of the through hole can be inclined such that the width of the through hole in the horizontal direction decreases from the upper part of the through hole toward the lower part of the through hole, thereby allowing the joining member to be easily disposed in a through hole having a relatively large depth in the vertical direction.

[0042] Conversely, the sidewalls of the recess can have a different slope than the sidewalls of the through hole. For example, the slope of the sidewalls of the recess can be closer to vertical than the slope of the sidewalls of the through hole. Therefore, the area of ​​the bottom surface of the recess can be fixed, allowing for precise control of the space for setting up the semiconductor device and more stable setting up of the semiconductor device.

[0043] Furthermore, trenches can be provided in the sidewalls of the recesses in the protective layer. The trenches can be formed recessed outwards along the circumferential direction of the bottom surface of the recess. The trenches can be filled with bonding members, such as solder, disposed on the bump portions, thereby providing an anchoring function that increases the bonding strength between the bonding members and the circuit board. Optionally, the trenches can be filled with molded members of molded semiconductor devices, thereby further increasing the bonding strength between the molded members and the circuit board.

[0044] Furthermore, a concave surface can be provided in the bottom surface of the recess of the protective layer. The concave surface increases the surface area of ​​the bottom surface of the recess of the protective layer, thereby reducing the degree of thermal deformation (e.g., expansion and / or contraction) of the protective layer caused by thermal stress. Therefore, the concave surface provided in the upper surface of the protective layer can prevent stress caused by thermal deformation of the protective layer from acting on the bump portion. For example, the concave surface can alleviate stress caused by thermal stress and prevent stress from being transmitted in the direction toward the bump portion. Therefore, the embodiment allows the semiconductor device to be stably attached to the circuit board, thereby improving the mechanical and electrical reliability between the circuit board and the semiconductor device. Furthermore, the embodiment allows the semiconductor device to operate stably, thereby improving the operational reliability of electronic products (e.g., servers) using semiconductor packaging.

[0045] Furthermore, the concave surface is configured as a curved surface that recesses from the upper surface of the protective layer toward the lower surface of the protective layer. Therefore, this embodiment can further improve the effect of preventing stress from acting on the bump portion through the concave surface. For example, when the concave surface has an angled rectangular shape, stress may concentrate at the angled portion, which may lead to deterioration of mechanical or electrical reliability. Conversely, according to the embodiment, the concave surface can have a concave curved shape, thereby preventing stress concentration at specific portions of the concave surface. Therefore, this embodiment can further improve the physical and / or electrical reliability of the semiconductor package.

[0046] Furthermore, the protective layer, bump portions, and semiconductor devices comprise different materials. For example, the protective layer may include solder resist, the bump portions may include a metallic material such as copper, and the semiconductor device may include a silicon material. In this case, the protective layer, bump portions, and semiconductor devices have different coefficients of thermal expansion. For example, the coefficient of thermal expansion of the protective layer may be greater than that of the bump portions and the semiconductor device. Therefore, when the same thermal stress is applied to each of the protective layer, bump portions, and semiconductor devices, the protective layer may experience a greater degree of thermal deformation than the bump portions and the semiconductor device. Therefore, embodiments may provide a concave surface in the upper surface of the protective layer and may prevent stress caused by thermal deformation (such as expansion and / or contraction) from acting on the junction between the circuit board and the semiconductor device, thereby improving the mechanical and / or electrical reliability of the semiconductor package.

[0047] Furthermore, the first and second portions of the bump portion according to the embodiment may have central axes offset from each other in the horizontal direction. For example, the central axis of the first portion of the bump portion in the horizontal direction may be offset from the central axis of the second portion in the horizontal direction. Therefore, due to the difference between the width of the first portion and the width of the second portion in the horizontal direction, the side surface of the bump portion may have a step. Moreover, since the central axes of the first and second portions in the horizontal direction are offset from each other, the horizontal distance of the step may be uneven along the outer periphery of the upper or lower surface of the bump portion. For example, the first side surface of the first portion and the first side surface of the second portion on one side of the bump portion may have a first horizontal distance between them in the horizontal direction, and the second side surface of the first portion and the second side surface of the second portion on the other side of the bump portion may have a second horizontal distance between them in the horizontal direction, the second horizontal distance being different from the first horizontal distance. Therefore, by offsetting the central axis of the first portion of the bump portion in the horizontal direction from the central axis of the second portion, the embodiment can prevent excessive warping of the circuit board in a particular direction. Furthermore, depending on the required characteristics of the multiple bump portions, the spacing between the multiple bump portions can be selectively increased and / or decreased while maintaining the spacing between the multiple bump portions, thereby minimizing signal interference and signal transmission loss, and thus improving communication characteristics.

[0048] For example, based on the direction of circuit board warping, the embodiment allows the central axis of the second portion of the bump portion to be offset by a predetermined distance from the central axis of the first portion of the bump portion in a predetermined direction. Therefore, warping of the circuit board in a specific direction can be prevented, and excessive stress acting on the circuit board can be avoided. Thus, the mechanical and / or electrical reliability of the circuit board can be improved. Additionally, the embodiment reduces circuit board warping, thereby allowing semiconductor devices to be stably attached to the circuit board. When the circuit board warps in a specific direction, height deviations may occur between the multiple bump portions disposed on the circuit board, and the terminals of the semiconductor devices may not be stably coupled to the multiple bump portions. In contrast, according to the embodiment, the central axes of the first and second portions of the bump portions can be offset from each other in the horizontal direction, thereby reducing the overall warping of the circuit board and allowing the semiconductor devices to be stably attached to the circuit board. Therefore, this embodiment allows the semiconductor devices to operate stably, thereby improving product reliability. Furthermore, the embodiment allows products using semiconductor packaging (e.g., servers) to operate stably. Attached Figure Description

[0049] Figure 1a This is a cross-sectional view of a circuit board according to an embodiment.

[0050] Figure 1bThis is a cross-sectional view of the circuit board according to the comparative example.

[0051] Figure 2 It is shown Figure 1a The diagram shows the layout of the first circuit layer.

[0052] Figure 3 It is shown Figure 1a The diagram shows the recess and through-hole of the first protective layer.

[0053] Figure 4 This illustrates the first embodiment. Figure 3 A cross-sectional view of the recess and through-hole of the first protective layer.

[0054] Figure 5 This illustrates the second embodiment. Figure 3 A cross-sectional view of the recess and through-hole of the first protective layer.

[0055] Figure 6 This illustrates the third embodiment. Figure 3 A cross-sectional view of the recess and through-hole of the first protective layer.

[0056] Figure 7 This illustrates the fourth embodiment. Figure 3 A cross-sectional view of the recess and through-hole of the first protective layer.

[0057] Figure 8a and 8b This is a cross-sectional view showing the detailed structure of the bump portion according to another embodiment.

[0058] Figure 9 This is a cross-sectional view showing the detailed structure of the bump portion according to yet another embodiment.

[0059] Figure 10 This is a cross-sectional view of a circuit board according to the second embodiment.

[0060] Figure 11 This is a cross-sectional view of a circuit board according to a third embodiment.

[0061] Figure 12 This is a cross-sectional view showing a semiconductor package according to the first embodiment.

[0062] Figure 13 This is a cross-sectional view showing a semiconductor package according to the second embodiment.

[0063] Figures 14a to 14f This is a cross-sectional view showing the method of manufacturing a circuit board according to the embodiment, in the order of the manufacturing process. Detailed Implementation

[0064] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0065] However, the spirit and scope of this disclosure are not limited to the described embodiments and may be implemented in various other forms, and one or more elements of the embodiments may be selectively combined and rearranged within the spirit and scope of this disclosure.

[0066] Furthermore, unless otherwise explicitly defined and described, the terms (including technical and scientific terms) used in the embodiments of this disclosure may be interpreted as having the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains, and terms such as those defined in common dictionaries may be interpreted as having the same meaning as they have in the context of the relevant field.

[0067] Furthermore, the terminology used in the embodiments of this disclosure is for describing embodiments and is not intended to limit the disclosure. In this specification, unless specifically stated in the phrase, singular forms may also include plural forms, and when described in “at least one (or more) of A, B, and C,” at least one of all combinations that can be combined with A, B, and C may be included. Additionally, terms such as first, second, A, B, (a), and (b) may be used when describing elements of embodiments of this disclosure.

[0068] These terms are used only to distinguish one element from another, and are not limited to the nature, order, or sequence of the elements. Furthermore, when an element is described as being “connected,” “coupled,” or “in contact” with another element, it can include not only situations where the element is directly “connected,” “coupled,” or “in contact” with another element, but also situations where the element is “connected,” “coupled,” or “in contact” with another element through which the element is connected, coupled, or “in contact” with other elements.

[0069] Furthermore, when described as being formed or disposed "above" or "below" each element, "above" or "below" can include not only when two elements are directly connected to each other, but also when one or more other elements are formed or disposed between the two elements. Additionally, when expressed as "above" or "below," it can include not only the upward direction but also the downward direction based on a single element.

[0070] The terminology used in this application is for describing particular embodiments only and is not intended to limit the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, terms such as “comprising” or “having” are intended to specify the presence of features, quantities, steps, operations, components, parts, or combinations thereof described in the specification, and should be understood to not exclude the presence or addition of one or more other features, quantities, steps, operations, components, parts, or combinations thereof.

[0071] Unless otherwise defined, all terms used herein, including technical or scientific terms, shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms defined in common dictionaries shall be interpreted as having the same meaning as they have in the context of the relevant art and shall not be interpreted in an ideal or overly formal sense unless expressly defined in this application.

[0072] In the following description, embodiments will be described in detail with reference to the accompanying drawings. Regardless of the reference numerals, the same or corresponding parts will be assigned the same reference numerals, and redundant descriptions will be omitted.

[0073] Before describing the implementation methods, a semiconductor-packaged electronic device (not shown) applying the implementation methods will be briefly described. The electronic device may be a smartphone, personal digital assistant, digital camera, digital still camera, vehicle, high-performance server, network system, computer, monitor, tablet computer, laptop, netbook, television, video game, smartwatch, automotive equipment, etc. However, the electronic device is not limited to these and may be any other electronic device capable of processing data.

[0074] The electronic device includes a motherboard (not shown). The motherboard may be physically and / or electrically connected to various components. For example, the motherboard may be connected to a semiconductor package of an embodiment. Furthermore, the semiconductor package includes a circuit board, a semiconductor chip, a bonding portion for electrically connecting the semiconductor device to the circuit board, a resin portion filling the space between the semiconductor device and the circuit board, and a molded portion surrounding the semiconductor device.

[0075] Semiconductor devices can include active and / or passive devices and can have a variety of functions. Active devices can be in the form of integrated circuits (ICs), in which hundreds to millions or more transistors are integrated into a single semiconductor device, such as logic chips or memory chips. For example, a logic chip can be an application processor (AP) device that includes at least one of a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor, a cryptographic processor, a microprocessor, and a microcontroller, or it can be an analog-to-digital converter, an application-specific integrated circuit (ASIC), or a group of devices that includes a specific combination of the components listed above. Memory chips can be stacked memory such as HBM. In addition, memory chips can include volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, etc.

[0076] The semiconductor package of the implementation can be any of, but is not limited to, chip-scale package (CSP), flip chip-to-chip-scale package (FC-CSP), flip chip ball grid array (FC-BGA), stacked package (POP), and system-in-package (SIP).

[0077] Figure 1a This is a cross-sectional view of a circuit board according to an embodiment. Figure 1b This is a cross-sectional view of the circuit board according to the comparative example. Figure 2 This is an explanation Figure 1a The plan view of the first circuit layer layout described in the document. Figure 3 It is shown Figure 1a A plan view of the recess and through-hole of the first protective layer shown; Figure 4 This illustrates the first embodiment. Figure 3 A cross-sectional view of the recess and through-hole of the first protective layer. Figure 5 This illustrates the second embodiment. Figure 3 A cross-sectional view of the recess and through-hole of the first protective layer. Figure 6 This illustrates the third embodiment. Figure 3 A cross-sectional view of the recess and through-hole of the first protective layer. Figure 7 This illustrates the fourth embodiment. Figure 3 A cross-sectional view of the recess and through-hole of the first protective layer. Figure 8a and 8b This is a cross-sectional view showing the detailed structure of the protrusion portion according to another embodiment. Figure 9 This is a cross-sectional view showing the detailed structure of the protrusion portion according to yet another embodiment. Figure 10 This is a cross-sectional view of the circuit board according to the second embodiment. Figure 11 This is a cross-sectional view of a circuit board according to a third embodiment. Figure 12 This is a cross-sectional view showing a semiconductor package according to the first embodiment. Figure 13 This is a cross-sectional view showing a semiconductor package according to a second embodiment. Hereinafter, a schematic structure of a circuit board according to an embodiment will be described with reference to the accompanying drawings.

[0078] refer to Figure 1a The circuit board 100 includes stacked layers 101, 102, and 103, a first protective layer 104 disposed on one surface of the stacked layers 101, 102, and 103, and a second protective layer 105 disposed on the other surface of the stacked layers 101, 102, and 103. The stacked layers 101, 102, and 103 may have a structure stacked in a vertical direction. Preferably, the stacked layers 101, 102, and 103 may include a plurality of insulating layers and a plurality of circuit layers stacked vertically between one surface and another surface. Here, one surface may refer to the upper surface of the stacked layers 101, 102, and 103, and the other surface may refer to the lower surface of the stacked layers 101, 102, and 103. In this case, the upper surface of the stacked layers 101, 102, and 103 may refer to the upper surface of the uppermost insulating layer among the plurality of insulating layers. Furthermore, the lower surface of the stacked layers 101, 102, and 103 may refer to the lower surface of the lowermost insulating layer among the plurality of insulating layers.

[0079] Built-in layers 101, 102, and 103 include a core layer 101, an upper laminate 102, and a lower laminate 103. The upper laminate 102 may be disposed on one surface of the core layer 101, and the lower laminate 103 may be disposed on another surface of the core layer 101, but the implementation is not limited thereto. Here, "disposed on one surface and another surface" should not be construed as limited to configurations that are in direct contact with one surface and another surface, and should also be understood to include configurations where another component is disposed between one surface and the upper laminate 102, and between the other surface and the lower laminate 103.

[0080] The core layer 101 may include a core insulating layer 141. The core insulating layer 141 may be formed of a resin such as epoxy resin or BT (bismaleimide triazine) and a reinforcing material such as glass fiber, and may be used to improve the rigidity of the circuit board 100.

[0081] Recently, with the increase in the number of terminals of semiconductor devices disposed on circuit board 100, wiring has become more complex, and therefore, the thickness of the upper stacked layer 102 and the lower stacked layer 103 tends to increase. Therefore, the core insulating layer 141 of the core layer 101 according to the embodiment can have a thickness of 120 μm to 1200 μm to improve the overall rigidity of the circuit board 100 and prevent excessive signal loss. Vias penetrating one surface and the other surface can be formed in the core insulating layer 141.

[0082] The vias in the core insulating layer 141 can be formed using mechanical drilling, CO2 laser, or similar methods. When forming vias in the core insulating layer 141 using mechanical drilling, the inner wall of the via can be perpendicular to one surface and / or another surface of the core insulating layer 141. When forming vias in the core insulating layer 141 using a CO2 laser, the inner wall of the via can include a plurality of recesses and / or protrusions arranged alternately in the vertical direction. Here, a recess can refer to a region recessed in the horizontal direction away from the center of the via in the core insulating layer 141, and a protrusion can refer to a region protruding and / or projecting out in the horizontal direction toward the center of the via in the core insulating layer 141.

[0083] Recesses and protrusions can be alternately arranged in the vertical direction along the inner wall of the via forming the core insulating layer 141. Here, alternating arrangement can mean providing protrusions between multiple recesses and vice versa. In the case of vias formed using mechanical drilling, the path for transmitting electrical signals can be shortened, which may be advantageous in terms of electrical characteristics, but process costs may increase. Furthermore, when recesses and protrusions are formed on the inner wall of the via using a CO2 laser, the core via electrode 142 provided on the inner wall of the via can be formed with increased thickness in subsequent processes, thereby providing the advantages of reduced impedance and reduced process costs. Therefore, depending on the application area of ​​the semiconductor packaging, the method for processing the vias provided in the core layer 101 can be freely and selectively used.

[0084] Core via electrodes 142 can be disposed within vias in the core insulating layer 141. Core via electrodes 142 are used for electrical connection between the upper stacked layer 102 and the lower stacked layer 103. Therefore, it is preferable that the core via electrodes 142 densely fill the vias for resistance or heat dissipation characteristics. However, as the thickness of the core insulating layer 141 increases as described above, it may become difficult to densely fill the vias with core via electrodes 142. For example, when attempting to fill vias disposed in a thick core insulating layer 141 as described above by an electroplating process, voids may appear inside the core via electrodes 142. These voids may expand due to heat generated during semiconductor packaging operations and may become a factor reducing the mechanical reliability of the circuit board.

[0085] Therefore, a core via electrode 142 with a predetermined thickness can be disposed on the inner wall of the via in the core insulating layer 141. The thickness of the core via electrode 142 refers not to the thickness in the direction perpendicular to the stacking direction of the upper stack 102, the core insulating layer 141, and the lower stack 103, but rather to the thickness in the horizontal direction perpendicular to it. The core via electrode 142 can be configured to have a thickness of 5 μm to 20 μm to prevent voltage drop as the thickness of the core insulating layer 141 increases, and to prevent the formation of voids. Since it is difficult to densely fill the interior of the core via electrode 142 with metal using processes such as electroplating, empty spaces can be formed therein. These empty spaces may cause problems in making it difficult to flatten the upper stack 102 when stacking it.

[0086] Insulating member 143 can be disposed inside core via electrode 142, thereby allowing the flatness of core layer 101 to be ensured. For example, insulating member 143 can be disposed in a via of core insulating layer 141, and core via electrode 142 can surround the side of insulating member 143 and can be disposed between the inner wall of the via and the outer surface of insulating member 143. The upper surface of insulating member 143 can be coplanar with the upper surface of core insulating layer 141, or can be configured to be closer to upper stack 102 in the vertical direction than the upper surface of core insulating layer 141. The lower surface of insulating member 143 can be coplanar with the lower surface of core insulating layer 141, or can be configured to be closer to lower stack 103 in the vertical direction than the lower surface of core insulating layer 141. This allows for free design to address flatness when stacking upper stack 102 and lower stack 103, or to ensure the flatness of sixth circuit layer 116 and / or seventh circuit layer 122, which will be described below.

[0087] The upper layer 102 is disposed on one surface of the core layer 101. The upper layer 102 includes multiple insulating layers 106, 107, 108, 109 and 110 and multiple circuit layers 116, 117, 118, 119, 120 and 121.

[0088] The upper stacked layer 102 may include a first circuit layer 116, 117, 118, 119, 120, and 121 that are furthest from the core layer 101 in the vertical direction; a second circuit layer 117 that is closer to the core layer 101 in the vertical direction than the first circuit layer 116; a third circuit layer 118 that is closer to the core layer 101 in the vertical direction than the second circuit layer 117; a fourth circuit layer 119 that is closer to the core layer 101 in the vertical direction than the third circuit layer 118; a fifth circuit layer 120 that is closer to the core layer 101 in the vertical direction than the fourth circuit layer 119; and a sixth circuit layer 121 that is closer to the core layer 101 in the vertical direction than the fifth circuit layer 120. Here, the first circuit layer 116 refers to the uppermost circuit layer furthest from the core layer 101 among the circuit layers disposed in the upper stacked layer 102; therefore, the first circuit layer 116 may also be referred to as the upper circuit layer.

[0089] The first to sixth circuit layers 116, 117, 118, 119, 120, and 121 can be used for electrical connections to semiconductor devices disposed on the circuit board 100. Each of the first to sixth circuit layers 116, 117, 118, 119, 120, and 121 can be freely designed considering impedance. Additionally, via electrodes 131, 132, 133, 134, and 135 can be configured to connect the first to sixth circuit layers 116, 117, 118, 119, 120, and 121. For example, the first via electrode 131 may be disposed between the first circuit layer 116 and the second circuit layer 117, the second via electrode 132 may be disposed between the second circuit layer 117 and the third circuit layer 118, the third via electrode 133 may be disposed between the third circuit layer 118 and the fourth circuit layer 119, the fourth via electrode 134 may be disposed between the fourth circuit layer 119 and the fifth circuit layer 120, and the fifth via electrode 135 may be disposed between the fifth circuit layer 120 and the sixth circuit layer 121, thereby electrically connecting the first to the sixth circuit layers 116, 117, 118, 119, 120 and 121.

[0090] The first to fifth via electrodes 131, 132, 133, 134, and 135 can be formed simultaneously during the formation of the first to fifth circuit layers 116, 117, 118, 119, and 120. For example, in the process of forming the fifth circuit layer 120 on the sixth circuit layer 121, a via can be formed in the fifth insulating layer 110 to expose a portion of the sixth circuit layer 121, and the fifth circuit layer 120 can be formed together with the fifth via electrode 135 filling the via of the fifth insulating layer 110. Thus, the fifth via electrode 135 can be distinguished as a protruding portion of the fifth circuit layer 120. Similarly, each of the first to fourth via electrodes 131, 132, 133, and 134 can be distinguished as a protruding portion of a corresponding one of the first to fourth circuit layers 116, 117, 118, and 119, and can be connected to another circuit layer disposed below the corresponding circuit layer.

[0091] The first circuit layer 116 may be disposed adjacent to the first protective layer 104. The first circuit layer 116 may include multiple circuit patterns. The multiple circuit patterns of the first circuit layer 116 may include pad portions 116a, bump portions 116b, and wiring portions 116c, depending on their arrangement, function, size, and / or shape.

[0092] The width of the pad portion 116a in the horizontal direction may be relatively larger than the width of each of the bump portion 116b and the wiring portion 116c in the horizontal direction. Optionally, the pad portion 116a may be positioned closer to the outer surface of the upper stacked layer 102 than the bump portion 116b. Optionally, the pad portion 116a may be a terminal connected to a semiconductor device and / or an external substrate, having a relatively larger size than the terminal connected to the semiconductor device and / or the external substrate connected to the bump portion 116b. Furthermore, the pad portion 116a may refer to a circuit layer in the first circuit layer 116 that overlaps in the vertical direction with the via 104a disposed in the first protective layer 104.

[0093] The width of the bump portion 116b in the horizontal direction may be relatively smaller than the width of the pad portion 116a in the horizontal direction. Alternatively, the pad portion 116a may be positioned further away from the outer surface of the upper stacked layer 102 than the bump portion 116b. Optionally, the bump portion 116b may be a bonding portion of a terminal connected to a semiconductor device and / or an external substrate. However, the bump portion 116b may be a bonding portion of a terminal connected to a semiconductor device and / or an external substrate, having a relatively smaller size than the terminal connected to the pad portion 116a of the semiconductor device and / or the external substrate. Furthermore, the bump portion 116b may refer to a circuit layer that overlaps with the recess 104b disposed in the first protective layer 104 in the vertical and / or horizontal directions.

[0094] The thickness of the bump portion 116b in the vertical direction may differ from the thickness of the pad portion 116a in the vertical direction. For example, the thickness of the bump portion 116b in the vertical direction may be greater than the thickness of the pad portion 116a in the vertical direction. The bump portion 116b may refer to an electrode on which bonding members (such as solder) for bonding with a semiconductor device are disposed. The bump portion 116b may refer to an electrode protruding above the bottom surface of the recess 104b disposed in the first protective layer 104 for bonding with a semiconductor device. For this purpose, the bump portion 116b may include a first portion 116b1 corresponding to the pad portion 116a and a second portion 116b2 disposed on the first portion 116b1. The second portion 116b2 of the bump portion 116b may protrude above the first portion 116b1, thereby allowing the semiconductor device to be stably disposed on the bump portion 116b and further allowing the semiconductor device to operate stably.

[0095] In other words, as the functionality and performance of semiconductor devices increase, the number of I / O terminals provided in the semiconductor devices also increases. Therefore, as the width and / or spacing of the I / O terminals in the semiconductor device becomes finer, electrical short circuits may occur when multiple bonding members come into contact with each other during the process of connecting the I / O terminals of the semiconductor device via bonding members such as solder. Therefore, as the terminal density of the semiconductor device increases, in order to reduce, for example, the amount of bonding members used with solder, the first circuit layer 116 may include a bump portion 116b protruding from the bottom surface of the recess 104b of the first protective layer 104. For example, this embodiment can perform a fine bonding process, such as applying bonding members such as solder to the upper surface of the bump portion 116b and then performing thermocompression bonding (hereinafter referred to as "TC bonding"). When performing the fine bonding process, the bump portion 116b may be configured to protrude above the bottom surface of the recess 104b of the first protective layer 104 to improve the alignment between the semiconductor device terminals and the bump portion 116b.

[0096] Therefore, the bump portion 116b may include a first portion 116b1 disposed on the upper stack 102 and a second portion 116b2 disposed on the first portion 116b1. The first portion 116b1 of the bump portion 116b may be the portion corresponding to the pad portion 116a and / or the wiring portion 116c, and the second portion 116b2 of the bump portion 116b may be a protrusion additionally disposed on the first portion 116b1. In this case, the first portion 116b1 and the second portion 116b2 may have different widths in the horizontal direction, and preferably, the width of the second portion 116b2 disposed above the first portion 116b1 in the horizontal direction may be smaller than the width of the first portion 116b1 in the horizontal direction. Therefore, this embodiment can provide a bump portion 116b including the second portion 116b2, which has a relatively small width in the horizontal direction, thereby reducing the spacing between multiple adjacent bumps or increasing the spacing between multiple bumps. Therefore, it can improve circuit integration or solve the problem of short circuits caused by adjacent solders in contact with each other.

[0097] The wiring portion 116c can electrically connect multiple pad portions 116a and / or multiple bump portions 116b. The wiring portion 116c can be a circuit line connecting the multiple pad portions 116a and / or bump portions 116b. For example, the wiring portion 116c can be a signal transmission line and can be referred to as a trace.

[0098] The sixth circuit layer 121 may contact one surface of the core layer 101. In this case, a portion of the sixth circuit layer 121 may be configured to cover the aforementioned insulating component 142. That is, the lower surface of the sixth circuit layer 121 may include a first portion that contacts the upper surface of the core via electrode 141, a second portion that contacts the upper surface of the insulating component 142, and a third portion that contacts the upper surface of the core layer 101.

[0099] The plurality of insulating layers 106, 107, 108, 109 and 110 of the upper stack 102 may include a first insulating layer 106 that is furthest from the core layer 101 in the vertical direction, a second insulating layer 107 that is closer to the core layer 101 in the vertical direction than the first insulating layer 106, a third insulating layer 108 that is closer to the core layer 101 in the vertical direction than the second insulating layer 107, a fourth insulating layer 109 that is closer to the core layer 101 in the vertical direction than the third insulating layer 108, and a fifth insulating layer 110 that is closer to the core layer 101 in the vertical direction than the fourth insulating layer 109.

[0100] The first to fifth insulating layers 106, 107, 108, 109, and 110 are configured to provide insulation in the vertical direction between the first to sixth circuit layers 116, 117, 118, 119, 120, and 121. For example, a thermosetting insulating material comprising inorganic fillers in the resin can be used for the first to sixth insulating layers 106, 107, 108, 109, and 110, and Ajinomoto laminated film (ABF) manufactured by Ajinomoto Co., Ltd. can be used. However, the embodiments are not limited to this, and a photoimageable dielectric (PID) material can be used to form fine patterns.

[0101] A first protective layer 104 may be disposed on the upper stacked layer 102. The first protective layer 104 protects the first circuit layer 116 from external moisture or contaminants. Furthermore, when semiconductor devices are mounted on the circuit board 100 using materials such as solder, the first protective layer 104 prevents short circuits between solders due to low wettability with the solder. A photocurable insulating material may be used for the first protective layer 104, and, for example, a solder resist may be used.

[0102] The first protective layer 104 may expose a bonding portion in the first circuit layer 116 on which bonding members (e.g., solder) are disposed for bonding to semiconductor devices and / or an external substrate. For example, the first protective layer 104 may include a via 104a. The via 104a can penetrate the first protective layer 104 from its upper surface toward its lower surface. In this case, the via 104a may overlap with the pad portion 116a in the vertical direction. For example, the via 104a may be provided in a region of the first protective layer 104 that overlaps with the pad portion 116a in the vertical direction. Therefore, in the region that overlaps in the vertical direction, the lower surface of the first protective layer 104 may include a portion that contacts the upper surface of the pad portion 116a, and at least a portion of the upper surface of the pad portion 116a may be exposed to the outside of the circuit board through the via 104a provided in the first protective layer 104.

[0103] The first protective layer 104 may further include a recess 104b, the depth of which in the vertical direction differs from the depth of the via 104a in the vertical direction. The recess 104b may be disposed in a region of the first circuit layer 116 where the bump portion 116b is disposed. The recess 104b may be configured to cover at least a portion of the side surface of the bump portion 116b, while exposing the remaining portion of the side surface and the upper surface of the bump portion 116b. Therefore, the first protective layer 104 can stably support the bump portion 116b using the recess 104b, thereby ensuring the height of the bump portion 116b and allowing the semiconductor device to be disposed more stably on the bump portion 116b.

[0104] The depth of the recess 104b of the first protective layer 104 in the vertical direction can be greater than the depth of the through hole 104a of the first protective layer 104 in the vertical direction. Therefore, the vertical length of the sidewall of the recess 104b of the first protective layer 104 can be less than the vertical length of the sidewall of the through hole 104a. Optionally, the bottom surface of the recess 104b of the first protective layer 104 can be positioned higher than the upper surface of the pad portion 116a. Therefore, the first protective layer 104 can completely cover the upper surface and side surface of the first portion 116b1 of the bump portion 116b, and can cover a portion of the side surface of the second portion 116b2 of the bump portion 116b.

[0105] In this case, in the comparative example, the size of the through-hole 104a that can be formed in the first protective layer 104 is limited. (See reference...) Figure 1b The circuit board according to the comparative example includes a multilayer 10, an upper circuit layer 20, a protective layer 30, and bump portions 50, with the protective layer 30 including vias 40. In this case, due to the resolution limitations of the exposure and development processes of the protective layer 30, there are limitations in reducing the size of the vias 40. Therefore, in the comparative example, due to the limitation in reducing the size of the vias 40 formed in the protective layer 30, it is difficult to achieve fine pitch between multiple bonding portions and / or pad portions. Furthermore, in the comparative example, protruding electrodes 50, such as metal pillars, are provided on the pad portions to achieve fine pitch, but the aforementioned metal pillars have a structure that is disposed in the vias 40 of the protective layer 30 without contacting the protective layer 30. Therefore, the protruding electrodes 50 may not be stably supported, thus limiting the height that the protruding electrodes 50 can have. In addition, during the process of forming the vias 40 in the protective layer 30, reliability problems may occur in the protruding electrodes 50. Furthermore, in the prior art, because the interface between the upper circuit layer 20 and the protruding electrode 50 is not covered by the protective layer 30, physical and / or electrical reliability can be reduced. For example, a bonding member such as solder can be disposed on the protruding electrode 50, and an intermetallic compound (IMC) can be formed due to the contact between the bonding member and the protruding electrode 50. In this case, the intermetallic compound can penetrate between the upper circuit layer 20 and the protruding electrode 50, thereby reducing adhesion between the upper circuit layer 20 and the protruding electrode or acting as a factor that reduces electrical characteristics.

[0106] This embodiment can provide a bump portion 116b, the thickness of which in the vertical direction is greater than the thickness of the pad portion 116a in the vertical direction. Furthermore, the bump portion 116b can overlap with a recess 104b disposed in the first protective layer 104 in the vertical and / or horizontal directions, allowing the bump portion 116b to be stably supported and / or protected by the first protective layer 104. Therefore, compared to the comparative example, this embodiment can increase the height of the bump portion 116b (preferably, the thickness of the second portion of the bump portion 116b), thereby fixing a support that allows the semiconductor device to be stably disposed on the upper stacked layer 102.

[0107] The bottom surface of the recess 104b of the first protective layer 104 can be positioned higher than the first portion 116b1 of the bump portion 116b. Therefore, the interface between the first portion 116b1 and the second portion 116b2 of the bump portion 116b can be positioned lower than the recess 104b of the first protective layer 104. That is, the interface between the first portion 116b1 and the second portion 116b2 of the bump portion 116b can be covered by the first protective layer 104. Therefore, this embodiment can prevent cracking at the interface between the first portion 116b1 and the second portion 116b2 of the bump portion 116b, or prevent intermetallic compounds from penetrating into the interface, thereby further improving the mechanical and / or electrical reliability of the circuit board and the semiconductor package containing the circuit board.

[0108] The recess 104b of the first protective layer 104 may be spaced apart from the through-hole 104a of the first protective layer 104 in the horizontal direction. For example, the first protective layer 104 may include a plurality of through-holes 104a spaced apart from each other in the horizontal direction, and each of the plurality of through-holes 104a may be spaced apart from the recess 104b and not connected to the recess 104b. Therefore, mechanical reliability and / or electrical reliability can be improved by preventing problems that may occur when the through-holes 104a and the recesses 104b of the first protective layer 104 are connected to each other. For example, electrical reliability problems that may occur when the through-holes 104a and the recesses 104b of the protective layer 104 are connected to each other, such as short circuits caused by the flow of bonding members such as solder, can be solved. Furthermore, for example, when the through-hole 104a and the recess 104b of the first protective layer 104 are connected to each other, the volume of the first protective layer 104 can be significantly smaller than the volume of the second protective layer 105. Due to this volume difference between the first and second protective layers 104 and 105, the circuit board may warp significantly in a specific direction. Therefore, this embodiment can prevent significant warping of the circuit board in a specific direction by preventing the through-hole 104a and the recess 104b from connecting to each other, thereby further improving the mechanical and / or electrical reliability of the circuit board and semiconductor package.

[0109] The recess 104b of the first protective layer 104 can be configured to surround a plurality of protrusion portions 116b, and the plurality of through holes 104a of the first protective layer 104 can be configured along the periphery of the recess 104b.

[0110] The lower layer 103 is disposed on the other surface of the core layer 101. The lower layer 103 includes a plurality of insulating layers 111, 112, 113, 114 and 115, a plurality of circuit layers 122, 123, 124, 125, 126 and 127, and a second protective layer 127.

[0111] The lower stacked layer 103 may include the seventh circuit layer 122 closest to the core layer 101 in the vertical direction, the eighth circuit layer 123 disposed below the seventh circuit layer 116, the ninth circuit layer 124 disposed below the eighth circuit layer 123, the tenth circuit layer 125 disposed below the ninth circuit layer, the eleventh circuit layer 126 disposed below the tenth circuit layer 125, and the twelfth circuit layer 127 disposed below the eleventh circuit layer 126. The seventh circuit layers 122, 123, 124, 125, 126, and twelfth circuit layers 127 may be used to electrically connect the motherboard (not shown) of the electronic device and semiconductor devices disposed on the circuit board 100. Each of the seventh to twelfth circuit layers 122, 123, 124, 125, 126, and 127 may be freely designed considering impedance.

[0112] Furthermore, via electrodes 136, 137, 138, 139, and 140 can be configured to connect the seventh to twelfth circuit layers 122, 123, 124, 125, 126, and 127. The sixth via electrode 136 can be disposed between the seventh circuit layer 122 and the eighth circuit layer 123; the seventh via electrode 137 can be disposed between the eighth circuit layer 123 and the ninth circuit layer 124; the eighth via electrode 138 can be disposed between the ninth circuit layer 124 and the tenth circuit layer 125; the ninth via electrode 139 can be disposed between the tenth circuit layer 125 and the eleventh circuit layer 126; and the tenth via electrode 140 can be disposed between the eleventh circuit layer 126 and the twelfth circuit layer 127, thereby electrically connecting the seventh to twelfth circuit layers 122, 123, 124, 125, 126, and 127.

[0113] As described above regarding the first to fifth via electrodes 131, 132, 133, 134, and 135 of the upper stacked layer 102, the sixth to tenth via electrodes 136, 137, 138, 139, and 140 may also be formed simultaneously during the formation of the eighth to twelfth circuit layers 123, 124, 125, 126, and 127. Therefore, as described above, the seventh via electrode 137 can be distinguished as a protruding portion of the ninth circuit layer 124. However, because the eighth to twelfth circuit layers 123, 124, 125, 126, and 127 are stacked in a direction different from the stacking direction of the upper stacked layer 102, the tilt direction of each of the via electrodes 131, 132, 133, 134, and 135 of the upper stacked layer 102 may be opposite to the tilt direction of each of the via electrodes 136, 137, 138, 139, and 140 of the lower stacked layer 103. For example, each of the via electrodes 131, 132, 133, 134, and 135 in the upper stacked layer 102 may have a slope in which its width decreases toward the core layer 101, and each of the via electrodes 136, 137, 138, 139, and 140 in the lower stacked layer 103 may also have a slope in which its width decreases toward the core layer 101. For example, the slope of each of the via electrodes 131, 132, 133, 134, and 135 in the upper stacked layer 102 may be symmetrical with respect to the slope of each of the via electrodes 136, 137, 138, 139, and 140 in the core layer 101 and the lower stacked layer 103.

[0114] The seventh circuit layer 122 may contact another surface of the core layer 101. In this case, a portion of the seventh circuit layer 122 may be configured to cover the aforementioned insulating member 142. That is, the lower surface of the seventh circuit layer 122 may include a first portion that contacts the lower surface of the core via electrode 141, a second portion that contacts the lower surface of the insulating member 142, and a third portion that contacts the lower surface of the core layer 101.

[0115] The plurality of insulating layers 111, 112, 113, 114, and 115 of the lower laminate 103 may include a sixth insulating layer 111 closest to the core layer 101 in the vertical direction, a seventh insulating layer 112 disposed below the sixth insulating layer 111, an eighth insulating layer 113 disposed below the seventh insulating layer 112, a ninth insulating layer 114 disposed below the eighth insulating layer 113, and a tenth insulating layer 115 disposed below the ninth insulating layer 114. The sixth to tenth insulating layers 111, 112, 113, 114, and 115 are configured to provide insulation in the vertical direction between the aforementioned seventh to twelfth circuit layers 122, 123, 124, 125, 126, and 127. Furthermore, for example, a thermosetting insulating material comprising inorganic fillers in the resin may be used for the sixth to tenth insulating layers 111, 112, 113, 114, and 115, and Ajinomoto laminated film (ABF) manufactured by Ajinomoto Co., Ltd. may be used. However, the implementation is not limited to this, and photoimageable dielectric (PID) materials can be used to form fine patterns.

[0116] The second protective layer 105 protects the twelfth circuit layer 127 from external moisture or contaminants. Furthermore, when semiconductor devices are mounted on the circuit board 100 using materials such as solder, the second protective layer 105 prevents short circuits between solders due to low wettability with the solder. A photocurable insulating material can be used for the second protective layer 105, and, for example, a solder resist can be used.

[0117] Furthermore, the via electrodes 131, 132, 133, 134, 135, 136, 137, 138, 139, and 140 of the upper stacked layer 102 and the lower stacked layer 103 can have a structure in which at least a portion of them overlap each other in the vertical direction. Therefore, voltage drop and / or signal loss can be reduced, and the design freedom of wiring can be increased. However, when the semiconductor device is mounted on the circuit board 100, if a load is applied to the vertically overlapping via electrodes 131, 132, 133, 134, 135, 136, 137, 138, 139, and 140 due to the load applied to the circuit board 100, cracks may appear at the interfaces between the via electrodes 131, 132, 133, 134, 135, 136, 137, 138, 139, and 140 and the circuit layers 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, and 127. Therefore, in this example, the aforementioned bump portion 116b may have a structure that does not vertically overlap with the via electrodes 131, 132, 133, 134, 135, 136, 137, 138, 139, and 140.

[0118] The detailed arrangement of the first circuit layer 116 according to the embodiment will be described in detail below, as well as the arrangement relationship between the first circuit layer 116 and the through holes 104a and recesses 104b of the first protective layer 104.

[0119] Reference Figure 2 A first circuit layer 116 may be disposed on the upper stacked layer 102. The first circuit layer 116 may include pad portions 116a, bump portions 116b, and wiring portions 116c. The pad portions 116a may be disposed around the bump portions 116b. For example, the pad portions 116a may be positioned closer to the outer surface of the upper stacked layer 102 than the bump portions 116b. In this case, the width of the pad portions 116a in the horizontal direction may be greater than the width of the bump portions 116b in the horizontal direction. That is, the pad portions 116a with a relatively large width in the horizontal direction may be positioned adjacent to the outer surface of the upper stacked layer 102, thereby ensuring the rigidity of the periphery of the upper surface of the upper stacked layer 102 and preventing significant warping of the circuit board in a particular direction.

[0120] Compared to pad portion 116a, bump portion 116b can have a relatively fine width or fine spacing. Bump portion 116b can connect to terminals of semiconductor devices with relatively small linewidths and / or pitches, while pad portion 116a can connect to terminals of semiconductor devices with relatively large linewidths and / or pitches and / or pads of external substrates. For example, pad portion 116a can be used as power routing for supplying power to semiconductor devices and / or connection members, and bump portion 116b can be used as signal routing for sending and receiving communication signals other than power signals to and from semiconductor devices and / or connection members. In this case, multiple pad portions 116a can be arranged around bump portion 116b at locations spaced apart from bump portion 116b, thereby achieving stable power supply without interfering with communication signals transmitted through pad portion 116a.

[0121] Additionally, the pad portion 116a can act as a shield to prevent interference signals (such as external noise) from being transmitted to the bump portion 116b. Therefore, the loss of communication signals transmitted through the bump portion 116b can be minimized to improve communication characteristics, thereby further enhancing the operational reliability of the circuit board and semiconductor package.

[0122] In this case, although the pad portion 116a is shown in the drawings as being disposed on one side of the bump portion 116b and on the opposite side, the implementation is not limited to this. For example, in the plan view of the upper stack 102, the pad portion 116a may be disposed on the left, right, upper and lower sides of the bump portion 116b, respectively.

[0123] The first circuit layer 116 further includes a wiring portion 116c. The wiring portion 116c may overlap with the bump portion 116b and the pad portion 116a in the horizontal direction. The wiring portion 116c may electrically connect the bump portion 116b and / or the pad portion 116a. For example, as... Figure 2 As shown, the wiring portion 116c can electrically connect to a plurality of bump portions 116b. However, the implementation is not limited to this, and the wiring portion 116c can electrically connect to a plurality of pad portions 116a or can electrically connect pad portions 116a and bump portions 116b.

[0124] In the following text, various embodiments of the through-hole 104a and the recess 104b of the first protective layer 104 will be described.

[0125] according to Figure 3 and Figure 4 In one embodiment, the first protective layer 104 may be disposed on the upper laminate 102.

[0126] The first protective layer 104 may include a via 104a. The via 104a may overlap with the pad portion 116a of the first circuit layer 116 of the upper stacked layer 102 in the vertical direction. In this case, the via 104a may overlap with a portion of the upper surface of the pad portion 116a in the vertical direction. However, the implementation is not limited to this, and the via 104a may overlap with the entire area of ​​the upper surface of the pad portion 116a in the vertical direction. Hereinafter, the case where the via 104a overlaps with a portion of the upper surface of the pad portion 116a in the vertical direction will be described. For example, the width of the via 104a in the horizontal direction may be smaller than the width of the pad portion 116a in the horizontal direction. Therefore, at least a portion of the upper surface of the pad portion 116a may be covered by the first protective layer 104, and another portion of the upper surface of the pad portion 116a may overlap with the via 104a in the vertical direction and may be exposed to the outside of the circuit board. For example, the upper surface of the pad portion 116a may include a first upper surface portion 116a1 that overlaps with the through-hole 104a of the first protective layer 104 in the vertical direction, and a second upper surface portion 116a2 that is located closer to the outer surface of the pad portion 116a than the first upper surface portion 116a1 and is covered by the first protective layer 104.

[0127] Multiple vias 104a may be provided. For example, the upper layer 102 may include multiple pad portions 116a spaced apart from each other in the horizontal direction, and multiple vias 104a of the first protective layer 104 may be provided to overlap with the corresponding multiple pad portions 116a in the vertical direction.

[0128] A recess 104b may be disposed inside a plurality of through holes 104a. For example, the plurality of through holes 104a may be disposed along the peripheral region of the recess 104b. The recess 104b may cover at least a portion of the protrusion portion 116b while exposing at least another portion of the protrusion portion 116b. For example, the recess 104b may be a recess positioned below the upper surface of the first protective layer 104 and above the lower surface of the first protective layer 104. The recess 104b may be disposed in the region in which the plurality of protrusion portions 116b are disposed. For example, the recess 104b may be provided to surround the plurality of protrusion portions 116b. That is, the recess 104b may be disposed around the plurality of protrusion portions 116b. In addition, the recesses 104b disposed around the plurality of protrusion portions 116b may be connected to each other.

[0129] In this case, the bottom surface 104b1 of the recess 104b can have a predetermined height. For example, the bottom surface 104b1 of the recess 104b can be positioned below the upper surface of the first protective layer 104 and above the lower surface of the first protective layer 104.

[0130] Furthermore, the bottom surface 104b1 of the recess 104b can be positioned below the upper surface of the protrusion 116b. Therefore, at least a portion of the protrusion 116b can overlap with the recess 104b in the horizontal direction. Thus, the upper surface of the protrusion 116b can be exposed to the outside without being covered by the first protective layer 104. Additionally, at least a portion of the side surface of the protrusion 116b can overlap with the recess 104b in the horizontal direction, thereby being exposed to the outside without being covered by the first protective layer 104. In this case, at least a portion of the side surface of the protrusion 116b that overlaps with the recess 104b in the horizontal direction can be exposed to the outside without being covered by the first protective layer 104. Furthermore, the area of ​​the protrusion 116b that overlaps with the recess 104b in the horizontal direction can be used as a joining portion, on which a joining member, such as solder, is disposed.

[0131] Furthermore, the bottom surface 104b1 of the recess 104b can be located on a different plane than the bottom surface of the through hole 104a. In this case, the through hole 104a overlaps with the upper surface of the pad portion 116a in the vertical direction; therefore, the bottom surface of the through hole 104a can refer to the upper surface of the pad portion 116a. The depth of the through hole 104a in the vertical direction can be different from the depth of the recess 104b in the vertical direction. The depth of the through hole 104a in the vertical direction can be greater than the depth of the recess 104b in the vertical direction. The bottom surface 104b1 of the recess 104b can be positioned higher than the bottom surface of the through hole 104a. That is, the bottom surface 104b1 of the recess 104b can be positioned higher than the upper surface of the pad portion 116a.

[0132] In this case, the thickness H1 of the pad portion 116a in the vertical direction can be less than the thickness H2 of the bump portion 116b in the vertical direction. For example, the bump portion 116b may include a first portion 116b1 and a second portion 116b2. The first portion 116b1 of the bump portion 116b may correspond to the pad portion 116a. Here, "corresponds" can mean that when the pad portion 116a is manufactured, the first portion 116b1 of the bump portion 116b is formed together with the pad portion 116a. Therefore, the thickness H1 of the pad portion 116a in the vertical direction can be equal to the thickness H2 of the first portion 116b1 of the bump portion 116b in the vertical direction. Furthermore, the thickness H2 of the bump portion 116b in the vertical direction can be greater than the thickness H3 of the second portion 116b2 than the thickness H1 of the pad portion 116a in the vertical direction. Therefore, the bottom surface 104b1 of the recess 104b can be positioned higher than the first portion 116b1 of the protrusion 116b, and thus the upper and side surfaces of the first portion 116b1 can be completely covered by the first protective layer 104. Furthermore, since the bottom surface 104b1 of the recess 104b is positioned higher than the upper surface of the first portion 116b1, at least a portion of the side surface of the second portion 116b2 can be covered by the first protective layer 104. For example, the bottom surface 104b1 of the recess 104b can be located between the upper surface and the lower surface of the second portion 116b2 of the protrusion 116b.

[0133] Therefore, a bump portion 116b with a vertical thickness H2 greater than the vertical thickness H1 of the pad portion 116a can be provided, and the bump portion 116b can overlap with the recess 104b provided in the first protective layer 104 in the vertical and / or horizontal directions, so that the bump portion 116b can be stably supported and / or protected by the first protective layer 104. Therefore, compared to the comparative example, the embodiment can increase the height of the bump portion 116b (preferably, the thickness of the second portion of the bump portion 116b), thereby ensuring that a support allowing a semiconductor device to be stably disposed on the upper stacked layer 102 is provided. Therefore, a second portion 116b2 of the bump portion 116b with a relatively small width in the horizontal direction can be used to mount the semiconductor device. Furthermore, the spacing between adjacent second portions 116b2 can be greater than the spacing between adjacent first portions 116b1, thereby solving the problem of short circuits in circuits where bonding members such as solder are electrically connected to each other. Furthermore, the bottom surface of the recess 104b of the first protective layer 104 can be positioned higher than the upper surface of the wiring portion 116c disposed in the area where the recess 104b is disposed, and therefore, the first protective layer 104 can be configured to completely cover the wiring portion 116c. Thus, the protrusion portion 116b can be supported while stably protecting the wiring portion 116c.

[0134] Furthermore, the bottom surface of the recess 104b of the first protective layer 104 can be positioned higher than the first portion 116b1 of the bump portion 116b. Therefore, the interface between the first portion 116b1 and the second portion 116b2 of the bump portion 116b can be positioned lower than the recess 104b of the first protective layer 104. That is, the interface between the first portion 116b1 and the second portion 116b2 of the bump portion 116b can be covered by the first protective layer 104. Therefore, this embodiment can prevent cracking at the interface between the first portion 116b1 and the second portion 116b2 of the bump portion 116b, or prevent intermetallic compounds from penetrating into the interface, thereby further improving the mechanical and / or electrical reliability of the circuit board and the semiconductor package containing the circuit board.

[0135] Furthermore, the side surface of the second portion 116b2 of the bump portion 116b may include an embedded portion covered by the first protective layer 104 and an exposed portion disposed on the embedded portion and exposed to the outside. That is, the exposed portion of the second portion 116b2 may overlap with the recess 104b in the horizontal direction. In this case, the thickness of the embedded portion and the thickness of the exposed portion of the second portion 116b2 of the bump portion 116b may be different from each other. For example, the thickness of the exposed portion of the second portion 116b2 of the bump portion 116b may be greater than the thickness of the embedded portion. That is, the thickness H31 of the exposed portion may be in the range of 120% to 600% of the thickness H32 of the embedded portion. When the thickness H31 of the exposed portion is less than 120% of the thickness H32 of the embedded portion, it may be difficult to sufficiently fix the contact area with the bonding member, and therefore, the bonding strength with the bonding member may be reduced, making it difficult to stably mount the semiconductor device. When the thickness H31 of the exposed portion exceeds 600% of the thickness H32 of the embedded portion, the thickness of the exposed portion may be excessively greater than the thickness of the embedded portion supported by the first protective layer 104. Therefore, the second portion 116b2 of the protrusion portion 116b may be difficult to stably support by the first protective layer 104. As a result, mechanical reliability problems may occur, such as the breakage of the protrusion portion 116b.

[0136] Meanwhile, the slope of the sidewall of the through hole 104a and the slope of the sidewall of the recess 104b in the first protective layer 104 can be the same as each other. Optionally, the slope of the sidewall of the through hole 104a and the slope of the sidewall of the recess 104b in the first protective layer 104 can be different from each other.

[0137] Preferably, the through-hole 104a may overlap with the pad portion 116a, which has a relatively large width in the horizontal direction, in the vertical direction, and may have a relatively large depth in the vertical direction. Conversely, the recess 104b may be provided in the region where the bump portion 116b, which has a relatively small width in the horizontal direction, is provided, and may have a relatively small depth in the vertical direction. Therefore, this embodiment allows the corresponding sidewalls of the through-hole 104a and the recess 104b to have different inclination angles.

[0138] according to Figure 5In this embodiment, the sidewall of the through-hole 104a may have a predetermined inclination relative to the upper or lower surface of the first protective layer 104. For example, the sidewall of the through-hole 104a may have an inclination such that the width of the through-hole 104a in the horizontal direction decreases from the upper part of the through-hole 104a toward the lower part of the through-hole 104a. Therefore, the volume of the joining member within the relatively large volume of the through-hole 104a can be adjusted, thereby reducing manufacturing costs. In addition, the sidewall of the through-hole 104a may have an inclination such that the width of the through-hole 104a in the horizontal direction decreases from the upper part of the through-hole 104a toward the lower part of the through-hole 104a, thereby allowing the joining member to be easily disposed within the through-hole 104a having a relatively large depth in the vertical direction.

[0139] Conversely, the sidewall of the recess 104b can have a different inclination than the sidewall of the through hole 104a. For example, the inclination of the sidewall of the recess 104b can be closer to vertical than the inclination of the sidewall of the through hole 104a. Therefore, the area of ​​the bottom surface 104b1 of the recess 104b can be ensured, allowing for precise control of the space for setting the semiconductor device and more stable setting of the semiconductor device.

[0140] according to Figure 6 In one embodiment, a groove 104b2 may be provided in the sidewall of the recess 104b. The groove 104b2 may be configured to be recessed from the sidewall of the recess 104b in an outward direction away from the recess 104b. The groove 104b2 may be provided in the inner wall of the recess 104b by adjusting the amount of exposure in the area in which the recess 104b is to be formed during the process of forming the recess 104b. For example, curing of the portion adjacent to the periphery of the bottom surface 104b1 of the recess 104b may be prevented by adjusting the amount of exposure in the area in which the recess 104b is to be formed. Therefore, a groove 104b2 recessed in the outward direction may be provided in the sidewall of the recess 104b. That is, the groove 104b2 may be provided at the boundary between the sidewall and the bottom surface of the recess 104b. In addition, the groove 104b2 may be provided along the circumferential direction of the bottom surface 104b1 of the recess 104b. The trench 104b2 may be filled with bonding members, such as solder, disposed on the bump portion 116b, thereby serving as an anchor to enhance the bonding strength between the bonding members and the circuit board. Alternatively, the trench 104b2 may be filled with molding members of molded semiconductor devices, thereby further enhancing the bonding strength between the molding members and the circuit board.

[0141] according to Figure 7 In some embodiments, the bottom surface 104b1 of the first protective layer 104 may not be flat and may have a curved profile. For example, the bottom surface 104b1 of the first protective layer 104 may include a concave surface recessed toward the upper laminate 102.

[0142] In other words, the recess 104b of the first protective layer 104 is disposed between the plurality of protrusions of the protrusion portion 116b. Therefore, the concave surface disposed on the bottom surface 104b1 of the first protective layer 104 can be recessed between the plurality of protrusions in the downward direction or in the direction toward the upper surface of the insulating layer 110. The concave surface of the first protective layer 104 can be used to increase the surface area of ​​the upper surface of the first protective layer 104, and thus prevents stress caused by thermal cycling (e.g., expansion and / or contraction) from being transmitted to the protrusion portion 116b.

[0143] For example, the concave surface provided on the upper surface of the first protective layer 104 increases the surface area of ​​the upper surface of the first protective layer 104. Therefore, compared with the case where the upper surface of the first protective layer 104 is a flat surface, it can be used to increase the surface area of ​​the upper surface of the first protective layer 104 between the protrusion portions 116b.

[0144] Therefore, the implementation can solve the problem of cracking of the bump portion 116b due to thermal stress acting on the circuit board, and thus can solve the reliability problem of the conductive adhesive such as solder disposed on the bump portion 116b and / or the terminals of the semiconductor device being electrically separated from the bump portion 116b.

[0145] For example, when thermal deformation occurs (such as expansion and / or contraction of the circuit board), the resulting stress can act on the circuit board and can be transmitted to the bump portion 116b. Here, thermal deformation can mean a change in volume of the first protective layer 104 due to expansion and / or contraction of the first protective layer 104.

[0146] When the first protective layer 104 undergoes repeated thermal deformation, stress may act on the bump portions 116b disposed in the first protective layer 104, and due to this stress, cracks may occur at the connection between the first portion 116b1 and the second portion 116b2 of the bump portions 116b. Therefore, the bump portions 116b may delaminate from the circuit board, resulting in mechanical reliability problems and / or electrical reliability problems.

[0147] Furthermore, when the first protective layer 104 undergoes repeated thermal deformation, stress may act on the bonding members (such as solder) disposed on the bump portion 116b, and cracks may occur in the bonding members. Therefore, an electrical open circuit problem may occur between the semiconductor device and the bump portion.

[0148] The concave surface provided on the bottom surface 104b1 of the recess 104b of the first protective layer 104 increases the surface area of ​​the bottom surface 104b1 of the recess 104b of the first protective layer 104, and thus reduces the degree of thermal deformation of the first protective layer 104 caused by thermal stress, such as the degree of expansion and / or contraction. Therefore, the concave surface provided on the upper surface of the first protective layer 104 can prevent stress caused by thermal deformation of the first protective layer 104 from acting on the bump portion 116b. For example, the concave surface can alleviate stress caused by thermal stress and prevent stress from being transmitted in the direction toward the bump portion 116b. Therefore, this embodiment allows semiconductor devices to be stably attached to a circuit board, thereby improving the mechanical and electrical reliability between the circuit board and the semiconductor device. Furthermore, this embodiment allows semiconductor devices to operate stably, thereby improving the operational reliability of electronic products (e.g., servers) using semiconductor packaging.

[0149] Furthermore, the concave surface is configured as a curved surface recessed from the upper surface of the first protective layer 104 toward its lower surface. Therefore, this embodiment can further improve the effect of the concave surface in preventing stress from acting on the bump portion. For example, when the concave surface has an angled rectangular shape, stress may concentrate at the angled portion, and mechanical or electrical reliability may be degraded as a result. Conversely, according to this embodiment, the concave surface can have a concave curved surface, thereby preventing stress concentration at specific portions of the concave surface. Therefore, this embodiment can further improve the physical and / or electrical reliability of the semiconductor package.

[0150] Furthermore, the first protective layer 104, the bump portion 116b, and the semiconductor device comprise different materials. For example, the first protective layer 104 may comprise a solder resist, the bump portion 116b may comprise a metallic material such as copper, and the semiconductor device may comprise a silicon material. In this case, the coefficients of thermal expansion of the first protective layer 104, the bump portion 116b, and the semiconductor device are different from each other. For example, the coefficient of thermal expansion of the first protective layer 104 may be greater than that of the bump portion 116b and the semiconductor device. Therefore, when the same thermal stress is applied to each of the first protective layer 104, the bump portion 116b, and the semiconductor device, the degree of thermal deformation of the first protective layer 104 may be the greatest compared to the degree of thermal deformation of the bump portion 116b and the semiconductor device. Therefore, the embodiment may allow a concave surface to be provided on the upper surface of the first protective layer 104 and may prevent stress caused by thermal deformation (such as expansion and / or contraction) from acting on the junction between the circuit board and the semiconductor device, thereby improving the mechanical and / or electrical reliability of the semiconductor package.

[0151] according to Figure 8a and 8bIn each of the embodiments (a) and (b), the circuit board may include a stacked layer 201, bump portions 202 and 206, and a protective layer 205. The protective layer 205 may include a recess 206 as described in the previous embodiments.

[0152] The bump portions 202 and 206 may include first portions 203 and 207 having a first width and being spaced apart from each other in the horizontal direction, and second portions 204 and 208 disposed on the first portions 203 and 207 and having a second width in the horizontal direction that is less than the first width.

[0153] In this embodiment, the central axis of the first portion 203 or 207 of the bump portion 202 or 206 in the horizontal direction and the central axis of the second portion 204 or 208 in the horizontal direction may be offset from each other. In this case, the circuit board may include multiple bump portions, and in each bump portion, the central axis of the first portion in the horizontal direction and the central axis of the second portion in the horizontal direction may be offset from each other, and the offset directions of the corresponding bump portions may be the same. Alternatively, in each bump portion, the central axis of the first portion in the horizontal direction and the central axis of the second portion in the horizontal direction may be offset from each other, and the offset directions of the corresponding bump portions may be different from each other. In the following, an embodiment in which the offset directions of the corresponding bump portions are different from each other will be described, but the embodiment is not limited thereto.

[0154] according to Figure 8a In one embodiment, the first bump portion 202 may include: a first portion 203 disposed on the first pad portion 220 and having a first width in the horizontal direction; and a second portion 204 disposed on the first portion 203 and having a second width in the horizontal direction that is less than the first width. Furthermore, the central axis X1 in the horizontal direction of the first portion 203 and the central axis X2 in the horizontal direction of the second portion 204 of the first bump portion 202 may be offset from each other. That is, the outer surfaces of the first portion 203 and the second portion 204 of the first bump portion 202 may have steps.

[0155] In this case, the horizontal central axis X1 of the first portion 203 of the first protrusion portion 202 may not be aligned with the horizontal central axis X2 of the second portion 204 of the first protrusion portion 202, and may be spaced apart from the central axis X2 in the horizontal direction. That is, the horizontal central axis X1 of the first portion 203 of the first protrusion portion 202 and the horizontal central axis X2 of the second portion 204 of the first protrusion portion 202 may be offset from each other. Here, when the upper surface of the first portion 203 of the first protrusion portion 202 has a circular or elliptical shape, the horizontal central axis X1 of the first portion 203 of the first protrusion portion 202 may refer to the intersection point of the major axis and the minor axis of the upper surface of the first portion 203. Alternatively, when the upper surface of the first portion 203 of the first protrusion portion 202 has a rectangular shape, the horizontal central axis X1 of the first portion 203 may refer to the intersection point of the line segments connecting two pairs of opposite vertices on the upper surface of the first portion 203 of the first protrusion portion 202. Correspondingly, the horizontal central axis X2 of the second part 204 of the first protrusion 202 can refer to the intersection point where the major axis and the minor axis intersect, or the intersection point of two line segments connecting two pairs of opposite vertices.

[0156] The horizontal central axis X1 of the first portion 203 of the first protrusion portion 202 and the horizontal central axis X2 of the second portion 204 of the first protrusion portion 202 can be offset from each other, and for example, they can have a horizontal gap W3 between them. For example, the horizontal central axis X2 of the second portion 204 of the first protrusion portion 202 can be horizontally shifted by a gap W3 relative to the horizontal central axis X1 of the first portion 144 and the second portion 145 of the first protrusion portion 202. Here, the shift can mean that the central axis X2 of the second portion 204 of the first protrusion portion 202 and the central axis X1 of the first portion 203 of the first protrusion portion 202 are not aligned in the vertical direction and are offset from each other. For example, the above shift can mean that the horizontal distance from the horizontal central axis X0 (described below) of the stack 201 to the central axis X2 of the second portion 204 of the first protrusion portion 202 is different from the horizontal distance from the horizontal central axis X0 of the stack 201 to the central axis X1 of the first portion 203 of the first protrusion portion 202. For example, the horizontal distance from the central axis X0 of the stack 201 in the horizontal direction to the central axis X2 of the second portion 204 of the first protrusion portion 202 can be less than or greater than the horizontal distance from the central axis X0 of the stack 201 in the horizontal direction to the central axis X1 of the first portion 203 of the first protrusion portion 202. Furthermore, the aforementioned displacement means that the central axis X1 of the first portion 203 of the first protrusion portion 202 in the horizontal direction and the central axis X2 of the second portion 204 of the first protrusion portion 202 are not aligned with each other and are offset from each other. In the following text, for ease of description, the terms "displacement" and / or "offset" will be used in the same sense as described above.

[0157] Warpage of the circuit board 100 in a specific direction can be mitigated by the direction and distance of displacement of the central axis X2 of the second portion 204 of the first bump portion 202 relative to the central axis X1 of the first portion 203 of the first bump portion 202. In this case, warpage of the circuit board 100 in a specific direction can occur according to the direction and distance of displacement of the central axis X2 of the second portion 204 of the first bump portion 202 relative to the central axis X1 of the first portion 203 of the first bump portion 202. Here, mitigating warpage can mean that the central axes of the first portion 203 and the second portion 204 of the first bump portion 202 are offset from each other, causing the circuit board to warp in a direction opposite to the warpage direction of the circuit board 100 before the aforementioned offset is applied.

[0158] By offsetting the central axis X2 of the second portion 204 of the first bump portion 202 relative to the central axis X1 of the first portion 203 of the first bump portion 202 based on the warping direction of the circuit board 100, warping of the circuit board 100 in a specific direction can be prevented, and excessive stress acting on the circuit board can be avoided, thereby improving the mechanical and / or electrical reliability of the circuit board. Furthermore, this embodiment can mitigate circuit board warping, thereby allowing semiconductor devices to be stably attached to the circuit board. In this case, when the circuit board warps in a specific direction, a high degree of misalignment may occur between multiple bonding portions disposed in the circuit board, and the terminals of the semiconductor devices may not be stably coupled to the multiple bonding portions. In contrast, according to the embodiment, the overall warping of the circuit board can be mitigated by offsetting the central axes X1 and X2 of the first portion 203 and the second portion 204 of the first bump portion 202, and the semiconductor devices can be stably attached to the circuit board. Therefore, this embodiment can allow the semiconductor devices to operate stably, thereby improving product reliability. Furthermore, this embodiment can allow products using semiconductor packaging (e.g., servers) to operate stably.

[0159] Furthermore, since the horizontal central axis X2 of the second part 204 of the first protrusion portion 202 is offset relative to the horizontal central axis X1 of the first part 203 of the first protrusion portion 202, the horizontal distance between the steps at the outer surfaces of the first part 203 and the second part 204 of the first protrusion portion 202 can have different horizontal distances along the circumferential direction of the upper and / or lower surfaces of the first protrusion portion 202.

[0160] In other words, based on the vertical cross-section of the first protrusion portion 202, the step between the outer surface of the first portion 203 and the outer surface of the second portion 204 on one side of the first protrusion portion 202 may have a first horizontal distance W1, and the step between the outer surface of the first portion 203 and the outer surface of the second portion 204 on the opposite side may have a second horizontal distance W2 different from the first horizontal distance W1. Furthermore, the steps provided at the outer surfaces of the first portion 203 and the second portion 204 of the first protrusion portion 202 may be non-uniform along the circumferential direction of the upper and / or lower surfaces of the first protrusion portion 202.

[0161] In this case, the first horizontal distance W1 and the second horizontal distance W2 can be determined based on the offset direction and degree between the corresponding central axes X1 and X2 of the first portion 203 and the second portion 204 of the first bump portion 202. Here, the offset direction can refer to the direction in which the central axis X2 of the second portion 204 of the first bump portion 202 is positioned relative to the central axis X1 of the first portion 203 of the joint portion 260 in the horizontal direction, and the offset degree can refer to the horizontal distance between the central axis X1 of the first portion 203 of the joint portion 260 in the horizontal direction and the central axis X2 of the second portion 204 of the first bump portion 202 in the horizontal direction. Furthermore, according to this embodiment, the central axis X2 of the second portion 204 of the first bump portion 202 in the horizontal direction can be offset relative to the central axis X1 of the first portion 203 of the joint portion 260 in the horizontal direction, thereby reducing the overall warping of the circuit board 100.

[0162] In this case Figure 8a It is explained that the horizontal central axis X2 of the second portion 204 of the first protrusion portion 202 is offset in the first horizontal direction relative to the horizontal central axis X1 of the first portion 203 of the first protrusion portion 202, and Figure 8b This indicates that the second protrusion portion is offset in a second horizontal direction opposite to the first horizontal direction.

[0163] refer to Figure 8b In (a) and (b), the second protrusion portion 206 may include a first portion 207 and a second portion 208 disposed on the first portion 207. The first portion 207 and the second portion 208 of the second protrusion portion 206 may have different widths in the horizontal direction, and furthermore, the central axis X3 of the first portion 207 in the horizontal direction and the central axis X4 of the second portion 208 in the horizontal direction may not be aligned with each other and may be spaced apart from each other in the horizontal direction. The central axis X3 of the first portion 207 in the horizontal direction and the central axis X4 of the second portion 208 in the horizontal direction of the second protrusion portion 206 may be offset from each other.

[0164] The central axis X3 of the first portion 207 of the second protrusion portion 206 in the horizontal direction and the central axis X4 of the second portion 208 of the second protrusion portion 206 in the horizontal direction can be offset from each other, and for example, they can have a horizontal gap W6 between them. For example, the central axis X4 of the second portion 208 of the second protrusion portion 206 can be offset horizontally by a gap W6 relative to the central axis X3 of the first portion 207 of the second protrusion portion 206.

[0165] The warping of the circuit board 100 in a specific direction can be mitigated by the direction and distance in which the central axis X4 of the second portion 208 of the second bump portion 206 moves or shifts relative to the central axis X3 of the first portion 207 of the second bump portion 206.

[0166] In this case, the warping of the circuit board 100 in a specific direction can occur according to the direction and distance of the offset of the central axis X4 of the second portion 208 of the second bump portion 206 relative to the central axis X3 of the first portion 207 of the second bump portion 206. Here, reducing warping can mean that the central axes of the first portion 207 and the second portion 208 of the second bump portion 206 are offset from each other, so that the circuit board warps in a direction opposite to the warping direction of the circuit board 100 before the aforementioned offset is applied.

[0167] By offsetting the central axis X4 of the second portion 208 of the second bump portion 206 relative to the central axis X3 of the first portion 207 of the second bump portion 206 based on the warping direction of the circuit board 100, warping of the circuit board 100 in a specific direction can be prevented, and excessive stress acting on the circuit board can be avoided, thereby improving the mechanical and / or electrical reliability of the circuit board. Furthermore, this embodiment can mitigate circuit board warping, allowing semiconductor devices to be stably attached to the circuit board. In this case, when the circuit board warps in a specific direction, a high degree of misalignment may occur between multiple bonding portions disposed in the circuit board, and the terminals of the semiconductor devices may not be stably coupled to the multiple bonding portions. In contrast, according to the embodiment, the overall warping of the circuit board can be mitigated by offsetting the central axes X3 and X4 of the first portion 207 and the second portion 208 of the second bump portion 206, and the semiconductor devices can be stably attached to the circuit board. Therefore, this embodiment can allow the semiconductor devices to operate stably, thereby improving product reliability. Furthermore, this embodiment can allow products using semiconductor packaging (e.g., servers) to operate stably.

[0168] Furthermore, since the horizontal central axis X4 of the second portion 208 of the second protrusion portion 206 is offset relative to the horizontal central axis X3 of the first portion 207 of the second protrusion portion 206, the horizontal distance between the steps at the outer surfaces of the first portion 207 and the second portion 208 of the second protrusion portion 206 can have different horizontal distances along the circumferential direction of the upper and / or lower surfaces of the second protrusion portion 206.

[0169] In other words, based on the vertical cross-section of the second protrusion portion 206, the step between the outer surface of the first portion 207 and the outer surface of the second portion 208 on one side of the second protrusion portion 206 may have a third horizontal distance W4, and the step between the outer surface of the first portion 207 and the outer surface of the second portion 208 on the opposite side may have a fourth horizontal distance W5 different from the third horizontal distance W4. Furthermore, the steps provided at the outer surfaces of the first portion 207 and the second portion 208 of the second protrusion portion 206 may be non-uniform along the circumferential direction of the upper and / or lower surfaces of the second protrusion portion 206.

[0170] In this case, the third horizontal distance W4 and the fourth horizontal distance W5 can be determined based on the offset direction and degree between the corresponding central axes X3 and X4 of the first portion 207 and the second portion 208 of the second bump portion 206. Here, the offset direction can refer to the direction in which the central axis X4 of the second portion 208 of the second bump portion 206 is positioned relative to the central axis X3 of the first portion 207 of the second bump portion 206 in the horizontal direction, and the offset degree can refer to the horizontal distance between the central axis X3 of the first portion 207 of the second bump portion 206 in the horizontal direction and the central axis X2 of the second portion 208 of the second bump portion 206 in the horizontal direction. Furthermore, according to this embodiment, the central axis X2 of the second portion 208 of the second bump portion 206 in the horizontal direction can be offset relative to the central axis X3 of the first portion 207 of the second bump portion 206 in the horizontal direction, thereby reducing the overall warpage of the circuit board 100.

[0171] Meanwhile, the circuit board according to the embodiment may include only the first bump portion 202, may include only the second bump portion 206, or may include both the first bump portion 202 and the second bump portion 206. Furthermore, according to the embodiment, both the first bump portion 202 and the second bump portion 206 may be provided based on the position of the corresponding engagement portion.

[0172] according to Figure 9 In some embodiments, the circuit board may include a stacked layer 301, a plurality of bump portions 302 and 306 disposed on the stacked layer 301, and a protective layer 305 including a through-hole 304a and a recess 305b. The plurality of bump portions 302 and 306 may be positioned in different directions relative to the central axis X0 in the horizontal direction of the stacked layer 301. The central axis X0 of the stacked layer 301 may refer to the point where two line segments connecting two pairs of opposite vertices of the stacked layer 301 intersect in a plan view of the stacked layer 301.

[0173] The plurality of bump portions 302 and 306 may include a first bump portion 302 positioned on one side relative to the central axis X0 of the stack 301 and a second bump portion 306 positioned on the opposite side relative to the central axis X0 of the stack 301.

[0174] The first bump portion 302 may include a first portion 303 disposed on a first pad portion of the first circuit layer 320 and a second portion 304 disposed on the first portion 303. Furthermore, the width of the first portion 303 in the horizontal direction may be greater than the width of the second portion 304 in the horizontal direction, and the central axes of the first portion 303 and the second portion 304 in the horizontal direction may be offset from each other.

[0175] The second bump portion 306 may include a first portion 307 disposed on the second pad portion of the first circuit layer 320 and a second portion 308 disposed on the first portion 307. Furthermore, the width of the first portion 307 in the horizontal direction may be greater than the width of the second portion 308 in the horizontal direction, and the central axes of the first portion 307 and the second portion 308 in the horizontal direction may be offset from each other.

[0176] In this case, the offset direction of the central axis in the horizontal direction of the first part 303 and the second part 304 of the first protrusion portion 302 may be different from the offset direction of the central axis in the horizontal direction of the first part 307 and the second part 308 of the second protrusion portion 306.

[0177] In other words, the central axis of the second portion 304 of the first bump portion 302 can be offset (offset 1) relative to the central axis of the first portion 303 in a first horizontal direction. For example, the central axis of the second portion 304 of the first bump portion 302 can be offset (offset 1) relative to the central axis of the first portion 303 in a direction away from the central axis X0 in the horizontal direction of the stack 301.

[0178] The central axis of the second portion 308 of the second protrusion portion 306 may be offset relative to the central axis of the first portion 307 in a second horizontal direction opposite to the first horizontal direction (offset 2). For example, the central axis of the second portion 308 of the second protrusion portion 306 may be offset relative to the central axis of the first portion 307 in a direction away from the central axis X0 in the horizontal direction of the stack 301 (offset 2).

[0179] In other words, the central axis of the corresponding second portions 304 and 308 of the multiple bump portions 302 and 306 in the horizontal direction can be offset relative to the central axis of the corresponding first portions 303 and 307 in the horizontal direction in the direction away from the central axis X0 in the horizontal direction of the stack 301, thereby further reducing the warping of the circuit board in a specific direction.

[0180] according to Figure 10 In one embodiment, the circuit board includes a stacked structure 710 stacked in a vertical direction. The stacked structure 710 may include a core layer 711, an upper stacked layer 712, and a lower stacked layer 713 stacked in a vertical direction. The upper stacked layer 712 may include a first protective layer, which includes through-holes and recesses as described in previous embodiments. The lower stacked layer 713 may include a second protective layer.

[0181] Additionally, the circuit board may include at least one connecting member 720 embedded in the stacked structure 710. In this case, Figure 10 The basic structure of the stacked structure 710 shown corresponds to the structure of the circuit board shown in Figure 1, and its detailed description will be omitted. The connecting member 720 can be used to electrically connect multiple semiconductor devices to each other.

[0182] Recently, with the increase in the number of signals processed by semiconductor devices, the size of semiconductor devices has tended to increase. This increase in the size of semiconductor devices can reduce their yield. Therefore, there is a trend towards dividing the pattern size or functional portions of semiconductor devices, placing the cores on a circuit board, and embedding connection members 720 with the function of electrically connecting the cores in the circuit board. However, the connection members 720 are not limited to this, and can also connect semiconductor devices to another semiconductor device with different functions, such as memory. In addition, in the stacked structure 710, embedding the connection members 720 in the upper stacked layer 712 described with reference to FIG. 1 may be advantageous in preventing signal loss. That is, the connection members 720 electrically connect multiple semiconductor devices disposed on the circuit board, and therefore, reducing the signal transmission distance while positioning the connection members 720 adjacent to multiple semiconductor devices may be advantageous in reducing signal transmission loss. Therefore, the connection members 720 may be disposed in the upper part of the upper stacked layer 712 of the circuit board. As an example, the connection member 720 according to the invention will be described as being disposed in the upper part of the upper stacked layer 712.

[0183] In this case, the upper layer 712 may include a first insulating layer 712-1 and a second insulating layer 712-2, and the first insulating layer 712-1 and the second insulating layer 712-2 may have through holes 712C, and the through holes 712C of the first insulating layer 712-1 and the second insulating layer 712-2 may form cavities.

[0184] The connecting member 720 can be disposed within the cavity, and the connecting member 720 can be embedded by the third insulating layer 712-3 of the upper laminate 712. The connecting member 720 can be disposed on the upper surface of the core layer 711 that overlaps with the cavity in the vertical direction, and the third insulating layer 712-3 of the upper laminate 712 can be configured to fill the cavity and surround the side portion of the connecting member 720 embedded in the cavity. In this case, a dummy pattern can be provided on the upper surface of the core layer 711 to allow the connecting member 720 to be stably disposed and to ensure the flatness of the connecting member 720.

[0185] Typically, only the second insulating layer 712-2 has a through-hole and the connecting member 720 is embedded in the third insulating layer 712-3, or only the first insulating layer 712-1 has a through-hole and the connecting member 720 is embedded in the second insulating layer 712-2. However, in this case, the flatness of the upper surface of the third insulating layer 712-3 may deteriorate. Furthermore, when the thickness of the connecting member 720 is greater than the thickness of the first insulating layer 712-1 and / or the thickness of the second insulating layer 712-2, the flatness of the upper surface of the third insulating layer 712-3 may deteriorate further. Therefore, it is necessary to improve the flatness of the third insulating layer 712-3 by reducing the difference between the thickness of the connecting member 720 and the depth of the cavity, thereby improving the flatness of the upper surface of the upper laminate 712.

[0186] In this case, to reduce the difference between the cavity depth and the thickness of the connecting member 720, it may be advantageous to form the cavity across the first insulating layer 712-1 and the second insulating layer 712-2. In this case, the through-hole in the second insulating layer 712-2 can be formed with a second tilt angle, which is greater than the first tilt angle of the inner wall of the through-hole forming the first insulating layer 712-1. Therefore, to improve the alignment of the connecting member 720 and prevent gaps from forming when the cavity is filled with the third insulating layer 712-3, the tilt angles of the inner walls of the through-hole forming the first insulating layer 712-1 and the inner walls of the through-hole forming the second insulating layer 712-2 can be different from each other.

[0187] Furthermore, although the inclination angle of the inner wall of the through hole forming the first insulating layer 712-1 is shown to be gentler than the inclination angle of the inner wall of the through hole forming the second insulating layer 712-2, the implementation is not limited to this, and the inclination angle of the inner wall of the through hole forming the second insulating layer 712-2 may be gentler than the inclination angle of the inner wall of the through hole forming the first insulating layer 712-1.

[0188] Furthermore, when the connecting member 720 is embedded, a metal member (not shown) can be disposed around the cavity to improve its positional alignment. This improved positional alignment, in turn, improves the positional alignment of via electrodes and circuit layers disposed in subsequent processes.

[0189] Furthermore, the via electrodes disposed in the upper stack layer 712 can have different widths depending on their positions. For example, the upper stack layer 712 may include a first via electrode 712-4 that overlaps with the connecting member 720 in the vertical direction, and a second via electrode 712-5 that overlaps with the first via electrode 712-4 in the horizontal direction but does not overlap with the connecting member 720 in the vertical direction. The first via electrode 712-4 can be directly connected to a pad portion 721 disposed on the upper surface of the connecting member 720. In this case, the width of the pad portion 721 can be smaller than the width of the circuit layer embedded in the lower surface of the first insulating layer 712-1. Therefore, the width of the first via electrode 712-4 in the horizontal direction can be smaller than the width of the second via electrode 712-5 in the horizontal direction.

[0190] Furthermore, the circuit board includes a bump portion 730 disposed on the upper layer 712. In this case, the bump portion 730 can overlap with the connecting member 720 in the vertical direction. Therefore, the recess disposed in the first protective layer can overlap with the connecting member 720 in the vertical direction.

[0191] The bump portion 730 may be disposed between the pad portion 721 of the connecting member 720 and the terminal of the semiconductor device. Therefore, this embodiment can use the first portion 731 and the second portion 732 of the bump portion 730 to increase circuit density and further provide a more stable electrical connection between the semiconductor device and the connecting member. Thus, this embodiment can allow the semiconductor device to operate stably, thereby improving the operational reliability of the semiconductor package.

[0192] according to Figure 11 In one embodiment, the circuit board may include a stacked layer 810. The stacked layer 810 may include insulating layers 811 provided as multiple layers stacked in a vertical direction, circuit layers 812 disposed on corresponding surfaces of the multiple insulating layers 811, and via electrodes 813 electrically connected in the vertical direction to the circuit layers 812 disposed in different layers. In this case, Figure 11The circuit board of FIG8 may differ from the circuit board of the previous embodiment in the structure of the stacked layer 810. That is, unlike the insulating layer of the previous embodiment, the insulating layer 811 of the circuit board of FIG8 may have a structure in which the uppermost insulating layer is stacked in only one direction, and therefore may have a structure in which the bonding portions are stacked in one direction along the vertical direction, without including the core layer. In addition, the connecting member 820 may be embedded in the stacked layer 810. In addition, the upper circuit layer of the stacked layer 810 may be embedded in the insulating layer 811. In this case, the bump portion 840 may include a first portion and a second portion as described in the previous embodiment, the first portion of the bump portion 840 may be embedded in the insulating layer 811, and the second portion of the bump portion 840 may protrude above the insulating layer 811.

[0193] Additionally, the connection portion 830 may be disposed between the first portion of the bump portion 840 and the pad portion 821.

[0194] In other words, the circuit board in Figure 1 can be a core-based substrate, and Figure 11 The circuit board can be a coreless substrate. Therefore, the pad portions of the upper circuit layer in the circuit board of Figure 1 can protrude above and below the insulating layer. Conversely, the pad portions of the upper circuit layer in the upper circuit layer can protrude above and below the insulating layer. Figure 11 The pad portion of the upper insulating layer in the circuit board can have a structure embedded in the insulating layer 811 of the stacked layer 810. For example, the circuit board can have an ETS (Embedded Trace Substrate) structure.

[0195] according to Figure 12 In one embodiment, semiconductor devices 930 and 940 may be disposed on a circuit board according to this embodiment to provide a semiconductor package.

[0196] For example, semiconductor devices 930 and 940 can be set in Figure 10 On the circuit board shown. That is, the semiconductor package may include a multilayer insulating layer 910 in which interconnecting members are embedded, and a bump portion 920 disposed on the multilayer insulating layer 910. The bump portion 920 may include a first portion 921 having a first width in the horizontal direction and a second portion 922 having a second width in the horizontal direction less than the first width and disposed on the first portion 921.

[0197] A connecting portion 940 may be disposed on the bump portion 920, and semiconductor devices 930 and 940 may be disposed on the connecting portion 940. In this case, the connecting portion 940 may be disposed on the second portion 922 of the bump portion 920, and semiconductor devices 930 and 940 may be attached to the connecting portion 940. The connecting portion 940 may be provided as a side surface surrounding the second portion 922 of the bump portion 920. For example, the connecting portion 940 may contact the side surface of the second portion 922 of the bump portion 920. In addition, the connecting portion 940 may contact the upper surface of the first portion 921 provided by the step between the first portion 921 and the second portion 922 of the bump portion 920. In this case, the step of the bump portion 920 may have different horizontal distances along the circumferential direction of the upper and / or lower surfaces of the bump portion 920, and therefore, the connecting portion 940 may be configured to have different widths along the circumferential direction of the bump portion 920 in the region that overlaps with the second portion 922 of the bump portion 920 in the horizontal direction. Furthermore, the connecting portion 940 may not contact the side surface of the first portion 921 of the bump portion 920 through the step between the first portion 921 and the second portion 922. For example, the aforementioned step can prevent the connecting portion 940 from overflowing toward the side surface of the first portion 921 of the bump portion 920, thereby allowing easy adjustment of the volume of the connecting portion 940. In addition, an intermetallic compound (IMC) can be formed when the connecting portion 940 and the bump portion 920 are in contact with each other, and the above steps can prevent the circuit layer disposed in the stacked layer 910 from contacting the connecting portion 940, thereby preventing interface separation between different components of the stacked layer 910 or degradation of electrical characteristics due to the formation of the intermetallic compound.

[0198] Alternatively, the connection portion 940 can also be disposed in a through-hole of the first protective layer disposed in the circuit board. In this case, the through-hole of the first protective layer can expose the pad portion of the circuit board, and therefore, the connection portion 940 can electrically connect the pad portion and the terminal of the semiconductor device.

[0199] Furthermore, the semiconductor package may also include an embedded insulating layer 960 for molding semiconductor devices. The embedded insulating layer 960 can embed the semiconductor devices. In this case, the embedded insulating layer 960 can be provided to fill recesses disposed in the protective layer. Therefore, the adhesion between the embedded insulating layer 960 and the circuit board can be further improved.

[0200] According to the above Figure 12 The circuit board can be used as a semiconductor packaging substrate for semiconductor packaging, and therefore can electrically connect semiconductor devices and the motherboard.

[0201] Furthermore, the aforementioned circuit board can be used as an intermediary layer between a semiconductor packaging substrate and a semiconductor device in semiconductor packaging. (Reference) Figure 13 In one embodiment, the semiconductor package may include an interposer 1000, a first bonding member 1010, a plurality of semiconductor devices 1020 and 1030, a second bonding member 1040, and a semiconductor package substrate 1050.

[0202] Interposer 1000 may include a circuit board as described with reference to the previous figures. That is, as the terminal density of semiconductor devices increases, the wiring becomes more complex, and therefore, the thickness of the circuit board increases. With increased thickness, the yield of the circuit board may decrease. Therefore, the circuit board may be divided into an interposer 1000 and a semiconductor packaging substrate 1050 for use. The aforementioned circuit board can be used as... Figure 9 The semiconductor packaging substrate in the embodiments, and in addition, can also be used as such Figure 13 Intermediate layer 1000 in the implementation method.

[0203] Semiconductor devices 1020 and 1030 are disposed on the interposer layer 1000. Multiple semiconductor devices 1020 and 1030 may be disposed on the interposer layer 1000 and spaced apart from each other in the horizontal direction, but the implementation is not limited to this. For example, semiconductor devices 1020 and 1030 may be stacked and disposed on the interposer layer 1000 not only in the horizontal direction but also in the vertical direction. Connecting members electrically connecting semiconductor devices 1020 and 1030 may be disposed in the interposer layer 1000.

[0204] The first bonding member 1010 may be disposed between the interposer 1000 and the semiconductor devices 1020 and 1030. The first bonding member 1010 may be disposed on a bonding portion disposed in the interposer 1000, and therefore, the semiconductor devices 1020 and 1030 may be attached to the interposer 1000 by a thermocompression bonding method. In this case, the semiconductor devices 1020 and 1030 include terminals 1025 and 1035, and the terminals 1025 and 1035 may be electrically connected to the bonding portion and the circuit layer of the interposer 1000 via the first bonding member 1010.

[0205] A semiconductor packaging substrate 1750 is disposed on the lower surface of the interposer layer 1000. The semiconductor packaging substrate 1000 can electrically connect the motherboard of an electronic device to the interposer layer 1700.

[0206] In this case, the second bonding member 1040 may be disposed between the interposer 1000 and the semiconductor packaging substrate 1050, and thus the interposer 1000 and the semiconductor packaging substrate 1050 may be electrically coupled to each other.

[0207] The method of manufacturing a circuit board according to the embodiments will be described below in process order.

[0208] Figures 14a to 14f This is a cross-sectional view showing the method of manufacturing a circuit board according to the embodiment, in the order of the manufacturing process.

[0209] Reference Figure 14a According to this embodiment, a core component can be prepared as the basis for manufacturing a circuit board, and the core component can be used to manufacture the core layer 1110. The core layer 1110 may include a core insulating layer and a core via electrode, and may include an insulating component penetrating the core via electrode. In addition, when manufacturing the core layer 1110, a portion of the circuit layer of the upper stack and a portion of the circuit layer of the lower stack may be manufactured together with the core via electrode.

[0210] Next, refer to Figure 14b According to the embodiment, a process can be performed to manufacture an upper stacked layer 1120 and a lower stacked layer 1130 on the upper and lower sides of the core layer 1110, respectively. In this case, an upper circuit layer can be formed on the upper surface of the upper stacked layer 1120. The upper circuit layer may include a pad portion 1121, a first portion 1122 of a bump portion, and a wiring portion 1123.

[0211] Next, refer to Figure 14c A process of laminating a dry film (not shown) onto the upper lamination 1120 can be performed. In this case, the dry film may include an opening exposing the location of the second portion 1124 to be formed of the bump portion. Subsequently, according to an embodiment, the opening of the dry film may be filled with a conductive material to form a bump portion 1125 including the first portion 1122 and the second portion 1124.

[0212] Next, refer to Figure 14d The process of forming a first protective layer 1126 on the upper stacked layer 1120 can be performed. In this case, the first protective layer 1126 can be configured to completely cover the pad portion 1121, bump portion 1125 and wiring portion 1123 of the upper stacked layer 11120.

[0213] Next, refer to Figure 14e Exposure and development processes can be performed relative to the areas where recesses will be formed in the first protective layer 1126 and the areas where vias will be formed in the first protective layer 1126. Therefore, according to the embodiment, a process can be performed to cure the remaining areas excluding the areas where recesses and vias will be formed. Subsequently, according to the embodiment, a process can be performed to reduce the thickness of the uncured areas by etching to form the recesses 1128. In this case, the thickness of the areas where vias will be formed can also be reduced to correspond to the thickness of the recesses 1128.

[0214] Next, refer to Figure 14fA process can be performed to solidify the area in which the recess 1128 is formed. Subsequently, according to this embodiment, the area in which the through-hole is to be formed can be additionally developed to form the through-hole 1129.

[0215] Furthermore, when a circuit board having the features of the present invention described above is used in IT equipment or home appliances such as smartphones, server computers, or TVs, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the features of the present invention performs a semiconductor packaging function, it can safely protect the semiconductor chip from external moisture or contaminants, and can solve problems such as leakage current, electrical short circuits between terminals, or electrical disconnection of terminals supplying power to the semiconductor chip. In addition, when the circuit board performs a signal transmission function, noise problems can be solved. Therefore, a circuit board having the features of the present invention described above allows for the maintenance of stable functionality in IT equipment or home appliances, thus enabling functional integrity and technical interoperability of the entire product and circuit board using the present invention.

[0216] When a circuit board having the features of the present invention described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, or can safely protect the semiconductor chip controlling the transportation device from external influences, and solve problems such as leakage current, electrical short circuits between terminals, or electrical disconnection of terminals supplying power to the semiconductor chip, thereby further improving the stability of the transportation device. Therefore, the transportation device and circuit board to which the present invention is applied can achieve functional integrity or technical interoperability with each other.

[0217] The features, structures, and effects described in the above embodiments are included in at least one embodiment, but are not limited to one embodiment. Furthermore, even with respect to other embodiments, those skilled in the art to which the embodiments pertain can combine or modify the features, structures, and effects shown in each embodiment. Therefore, it should be understood that content related to such combinations and modifications is included within the scope of the embodiments.

[0218] This description focuses on this embodiment, but it is merely illustrative and does not limit the scope of the embodiment. Those skilled in the art will understand that various modifications and applications not shown above are possible without departing from the essential characteristics of the embodiment. For example, each component specifically represented in the embodiment can be modified and implemented. Furthermore, it should be understood that differences associated with these changes and applications are included within the scope of the embodiment defined in the appended claims.

Claims

1. A circuit board, comprising: A multilayer insulating layer comprising an upper surface and a lower surface, a plurality of insulating layers stacked between the upper surface and the lower surface, and an upper circuit layer disposed on the upper surface; as well as A protective layer is disposed on the upper circuit layer of the multilayer insulating layer. The protective layer includes a through-hole having a first depth in the vertical direction and a recess having a second depth in the vertical direction different from the first depth. The through hole and the recess are spaced apart from each other in the horizontal direction.

2. The circuit board according to claim 1, wherein the first depth of the through hole is greater than the second depth of the recess.

3. The circuit board of claim 1, wherein the upper circuit layer comprises: A protrusion portion, wherein the protrusion portion is disposed in the recess and protrudes from the bottom surface of the recess; and The pad portion is disposed in the through hole. At least a portion of the upper surface of the pad portion overlaps with the via in the vertical direction.

4. The circuit board of claim 3, wherein the upper circuit layer further comprises wiring portions connected to at least one of the pad portions and the bump portions, and The wiring portion is covered by the protective layer.

5. The circuit board of claim 3, wherein the bottom surface of the recess includes a concave surface recessed toward the multilayer insulating layer.

6. The circuit board of claim 5, wherein the bump portion comprises a plurality of bumps spaced apart from each other in a horizontal direction, and The concave surface is disposed between the plurality of protrusions.

7. The circuit board of claim 1, wherein the sidewall of the recess includes a groove recessed outward from the recess.

8. The circuit board of claim 7, wherein the trench is located at the boundary between the bottom surface of the recess and the sidewall of the recess.

9. The circuit board of claim 8, wherein the trench is provided along the circumferential direction of the bottom surface of the recess.

10. The circuit board of claim 3, wherein the thickness of the bump portion in the vertical direction is greater than the thickness of the pad portion in the vertical direction.

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