Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device using a high-quality semiconductor film is provided. In addition, a high-performance semiconductor device is provided. A semiconductor device includes first and second transistors, first and second insulating layers, and first and second single crystal substrates. A channel of the first transistor is formed in a first single crystal semiconductor included in the first single crystal substrate. The second transistor is positioned above the first transistor and a channel thereof is formed in a second single crystal semiconductor in contact with the first single crystal substrate. The second single crystal substrate is positioned above the second transistor. The first insulating layer is positioned between the first transistor and the second transistor. The second insulating layer is positioned between the first insulating layer and the second transistor and includes a first junction surface in contact with the first insulating layer. The first single crystal semiconductor includes silicon and the second single crystal semiconductor includes a metal oxide.

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device, a storage device, a display device, and an electronic device.

[0002] Note that one aspect of the present invention is not limited to the technical fields described above. Examples of technical fields encompassing one aspect of the present invention disclosed in this specification include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, methods for driving these devices, and methods for manufacturing these devices. A semiconductor device refers to any device capable of operating by utilizing the characteristics of semiconductors. Background Technology

[0003] In recent years, semiconductor devices have been developed, with LSIs, CPUs, and memory being the main devices that utilize semiconductor devices. A CPU is an assembly of semiconductor integrated circuits (including at least transistors and memory) formed by processing semiconductor wafers to form chips, and semiconductor elements having electrodes formed as connection terminals.

[0004] Semiconductor circuits (IC chips) such as LSI, CPU, and memory are mounted on circuit boards, such as printed circuit boards, and are used as components of various electronic devices.

[0005] Furthermore, the technique of constructing transistors using semiconductor thin films formed on substrates with insulating surfaces has attracted considerable attention. These transistors are widely used in electronic devices such as integrated circuits and image display devices (simply referred to as display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors. Among other materials, oxide semiconductors have also garnered attention.

[0006] It is known that the leakage current of transistors using oxide semiconductors is extremely small in the non-conducting state. For example, Patent Document 1 discloses a low-power CPU that utilizes the characteristic of low leakage current of transistors using oxide semiconductors. Furthermore, Patent Document 2 discloses a storage device that uses oxide semiconductors to achieve long-term retention of stored content.

[0007] In addition, Non-Patent Document 1 reports a polycrystalline indium oxide film with high Hall mobility and a transistor using the same.

[0008] [Preliminary Technology Documents]

[0009] [Patent Literature]

[0010] [Patent Document 1] Japanese Patent Application Publication No. 2012-257187

[0011] [Patent Document 2] Japanese Patent Application Publication No. 2011-151383

[0012] [Non-patent literature]

[0013] [Non-Patent Literature 1] Y. Magari et al., “High-mobility hydrogenated polycrystalline In2O3 (In2O3:H) thin-film transistors”, Nature Communications 13, 1078, (2022). Summary of the Invention

[0014] The technical problem that the invention aims to solve

[0015] One objective of this invention is to provide a semiconductor device using a high-quality semiconductor film. Another objective of this invention is to provide a semiconductor device using a single-crystal oxide semiconductor film. Another objective of this invention is to provide a high-performance semiconductor device. Another objective of this invention is to provide a semiconductor device with good electrical characteristics. Another objective of this invention is to provide a highly reliable semiconductor device. Another objective of this invention is to provide a semiconductor device that is easily implemented with high integration. Another objective of this invention is to provide a low-power semiconductor device.

[0016] One objective of this invention is to provide a semiconductor device with a novel structure. Another objective of this invention is to at least mitigate at least one of the problems of prior art.

[0017] Note that the description of these objectives does not preclude the existence of other objectives. Note that one embodiment of the invention does not necessarily require achieving all of the above objectives. Furthermore, objectives other than those described above can be extracted from the description in the specification, drawings, claims, etc.

[0018] means of solving technical problems

[0019] One aspect of the present invention is a semiconductor device comprising a first transistor, a second transistor, a first insulating layer, a second insulating layer, a first single-crystal substrate, and a second single-crystal substrate. The channel of the first transistor is formed in the first single-crystal semiconductor included in the first single-crystal substrate. The second transistor is located above the first transistor, and its channel is formed in the second single-crystal semiconductor in contact with the second single-crystal substrate. The second single-crystal substrate is located above the second transistor. The first insulating layer is located between the first transistor and the second transistor. The second insulating layer is located between the first insulating layer and the second transistor and includes a first bonding surface in contact with the first insulating layer. The first single-crystal semiconductor comprises silicon. Furthermore, the second single-crystal semiconductor comprises a metal oxide.

[0020] Furthermore, in the above structure, it is preferable that the second single-crystal substrate has a cubic crystal structure, and the second single-crystal semiconductor has a cubic crystal structure.

[0021] In addition, in the above structure, it is preferred that the second single crystal substrate includes an oxide containing yttrium and zirconium, and the second single crystal semiconductor includes indium oxide.

[0022] Furthermore, in the above structure, it is preferable that the lattice mismatch of the second single-crystal semiconductor relative to the second single-crystal substrate is -5% or more and 5% or less.

[0023] Furthermore, in the above structure, it is preferable to further include a first conductive layer and a second conductive layer. In this case, the first conductive layer is connected to one of the source electrode and drain electrode of the first transistor and is embedded in the first insulating layer. Additionally, the second conductive layer is connected to one of the source electrode and drain electrode of the second transistor, is embedded in the second insulating layer, and includes a second bonding surface that contacts the first conductive layer.

[0024] Another aspect of the present invention is a method for manufacturing a semiconductor device, comprising the following steps: preparing a first single-crystal substrate having a first transistor and a first insulating layer on the first transistor and including a first single-crystal semiconductor; preparing a second single-crystal substrate; forming a semiconductor film including a second single-crystal semiconductor on the second single-crystal substrate; processing the semiconductor film into an island shape to form a semiconductor layer; forming a gate insulating layer, a gate electrode, a source electrode, and a drain electrode on the semiconductor layer to manufacture a second transistor; forming a second insulating layer on the second transistor; and bonding the top surface of the first insulating layer and the top surface of the second insulating layer.

[0025] Furthermore, in the above manufacturing method, it is preferred that the first single-crystal semiconductor comprises silicon, and the second single-crystal semiconductor comprises metal oxide.

[0026] Furthermore, in the above manufacturing method, it is preferable that the second single-crystal substrate has a cubic crystal structure, and the second single-crystal semiconductor has a cubic crystal structure.

[0027] In addition, in the above manufacturing method, it is preferred that the second single crystal substrate includes an oxide containing yttrium and zirconium, and the second single crystal semiconductor includes indium oxide.

[0028] Furthermore, in the above manufacturing method, it is preferable that the lattice mismatch of the second single-crystal semiconductor relative to the second single-crystal substrate is -5% or more and 5% or less.

[0029] Invention Effects

[0030] According to one aspect of the present invention, a semiconductor device using a high-quality semiconductor film can be provided. Additionally, according to one aspect of the present invention, a semiconductor device using a single-crystal oxide semiconductor film can be provided. Furthermore, according to one aspect of the present invention, a high-performance semiconductor device can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with good electrical characteristics can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with high reliability can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device that is easy to implement with high integration can be provided. Furthermore, according to one aspect of the present invention, a low-power semiconductor device can be provided.

[0031] According to one aspect of the present invention, a semiconductor device having a novel structure can be provided. According to one aspect of the present invention, at least one of the problems of the prior art can be mitigated.

[0032] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the invention does not necessarily require all of the aforementioned effects. Furthermore, effects other than those described above can be extracted from the description in the specification, drawings, claims, etc. Attached Figure Description

[0033] Figures 1A to 1I This is a diagram illustrating the manufacturing process of a semiconductor device.

[0034] Figures 2A to 2D This is a diagram illustrating the manufacturing process of a semiconductor device.

[0035] Figure 3A and Figure 3B This is a schematic diagram illustrating the area near the mating surface.

[0036] Figure 4A and Figure 4B This is a schematic diagram illustrating the area near the mating surface.

[0037] Figures 5A to 5E This is a diagram illustrating the manufacturing process of a semiconductor device.

[0038] Figures 6A to 6D This is an example of the structure of a semiconductor device.

[0039] Figure 7 This is an example of the structure of a semiconductor device.

[0040] Figure 8 This is an example of the structure of a semiconductor device.

[0041] Figures 9A to 9D This is an example of the structure of a semiconductor device.

[0042] Figures 10A to 10D This is an example of the structure of a semiconductor device.

[0043] Figures 11A1 to 11D2 This is a diagram illustrating the manufacturing process of a semiconductor device.

[0044] Figures 12A1 to 12C2 This is a diagram illustrating the manufacturing process of a semiconductor device.

[0045] Figure 13 This is an example of the structure of a storage device.

[0046] Figure 14A and Figure 14B This is an example of the structure of a storage device.

[0047] Figures 15A to 15D This is an example of the structure of a storage device.

[0048] Figure 16 This is an example of the structure of a storage device.

[0049] Figure 17A and Figure 17B This is an example of the structure of a display device.

[0050] Figure 18 This is an example of the structure of a display device.

[0051] Figures 19A to 19C This is an example of the structure of a display device.

[0052] Figure 20A and Figure 20B This is an example of the structure of a display device.

[0053] Figures 21A to 21D This is an example of the structure of an electronic device.

[0054] Figures 22A to 22F This is an example of the structure of an electronic device.

[0055] Figures 23A to 23G This is an example of the structure of an electronic device.

[0056] Figure 24A and Figure 24B This is a structural example of an electronic component.

[0057] Figures 25A to 25CThis is an example of the architecture of a mainframe computer.

[0058] Figure 26A and Figure 26B This is a cross-sectional image according to an embodiment.

[0059] Figure 27A and Figure 27B This is a cross-sectional image according to an embodiment. Detailed Implementation

[0060] The embodiments will now be described with reference to the accompanying drawings. However, those skilled in the art will readily understand that the embodiments can be implemented in many different forms, and their manner and details can be varied in various ways without departing from the spirit and scope of the invention. Therefore, the invention should not be construed as being limited to the contents described in the embodiments shown below.

[0061] Note that in the structure of the invention described below, the same symbols are used in different figures to represent the same parts or parts with the same function, and repeated descriptions are omitted. Furthermore, when representing parts with the same function, the same shading lines are sometimes used without additional symbols.

[0062] Note that in the various figures described in this specification, the size of the constituent elements, the thickness of the layers, and the area are sometimes exaggerated for clarity. Therefore, the present invention is not limited to the dimensions shown in the figures.

[0063] The ordinal numbers such as "first" and "second" used in this specification are appended to avoid confusion of the constituent elements, and are not intended to limit the quantity.

[0064] A transistor is a type of semiconductor device that can amplify current or voltage, control switching operations (turning on or off), etc. The transistors discussed in this specification include IGFETs (Insulated Gate Field Effect Transistors) and thin-film transistors (TFTs).

[0065] Furthermore, in cases where transistors with different polarities are used or the direction of current changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification, the "source" and "drain" can be used interchangeably.

[0066] Furthermore, in this specification, "electrical connection" includes connections made via "elements that have a certain electrical function." Here, "elements that have a certain electrical function" are not particularly limited as long as they can transmit and receive electrical signals between the connected objects. For example, "elements that have a certain electrical function" include, in addition to electrodes or wiring, switching elements such as transistors, resistors, coils, capacitors, and other elements with various functions.

[0067] Note that in this specification, the connection between two nodes via insulators such as the dielectric of a capacitor, the gate insulating film of a transistor, or the interlayer insulating film is not included in the "electrical connection" section.

[0068] Note that in this specification, etc., "generally consistent top surface shape" means that at least a portion of the edges of each layer in the stack overlaps. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion thereof. However, strictly speaking, there are cases where the edges do not overlap, such as when the upper layer is inside or outside the lower layer; in these cases, it can sometimes be said that the "generally consistent top surface shape" also applies.

[0069] Note that in this specification, the top surface shape of a constituent element refers to the outline shape of the constituent element when viewed from a plane. Furthermore, "viewed from a plane" means the view taken from the normal direction of the surface on which the constituent element is formed or the surface of the support (e.g., a substrate) on which the constituent element is formed.

[0070] Note that the directions such as "up" and "down" will be used in accordance with the directions in the accompanying drawings in the following description. However, for the sake of simplicity, the directions indicated by "up" or "down" in the specification may sometimes be inconsistent with those in the accompanying drawings. For example, when describing the stacking sequence (or formation sequence) of laminates, etc., even if the surface on the side where the laminate is located (the surface to be formed, the supporting surface, the adhesive surface, the flat surface, etc.) is located on the upper side of the laminate in the accompanying drawings, there may be cases where the surface to be formed is shown as down and the laminate side is shown as up.

[0071] Furthermore, in this specification and other materials, the terms "film" and "layer" may be interchanged. For example, sometimes "insulating layer" and "insulating film" may be interchanged.

[0072] Furthermore, unless otherwise specified in this specification, the off-state current refers to the drain current when the transistor is in the off state (also known as the non-conducting state or the blocked state). Unless otherwise specified, in an n-channel transistor, the off state refers to the state where the voltage Vgs between the gate and source is lower than the threshold voltage Vth (in a p-channel transistor, Vgs is higher than Vth).

[0073] (Implementation Method 1)

[0074] In this embodiment, a semiconductor device and a method for manufacturing the same according to one aspect of the present invention are described.

[0075] One embodiment of the present invention has the following structure: a first transistor having a channel formed in a portion of a first single-crystal substrate and a second transistor having a channel formed in a single-crystal semiconductor film above it. Preferably, a metal oxide is used as the semiconductor film included in the second transistor.

[0076] Preferably, the semiconductor film with a single-crystal structure for the second transistor is formed by epitaxy using a second single-crystal substrate different from the first single-crystal substrate described above. When the crystal structure of the second single-crystal substrate and the crystal structure of the semiconductor film are in the same crystal system, the lattice mismatch between them is small, thus a semiconductor film with good crystallinity can be obtained. Note that this is not a limitation, even if epitaxial growth can be performed when the crystal structures of the two are different.

[0077] As the metal oxide used for semiconductor films, oxides containing indium, zinc, tin, etc., are preferred. Metal oxides that are easily crystallizable are particularly preferred. For example, indium oxide is easily crystallizable at low temperatures, thereby obtaining a single-crystal film with good crystallinity, and is therefore preferred. Furthermore, single-crystal or polycrystalline indium oxide exhibits extremely high reliability, and is therefore preferred. In particular, single-crystal indium oxide films are preferred. For example, sometimes impurities such as hydrogen are concentrated at the grain boundaries of polycrystalline films. Sometimes, these hydrogens generate charge carriers in the semiconductor film, increasing the charge carrier concentration in the semiconductor film, which leads to variations in the threshold voltage of the transistor. Therefore, by using a single-crystal indium oxide film as the semiconductor film, transistors with very good electrical characteristics can be realized.

[0078] For example, when a cubic oxide film such as indium oxide is used as the semiconductor film, it is preferable to use the same cubic single-crystal substrate as the second single-crystal substrate. For example, cubic single-crystal substrates such as YSZ (yttrium-stabilized zirconium oxide), zirconium oxide, and silicon are preferred. Alternatively, a tetragonal single-crystal substrate can be used to form a semiconductor film with a cubic single-crystal structure. Furthermore, the material and crystal structure of the second single-crystal substrate can be appropriately selected according to the crystal structure of the desired semiconductor film. For example, single-crystal substrates such as silicon carbide, gallium nitride, and gallium oxide can also be used. Even when the crystal structure of the second single-crystal substrate differs from the crystal structure of the desired semiconductor film, epitaxial growth can sometimes be achieved by providing a buffer layer to mitigate the strain between them.

[0079] Furthermore, the smaller the lattice mismatch between the second single-crystal substrate and the semiconductor film, the better. Here, the lattice mismatch is equivalent to the difference between the length of the unit lattice vector of the substrate and the length of the unit lattice vector of the thin film during epitaxial growth on the substrate, divided by the length of the unit lattice vector of the substrate. Alternatively, a lattice constant can be used instead of the unit lattice vector. For example, when the substrate and the thin film have the same crystal structure, the difference between the two lattice constants divided by the lattice constant of the substrate can be used as the lattice mismatch. The smaller the lattice mismatch between the second single-crystal substrate and the semiconductor film, the better; for example, preferably -5% or more and 5% or less, more preferably -4% or more and 4% or less, further preferably -3% or more and 3% or less, and even more preferably -2% or more and 2% or less. Here, the lattice mismatch is positive when the unit lattice vector of the thin film is greater than that of the substrate, and negative when the unit lattice vector of the thin film is less than that of the substrate. Furthermore, when setting the aforementioned buffer layer, by forming a thick buffer layer, epitaxial growth can sometimes be performed even when using combinations with large lattice mismatches. In this case, the lattice mismatch can be less than -5% or greater than 5%. For example, the lattice mismatch between the second single-crystal substrate and the semiconductor film can also be greater than -20% and less than 20%, greater than -15% and less than 15%, or greater than -10% and less than 10%.

[0080] A semiconductor substrate can be used as the first single-crystal substrate. Typically, a single-crystal silicon substrate is preferred. Alternatively, a semiconductor substrate composed of a single element, a compound semiconductor substrate, or an insulating substrate on which a single-crystal semiconductor thin film is formed can also be used. A first transistor, whose channel is formed in a portion of the first single-crystal substrate, can be disposed in the first single-crystal substrate. Furthermore, a first insulating layer having a bonding surface with a second single-crystal substrate is disposed on the first transistor.

[0081] A single-crystal semiconductor film is formed on a second single-crystal substrate, and then the semiconductor film is processed into an island shape. By forming a gate insulating layer, a gate electrode, a source electrode, and a drain electrode on the island-shaped semiconductor film (hereinafter also referred to as the semiconductor layer), a transistor whose channel is formed in the single-crystal semiconductor can be fabricated on the second single-crystal substrate. Then, a second insulating layer having a bonding surface with the first single-crystal substrate is formed on the transistor.

[0082] Next, the first single-crystal substrate and the second single-crystal substrate are bonded together. At this time, bonding is performed with the surface of the first insulating layer in contact with the surface of the second insulating layer. Using the same material for both the first and second insulating layers improves the bonding strength, which is preferred. Furthermore, the flatter the surfaces of the first and second insulating layers, the better; therefore, pre-planarization is preferable. After bonding, both the second insulating layer side of the first insulating layer and the first insulating layer side of the second insulating layer become bonding surfaces.

[0083] Through the above-described process, a semiconductor device can be manufactured comprising a first transistor with a channel formed in a portion of a first single-crystal substrate and a second transistor with a channel formed in a single-crystal semiconductor film. At this time, the stacked structure including the first transistor and the stacked structure including the second transistor are reversed vertically, with the aforementioned bonding surface as the boundary.

[0084] After bonding the first and second single-crystal substrates together, the second single-crystal substrate can be removed, or thinning can be achieved through grinding the second single-crystal substrate (also known as back-side grinding). Furthermore, functional elements such as light-emitting elements, light-receiving elements, sensor elements, and transistors can be fabricated on the back side of the second single-crystal substrate (the side opposite to the second transistor). In this case, the functional element can be connected to the second transistor via a connector provided in the second single-crystal substrate. Thus, high-performance semiconductor devices can be manufactured. For example, when a display element is used as a functional element, circuitry and the display element can be stacked, thereby realizing a display device with a small chip area, extremely high resolution, and high display quality.

[0085] The following are more specific examples, with reference to the accompanying drawings.

[0086] [Example 1 of a semiconductor device manufacturing method]

[0087] The following describes an example of a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 1A to 2D Cross-sectional schematic diagrams are shown for each step of the manufacturing method illustrated below.

[0088] First, prepare substrate 11 ( Figure 1A The substrate 11 can be a single-crystal substrate. For example, single-crystal substrates of YSZ, zirconium oxide, silicon, silicon carbide, gallium nitride, gallium oxide, etc., can be used. Furthermore, rare-earth oxides such as yttrium oxide, erbium oxide, gadolinium oxide, and ytterbium oxide, as well as oxides of lanthanides, can also be used. In particular, when indium oxide is used in the semiconductor film 21f, yttrium oxide or erbium oxide is preferred. As the substrate 11, a material with a small lattice mismatch with the subsequently formed semiconductor film 21f can be used. Furthermore, when the substrate 11 is removed later, it is not limited to an insulating substrate; conductive substrates and semiconductor substrates can also be used.

[0089] Next, a semiconductor film 21f is formed on the substrate 11. Figure 1B Metal oxides can be used as the semiconductor film 21f. In particular, oxide films with indium, tin, or zinc as the main components are preferred. Among them, single-crystal indium oxide is particularly preferred because it has high mobility and high reliability.

[0090] Semiconductor films 21f can be formed using methods such as atomic layer deposition (ALD), sputtering, chemical vapor deposition (CVD), pulsed laser deposition (PLD), molecular beam epitaxy (MBE), and wet deposition.

[0091] Semiconductor film 21f is preferably deposited while the substrate 11 is heated. This results in a single-crystal film with fewer defects. Furthermore, a higher heating temperature of the substrate 11 leads to a cleaner surface and reduced lattice defects, which is preferred. On the other hand, if the temperature of the substrate 11 during deposition is too high, oxygen may escape from the film, preventing the formation of the desired film composition. Therefore, the temperature of the substrate 11 during semiconductor film 21f deposition can be set to above room temperature and below 1200 degrees Celsius, preferably above 100 degrees Celsius and below 600 degrees Celsius. Alternatively, the substrate 11 can be preheated at a high temperature (above 1000 degrees Celsius) in the deposition apparatus, and then the surface temperature of the substrate 11 can be lowered to below 600 degrees Celsius without exposure to the atmosphere to deposit semiconductor film 21f.

[0092] Indium oxide (IO) is particularly preferred as the semiconductor film 21f. Increasing the ratio of the number of indium atoms in the metal oxide to the sum of the atomic numbers of all metal elements improves the field-effect mobility of the transistor. Furthermore, by using IO with a single-crystal structure in the channel formation region of the transistor, a transistor with extremely high reliability can be achieved. Additionally, IO has a bandgap of 2.5 eV or more and 3.7 eV or less. Using IO with a large bandgap in the channel formation region of the transistor reduces the off-state current of the transistor, thereby significantly reducing the power consumption of the semiconductor device.

[0093] When using a film with a cubic crystal structure, such as indium oxide, as the semiconductor film 21f, a substrate with a cubic crystal structure is preferably used as the substrate 11. This allows for epitaxial growth of the semiconductor film 21f, thereby improving the crystallinity of the semiconductor film 21f. For example, cubic zirconium oxide or yttrium-stabilized zirconium oxide (YSZ) can be used as the substrate 11. Note that when the semiconductor film 21f and the substrate 11 have the same crystal structure, there are no particular restrictions on the crystal orientation of the surface of the substrate 11. For example, the crystal orientation of the surface of the substrate 11 can be

[100] ,

[110] , or

[111] . Note that when a YSZ substrate is used as the substrate 11 and an indium oxide film is used as the semiconductor film 21f, from the viewpoint of lattice mismatch, which will be explained later, a YSZ substrate with a surface crystal orientation of

[100] or

[111] is particularly preferred as the substrate 11. Alternatively, a substrate whose surface is tilted from a specific crystal plane, i.e., a substrate with a tilt angle of 0° or more, can also be used as the substrate 11.

[0094] Furthermore, the lattice mismatch between the semiconductor film 21f and the substrate 11 is preferably small. By selecting a material for the substrate 11 with a small lattice mismatch, the crystallinity of the semiconductor film 21f can be improved.

[0095] One method for evaluating the degree of lattice mismatch is to use the lattice mismatch value shown below. The lattice mismatch Δa[%] of the crystal contained in the formed film (e.g., semiconductor film 21f) relative to the crystal contained in the formed film (e.g., substrate 11) can be calculated as Δa = ((L1-L2) / L2) × 100. Here, L1 is the length of the unit lattice vector or lattice constant of the crystal contained in the formed film, and L2 is the length of the unit lattice vector or lattice constant of the crystal contained in the formed film.

[0096] The smaller the absolute value of the lattice mismatch Δa between the substrate 11 and the semiconductor film 21f, the better, and most preferably 0. For example, Δa is preferably -5% or more and less than 5%, more preferably -4% or more and less than 4%, further preferably -3% or more and less than 3%, and even more preferably -2% or more and less than 2%. The smaller the lattice mismatch Δa, the greater the distortion of the semiconductor film 21f, and the larger the critical thickness relative to the mismatch dislocation. Therefore, even if the semiconductor film 21f is relatively thick, a film with high crystallinity can be achieved.

[0097] For example, the lattice constant of indium oxide with a cubic crystal structure (argentite type) is 1.0117 nm (refer to ICSD (Inorganic Crystal Structure Database) coll.code.14387). On the other hand, the lattice constant of YSZ (ZrO2) with a cubic crystal structure (fluorite type) is...0.9 Y 0.1 O 1.95 The lattice constant of YSZ is 0.51481 nm (refer to ICSDcoll.code.248790). Therefore, the lattice mismatch between the grains contained in the indium oxide film and the grains contained in YSZ is -1.74%. Here, since the lattice constant of YSZ varies with the yttrium content, by setting the yttrium content contained in YSZ to 2 atomic% or more and 15 atomic% or less, preferably 5 atomic% or more and 10 atomic% or less, the lattice mismatch between YSZ and indium oxide can be reduced, thereby forming a single-crystal indium oxide film with fewer defects.

[0098] Note that the crystal structure of the substrate 11 and the crystal structure of the semiconductor film 21f may sometimes have different crystal orientations. For example, a film containing a hexagonal or trigonal crystal structure may be used under indium oxide containing a cubic crystal structure. For example, by setting the crystal orientation of the surface of the substrate 11 to

[001] and the crystal orientation of the bottom surface of the semiconductor film 21f to

[111] , the crystal orientation conditions required for epitaxial growth can be met. Examples of hexagonal or trigonal crystals include wurtzite-type structures, YbFe2O4-type structures, Yb2Fe3O7-type structures, and their variants.

[0099] Note that the semiconductor film 21f is not limited to indium oxide; metal oxide films with indium, tin, or zinc as the main components can be used. Here, "main component" refers to the component whose target atom accounts for more than 0.1% of the total number of atoms of the metal elements constituting the metal oxide. Sometimes, elements with a ratio less than 0.1% are referred to as impurities.

[0100] Figure 3A and Figure 3B A cross section near the interface between substrate 11 and semiconductor film 21f is schematically shown. Figure 3A This corresponds to the case where the lattice constant of the crystal in semiconductor film 21f is smaller than that of the crystal in substrate 11, i.e., Δa < 0. Figure 3B This is equivalent to the case where Δa > 0.

[0101] In substrate 11, element 15s is periodically arranged, and in semiconductor film 21f formed on substrate 11, element 15f is periodically arranged. Due to the difference in lattice constants between substrate 11 and semiconductor film 21f, the lattice of semiconductor film 21f near substrate 11 is deformed, maintaining the continuity of the lattice at the interface. The thicker the region of lattice deformation in semiconductor film 21f, the easier it is to mitigate distortion and the less likely dislocations will occur. The thickness of this region is sometimes one atomic layer in thinner cases, and sometimes several μm in thicker cases.

[0102] At this time, the lattice of the semiconductor film 21f deforms in a manner that expands or contracts in the in-plane direction, while sometimes it hardly deforms in the film thickness direction. For example, in the general relationship between stress and distortion, when an external force is applied to an object and it extends in a certain direction, it generally contracts in a direction orthogonal to that extension direction (the opposite is true when it contracts due to an external force), but the semiconductor film 21f sometimes exhibits a different tendency.

[0103] Figure 4A and Figure 4B An example is shown where an intermediate layer 16 exists between the substrate 11 and the semiconductor film 21f. The intermediate layer 16 serves as a buffer layer to mitigate stress caused by lattice mismatch between the substrate 11 and the semiconductor film 21f. When the intermediate layer 16 is present, the distortion generated in the semiconductor film 21f is mitigated, thus allowing the semiconductor film 21f to be formed as a film with few defects such as dislocations and good crystallinity. Due to the presence of sites where atoms are absent, the intermediate layer 16 is sometimes a low-density region. Furthermore, the element 15m located in the intermediate layer 16 may contain elements constituting the semiconductor film 21f, as well as elements constituting the substrate 11. In this case, the intermediate layer 16 can also be referred to as a mixed layer.

[0104] For example, the intermediate layer 16 can be identified in a cross-sectional image near the interface between the substrate 11 and the semiconductor film 21f, observed using high-angle annular dark field scanning transmission electron microscopy (HAADF-STEM). The intermediate layer 16 may be observed as a layer with lower contrast than other areas. The thickness of the intermediate layer 16 varies depending on the crystal orientation of the substrate 11, sometimes consisting of one, two, or more atomic layers.

[0105] Next, a conductive film 24f is formed on the semiconductor film 21f. Figure 1C As the conductive film 24f, conductive materials that do not readily diffuse oxygen, such as titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide, can be used. This suppresses the decrease in conductivity caused by oxidation due to oxygen contained in the semiconductor film 21f, etc. The conductive film 24f can be deposited using methods such as sputtering, ALD, and CVD.

[0106] Next, a photoresist mask is formed on the conductive film 24f, and unwanted portions of the conductive film 24f and the semiconductor film 21f are removed by etching to form island-shaped conductive layer 24 and semiconductor layer 21. Figure 1D Then, the resist mask is removed. Dry etching or wet etching can be used for etching, but dry etching is preferred because it facilitates fine machining.

[0107] Next, an insulating layer 32 serving as a barrier film and an insulating layer 33a serving as an interlayer insulating film are sequentially formed in such a manner that the conductive layer 24 and the semiconductor layer 21 are covered. Figure 1E Insulating layer 32 and insulating layer 33a can be formed by sputtering, ALD, CVD, etc.

[0108] As the insulating layer 32, insulating materials such as silicon nitride, aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate) are preferably used. They are barrier to oxygen, hydrogen, and water, thus preventing these impurities from diffusing into the semiconductor layer 21.

[0109] Silicon oxide, silicon oxynitride, silicon oxynitride, or other insulating materials are preferably used as the insulating layer 33a. By using a material with a low dielectric constant as the insulating layer 33a, parasitic capacitance can be reduced.

[0110] Note that in this specification, etc., oxynitrides refer to materials in which the content of oxygen atoms is greater than the content of nitrogen atoms in their composition. Nitrogen oxides refer to materials in which the content of nitrogen atoms is greater than the content of oxygen atoms in their composition. For example, when described as "silicon oxynitride," it refers to a material in which the content of oxygen atoms is greater than the content of nitrogen atoms in its composition, while when described as "silicon oxynitride," it refers to a material in which the content of nitrogen atoms is greater than the content of oxygen atoms in its composition.

[0111] Next, by etching away a portion of insulating layer 33a, insulating layer 32, and conductive layer 24, a trench is formed that reaches semiconductor layer 21 and substrate 11. Figure 1F At this point, the conductive layer 24 is divided into two parts by the groove. Then, an insulating film 22f is formed along the groove. Figure 1G Next, a conductive film that will become the conductive layer 23 is formed on the insulating film 22f by filling the trench. Then, planarization is performed using CMP until the insulating layer 33a is exposed, thereby forming the insulating layer 22 and the conductive layer 23 within the trench. Figure 1H Insulating layer 22 is used as the gate insulating layer, and conductive layer 23 is used as the gate electrode. Additionally, a pair of conductive layers 24 separated on semiconductor layer 21 are used as the source electrode and drain electrode, respectively. The transistor 10 can be manufactured through the above process.

[0112] As the insulating layer 22, a single layer or stack of insulating materials such as silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, and hafnium aluminate can be used. The insulating layer 22 can be formed by deposition methods such as sputtering, CVD, and ALD, but the ALD method, which has high step coverage, can form a uniform thickness even inside the tank, so it is preferred from the viewpoint of pressure resistance.

[0113] As the conductive layer 23, low-resistance conductive materials such as tungsten, molybdenum, copper, and aluminum are preferably used. Furthermore, it is preferable that the conductive layer 23 has a stacked structure, with a film of a conductive material that does not readily diffuse oxygen, which can be used in the conductive layer 24, provided on the side in contact with the insulating layer 22. This prevents the conductivity of the conductive layer 23 from decreasing due to oxidation caused by oxygen diffusing from the insulating layer 22, etc.

[0114] Next, an insulating layer 33b is formed to cover the transistor 10 and the insulating layer 33a. The insulating layer 33b serves as an interlayer insulating film and can be formed using the same method as the insulating layer 33a. Then, openings leading to the conductive layer 24 are formed in the insulating layers 33b, 33a, and 32. Next, a conductive film is formed to fill these openings, and then planarized using CMP (Continuous Metallurgy Processing) until the insulating layer 33b is exposed, forming a plug 61c that connects to the conductive layer 24. This conductive film is preferably formed using CVD (Continuous Chemical Deposition) method.

[0115] Next, a conductive film is formed, and the unwanted portions of the conductive film are removed by etching to form the conductive layer 71c. Figure 1I The conductive layer 71c is connected to the conductive layer 24 via the plug 61c.

[0116] Next, insulating layer 33c is formed to cover insulating layer 33b and conductive layer 71c. Then, an opening is formed in insulating layer 33c to reach conductive layer 71c, and plug 61d is formed in the opening. Next, conductive layer 71d is formed on insulating layer 33c. Then, insulating film is formed to cover insulating layer 33c and conductive layer 71d, and planarization is performed until the top surface of conductive layer 71d is exposed, thereby forming insulating layer 33d. Figure 2A Thus, a structure can be achieved in which the conductive layer 71d is embedded in the insulating layer 33d and their top surfaces are planarized and highly uniform.

[0117] The above steps complete the process on one side of substrate 10.

[0118] Next, a substrate 51 with transistor 50 is prepared ( Figure 2B ).

[0119] The substrate 51 is a single-crystal semiconductor substrate on which a transistor 50 is disposed. The transistor 50 includes a semiconductor region 51c formed in a portion of the substrate 51. The substrate 51 can typically be single-crystal silicon. Alternatively, semiconductors composed of a single element such as germanium, or compound semiconductors composed of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, gallium nitride, etc., can be used. Furthermore, semiconductor substrates having an insulating region within the aforementioned semiconductor substrates, such as SOI (Silicon On Insulator) substrates, can also be used. Alternatively, substrates with a thin-film semiconductor film disposed on an insulating substrate such as a glass substrate, quartz substrate, sapphire substrate, YSZ substrate, or resin substrate can also be used.

[0120] Transistor 50 is disposed on substrate 51 and includes a conductive layer 53 serving as a gate, an insulating layer 52 serving as a gate insulating layer, a semiconductor region 51c formed by a portion of substrate 51, and a pair of low-resistance regions 54 serving as source and drain regions. The channel of transistor 50 is formed in the single-crystal semiconductor of substrate 51. Transistor 50 can be p-channel or n-channel. A device separation layer 81 is disposed in substrate 51 between two adjacent transistors 50.

[0121] In transistor 50, the semiconductor region 51c forming the channel has a convex shape (fin shape). Additionally, although in Figure 2B Not shown in the figure, but a conductive layer 53 is provided in the depth direction, covering the sides and top surface of the semiconductor region 51c through an insulating layer 52. This transistor 50 is also called a FIN-type transistor.

[0122] An insulating layer 82 is provided to cover a portion of the transistor 50, and insulating layers 83a to 83d are sequentially provided on the insulating layer 82. A conductive layer 71a is embedded in the insulating layer 83b and is connected to the low-resistance region 54 via a connector 61a that penetrates the insulating layers 83a and 82. Furthermore, the conductive layer 71b is embedded in the insulating layer 83d and is connected to the conductive layer 71a via a connector 61b that penetrates the insulating layer 83c.

[0123] The top surface of the insulating layer 83d becomes the bonding surface, so it is preferably planarized using the CMP method. This allows for a structure where the top surfaces of both the insulating layer 83d and the conductive layer 71b are planarized and have a uniform height.

[0124] Next, substrate 51 is bonded to substrate 11. Figure 2C ).

[0125] The substrates 51 and 11 are bonded by overlapping the insulating layers 33d and 83d with the insulating layers facing each other. At this time, it is important to adjust the position so that the conductive layers 71d and 71b are in contact.

[0126] Insulating layers 33d and 83d are preferably a combination capable of being bonded. In particular, they are preferably made of the same material. Silicon oxide is preferred as it is used for each layer because it allows for strong bonding. Furthermore, using the same material for conductive layers 71b and 71d reduces contact resistance, which is also preferred. In particular, copper is easy to bond and allows for low contact resistance when used for each layer.

[0127] During bonding, by pressing a portion of substrate 51 or substrate 11, van der Waals bonds, hydrogen bonds, etc., can be extended to the entire bonding surface starting from that portion. When one or both bonding surfaces have hydrophilic surfaces, hydroxyl groups, water molecules, etc., act as adhesives. During subsequent heat treatment, water molecules diffuse, and residual components form silanol groups (Si-OH), which are then bonded by hydrogen bonds. Furthermore, due to hydrogen desorption, siloxane bonds (O-Si-O) are formed, and the bonding portion becomes covalent, achieving a stronger bond.

[0128] Semiconductor devices can be manufactured using the above-described process.

[0129] Figure 2D The semiconductor device shown has a structure in which transistor 50 with a channel formed in a portion of a single-crystal substrate and transistor 10 with a channel formed in a single-crystal oxide semiconductor are stacked.

[0130] [Example 2 of a semiconductor device manufacturing method]

[0131] The following is an example of a method for manufacturing a semiconductor device using a semiconductor film formation method different from that described above.

[0132] First, prepare substrate 11a ( Figure 5A A single-crystal semiconductor substrate is used as substrate 11a. Preferably, substrate 11a is selected with a small lattice mismatch with the subsequently formed base film 12. The case where a silicon substrate is used as substrate 11a will be described here.

[0133] Next, a single-crystal base film 12 is formed on the substrate 11a. The base film 12 can be formed using the same deposition method as the semiconductor film 21f described above. By epitaxially growing on the substrate 11a, a high-quality single-crystal base film 12 can be obtained. The base film 12 is preferably an insulating film. That is, the base film 12 is preferably a film comprising a single-crystal insulator.

[0134] As the base film 12, oxides such as YSZ and zirconium oxide can typically be used. In addition, rare earth oxides such as yttrium oxide, erbium oxide, gadolinium oxide, and ytterbium oxide, as well as oxides of lanthanides, can also be used. In particular, when indium oxide is used in the semiconductor film 21f, yttrium oxide or erbium oxide is preferred.

[0135] For example, a silicon substrate can be used as substrate 11a, and a YSZ film can be used as base film 12. Note that this is not a limitation; any of the following can be used as base film 12: insulating film, conductive film, and semiconductor film. As base film 12, it is preferable to select a film with a small lattice mismatch with both substrate 11a and semiconductor film 21f. For example, it is preferable to select base film 12 such that the lattice mismatch Δa with both substrate 11a and semiconductor film 21f is within the following range: Δa is -20% or more and 20% or less, preferably -10% or more and 10% or less, more preferably -7% or more and 7% or less, further preferably -5% or more and 5% or less, and even more preferably -4% or more and 4% or less. In addition, a buffer layer for mitigating strain may be provided between substrate 11a and base film 12 and between base film 12 and semiconductor film 21f, or both.

[0136] When a silicon substrate is used as substrate 11a, a native oxide film is formed on the surface of substrate 11a. Therefore, a step to remove the native oxide film can be added before forming the base film 12. The native oxide film can be removed by wet etching using an acid such as hydrofluoric acid. Alternatively, it can be removed by dry etching. When using dry etching, it is preferable to continuously deposit the base film 12 after etching in a manner that prevents substrate 11a from being exposed to the atmosphere. This can suppress the re-formation of the native oxide film on substrate 11a.

[0137] Alternatively, the base film 12 can be formed without removing the native oxide film of the substrate 11a. Even with a native oxide film, a base film 12 with a crystal structure reflecting the crystallinity of the substrate 11a can sometimes be formed. In this case, a layer 12a serving as a buffer layer may be formed between the substrate 11a and the base film 12. By providing the layer 12a between the substrate 11a and the base film 12, the lattice strain of the base film 12 caused by the lattice mismatch between the substrate 11a and the base film 12 can be mitigated, thereby forming a base film 12 with a high-quality single-crystal structure.

[0138] Next, a semiconductor film 21f with a single crystal structure is formed on the substrate film 12. Figure 5B Since the base film 12 has a single crystal structure, the semiconductor film 21f can be epitaxially grown in the same manner as described above to form a film with a high-quality single crystal structure.

[0139] Then, in the same manner as described above, semiconductor layer 21, conductive layer 24, insulating layer 32, insulating layer 33a, insulating layer 22, and conductive layer 23 are formed to manufacture transistor 10. Furthermore, insulating layer 33d and conductive layer 71d are formed in the same manner as described above. Figure 5C ).

[0140] Next, the substrate 51 is bonded to the substrate 11a by bonding the insulating layer 33d to the insulating layer 83d. Figure 5D ).

[0141] Semiconductor devices can be manufactured through the above-described processes. By using the method shown here, the range of materials that can be selected for the substrate 11a can be expanded without the need to use expensive materials, thereby reducing costs. For example, a single-crystal silicon substrate can be used as the substrate 11a.

[0142] Then, as Figure 5E As shown, substrate 11a can also be removed. When removing substrate 11a, for example, force can be applied upwards to the end of substrate 11a to peel it off with the area of ​​lowest adhesion as the peeling surface. In this case, it is preferable to peel between substrate 11a and base film 12. In addition, when layer 12a is included between substrate 11a and base film 12, peeling may sometimes occur inside layer 12a, at the interface between layer 12a and substrate 11a, or at the interface between layer 12a and base film 12.

[0143] Alternatively, substrate 11a can be removed by chemical methods such as etching, physical methods such as grinding, polishing, or sandblasting, or combinations thereof. Alternatively, peeling can be achieved at the interface between substrate 11a and semiconductor film 21f by immersing a liquid such as water or alcohol in the liquid. In this case, substrate 11a can be immersed in the liquid, or the liquid can be in contact with the sides of substrate 11a and base film 12. Furthermore, using a conductive liquid (such as an ionic liquid or water containing carbon dioxide) can suppress static electricity during peeling, which is preferable.

[0144] After removing the substrate 11a, when layer 12a remains on the base film 12, it is preferable to remove it by etching, CMP, or similar methods. Furthermore, sometimes a damaged layer forms on or near the surface of the base film 12. In this case, it is preferable to remove the upper portion of the base film 12 by etching or CMP. Alternatively, the entire base film 12 may be removed to expose the semiconductor layer 21 and the insulating layer 32, and a new insulating layer may be formed in contact with their surfaces.

[0145] After removing the substrate 11a, it is possible to place it above the transistor 10 ( Figure 5E Functional components such as light-emitting elements, light-receiving elements, sensor elements, and transistors are manufactured above the base film 12.

[0146] Furthermore, although the substrate 11a is removed here, it can also be ground and thinned using back-side grinding or other methods. In this case, the substrate 11a is preferably thinned to a thickness sufficient to form a through-hole for inserting the plug. The thickness of the substrate 11a can be, for example, 1 μm or more and 100 μm or less, preferably 1 μm or more and 50 μm or less, and more preferably 1 μm or more and 20 μm or less.

[0147] The above is an explanation of examples of manufacturing methods.

[0148] At least a portion of this embodiment can be implemented in combination with other embodiments described in this specification.

[0149] (Implementation Method 2)

[0150] In this embodiment, an example of the structure of a transistor and an example of its manufacturing method that can be used in a semiconductor device according to one aspect of the present invention will be described.

[0151] [Example of a semiconductor device structure]

[0152] Figures 6A to 6D These are the top view and cross-sectional view of transistor 200. Figure 6A This is a top view of transistor 200. Figures 6B to 6D They correspond to Figure 6A The diagram shows the cross-sections of the cut lines A1-A2, A3-A4, and A5-A6. Figure 6B This is equivalent to the cross-section along the channel length of transistor 200. Figure 6C , 6D Both are equivalent to the cross-section in the channel width direction of a transistor. Figure 7 yes Figure 6B A magnified image. Additionally, in Figure 6A In the middle, omissions are made. Figure 7 The description of some of the constituent elements shown.

[0153] Transistor 200 includes a semiconductor layer 230, conductive layers 242a and 242b, an insulating layer 250, and a conductive layer 260 disposed on an insulating layer 250 on an insulating layer 201 disposed on a substrate (not shown). An insulating layer 275 is disposed covering the semiconductor layer 230, conductive layers 242a and 242b, and an insulating layer 280 is disposed on the insulating layer 275. The insulating layers 280 and 275 have trenches extending to the semiconductor layer 230, separating the conductive layers 242a and 242b by these trenches. The insulating layer 250 is disposed inside the trenches along the surfaces of the insulating layers 280, 275, 242a, 242b, and 230. The conductive layer 260 is disposed on the insulating layer 250 to fill the trenches. In addition, insulating layers 282, 283 and 285 are sequentially provided to cover insulating layers 280, 250 and conductive layer 260.

[0154] The semiconductor layer 230 functions as the channel formation region of the transistor 200. Additionally, the conductive layer 260 functions as the gate electrode of the transistor 200. The insulating layer 250 functions as the gate insulator of the transistor 200.

[0155] The conductive layer 242a is used as one of the source electrode and the drain electrode of the transistor 200, and the conductive layer 242b is used as the other.

[0156] Conductive layers 242a and 242b preferably have a stacked structure. The side in contact with the semiconductor layer 230 is preferably made of a conductor that is not easily oxidized, such as a metal nitride. This prevents excessive oxidation of conductive layers 242a and 242b due to oxygen in the semiconductor layer 230. Furthermore, the side not in contact with the semiconductor layer 230 is preferably made of a metal or alloy with higher conductivity than the layer in contact with the semiconductor layer 230. This allows conductive layers 242a and 242b to be used as highly conductive wiring or electrodes.

[0157] Metal nitrides are preferably used on the side of conductive layers 242a and 242b that contacts the semiconductor layer 230. For example, nitrides containing tantalum, titanium, molybdenum, tungsten, tantalum and aluminum, or titanium and aluminum can be used. Additionally, ruthenium, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel can also be used. These materials are preferred because they are conductive materials that are not easily oxidized or maintain conductivity even after absorbing oxygen.

[0158] The insulating layer 201 is the layer in contact with the semiconductor layer 230 and can be made of a material with a single-crystal structure. For example, single-crystal materials such as YSZ, zirconium oxide, silicon, silicon carbide, gallium nitride, and gallium oxide can be used. In particular, oxide insulating materials such as zirconium oxide or YSZ are preferred. Furthermore, rare-earth oxides such as yttrium oxide, erbium oxide, gadolinium oxide, and ytterbium oxide, as well as oxides of lanthanides, can also be used. In particular, when indium oxide is used as the semiconductor layer 230, yttrium oxide or erbium oxide is preferred.

[0159] Therefore, reducing the impurity concentration in the semiconductor layer 230 is effective in stabilizing the electrical characteristics of the transistor 200. To further reduce the impurity concentration in the semiconductor layer 230, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon. Note that impurities in the semiconductor layer 230 refer, for example, to elements other than the main components constituting the semiconductor layer 230. For example, elements with a concentration less than 0.1 atomic% can be considered impurities.

[0160] Furthermore, it is preferable to use a metal oxide (hereinafter also referred to as an oxide semiconductor) as a semiconductor layer 230.

[0161] The bandgap of the metal oxide used as a semiconductor is preferably 2 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wider bandgap, the off-state current of the transistor can be reduced. A transistor that thus incorporates a metal oxide in the channel formation region is called an OS transistor. OS transistors have low off-state currents, so the power consumption of semiconductor devices can be significantly reduced. Furthermore, OS transistors have high frequency characteristics, enabling semiconductor devices to operate at high speeds.

[0162] Indium oxide (IO) is preferably used as the semiconductor layer 230. In particular, a single-crystal IO film is preferred. Furthermore, a crystalline film is preferably used as the semiconductor layer 230, and a single-crystal IO film is especially preferred; however, polycrystalline or microcrystalline IO films can also be used. By using IO with a single-crystal structure, carrier scattering at grain boundaries can be suppressed, thereby enabling transistors with high field-effect mobility. Furthermore, transistors with high reliability can be achieved.

[0163] When using indium oxide with a polycrystalline structure, it is preferable that no grain boundaries are observed at least in the channel formation region (the region overlapping with the conductive layer 260). Thus, even indium oxide with a polycrystalline structure can achieve the same effect as in the case of a single-crystal structure.

[0164] The thickness of the semiconductor layer 230 is preferably 2 nm or more and 50 nm or less, more preferably 2.5 nm or more and 30 nm or less, even more preferably 2.5 nm or more and 20 nm or less, even more preferably 5 nm or more and 20 nm or less, and even more preferably 5 nm or more and 10 nm or less. By setting the thickness of the semiconductor layer 230 within the above range, the crystallinity of the semiconductor layer 230 can be improved.

[0165] In highly crystalline oxide semiconductors, such as IGZO (In-Ga-Zn-O type oxide) films, indium oxide (IO) is a film where one or both hydrogen and oxygen are readily mobile. Therefore, compared to IGZO films, IO can be considered a film where one or both hydrogen and oxygen are readily supplied and discharged. Consequently, it can be said that excess oxygen or hydrogen, which could potentially become charge carriers or fixed charges, does not easily accumulate in the semiconductor layer 230, thus enabling the realization of transistors with excellent electrical characteristics and reliability.

[0166] In the semiconductor layer 230, the concentration of elements that reduce crystallinity is preferably reduced. For example, the concentration of elements such as boron and aluminum is preferably 1 atomic% or less, more preferably 0.1 atomic% or less, and even more preferably 0.01 atomic% (100 ppm) or less.

[0167] Furthermore, gallium readily bonds with excess oxygen atoms, so when a higher gallium content is present, the threshold voltage variation in the PBTS (Positive Bias Temperature Stress) test can sometimes be larger. Therefore, the gallium concentration in the semiconductor layer 230 is preferably 1 atomic% or less, more preferably 0.1 atomic% or less, and even more preferably 0.01 atomic% (100 ppm) or less.

[0168] In addition, tin oxide, zinc oxide, indium tin oxide, indium titanium oxide, indium gallium oxide, indium gallium aluminum oxide, indium gallium tin oxide, gallium zinc oxide, aluminum zinc oxide, indium aluminum zinc oxide, indium tin zinc oxide, indium titanium zinc oxide, indium gallium zinc oxide, indium gallium tin zinc oxide, indium gallium aluminum zinc oxide, and indium gallium aluminum zinc oxide can also be used as the metal oxide for semiconductor layer 230. Alternatively, silicon-containing indium tin oxide, gallium tin oxide, aluminum tin oxide, etc., can also be used. When using the above materials, it is preferable to have a film that is at least crystalline, and more preferably has a single crystal structure.

[0169] The insulating layer 250, used as the gate insulating layer, preferably has the function of trapping and fixing hydrogen. This reduces the hydrogen concentration in the channel formation region of the semiconductor layer 230. Consequently, the channel formation region can be made type I or substantially type I.

[0170] Here, the insulating layer 250 preferably has a stacked structure of a first layer, a second layer on the first layer, and a third layer on the second layer in contact with the semiconductor layer 230. In this case, the first layer preferably has the function of capturing and fixing hydrogen.

[0171] Metal oxides with amorphous structures can be cited as insulators capable of trapping and fixing hydrogen. For example, magnesium oxide or oxides containing one or both of aluminum and hafnium are preferred as the first layer. These amorphous metal oxides sometimes possess the property that oxygen atoms have dangling bonds, which trap or fix hydrogen. In other words, amorphous metal oxides have a high ability to trap or fix hydrogen.

[0172] Furthermore, a high-k material is preferably used for the first layer. An example of a high-k material is an oxide containing one or both of aluminum and hafnium. When a high-k material is used as the first layer, the gate potential applied during transistor operation can be reduced while maintaining the physical thickness of the gate insulator. Additionally, the equivalent oxide thickness (EOT) of the insulator used as the gate insulator can be reduced.

[0173] Therefore, as the first layer, it is preferable to use an oxide containing one or both of aluminum and hafnium, more preferably an oxide having an amorphous structure and containing one or both of aluminum and hafnium, and even more preferably aluminum oxide having an amorphous structure.

[0174] Next, as the second layer, an insulator with a thermally stable structure, such as silicon oxide or silicon oxynitride, is preferably used.

[0175] Alternatively, a structure in which a fourth layer is provided on the second layer can also be adopted. In this case, an insulator that can be used for the first layer can be provided as the fourth layer. For example, hafnium oxide can be used as the fourth layer. Here, by providing a fourth layer between the third and second layers, hydrogen contained in the second layer and the like can be captured and fixed more effectively.

[0176] The third layer preferably has oxygen-barrier properties. The third layer is disposed between the channel formation region of the semiconductor layer 230 and the conductive layer 260, and between the insulating layer 280 and the conductive layer 260. By employing this structure, oxygen diffusion from the channel formation region of the semiconductor layer 230 to the conductive layer 260, thus preventing the formation of oxygen vacancies in the channel formation region of the semiconductor layer 230, can be suppressed. Furthermore, oxygen diffusion from the semiconductor layer 230 and the insulating layer 280 to the conductive layer 260, thus preventing oxidation of the conductive layer 260, can also be suppressed. The third layer preferably allows oxygen to permeate at least less than the insulating layer 280. For example, a silicon nitride film is preferably used as the third layer. In this case, the third layer is an insulator containing at least nitrogen and silicon.

[0177] Furthermore, the third layer preferably has hydrogen-barrier properties. This prevents impurities such as hydrogen contained in the conductive layer 260 from diffusing into the semiconductor layer 230.

[0178] The insulating layer 275 preferably has oxygen-barrier properties. The insulating layer 275 is disposed between the insulating layer 280 and the conductive layer 242a, and between the insulating layer 280 and the conductive layer 242b. By employing this structure, oxygen diffusion from the insulating layer 280 to the conductive layers 242a and 242b can be suppressed. Therefore, oxygen in the insulating layer 280 can be prevented from causing oxidation of the conductive layers 242a and 242b, thus preventing an increase in resistivity and a decrease in on-state current. The insulating layer 275 preferably allows oxygen to permeate at least less than the insulating layer 280. For example, silicon nitride is preferably used as the insulating layer 275. In this case, the insulating layer 275 is an insulator containing at least nitrogen and silicon.

[0179] In this embodiment, it is preferable that the semiconductor device, in addition to the structure described above, also has a structure that suppresses hydrogen ingress into the transistor 200, etc. For example, it is preferable to provide an insulator with the function of suppressing hydrogen diffusion in a manner that covers the transistor 200. In the semiconductor device described in this embodiment, this insulator is, for example, insulating layer 282 and insulating layer 283, etc. Alternatively, the same film may be provided under the transistor 200.

[0180] One or more of insulating layers 282 and 283 are preferably used as barrier insulators to inhibit the diffusion of impurities such as water and hydrogen from above the transistor 200 to the transistor 200. Therefore, one or more of insulating layers 282 and 283 preferably contain an insulating material that functions to inhibit the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms (making it difficult for the aforementioned impurities to permeate). Furthermore, it is preferable to contain an insulating material that functions to inhibit the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (making it difficult for the aforementioned oxygen to permeate).

[0181] Both insulating layers 282 and 283 preferably contain an insulator that functions to suppress the diffusion of impurities such as water, hydrogen, and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, or silicon oxynitride can be used. For instance, silicon nitride, which has higher hydrogen barrier properties, is preferably used as insulating layer 283. Furthermore, insulating layer 282 preferably contains aluminum oxide or magnesium oxide, which have a high ability to trap and fix hydrogen. This suppresses the diffusion of impurities such as water and hydrogen from the interlayer insulating film disposed outside insulating layer 283 to transistor 200. Additionally, it suppresses the diffusion of oxygen contained in insulating layer 280 to the upper part of transistor 200 via insulating layer 282. Moreover, by providing a film identical to one or both of insulating layers 282 and 283 below transistor 200, the diffusion of impurities such as water and hydrogen from the substrate side to transistor 200 can be suppressed.

[0182] Insulating layers 271a and 271b are inorganic insulators that serve as etch stop layers during the processing of conductive layers 242a and 242b, protecting the conductive layers 242a and 242b. Furthermore, since they are in contact with conductive layers 242a and 242b respectively, insulating layers 271a and 271b are preferably made of inorganic insulators that do not easily oxidize conductive layers 242a and 242b. For example, a structure can be adopted in which insulating layers 271a and 271b have a stacked structure, with silicon nitride used on the side in contact with conductive layers 242a and 242b, and silicon oxide used elsewhere.

[0183] An opening is formed in insulating layers 285, 283, 282, 280, 275, and 271a, leading to conductive layer 242a. Conductive layer 240a and insulating layer 241a are disposed within this opening. Insulating layer 241a is disposed in contact with the sidewall of this opening, and conductive layer 240a is disposed inside insulating layer 241a. Similarly, an opening is formed in insulating layers 285, 283, 282, 280, 275, and 271b, leading to conductive layer 242b. Conductive layer 240b and insulating layer 241b are disposed within this opening. Insulating layer 241b is disposed in contact with the sidewall of this opening, and conductive layer 240b is disposed inside insulating layer 241b. The conductive layers 240a and 240b are used as vias to connect wiring or other components disposed on the transistor 200 to the source or drain of the transistor 200.

[0184] Conductive layers 240a and 240b are preferably made of conductive materials with tungsten, copper, or aluminum as the main components. Furthermore, conductive layers 240a and 240b may also have a stacked structure.

[0185] For example, such as Figure 7As shown, conductive layers 240a and 240b can also have a two-layer stacked structure. Conductive layer 240a includes a conductive layer 240a1 formed along the opening and a conductive layer 240a2 formed inside the conductive layer 240a1. Furthermore, conductive layer 240b includes a conductive layer 240b1 formed along the opening and a conductive layer 240b2 formed inside the conductive layer 240b1.

[0186] As conductive layers 240a1 and 240b1, conductive materials such as tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, and ruthenium oxide, which have the function of suppressing the permeation of impurities such as water and hydrogen, are preferably used. Alternatively, a single layer or a stack of conductive materials with the function of suppressing the permeation of impurities such as water and hydrogen can also be used. By providing conductive layers 240a1 and 240b1, impurities such as water and hydrogen can be prevented from mixing into the semiconductor layer 230 through conductive layers 240a2 and 240b2. Furthermore, conductive layers 240a2 and 240b2 can be made of the conductive materials described above that can be used for conductive layers 240a and 240b.

[0187] In addition, such as Figure 6B As shown, the top surfaces of conductive layers 240a and 240b can be formed in a manner that is flush with or substantially aligned with the top surface of insulating layer 285. Furthermore, as... Figure 7 As shown, the lower portion of conductive layer 240a is sometimes formed by embedding it in conductive layer 242a. Similarly, the lower portion of conductive layer 240b is sometimes formed by embedding it in conductive layer 242b.

[0188] As insulating layers 241a and 241b, any barrier insulator suitable for insulating layer 275, etc., can be used. For example, silicon nitride can be used as insulating layers 241a and 241b. Insulating layers 241a and 241b are respectively provided in contact with insulating layers 285, 283, 282, 275, and either insulating layer 271a or 271b. This prevents impurities such as water and hydrogen contained in insulating layers 280, etc., from mixing into the semiconductor layer 230 through conductive layers 240a and 240b. In particular, silicon nitride has high hydrogen barrier properties, so it is preferred. Furthermore, it prevents oxygen contained in insulating layer 280 from being absorbed by conductive layers 240a and 240b.

[0189] The conductive layer 260 is used as the gate electrode of the transistor 200. Here, as... Figure 6A and Figure 6C As shown, the conductive layer 260 preferably extends in the channel width direction. By employing this structure, the conductive layer 260 is used as wiring when multiple transistors are disposed.

[0190] The conductive layer 260 can also have a stacked structure. Figure 7An example is shown where the conductive layer 260 includes a conductive layer 260a located on the side in contact with the insulating layer 250 and a conductive layer 260b thereon. In this case, as the conductive layer 260a, it is preferable to use a conductive material that is not easily oxidized, such as titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, or ruthenium oxide, or a conductive material that has the function of inhibiting oxygen diffusion. Furthermore, as the conductive layer 260b, it is preferable to use a low-resistance conductive material such as tungsten, copper, or aluminum.

[0191] The insulating layer 280 preferably has a low relative permittivity. By using a material with a low relative permittivity in the interlayer film, parasitic capacitance generated between the wirings can be reduced. For example, the insulating layer 280 preferably comprises one or more of silicon oxide, silicon oxynitride, fluorinated silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, and porous silicon oxide. Silicon oxide and silicon oxynitride are preferred because they have thermal stability. In particular, materials such as silicon oxide, silicon oxynitride, and porous silicon oxide are preferred because they readily form regions containing oxygen that has been released upon heating.

[0192] [Example of variation]

[0193] Below, we will illustrate an example where a portion of the structure differs from the examples described above. Additionally, descriptions of parts repeated above will be omitted.

[0194] [Example 1 of the variation]

[0195] Figure 8 An example is shown where transistor 200 includes a conductive layer 205 serving as a back gate. Figure 8 The structure shown includes a conductive layer 205 and an insulating layer 202.

[0196] The conductive layer 205 is embedded in the insulating layer 202. The insulating layer 201 is provided to cover both the insulating layer 202 and the conductive layer 205.

[0197] The conductive layer 205 serves as the second gate (back gate) of the transistor 200. The conductive layer 205 is disposed in the region where it overlaps with the conductive layer 260, separated by the semiconductor layer 230. By providing the conductive layer 205 and supplying it with an appropriate potential, the threshold voltage of the transistor 200 can be controlled. Furthermore, the potential on the back channel side of the semiconductor layer 230 can be fixed, reducing the non-uniformity of the electrical characteristics of the transistor 200. Alternatively, the same potential or signal as any one of the conductive layers 242a, 242b, and 260 can be supplied to the conductive layer 205.

[0198] The conductive layer 205 can be made of the same material as the conductive layer 260. Alternatively, the conductive layer 205 can also have a stacked structure.

[0199] At this time, insulating layer 201 is used as a second gate insulating layer.

[0200] The insulating layer 202 can be a silicon oxide film. Alternatively, when an insulating film such as silicon nitride or aluminum oxide that has oxygen-barrier properties is provided between the insulating layer 202 and the conductive layer 205, the oxidation of the conductive layer 205 can be suppressed, which is preferred.

[0201] [Example 2]

[0202] Figures 9A to 9D An example of a transistor 200 whose structure differs from the structure described above is shown. Figure 9A It is a top view. Figures 9B to 9D These are cross-sectional views. Figures 9A to 9D The structure shown includes an insulating layer 255, which differs from the structure described above. Additionally, the insulating layer 250 contacts the side surface of the insulating layer 255.

[0203] Furthermore, both conductive layer 242a and conductive layer 242b have a two-layer structure. Conductive layer 242a has a stacked structure of conductive layer 242a1 and conductive layer 242a2 on conductive layer 242a1. Conductive layer 242b has a stacked structure of conductive layer 242b1 and conductive layer 242b2 on conductive layer 242b1.

[0204] An insulating layer 255 is disposed inside an opening formed in an insulating layer 280, etc., and contacts the side surface of the insulating layer 280, the side surface of the conductive layer 242a2, the side surface of the conductive layer 242b2, the top surface of the conductive layer 242a1, the top surface of the conductive layer 242b1, and the top surface of the insulating layer 201 in the opening. In other words, the insulating layer 255 can be described as being formed in a sidewall shape, in contact with the sidewall of the opening formed in the insulating layer 280, etc. Here, the sidewall of the opening corresponds, for example, to the side surface of the insulating layer 280, etc., in the opening.

[0205] The insulating layer 255 preferably has oxygen-barrier properties. When the insulating layer 255 has oxygen-barrier properties, the oxidation of the sides of the conductive layers 242a and 242b, resulting in the formation of an oxide film on those sides, can be suppressed. Therefore, the decrease in the on-state current or the decrease in the field-effect mobility of the transistor 200 can be suppressed. As the insulating layer 255, a barrier insulator suitable for insulating layers 275, etc., can be used. For example, silicon nitride can be used as the insulating layer 255.

[0206] An opening in the insulating layer 280 overlaps with the area between the conductive layers 242a2 and 242b2. In a top view, the side surface of the insulating layer 280 in the opening is aligned or substantially aligned with the side surfaces of the conductive layers 242a2 and 242b2. Furthermore, portions of the conductive layers 242a1 and 242b1 are formed to protrude inwards from the opening. In other words, in the conductive layer 242a1, the portion on its top surface where the insulating layer 255 is formed (hereinafter, sometimes referred to as the protrusion of the conductive layer 242a1) is formed in such a way that it protrudes towards the conductive layer 260 compared to the conductive layer 242a2. Similarly, in the conductive layer 242b1, the portion on its top surface where the insulating layer 255 is formed (hereinafter, sometimes referred to as the protrusion of the conductive layer 242b1) is formed in such a way that it protrudes towards the conductive layer 260 compared to the conductive layer 242b2.

[0207] Here, a portion of the top surface of conductive layer 242a1 contacts conductive layer 242a2, and a portion of the top surface of conductive layer 242b1 contacts conductive layer 242b2. Therefore, the insulating layer 255 contacts other portions of the top surface of conductive layer 242a1, other portions of the top surface of conductive layer 242b1, the side surface of conductive layer 242a2, and the side surface of conductive layer 242b2 on the inner side of the opening. Additionally, the insulating layer 250 contacts the top surface of semiconductor layer 230, the side surface of conductive layer 242a1, the side surface of conductive layer 242b1, and the side surface of insulating layer 255.

[0208] The insulating layer 255 is formed into a sidewall shape by anisotropic etching to contact the sidewall of the opening provided in the insulating layer 280. The insulating layer 255 is formed to contact the sidewalls of the conductive layer 242a2 and the sidewalls of the conductive layer 242b2, and has the function of protecting the conductive layer 242a2 and the conductive layer 242b2.

[0209] [Example 3]

[0210] Figures 10A to 10D The following is a structural example of the transistor 200 illustrated below. Figures 10A to 10D The structure shown does not include the insulating layer 255, which is different from the modified example 2 described above.

[0211] Without the insulating layer 255, a portion of the insulating layer 250 is configured to overlap with the protrusions of the conductive layer 242a1 and the conductive layer 242b1. Furthermore, a portion of the conductive layer 260 is sometimes configured to overlap with the protrusions of the conductive layer 242a1 and the conductive layer 242b1. Here, the protrusions of the conductive layer 242a1 and the conductive layer 242b1 are in contact with the insulating layer 250. Additionally, the side surface of the insulating layer 250 is in contact with the side surface of the insulating layer 280, the side surface of the conductive layer 242a2, and the side surface of the conductive layer 242b2.

[0212] The insulating layer 250 is configured to reflect the shape of the opening in the insulating layer 280. Therefore, the insulating layer 250 is formed to reflect the shape of the conductive layers 242a1 and 242b1 that protrude into the opening.

[0213] like Figure 10B As shown, when viewed in cross-section along the channel length of transistor 200, the distance between conductive layers 242a1 and 242b1 is smaller than the distance between conductive layers 242a2 and 242b2. By employing this structure, the distance between the source and drain can be further reduced, and the channel length can be correspondingly reduced. Therefore, the frequency characteristics of transistor 200 can be improved. Thus, by miniaturizing the semiconductor device, a semiconductor device with improved operating speed can be provided.

[0214] [Example of manufacturing method]

[0215] Hereinafter, an example of a method for manufacturing a transistor according to one aspect of the present invention will be described. The transistor 200 shown in the above-described [Structure Example of a Semiconductor Device] and FIG6, etc., will be used as an example for description.

[0216] Figure 11A1 , Figure 11B1 , Figure 11C1 , Figure 11D1 , Figure 12A1 , Figure 12B1 and Figure 12C1 The following are cross-sectional schematic diagrams of each stage of an example manufacturing method. Figure 11A2 , Figure 11B2 , Figure 11C2 , Figure 11D2 , Figure 12A2 , Figure 12B2 and Figure 12C2 This is a 3D diagram. Note that a portion is shown in the 3D diagram. Furthermore, in the 3D diagram, some constituent elements (such as insulating layers) are represented by dashed lines to indicate their outlines.

[0217] First, a structure in which a semiconductor film 230f is formed on an insulating layer 201 is prepared. The insulating layer 201 corresponds to the substrate 11 or base film 12 in Embodiment 1. Furthermore, the semiconductor film 230f corresponds to the semiconductor film 21f in Embodiment 1, and its manufacturing method can be referred to therein. Note that this point in time corresponds to the point in Embodiment 1. Figure 1B The stage.

[0218] Preferably, the semiconductor film 230f is subjected to heat treatment. For example, as a heat treatment, it can be performed at a nitrogen gas to oxygen gas flow ratio of 4:1 and a temperature of 450°C for 1 hour. By performing heat treatment, the crystallinity of the semiconductor film 230f can be improved. In addition, by performing heat treatment, oxygen can be supplied to the semiconductor film 230f, thereby reducing oxygen vacancies in the semiconductor film 230f. As a result, the reliability of the transistor 200 can be improved. Furthermore, by performing heat treatment, hydrogen in the semiconductor film 230f can be removed.

[0219] Next, a conductive film 242f is deposited on the semiconductor film 230f. Figure 11A1 , Figure 11A2 After depositing the semiconductor film 230f, a conductive film 242f is deposited on and in contact with the semiconductor film 230f without etching or other processes. This allows the top surface of the semiconductor film 230f to be protected by the conductive film 242f. Consequently, impurity diffusion into the semiconductor layer 230 constituting the transistor can be suppressed, thus improving the electrical characteristics and reliability of the semiconductor device.

[0220] The conductive film 242f can be deposited using sputtering, CVD, MBE, PLD or ALD methods.

[0221] In this embodiment, tantalum nitride is deposited as the conductive film 242f using a sputtering method. Furthermore, a heat treatment may be performed before depositing the conductive film 242f. This heat treatment can also be performed under reduced pressure, wherein the conductive film 242f is continuously deposited without exposure to the atmosphere. By performing this treatment, moisture and hydrogen adsorbed on the surface of the semiconductor film 230f can be removed, and the moisture and hydrogen concentrations in the semiconductor film 230f can be reduced. The heat treatment temperature is preferably 100°C or higher and 400°C or lower.

[0222] Next, the semiconductor film 230f and the conductive film 242f are processed into islands using photolithography to form the semiconductor layer 230 and the conductive layer 242. Figure 11B1 , Figure 11B2 ).

[0223] The above processing can be performed using either dry etching or wet etching. Dry etching is suitable for microfabrication. Furthermore, the semiconductor film 230f and the conductive film 242f can also be processed under different conditions.

[0224] Alternatively, a layer serving as a hard mask can be formed on the conductive film 242f. Using a hard mask improves processability and facilitates fabrication into the desired shape, making it a preferred option.

[0225] Here, it is preferable to process the semiconductor layer 230 and the conductive layer 242 into an island shape in one step. In this case, the side end of the conductive layer 242 is preferably aligned or substantially aligned with the side end of the semiconductor layer 230. By adopting the above structure, the number of steps in the semiconductor device according to one aspect of the present invention can be reduced. Thus, a method for manufacturing a semiconductor device with high productivity can be provided.

[0226] like Figure 11B1 As shown, the sides of the semiconductor layer 230 and the conductive layer 242 can also have a tapered shape. The tapered angle of the sides of the semiconductor layer 230 and the conductive layer 242 can be, for example, 60° or more and less than 90°. When the sides have such a tapered shape, the coverage of the insulating layer 275 and the like in subsequent processes is improved, and defects such as voids can be reduced.

[0227] Note that in lithography, the photoresist is first exposed through a mask. Then, a developer is used to remove or leave the exposed areas, forming a photoresist mask. Next, etching is performed through this photoresist mask to process conductors, semiconductors, or insulators into the desired shape. For example, a KrF stimulated excimer laser, an ArF stimulated excimer laser, or EUV (Extreme Ultraviolet) light can be used to expose the photoresist mask to form it. Alternatively, immersion lithography can be used, where exposure is performed with a liquid (e.g., water) filling the space between the substrate and the projection lens. Furthermore, electron beams or ion beams can be used instead of the aforementioned light. Note that when using electron beams or ion beams, a mask may sometimes be omitted.

[0228] Unwanted resist masks after processing can be removed by dry etching (such as ashing with oxygen plasma, sometimes referred to as oxygen plasma treatment), wet etching, wet etching after dry etching, or dry etching after wet etching.

[0229] Furthermore, a hard mask made of an insulator or conductor can also be used under a photoresist mask. When using a hard mask, an insulating or conductive film that serves as the hard mask material can be formed on the conductive film 242f, and a photoresist mask can be formed on it. Then, the hard mask material can be etched to form a hard mask of the desired shape. For example, tungsten can also be used as the hard mask material. Etching of the conductive film 242f, etc., can be performed either after removing the photoresist mask or without removing the photoresist mask. In the latter case, the photoresist mask may sometimes disappear during etching. The hard mask can also be removed by etching after etching the semiconductor film 230f, etc. On the other hand, if the hard mask material does not affect subsequent processes or can be used in subsequent processes, it is not necessary to remove the hard mask.

[0230] Alternatively, SOC (Spin On Carbon) films and SOG (Spin On Glass) films can be deposited between the workpiece and the resist mask. Using SOC and SOG films as masks improves the adhesion between the workpiece and the resist mask, thereby enhancing the durability of the mask pattern. For example, lithography can be performed by sequentially depositing an SOC film, an SOG film, and a resist mask on the workpiece.

[0231] Next, an insulating layer 275 is deposited in a manner that covers the semiconductor layer 230 and the conductive layer 242, and an insulating layer 280 is deposited on the insulating layer 275. Figure 11C1 , Figure 11C2 ).

[0232] As the insulating layer 280, it is preferable to form an insulating film that will become the insulating layer 280 by CMP treatment of the insulating film to form an insulator with a flat top surface. Alternatively, silicon nitride can be deposited on the insulating layer 280, for example by sputtering, and CMP treatment can be performed on the silicon nitride until the insulating layer 280 is reached.

[0233] Insulating layer 275 and insulating layer 280 can each be deposited, for example, by sputtering, CVD, MBE, PLD or ALD.

[0234] The insulating layer 275 is preferably an insulator that inhibits oxygen permeation. For example, silicon nitride is preferably deposited using the PEALD method as the insulating layer 275. Alternatively, aluminum oxide can be deposited using sputtering and silicon nitride can be deposited thereon using the PEALD method. When the insulating layer 275 has the above-described structure, the function of inhibiting the diffusion of impurities such as water and hydrogen, as well as oxygen, can be improved.

[0235] Furthermore, silicon oxide is preferably deposited using sputtering as the insulating layer 280. By depositing the insulating film that will become the insulating layer 280 using sputtering under an oxygen-containing atmosphere, an insulating layer 280 containing excess oxygen can be formed. By using a sputtering method that does not require the use of hydrogen-containing molecules as the deposition gas, the hydrogen concentration in the insulating layer 280 can be reduced. In addition, a heat treatment can be performed before depositing the insulating film. The heat treatment can also be performed under reduced pressure, wherein the insulating film is continuously deposited without exposure to the atmosphere. By performing this treatment, moisture and hydrogen adsorbed on the surface of the insulating layer 275 can be removed. The heat treatment can be performed under the conditions described above.

[0236] Next, the conductive layer 242, insulating layer 275, and insulating layer 280 are processed using photolithography to form openings (also called trenches) leading to the semiconductor layer 230 and insulating layer 201. Figure 11D1 , Figure 11D2 Here, the conductive layer 242 is divided to form conductive layers 242a and 242b. The openings formed in the insulating layers 280 and 275 overlap with the semiconductor layer 230.

[0237] Next, an insulating layer 250 is deposited to cover the openings formed in the insulating layer 280, etc. Here, the insulating layer 250 is deposited along the openings of the insulating layer 280. In addition, the insulating layer 250 is in contact with the insulating layer 280, the conductive layer 242a, the conductive layer 242b, the insulating layer 201, and the semiconductor layer 230.

[0238] The insulating layer 250 can be deposited using sputtering, CVD, MBE, PLD, or ALD methods. The insulating layer 250 is preferably formed with a relatively thin thickness, so ALD deposition, which offers good coverage and easy thickness control, is preferred.

[0239] In addition, when depositing the insulating layer 250 using the ALD method, ozone (O3), oxygen (O2), water (H2O), etc., can be used as oxidants. By using ozone (O3), oxygen (O2), etc., which do not contain hydrogen, as oxidants, the amount of hydrogen diffusing into the semiconductor layer 230 can be reduced.

[0240] In addition, it is preferable to perform microwave treatment before, after, or during the deposition of the insulating layer 250.

[0241] More specifically, microwave processing is preferably performed in an oxygen-containing atmosphere. Here, microwave processing refers, for example, to processing using a device that includes a power source for generating high-density plasma using microwaves. Furthermore, in this specification and the like, microwaves refer to electromagnetic waves with a frequency of 300 MHz or higher and 300 GHz or lower.

[0242] Microwave processing preferably utilizes a microwave processing apparatus, for example, that includes a power supply for generating high-density plasma using microwaves. The frequency of the microwave processing apparatus is typically 2.45 GHz. By using high-density plasma, a high density of oxygen free radicals can be generated. Furthermore, the power of the power supply for applying microwaves to the microwave processing apparatus is preferably 1000 W or more and 10000 W or less, more preferably 2000 W or more and 5000 W or less. Additionally, the microwave processing apparatus may also include a power supply that applies RF to one side of the substrate. Furthermore, by applying RF to one side of the substrate, oxygen ions generated by the high-density plasma can be efficiently introduced into the semiconductor layer 230.

[0243] Furthermore, the aforementioned microwave treatment is preferably performed under reduced pressure, preferably between 10 Pa and 1000 Pa, more preferably between 300 Pa and 700 Pa. The treatment temperature is preferably below 750°C, more preferably below 500°C, for example, around 250°C. Alternatively, heating treatment can be performed continuously after oxygen plasma treatment without exposure to external air. The heating temperature is preferably between 100°C and 750°C, more preferably between 300°C and 500°C.

[0244] Next, a conductive film that will become the conductive layer 260 is deposited. This conductive film can be deposited using sputtering, CVD, MBE, PLD, electroplating, or ALD methods. For example, titanium nitride and tungsten films can be deposited in layers using CVD.

[0245] Next, CMP is used to polish the insulating layer 250 and the conductive film that will become the conductive layer 260 until the insulating layer 280 is exposed. That is, a portion of the insulating layer 250 and the conductive film exposed from the opening is removed. Thus, the insulating layer 250 and the conductive layer 260 are formed in the opening leading to the semiconductor layer 230. Figure 12A1 , Figure 12A2 ).

[0246] Thus, the insulating layer 250 is disposed in contact with the conductive layer 242a, conductive layer 242b, semiconductor layer 230, and insulating layer 201 in the aforementioned opening. Furthermore, the conductive layer 260 is disposed such that it is embedded in the aforementioned opening with the insulating layer 250 in between. This forms the transistor 200.

[0247] Next, an insulating layer 282 is deposited on the insulating layer 250, the conductive layer 260, and the insulating layer 280. The insulating layer 282 can be deposited using methods such as sputtering, CVD, MBE, PLD, or ALD. Sputtering is preferred for depositing the insulating layer 282. By using sputtering, which does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulating layer 282 can be reduced.

[0248] Here, by using sputtering to deposit the insulating layer 282 in an oxygen-containing atmosphere, oxygen can be added to the insulating layer 280 during the deposition process. This allows the insulating layer 280 to contain excess oxygen.

[0249] Next, an insulating layer 285 is formed on the insulating layer 282. Figure 12B1 , Figure 12B2 The insulating layer 285 can be deposited using sputtering, CVD, MBE, PLD, or ALD methods. Sputtering is preferred for depositing the insulating layer 285. By using sputtering, which does not require hydrogen-containing molecules to be used in the deposition gas, the hydrogen concentration in the insulating layer 285 can be reduced.

[0250] Next, openings leading to conductive layers 242a and 242b are formed in insulating layers 275, 280, 282, and 285, respectively. These openings can be formed using lithography. Dry etching is preferably used to process the workpiece when forming these openings. Furthermore, the shape of the opening when viewed from above can be a circle, an ellipse, or a polygon, or a polygon with rounded corners.

[0251] Next, a heat treatment can be performed after the opening is formed. The heat treatment temperature can be 100°C or higher and 600°C or lower, preferably 250°C or higher and 550°C or lower, and more preferably 350°C or higher and 450°C or lower. The heat treatment is preferably performed in a nitrogen atmosphere or an inactive gas atmosphere. In addition, since the heat treatment is performed with the conductive layers 242a and 242b exposed, it is preferable to perform it in an atmosphere that does not contain oxidizing gases or oxygen gases. For example, it is preferable to perform the heat treatment at 400°C for 1 hour in a nitrogen atmosphere. In addition, the above-mentioned heat treatment can also be performed under reduced pressure. Through the above-mentioned heat treatment, the oxygen contained in the insulating layer 280 can be supplied to the semiconductor layer 230 through the insulating layer 250. In addition, by performing the heat treatment during the stage of forming the opening in the insulating layer 280, a portion of the oxygen contained in the insulating layer 280 can be released, thereby adjusting the amount of oxygen contained in the insulating layer 280. As a result, reliability loss due to excess oxygen can be prevented.

[0252] Next, insulating films that will become insulating layers 241a and 241b are deposited along the shape of the aforementioned openings. These insulating films can be deposited using methods such as sputtering, CVD, MBE, PLD, or ALD. Since the insulating films that will become insulating layers 241a and 241b are deposited in openings with high aspect ratios, ALD deposition is preferred. As the insulating films that will become insulating layers 241a and 241b, insulating films with oxygen-suppressing properties are preferred. For example, silicon nitride is preferably deposited using the PEALD method. Silicon nitride has high hydrogen barrier properties, so it is preferred.

[0253] Next, anisotropic etching is performed on the insulating film to form insulating layers 241a and 241b. Here, insulating layer 241a is formed to cover the sidewalls of the openings in conductive layer 242a, and insulating layer 241b is formed to cover the sidewalls of the openings in conductive layer 242b. The anisotropic etching of the insulating film that will become insulating layers 241a and 241b can be performed using dry etching or similar methods. For example, reactive ion etching is preferred. By providing insulating layers 241a and 241b on the sidewalls of the openings, oxygen permeation from the outside can be suppressed, and oxidation of the subsequently formed conductive layers 240a and 240b can be prevented. Furthermore, impurities such as water and hydrogen contained in insulating layer 280 can be prevented from diffusing into conductive layers 240a and 240b. Note that sometimes, due to this anisotropic etching, a recess is formed on a portion of the top surface of conductive layers 242a and 242b.

[0254] Next, a conductive film is deposited to form conductive layers 240a and 240b. This conductive film preferably has a multilayer structure including a conductor that inhibits the permeation of impurities such as water and hydrogen. For example, a multilayer of tantalum nitride, titanium nitride, etc., with tungsten, molybdenum, copper, etc., can be used. The conductive film to form conductive layers 240a and 240b can be deposited using sputtering, CVD, MBE, PLD, or ALD methods.

[0255] Next, by performing CMP treatment, a portion of the conductive film that will become conductive layer 240a and conductive layer 240b is removed, exposing the top surface of insulating layer 285. Figure 12C1 , Figure 12C2 As a result, the conductive film remains only at the aforementioned opening, thereby allowing the formation of conductive layers 240a and 240b with flat top surfaces. Note that sometimes a portion of the top surface of the insulating layer 285 is removed due to this CMP process.

[0256] Alternatively, a heat treatment can be performed after the formation of conductive layers 240a and 240b. This heat treatment can be performed under the same conditions as described above. By performing this heat treatment, the amount of oxygen supplied to the semiconductor layer 230 can be adjusted. This, in turn, improves the electrical characteristics and reliability of the transistor 200.

[0257] Through the above processes, it is possible to manufacture Figures 6A to 6D The transistor 200 shown.

[0258] The transistor 200 shown in this embodiment can be replaced with the transistor 10 shown in Embodiment 1. Thus, a semiconductor device comprising a transistor having a channel formed in a single-crystal substrate and a transistor having a channel formed in an oxide semiconductor film can be realized.

[0259] At least a portion of this embodiment can be implemented in combination with other embodiments described in this specification.

[0260] (Implementation Method 3)

[0261] In this embodiment, refer to Figures 13 to 16 This invention describes a storage device according to one aspect of the present invention. In this embodiment, an example of a storage device structure is described, in which a layer including storage cells is stacked on top of a drive circuit including a readout amplifier.

[0262] As for the transistors included in the drive circuit including the sense amplifier illustrated below, transistors with channels formed in a single-crystal substrate as illustrated in Embodiment 1 (referred to as Si transistors) can be used. Alternatively, as transistors included in the memory cells, transistors with channels formed in a single-crystal oxide semiconductor as illustrated in Embodiment 1 (referred to as OS transistors) can be used.

[0263] <Example of storage device structure>

[0264] Figure 13 A block diagram illustrating a structural example of a storage device 480 according to one aspect of the present invention. Figure 13 The storage device 480 shown includes a layer 420 and a stacked layer 470.

[0265] Layer 420 is a layer that includes Si transistors. In layer 470, element layers 430[1] to 430[m] (m is an integer greater than or equal to 2) are stacked. Element layers 430[1] to 430[m] are layers that include OS transistors. Layer 470, which has layers including OS transistors, can be stacked on layer 420.

[0266] The OS transistors and capacitors included in the element layers 430[1] to 430[m] constitute the memory cells. Figure 13An example is shown in which a plurality of storage cells 432, arranged in a matrix of m rows and n columns (n ​​being an integer greater than 2), are included in element layers 430[1] to 430[m].

[0267] exist Figure 13 In this embodiment, the storage unit 432 in the first row and first column is represented as storage unit 432[1, 1], and the storage unit 432 in the m-th row and n-th column is represented as storage unit 432[m, n]. Furthermore, in this embodiment, etc., sometimes "row i" is used to represent any row. Also, sometimes "column j" is used to represent any column. Therefore, i is an integer greater than or equal to 1 and less than or equal to m, and j is an integer greater than or equal to 1 and less than or equal to n. Furthermore, in this embodiment, etc., the storage unit 432 in the i-th row and j-th column is represented as storage unit 432[i, j]. Note that in this embodiment, etc., when represented as "i+α" (α is a positive or negative integer), "i+α" is not less than 1 and not greater than m. Similarly, when represented as "j+α", "j+α" is not less than 1 and not greater than n.

[0268] Furthermore, as an example, Figure 13 The diagram shows m wirings WL extending in the row direction, m wirings PL extending in the row direction, and n wirings BL extending in the column direction. In this embodiment, the first (row 1) wiring WL is denoted as wiring WL[1], and the m (row 1) wiring WL is denoted as wiring WL[m]. Similarly, the first (row 1) wiring PL is denoted as wiring PL[1], and the m (row 1) wiring PL is denoted as wiring PL[m]. Similarly, the first (column 1) wiring BL is denoted as wiring BL[1], and the n (column 1) wiring BL is denoted as wiring BL[n]. Note that the number of component layers 430[1] to 430[m] and the number of wirings WL (and wiring PL) may be different.

[0269] Multiple storage cells 432 located in row i are electrically connected to the wiring WL (wiring WL[i]) and wiring PL (wiring PL[i]) in row i. Multiple storage cells 432 located in column j are electrically connected to the wiring BL (wiring BL[j]) in column j.

[0270] Wiring BL is used as the bit line for writing and reading data. Wiring WL is used as the word line for controlling the on or off (conducting or de-conducting) state of the access transistors used as switches. Wiring PL is used as the constant potential line connected to the capacitor. Additionally, wiring for transmitting the back gate potential can be provided separately.

[0271] The memory cells 432 included in the element layers 430[1] to 430[m] are connected to the sense amplifier 446 via wiring BL. The wiring BL can be configured in a direction parallel to or perpendicular to the surface of the substrate on which the layer 420 is disposed. By forming the wiring BL extending from the memory cells 432 included in the element layers 430[1] to 430[m] by wiring configured in a direction parallel to the substrate surface and wiring configured in a direction perpendicular to the substrate surface, the wiring length between the element layer 430 and the sense amplifier 446 can be shortened. Since the signal transmission distance between the memory cells and the sense amplifier can be shortened and the resistance and parasitic capacitance of the bit lines can be significantly reduced, power consumption and signal delay can be reduced. Thus, the power consumption and signal delay of the memory device 480 can be reduced. Furthermore, it can operate even if the capacitance of the capacitors included in the memory cells 432 is reduced. Thus, the miniaturization of the memory device 480 can be achieved.

[0272] Layer 420 includes PSW471 (power switch), PSW472, and peripheral circuitry 422. Peripheral circuitry 422 includes drive circuitry 440, control circuitry 473, and voltage generation circuitry 474. Note that all circuits included in layer 420 are circuits that include Si transistors.

[0273] In the storage device 480, circuits, signals, and voltages can be appropriately selected or omitted as needed. Alternatively, other circuits or signals can be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are signals input from the outside, while signal RDA is a signal output to the outside. Signal CLK is the clock signal.

[0274] In addition, signals BW, CE, and GW are control signals. Signal CE is the chip enable signal, signal GW is the global write enable signal, and signal BW is the byte write enable signal. Signal ADDR is the address signal. Signal WDA is the write data signal, and signal RDA is the read data signal. Signals PON1 and PON2 are power gating control signals. Furthermore, signals PON1 and PON2 can also be generated in control circuit 473.

[0275] The control circuit 473 is a logic circuit that controls the overall operation of the storage device 480. For example, the control circuit performs logical operations on signals CE, GW, and BW to determine the operating mode of the storage device 480 (e.g., write operation, read operation). Alternatively, the control circuit 473 generates control signals for the drive circuit 440 to execute the aforementioned operating mode.

[0276] The voltage generation circuit 474 has the function of generating a negative voltage. The signal WAKE has the function of controlling the input signal CLK to the voltage generation circuit 474. For example, when a signal of level H is applied as the signal WAKE, the signal CLK is input to the voltage generation circuit 474, and the voltage generation circuit 474 generates a negative voltage.

[0277] The driver circuit 440 is used to write and read data from the storage unit 432. In addition to the row decoder 442, column decoder 444, row driver 443, column driver 445, input circuit 447, and output circuit 448, the driver circuit 440 also includes the aforementioned sense amplifier 446.

[0278] Row decoder 442 and column decoder 444 are used to decode the signal ADDR. Row decoder 442 is used to specify the circuit to be accessed in a row, and column decoder 444 is used to specify the circuit to be accessed in a column. Row driver 443 is used to select the wiring WL specified by row decoder 442. Column driver 445 has the following functions: writing data to memory cell 432; reading data from memory cell 432; and storing the read data.

[0279] Input circuit 447 has the function of holding signal WDA. The data held in input circuit 447 is output to column driver 445. The output data of input circuit 447 is the data written to memory cell 432 (Din). The data read from memory cell 432 by column driver 445 (Dout) is output to output circuit 448. Output circuit 448 has the function of holding Dout. In addition, output circuit 448 has the function of outputting Dout to the outside of memory device 480. The data output from output circuit 448 is signal RDA.

[0280] PSW471 controls the supply of VDD to the peripheral circuit 422. PSW472 controls the supply of VHM to the row driver 443. Here, the high supply voltage of the storage device 480 is VDD, and the low supply voltage is GND (ground potential). Furthermore, VHM is a high supply potential used to make the word line high, which is higher than VDD. Signal PON1 controls the on / off state of PSW471, and signal PON2 controls the on / off state of PSW472. Figure 13 In the peripheral circuit 422, the number of power domains supplied with VDD is 1, but it can also be multiple. In this case, a power switch can be set for each power domain.

[0281] Component layers 430[1] to 430[m] can be stacked on layer 420. Figure 14A This is a perspective view of a storage device 480 in which five (m=5) element layers 430[1] to 430[5] are stacked on layer 420.

[0282] exist Figure 14A In this context, the component layer 430 located in the first layer is referred to as component layer 430[1], the component layer 430 located in the second layer is referred to as component layer 430[2], and the component layer 430 located in the fifth layer is referred to as component layer 430[5]. Furthermore, Figure 14A The diagram shows wirings WL and PL extending in the X direction, and wirings BL and BLB extending in the Y and Z directions (perpendicular to the substrate surface where the drive circuitry is located). Wiring BLB is an inverted bit line. Note that for clarity, a portion of the wirings WL and PL included in each of component layers 430 is omitted from the description.

[0283] Figure 14B This is an explanation Figure 14A The schematic diagram shows an example of a structure of a sense amplifier 446 connected to wiring BL and wiring BLB and a memory cell 432 included in the component layers 430[1] to 430[5] connected to wiring BL and wiring BLB. In addition, a structure in which multiple memory cells (memory cells 432) are electrically connected to a wiring BL and wiring BLB is also called a "memory string".

[0284] Figure 14B An example of the circuit structure of a memory cell 432 connected to a wiring BLB is shown. The memory cell 432 includes a transistor 437 and a capacitor 438. Regarding the transistor 437, the capacitor 438 and the wirings (BL and WL, etc.), wiring BL[1] and wiring WL[1] are sometimes referred to as wiring BL and wiring WL, etc.

[0285] In memory cell 432, one of the source and drain of transistor 437 is connected to wiring BL. The other of the source and drain of transistor 437 is connected to one electrode of capacitor 438. The other electrode of capacitor 438 is connected to wiring PL. The gate of transistor 437 is connected to wiring WL.

[0286] The wiring PL is a wire that supplies a constant potential to maintain the potential of capacitor 438. The number of wires can be reduced by connecting multiple wiring PLs together as a single wire.

[0287] In one embodiment of the present invention, while stacking OS transistors, wiring used as bit lines is arranged in a direction perpendicular to the surface of the substrate on which layer 420 is disposed. Furthermore, transistors 437 and capacitors 438 included in the memory cell 432 are arranged in a direction perpendicular to the surface of the substrate on which layer 420 is disposed. By arranging each element and each wiring in a direction perpendicular to the substrate surface, the wiring length between element layers can be shortened, and the element density per unit area can be increased. Thus, a memory device with excellent storage capacity and reduced power consumption can be realized.

[0288] [Structure example of memory cell 432 and sense amplifier 446]

[0289] Figure 15A and Figure 15B This is a circuit diagram corresponding to the aforementioned storage unit 432 and a diagram of the circuit blocks corresponding to that circuit diagram. For example... Figure 15A and Figure 15B As shown, storage unit 432 is sometimes represented as a block in accompanying drawings, etc. Furthermore, in... Figure 15A and Figure 15B The same representation can be used when the wiring BL shown is replaced with wiring BLB.

[0290] also, Figure 15C and Figure 15D This is a circuit diagram corresponding to the aforementioned readout amplifier 446 and a diagram of the circuit blocks corresponding to that circuit diagram. The readout amplifier 446 shows a switching circuit 482, a pre-charge circuit 483, a pre-charge circuit 484, and an amplification circuit 485. In addition to wiring BL and BLB, wiring SA_OUT and SA_OUTB, which output the read signal, are also shown.

[0291] like Figure 15C As shown, the switching circuit 482 includes, for example, N-type transistors 482_1 and 482_2. Transistors 482_1 and 482_2 switch the conduction state of wiring pairs SA_OUT and SA_OUTB, as well as wiring pairs BL and BLB, according to the signal CSEL.

[0292] like Figure 15C As shown, the pre-charge circuit 483 is composed of N-type transistors 483_1 to 483_3. The pre-charge circuit 483 is used to pre-charge wiring BL and wiring BLB to an intermediate potential VPRE equivalent to potential VDD / 2 according to the signal EQ.

[0293] like Figure 15CAs shown, the pre-charge circuit 484 is composed of P-type transistors 484_1 to 484_3. The pre-charge circuit 484 is used to pre-charge wiring BL and wiring BLB to an intermediate potential VPRE equivalent to potential VDD / 2 according to the signal EQB.

[0294] like Figure 15C As shown, the amplifier circuit 485 consists of P-type transistors 485_1 and 485_2 and N-type transistors 485_3 and 485_4 connected to the wiring SAP or wiring SAN. The wiring SAP or wiring SAN is a wiring that supplies VDD or VSS. Transistors 485_1 to 485_4 are transistors that form the inverter loop.

[0295] also, Figure 15D It corresponds to Figure 15C The circuit block diagram of the readout amplifier 446 is described in the example. Figure 15D As shown, the readout amplifier 446 is sometimes represented as a block in the accompanying drawings, etc.

[0296] Figure 16 yes Figure 13 The circuit diagram of storage device 480. Figure 16 Use Figures 15A to 15D The circuit blocks described in the text.

[0297] like Figure 16 As shown, layer 470, having element layer 430[m], includes storage cells 432. As an example, Figure 16 The storage unit 432 shown is connected to a pair of wirings BL[1] and BLB[1] or BL[2] and BLB[2]. The storage unit 432 connected to the wiring BL is a storage unit for writing or reading data.

[0298] Wiring BL[1] and wiring BLB[1] are connected to the readout amplifier 446[1], and wiring BL[2] and wiring BLB[2] are connected to the readout amplifier 446[2]. The readout amplifier 446[1] and readout amplifier 446[2] can be configured according to... Figure 15C The data is read from the various signals described in the text.

[0299] At least a portion of this embodiment can be implemented in combination with other embodiments described in this specification.

[0300] (Implementation Method 4)

[0301] In this embodiment, an example of the structure of a display device using a transistor according to one aspect of the present invention will be described.

[0302] The transistor of one aspect of the present invention can be formed into an extremely miniature form, so a display device using the transistor of one aspect of the present invention can be an extremely high-definition display device. For example, the display device of one aspect of the present invention can be used in the display section of information terminal devices (wearable devices) such as watch-type and bracelet-type devices, and in the display section of VR devices such as head-mounted displays and AR devices such as glasses-type devices (HMDs).

[0303] In one embodiment of the present invention, the display device may have a driving circuit and a pixel circuit arranged in an overlapping manner. In this case, the transistor constituting the driving circuit may be a transistor with a channel formed in a single crystal substrate as illustrated in Embodiment 1, and the transistor constituting the pixel may be a transistor with a channel formed in a single crystal oxide semiconductor.

[0304] [Display Module]

[0305] Figure 17A A perspective view of display module 580 is shown. Display module 580 includes display device 500A and FPC 590.

[0306] The display module 580 includes a substrate 591 and a substrate 592. The display module 580 includes a display section 581. The display section 581 is an area for displaying images.

[0307] Figure 17B A perspective view of one side of the structure of substrate 591 is shown. A circuit section 582, a pixel circuit section 583 on the circuit section 582, and a pixel section 584 on the pixel circuit section 583 are stacked on the substrate 591. Furthermore, a terminal section 585 for connecting to the FPC 590 is provided on a portion of the substrate 591 that does not overlap with the pixel section 584. The terminal section 585 is electrically connected to the circuit section 582 via a wiring section 586 composed of multiple wirings.

[0308] The pixel unit 584 includes a plurality of pixels 584a arranged periodically. Figure 17B The right side shows an enlarged view of pixel 584a. Pixel 584a includes a light-emitting element 110R that emits red light, a light-emitting element 110G that emits green light, and a light-emitting element 110B that emits blue light.

[0309] The pixel circuit section 583 includes a plurality of pixel circuits 583a arranged periodically. One pixel circuit 583a controls the light emission of three light-emitting devices included in one pixel 584a. One pixel circuit 583a may include three circuits controlling the light emission of one light-emitting device. For example, the pixel circuit 583a may adopt a structure having at least one selection transistor, one current control transistor (driving transistor), and a capacitor for each light-emitting device. In this case, the gate of the selection transistor is input with a gate signal, and the source is input with a source signal. Thus, an active matrix display panel can be realized.

[0310] The circuit section 582 includes circuitry for driving each pixel circuit 583a of the pixel circuit section 583. For example, it preferably includes one or both of a gate line driving circuit and a source line driving circuit. Furthermore, it may include at least one of an arithmetic circuit, a storage circuit, and a power supply circuit. Additionally, transistors disposed in the circuit section 582 may also constitute part of the pixel circuit 583a. That is, the pixel circuit 583a may be constituted by transistors included in the pixel circuit section 583 and transistors included in the circuit section 582.

[0311] The FPC590 is used for wiring to supply video signals or power potentials to the circuit section 582 from the outside. Additionally, ICs can be mounted on the FPC590.

[0312] The display module 580 can employ a structure in which one or both of the pixel circuit section 583 and circuit section 582 are stacked on the lower side of the pixel section 584, thus enabling the display section 581 to have an extremely high aperture ratio (effective display area ratio). For example, the aperture ratio of the display section 581 can be 40% or more and less than 100%, preferably 50% or more and less than 95%, more preferably 60% or more and less than 95%. Furthermore, the pixels 584a can be arranged in an extremely high density, thereby enabling the display section 581 to have extremely high resolution. For example, the display section 581 preferably has pixels 584a arranged with a resolution of 2000 ppi or more, more preferably 3000 ppi or more, further preferably 5000 ppi or more, and even more preferably 6000 ppi or more and less than 20000 ppi or less, or less than 30000 ppi.

[0313] This display module 580 is extremely clear, making it suitable for use in VR devices such as head-mounted displays or AR devices such as glasses. For example, because the display module 580 has a display section 581 with extremely high clarity, even when the user magnifies the display section through a lens, the pixels are not visible, thus achieving a highly immersive display. Furthermore, the display module 580 can also be applied to electronic devices with relatively small display sections. For example, it is suitable for use in the display sections of wearable electronic devices such as watches.

[0314] [Display Device 500A]

[0315] Figure 18 The display device 500A shown includes a substrate 301, light-emitting elements 110R, 110G, 110B, a capacitor 540, a transistor 310, and a transistor 320.

[0316] Transistor 310 corresponds to transistor 50, whose channel is formed in a single-crystal substrate, as illustrated in Embodiment 1. Furthermore, transistor 320 corresponds to transistor 10 or transistor 200, whose channel is formed in a single-crystal oxide semiconductor, as illustrated in Embodiments 1 and 2. Transistor 320 can use various transistors shown in Embodiment 2.

[0317] Transistor 310 is a transistor having a channel formation region in substrate 301. Substrate 301 can be, for example, a semiconductor substrate such as a single-crystal silicon substrate. Transistor 310 includes a portion of substrate 301, a conductive layer 311, a low-resistance region 312, an insulating layer 313, and an insulating layer 314. Conductive layer 311 serves as the gate electrode. Insulating layer 313 is located between substrate 301 and conductive layer 311 and serves as the gate insulating layer. Low-resistance region 312 is a region in substrate 301 doped with impurities and serves as one of the source and drain electrodes. Insulating layer 314 covers the sides of conductive layer 311.

[0318] In addition, a component separation layer 315 is provided between two adjacent transistors 310 in a manner embedded in the substrate 301.

[0319] Transistor 320 includes a semiconductor layer 351, an insulating layer 353, a conductive layer 354, a pair of conductive layers 355, an insulating layer 360, and a conductive layer 357.

[0320] A wiring layer 371 and a wiring layer 361 are disposed between the layer where transistor 310 is disposed and the layer where transistor 320 is disposed. Wiring layer 371 includes, at least at its uppermost part, an insulating layer 372 and a conductive layer 373 embedded in the insulating layer 372. Wiring layer 361 includes, at least at its lowermost part, an insulating layer 362 and a conductive layer 363 embedded in the insulating layer 362. The display device 500A is manufactured by bonding the wiring layers 361 and 371. In other words, the insulating layer 372, conductive layer 373, insulating layer 362, and conductive layer 363 all have bonding surfaces. By connecting conductive layer 363 to conductive layer 373, transistor 310 and transistor 320 can be electrically connected via various wiring connections.

[0321] A stacked structure consisting of insulating layer 360 to wiring layer 361 is formed sequentially from one side of insulating layer 360, and then the surface of wiring layer 361 is bonded to substrate 301. Therefore, the vertical relationship of the stacked structure from insulating layer 360 to wiring layer 361 is reversed compared to the vertical relationship of transistor 310, etc.

[0322] Transistor 320 is sandwiched between insulating layer 352 and insulating layer 359. Insulating layer 352 and insulating layer 359 preferably have barrier properties against hydrogen and oxygen. This prevents impurities from diffusing into transistor 320 and prevents oxygen from detaching from semiconductor layer 351. Insulating layer 352 and insulating layer 359 can be, for example, films that are less susceptible to hydrogen or oxygen diffusion than silicon oxide films, such as aluminum oxide films, hafnium oxide films, silicon nitride films, etc.

[0323] An insulating layer 356 and a conductive layer 357 embedded in the insulating layer 356 are disposed on the side closer to the substrate 301 than the insulating layer 352. Additionally, an insulating layer 360 is disposed between the conductive layer 357 and the semiconductor layer 351. The conductive layer 357 serves as the second gate electrode of the transistor 320, and a portion of the insulating layer 360 serves as the second gate insulating layer.

[0324] The insulating layer 360 is in contact with the semiconductor layer 351. The insulating layer 360 may correspond to the substrate 11 or the base film 12. Alternatively, an insulating film different from the substrate 11 and the base film 12 may be used. In addition, if it is difficult to reduce the thickness of the substrate 11 when using it as the insulating layer 360, the back gate may not be provided.

[0325] A semiconductor layer 351 is disposed on one side of the substrate 301 of the insulating layer 360. The semiconductor layer 351 preferably comprises a metal oxide (also known as an oxide semiconductor) film exhibiting semiconductor properties. A pair of conductive layers 355 are in contact with the semiconductor layer 351 and are used as source and drain electrodes.

[0326] An insulating layer 358 and an insulating layer 350 are provided to cover a pair of conductive layers 355 and a semiconductor layer 351. The insulating layer 358 serves as a barrier layer, preventing impurities such as water or hydrogen from diffusing into the semiconductor layer 351 and preventing oxygen from escaping from the semiconductor layer 351. The same insulating film as the insulating layer 352 described above can be used as the insulating layer 358. The insulating layer 350 serves as an interlayer insulating layer.

[0327] An opening is provided in insulating layer 358 and insulating layer 350 to reach semiconductor layer 351. An insulating layer 353 and a conductive layer 354, which are in contact with the top surface of semiconductor layer 351, are embedded inside the opening. The conductive layer 354 is used as a first gate electrode, and the insulating layer 353 is used as a first gate insulating layer.

[0328] The top surfaces of conductive layer 354, insulating layer 353, and insulating layer 350 (the surface on one side of substrate 301) are planarized to have the same or substantially the same height, and an insulating layer 359 is provided to cover them. The insulating layer 359 serves as a barrier layer to prevent impurities such as water or hydrogen from diffusing into the transistor 320. The insulating layer 359 can use the same insulating film as the insulating layer 352 described above.

[0329] Transistor 320 employs a structure in which a semiconductor layer forming a channel is sandwiched between two gates. Alternatively, the two gates can be connected and the same signal can be supplied to both gates to drive the transistor. Alternatively, the threshold voltage of the transistor can be controlled by applying a potential to one of the two gates to control the threshold voltage and applying a potential to the other to drive it.

[0330] An insulating layer 565 is provided in such a manner that it covers the insulating layer 359. The insulating layer 565 is used as an interlayer insulating layer.

[0331] A plug 575, electrically connected to one of the pair of conductive layers 355, is embedded in insulating layers 565, 359, 350, and 358. Preferably, the plug 575 includes a conductive layer 575a covering the side of the opening in the insulating layer 565 and a portion of the conductive layer 355, and a conductive layer 575b in contact with the conductive layer 575a. In this case, a conductive material that does not readily diffuse with oxygen is preferably used as the conductive layer 575a.

[0332] A conductive layer 364 is provided on one side of the substrate 301 of the insulating layer 565. The plug 575 connects the conductive layer 355 and the conductive layer 364.

[0333] In addition, a capacitor 540 is disposed on the insulating layer 564. The capacitor 540 includes a conductive layer 541, a conductive layer 545, and an insulating layer 543 located therebetween. The conductive layer 541 serves as one electrode of the capacitor 540, the conductive layer 545 serves as the other electrode of the capacitor 540, and the insulating layer 543 serves as the dielectric of the capacitor 540.

[0334] Conductive layer 541 is embedded in insulating layer 554 disposed on insulating layer 564. Conductive layer 541 is electrically connected to conductive layer 364 via connector 574. Insulating layer 543 is disposed covering conductive layer 541. Conductive layer 545 is disposed in the area where it overlaps with conductive layer 541 across insulating layer 543. Conductive layer 541 is connected to conductive layer 355 of transistor 320 via connector 574, conductive layer 364, and connector 575.

[0335] The plug 574 is disposed in an insulating layer 564, insulating layer 352, insulating layer 356, insulating layer 358, insulating layer 350, insulating layer 359 and insulating layer 565, and includes a conductive layer 574a and a conductive layer 574b. As the conductive layer 574a, a conductive material that does not easily diffuse with oxygen is preferably used.

[0336] An insulating layer 555a is provided to cover the capacitor 540, an insulating layer 555b is provided on the insulating layer 555a, and an insulating layer 555c is provided on the insulating layer 555b.

[0337] Inorganic insulating films can be appropriately used for insulating layers 555a, 555b, and 555c. For example, it is preferable to use silicon oxide films as insulating layers 555a and 555c, and silicon nitride films as insulating layer 555b. Thus, insulating layer 555b can be used as an etching protective film. Although an example is shown in this embodiment where a portion of insulating layer 555c is etched to form a recess, it is also possible not to form a recess in insulating layer 555c.

[0338] The insulating layer 555c is provided with light-emitting elements 110R, 110G and 110B.

[0339] Light-emitting element 110R includes a pixel electrode 111R, an organic layer 112R, a common layer 114, and a common electrode 113. Light-emitting element 110G includes a pixel electrode 111G, an organic layer 112G, a common layer 114, and a common electrode 113. Light-emitting element 110B includes a pixel electrode 111B, an organic layer 112B, a common layer 114, and a common electrode 113. The common layer 114 and the common electrode 113 are jointly disposed in light-emitting elements 110R, 110G, and 110B.

[0340] The organic layer 112R included in the light-emitting element 110R contains a light-emitting organic compound that emits at least red light. The organic layer 112G included in the light-emitting element 110G contains a light-emitting organic compound that emits at least green light. The organic layer 112B included in the light-emitting element 110B contains a light-emitting organic compound that emits at least blue light. Organic layers 112R, 112G, and 112B may each be referred to as EL layers, and each includes at least a layer (light-emitting layer) containing a light-emitting organic compound.

[0341] The display device 500A forms light-emitting devices separately for each light-emitting color, resulting in minimal chromaticity variation between low-brightness and high-brightness light emission. Furthermore, the organic layers 112R, 112G, and 112B are separated from each other, thus suppressing crosstalk between adjacent sub-pixels even when using a high-definition display panel. Therefore, a high-definition display panel with high display quality can be achieved.

[0342] An insulating layer 125, a resin layer 126, and a layer 128 are provided in the area between adjacent light-emitting elements.

[0343] The pixel electrodes 111R, 111G, and 111B of the light-emitting element are electrically connected to the conductive layer 355 of the transistor 320 via a plug 556 embedded in insulating layers 555a, 555b, and 555c, a conductive layer 541 embedded in insulating layer 554, and a plug 574. The height of the top surface of insulating layer 555c is the same as or approximately the same as the height of the top surface of plug 556. Various conductive materials can be used as the plug.

[0344] In addition, a protective layer 121 is provided on the light-emitting elements 110R, 110G and 110B. A substrate 170 is attached to the protective layer 121 by an adhesive layer 171.

[0345] No insulating layer covering the top surface of the pixel electrode 111 is provided between two adjacent pixel electrodes 111. Therefore, the spacing between adjacent light-emitting elements can be very small. Thus, a high-definition or high-resolution display device can be realized.

[0346] At least a portion of this embodiment can be implemented in combination with other embodiments described in this specification.

[0347] (Implementation Method 5)

[0348] In this embodiment, an example of the structure of a display device that can be used in a display device manufactured using a transistor according to one aspect of the present invention will be described. The display device shown below can be used in the pixel unit 584, etc., of Embodiment 4 described above.

[0349] In one aspect of the present invention, the EL layer is processed into a fine pattern using photolithography without using a shadow mask such as a fine metal mask (FMM). Therefore, a display device with high resolution and high aperture ratio, which is currently difficult to achieve, can be realized. Furthermore, since the EL layer can be manufactured separately, a display device with very vivid and high contrast can be realized. Alternatively, for example, both a metal mask and photolithography can be used to process the EL layer into a fine pattern.

[0350] Furthermore, part or all of the EL layer can be physically separated. This suppresses leakage current between light-emitting elements via a layer shared by adjacent light-emitting elements (also known as a common layer). Therefore, crosstalk caused by unintentional light emission can be suppressed, enabling display devices with very high contrast. In particular, display devices with high current efficiency at low brightness can be achieved.

[0351] One aspect of the present invention can also realize a display device that combines a white light-emitting element and a color filter. In this case, light-emitting elements with the same structure can be used for each light-emitting element in a pixel (sub-pixel) that emits light of different colors, and all layers in each light-emitting element can be used as a common layer. Furthermore, some or all of each EL layer can be cut using photolithography. As a result, leakage current through the common layer can be suppressed, and a display device with high contrast can be realized. In particular, in a device having a series structure of multiple light-emitting layers stacked with a highly conductive intermediate layer, leakage current through the intermediate layer can be effectively prevented, so a display device with high brightness, high definition, and high contrast can be realized.

[0352] When processing the EL layer using photolithography, degradation can sometimes occur due to partial exposure of the light-emitting layer. Therefore, it is preferable to provide an insulating layer that at least covers the sides of the island-shaped light-emitting layer. This insulating layer may also cover a portion of the top surface of the island-shaped EL layer. This insulating layer is preferably made of a material that blocks water and oxygen. For example, an inorganic insulating film that does not readily diffuse water or oxygen can be used. This suppresses degradation of the EL layer, enabling a highly reliable display device.

[0353] Furthermore, there is a region (recess) between two adjacent light-emitting elements where the EL layer of each light-emitting element is not disposed. When a common electrode or a common electrode and a common layer are formed to cover this recess, the common electrode sometimes breaks off due to a step at the end of the EL layer (also known as a break), resulting in the common electrode on the EL layer being insulated. Therefore, it is preferable to use a structure that fills the localized step between two adjacent light-emitting elements with a resin layer used as a planarization film (also known as LFP: Local Filling Planarization). This resin layer is used as a planarization film. As a result, the breakage of the common layer or common electrode can be suppressed, and a display device with high reliability can be realized.

[0354] Hereinafter, a more specific structural example of a display device according to one aspect of the present invention will be described with reference to the accompanying drawings.

[0355] [Structure Example 1]

[0356] Figure 19A This diagram illustrates a top view of a display device 100 according to one embodiment of the present invention. The display device 100 includes, on a substrate 101, a plurality of red-emitting elements 110R, a plurality of green-emitting elements 110G, and a plurality of blue-emitting elements 110B. Figure 19A To facilitate the differentiation of each light-emitting element, the symbols “R”, “G”, and “B” are attached to the light-emitting area of ​​each element.

[0357] The light-emitting elements 110R, 110G and 110B are all arranged in a matrix. Figure 19A This illustrates a so-called stripe arrangement where light-emitting elements of the same color are arranged in one direction. Note that the arrangement of light-emitting elements is not limited to this; other arrangements such as S-stripes, Delta, Bayer, and zigzag can also be used, as well as Pentile and Diamond arrangements.

[0358] As the light-emitting element 110R, the light-emitting element 110G, and the light-emitting element 110B, it is preferable to use an OLED (Organic Light Emitting Diode) or a QLED (Quantum-dot Light Emitting Diode). Examples of the light-emitting substance contained in the EL element include a substance that emits fluorescence (fluorescent material), a substance that emits phosphorescence (phosphorescent material), and a substance exhibiting thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) material). As the light-emitting substance contained in the EL element, an inorganic compound (quantum dot material, etc.) can be used in addition to an organic compound.

[0359] In addition, Figure 19A shows a connection electrode 111C electrically connected to the common electrode 113. The connection electrode 111C is supplied with a potential to be supplied to the common electrode 113 (for example, an anode potential or a cathode potential). The connection electrode 111C is disposed outside the display region where the light-emitting elements 110R and the like are arranged.

[0360] The connection electrode 111C may be disposed along the outer periphery of the display region. For example, it may be disposed along one side of the outer periphery of the display region, or may be disposed across two or more sides of the outer periphery of the display region. That is, when the top surface shape of the display region is a rectangle, the top surface shape of the connection electrode 111C may be a strip shape (rectangle), an L shape, a "U" shape (square bracket shape), a quadrangle, or the like.

[0361] Figure 19B , Figure 19C are respectively corresponding to Figure 19A are schematic cross-sectional views corresponding to the dashed-dotted line A1-A2 and the dashed-dotted line A3-A4 in the drawing. Figure 19B is a schematic cross-sectional view showing the light-emitting element 110R, the light-emitting element 110G, and the light-emitting element 110B, Figure 19C is a schematic cross-sectional view showing the connection portion 140 where the connection electrode 111C is connected to the common electrode 113.

[0362] The light-emitting element 110R includes a pixel electrode 111R, an organic layer 112R, a common layer 114, and a common electrode 113. The light-emitting element 110G includes a pixel electrode 111G, an organic layer 112G, the common layer 114, and the common electrode 113. The light-emitting element 110B includes a pixel electrode 111B, an organic layer 112B, the common layer 114, and the common electrode 113. The light-emitting element 110R, the light-emitting element 110G, and the light-emitting element 110B share the common layer 114 and the common electrode 113.

[0363] The organic layer 112R included in the light-emitting element 110R contains a light-emitting organic compound that emits at least red light. The organic layer 112G included in the light-emitting element 110G contains a light-emitting organic compound that emits at least green light. The organic layer 112B included in the light-emitting element 110B contains a light-emitting organic compound that emits at least blue light. Organic layers 112R, 112G, and 112B may each be referred to as EL layers, and each includes at least a layer (light-emitting layer) containing a light-emitting organic compound.

[0364] Hereinafter, when describing the common elements among light-emitting elements 110R, 110G, and 110B, they will sometimes be referred to as light-emitting element 110. Similarly, when describing the common elements among components such as organic layers 112R, 112G, and 112B, which are distinguished by letters, symbols with omitted letters will sometimes be used.

[0365] The organic layer 112 and the common layer 114 may each independently include one or more of an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer. For example, the organic layer 112 has a stacked structure of a hole injection layer, a hole transport layer, a light-emitting layer, and an electron transport layer stacked from the pixel electrode 111 side, and the common layer 114 includes an electron injection layer.

[0366] Pixel electrodes 111R, 111G, and 111B are all disposed in each light-emitting element. Furthermore, a common electrode 113 and a common layer 114 are provided as a single layer shared by all light-emitting elements. One of the pixel electrodes and the common electrode 113 uses a conductive film that is transparent to visible light, while the other uses a reflective conductive film. By making each pixel electrode transparent and the common electrode 113 reflective, a bottom-emitting type (bottom-emitting structure) display device can be realized; conversely, by making each pixel electrode reflective and the common electrode 113 transparent, a top-emitting type (top-emitting structure) display device can be realized. Furthermore, by making both the pixel electrode and the common electrode 113 transparent, a double-sided emitting type (double-sided emitting structure) display device can also be realized.

[0367] A protective layer 121 is provided on the common electrode 113 to cover the light-emitting elements 110R, 110G, and 110B. The protective layer 121 has the function of preventing impurities such as water from diffusing from above to each light-emitting element.

[0368] The end of the pixel electrode 111 preferably has a tapered shape. When the end of the pixel electrode 111 has a tapered shape, the organic layer 112 disposed along the end of the pixel electrode 111 can also have a tapered shape. By making the end of the pixel electrode 111 tapered, the coverage of the organic layer 112 disposed across the end of the pixel electrode 111 can be improved. Furthermore, by making the side of the pixel electrode 111 tapered, foreign matter (e.g., dust or particles) from the manufacturing process can be easily removed by washing or other processes, which is therefore preferred.

[0369] For example, it is preferable to have a region where the angle (also called the cone angle) formed by the inclined side and the substrate surface is less than 90°.

[0370] The organic layer 112 is processed into an island shape using photolithography. Therefore, the organic layer 112 has a shape at its ends where the angle between the top surface and the side surface is close to 90°. On the other hand, the thickness of organic films formed using FMM (Fine Metal Mask) and the like tends to decrease as they approach the ends. For example, the top surface is formed in a slope shape in the range of 1 μm to 10 μm from the ends, making it difficult to distinguish between the top surface and the side surface.

[0371] An insulating layer 125, a resin layer 126, and a layer 128 are provided between two adjacent light-emitting elements.

[0372] Between two adjacent light-emitting elements, the sides of each organic layer 112 are separated by a resin layer 126. The resin layer 126 is located between the two adjacent light-emitting elements and is disposed in such a way that it fills the ends of each organic layer 112 and the area between the two organic layers 112. The top surface of the resin layer 126 has a smooth convex shape, and a common layer 114 and a common electrode 113 are disposed to cover the top surface of the resin layer 126.

[0373] The resin layer 126 serves as a planarization film to fill the step between two adjacent light-emitting elements. By providing the resin layer 126, the common electrode 113 on the organic layer 112 can be prevented from being insulated due to the phenomenon of the step being interrupted at the end of the organic layer 112 (also known as a break). The resin layer 126 can also be referred to as an LFP (Local Filling Planarization) layer.

[0374] As resin layer 126, an insulating layer containing organic materials can be suitable. For example, acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimide amide resin, silicone resin, siloxane resin, benzocyclobutene resin, phenolic resin, and precursors of the above resins can be used as resin layer 126. Furthermore, organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerol, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin can also be used as resin layer 126.

[0375] Furthermore, a photosensitive resin can be used as the resin layer 126. A photoresist can also be used as the photosensitive resin. The photosensitive resin can be either a positive or negative material.

[0376] The resin layer 126 may also contain a material that absorbs visible light. For example, the resin layer 126 itself may be composed of a material that absorbs visible light, and the resin layer 126 may also contain a pigment that absorbs visible light. As the resin layer 126, for example, a resin that can be used as a color filter that transmits red, blue, or green light and absorbs other light; or a resin that contains carbon black as a pigment and is used as a black matrix; etc.

[0377] The insulating layer 125 contacts the side surface of the organic layer 112. Furthermore, the insulating layer 125 covers the upper end of the organic layer 112. Additionally, a portion of the insulating layer 125 contacts the top surface of the substrate 101.

[0378] An insulating layer 125 is located between the resin layer 126 and the organic layer 112 and serves as a protective film to prevent the resin layer 126 from contacting the organic layer 112. When the organic layer 112 comes into contact with the resin layer 126, the organic layer 112 may be dissolved due to organic solvents or the like used in forming the resin layer 126. Therefore, by providing an insulating layer 125 between the organic layer 112 and the resin layer 126, the sides of the organic layer 112 can be protected.

[0379] The insulating layer 125 can be an insulating layer containing inorganic materials. Inorganic insulating films such as oxide insulating films, nitride insulating films, oxynitride insulating films, and oxynitride insulating films can be used as the insulating layer 125. The insulating layer 125 can be a single-layer structure or a multilayer structure. Examples of oxide insulating films include silicon oxide films, aluminum oxide films, magnesium oxide films, indium gallium zinc oxide films, gallium oxide films, germanium oxide films, yttrium oxide films, zirconium oxide films, lanthanum oxide films, neodymium oxide films, hafnium oxide films, and tantalum oxide films. Examples of nitride insulating films include silicon nitride films and aluminum nitride films. Examples of oxynitride insulating films include silicon oxynitride films and aluminum oxynitride films. Examples of oxynitride insulating films include silicon oxynitride films and aluminum oxynitride films. In particular, by using inorganic insulating films such as alumina films, hafnium oxide films, and silicon oxide films formed by the ALD method to form insulating layer 125, an insulating layer 125 with fewer pinholes and excellent protection of the EL layer can be formed.

[0380] The insulating layer 125 can be formed using sputtering, CVD, PLD, ALD, or other methods. The insulating layer 125 is preferably formed using the ALD method, which provides good coverage.

[0381] Alternatively, a reflective film (e.g., a metal film selected from one or more of silver, palladium, copper, titanium, and aluminum) can be provided between the insulating layer 125 and the resin layer 126 to reflect the light emitted by the light-emitting layer. This can further improve the light extraction efficiency.

[0382] Layer 128 is a residual portion of a protective layer (also called a mask layer or sacrificial layer) used to protect the organic layer 112 during etching. Layer 128 can use a material that can also be used for the aforementioned insulating layer 125. In particular, it is preferable that both layer 128 and insulating layer 125 are made of the same material, thereby allowing the use of the same processing equipment, etc.

[0383] In particular, inorganic insulating films such as alumina films, hafnium oxide films, and silicon oxide films formed by the ALD method have fewer pinholes, thus providing excellent protection for the EL layer. Therefore, they are suitable for use in insulating layers 125 and 128.

[0384] The protective layer 121 may, for example, have a single-layer structure or a multilayer structure comprising at least an inorganic insulating film. Examples of inorganic insulating films include oxide films or nitride films such as silicon oxide films, silicon oxynitride films, silicon oxynitride films, silicon nitride films, aluminum oxide films, aluminum oxynitride films, and hafnium oxide films. Alternatively, semiconductor or conductive materials such as indium gallium oxide, indium zinc oxide, indium tin oxide, and indium gallium zinc oxide may be used as the protective layer 121.

[0385] The protective layer 121 can also be a laminate of an inorganic insulating film and an organic insulating film. For example, it is preferable to sandwich an organic insulating film between a pair of inorganic insulating films. Furthermore, the organic insulating film is preferably used as a planarization film. Therefore, the top surface of the organic insulating film can be flattened, thus improving the coverage of the inorganic insulating film thereon, thereby improving the barrier properties. In addition, the flattened top surface of the protective layer 121 is preferred because it reduces the influence of the uneven shape of the underlying structure when structures (e.g., color filters, electrodes of touch sensors, or lens arrays, etc.) are placed above the protective layer 121.

[0386] Figure 19C A connection portion 140 is shown, which electrically connects the connecting electrode 111C to the common electrode 113. In the connection portion 140, an opening is provided in the insulating layer 125 and the resin layer 126 on the connecting electrode 111C. The connecting electrode 111C is electrically connected to the common electrode 113 through this opening.

[0387] Notice, Figure 19C The diagram shows a connection portion 140 where the connecting electrode 111C and the common electrode 113 are electrically connected. However, the common electrode 113 can also be disposed on the connecting electrode 111C with a common layer 114 in between. In particular, when a carrier injection layer is used as the common layer 114, the resistivity of the material used for the common layer 114 is sufficiently low and its film thickness is also very thin, so in many cases, it is not a problem for the common layer 114 to be located in the connection portion 140. Therefore, the common electrode 113 and the common layer 114 can be formed using the same masking mask, thus reducing manufacturing costs.

[0388] [Structure Example 2]

[0389] The following describes a display device whose structure differs from that of Structural Example 1 described above. Note that parts that are the same as those in Structural Example 1 are sometimes omitted from the description with reference to Structural Example 1.

[0390] Figure 20A This is a cross-sectional schematic diagram of display device 100a. The main difference between display device 100a and the aforementioned display device 100 is the structure of the light-emitting element; and the former includes a coloring layer.

[0391] Display device 100a includes a light-emitting element 110W that emits white light. The light-emitting element 110W includes a pixel electrode 111, an organic layer 112W, a common layer 114, and a common electrode 113. The organic layer 112W emits white light. For example, the organic layer 112W may contain two or more light-emitting materials whose emitted colors are complementary. For example, the organic layer 112W may contain a light-emitting organic compound that emits red light, a light-emitting organic compound that emits green light, and a light-emitting organic compound that emits blue light. Furthermore, it may also contain a light-emitting organic compound that emits blue light and a light-emitting organic compound that emits yellow light.

[0392] Between two adjacent light-emitting elements 110W, each organic layer 112W is separated. This suppresses leakage current flowing through the organic layer 112W between adjacent light-emitting elements 110W, and thus suppresses crosstalk caused by this leakage current. Therefore, a display device with high contrast and color reproduction can be achieved.

[0393] An insulating layer 122 serving as a planarization film is provided on the protective layer 121, and a coloring layer 116R, a coloring layer 116G, and a coloring layer 116B are provided on the insulating layer 122.

[0394] As the insulating layer 122, an organic resin film or an inorganic insulating film with a planarized top surface can be used. Since the insulating layer 122 is the surface on which the coloring layers 116R, 116G, and 116B are formed, a planar top surface of the insulating layer 122 can ensure uniform thickness of the coloring layers 116R, etc., thereby improving color purity. Note that when the thickness of the coloring layers 116R, etc., is uneven, the light absorption varies depending on the region within the coloring layer 116R, which may lead to a decrease in color purity.

[0395] [Structure Example 3]

[0396] Figure 20B This is a cross-sectional schematic diagram of the display device 100b.

[0397] Light-emitting element 110R includes a pixel electrode 111, a conductive layer 115R, an organic layer 112W, and a common electrode 113. Light-emitting element 110G includes a pixel electrode 111, a conductive layer 115G, an organic layer 112W, and a common electrode 113. Light-emitting element 110B includes a pixel electrode 111, a conductive layer 115B, an organic layer 112W, and a common electrode 113. Conductive layers 115R, 115G, and 115B are all transparent and used as optical adjustment layers.

[0398] By using a film that reflects visible light as the pixel electrode 111 and a film that is both reflective and transmissive to visible light as the common electrode 113, a microcavity resonator (microcavity) structure can be realized. At this point, by adjusting the thicknesses of the conductive layers 115R, 115G, and 115B in a manner that achieves the most suitable optical path length, even using an organic layer 112 that emits white light, enhanced light can be obtained by extracting light of different wavelengths from the light-emitting elements 110R, 110G, and 110B respectively.

[0399] Furthermore, by setting color layers 116R, 116G, and 116B on the optical paths of light-emitting elements 110R, 110G, and 110B respectively, light with high color purity can be extracted.

[0400] In addition, an insulating layer 123 is provided covering the ends of the pixel electrode 111 and the conductive layer 115. The ends of the insulating layer 123 preferably have a tapered shape. By providing the insulating layer 123, the coverage of the organic layer 112W, the common electrode 113, and the protective layer 121 formed thereon can be improved.

[0401] The organic layer 112W and the common electrode 113 are respectively disposed as a continuous film in each light-emitting element. By adopting this structure, the manufacturing process of the display device can be greatly simplified, so it is preferred.

[0402] Here, the end of the pixel electrode 111 preferably has an almost vertical shape. This allows for a steeply sloping portion to be formed on the surface of the insulating layer 123, while a thin portion can be formed on a part of the organic layer 112W covering that portion, or a portion of the organic layer 112W can be separated. This allows for the suppression of leakage current generated between adjacent light-emitting elements through the organic layer 112W without processing the organic layer 112W using photolithography or similar methods.

[0403] The above illustrates an example of the structure of a display device.

[0404] At least a portion of this embodiment can be implemented in combination with other embodiments described in this specification.

[0405] (Implementation Method 6)

[0406] In this embodiment, Figures 21 to 23 are used to illustrate an electronic device according to one aspect of the present invention.

[0407] The electronic device of this embodiment includes a display panel (display device) using a transistor according to one aspect of the present invention in its display section. The display device according to one aspect of the present invention easily achieves high definition and high resolution, and furthermore, can achieve high display quality. Therefore, it can be used in the display section of various electronic devices.

[0408] As electronic devices, in addition to large-screen electronic devices such as television sets, desktop or laptop personal computers, monitors for computers, digital signage, and large game machines such as pinball machines, other examples include digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, portable information terminals, and sound reproduction devices.

[0409] In particular, because the display panel of one aspect of the present invention can improve clarity, it can be suitably used in electronic devices that include a relatively small display section. Examples of such electronic devices include watch-type and bracelet-type information terminal devices (wearable devices), wearable devices that can be worn on the head, VR devices such as head-mounted displays, AR devices such as glasses, and MR devices.

[0410] The display panel of one embodiment of the present invention preferably has extremely high resolutions such as HD (1280×720 pixels), FHD (1920×1080 pixels), WQHD (2560×1440 pixels), WQXGA (2560×1600 pixels), 4K (3840×2160 pixels), 8K (7680×4320 pixels), etc. In particular, a resolution of 4K, 8K, or higher is preferred. Furthermore, the pixel density (clarity) of the display panel of one embodiment of the present invention is preferably 100 ppi or higher, preferably 300 ppi or higher, more preferably 500 ppi or higher, further preferably 1000 ppi or higher, even more preferably 2000 ppi or higher, even more preferably 3000 ppi or higher, still more preferably 5000 ppi or higher, and even more preferably 7000 ppi or higher. By using the aforementioned display panel with one or both of high resolution and high definition, the sense of realism and depth can be further enhanced. Furthermore, there are no particular limitations on the screen ratio (aspect ratio) of the display panel according to one aspect of the present invention. For example, the display panel can accommodate various screen ratios such as 1:1 (square), 4:3, 16:9, and 16:10.

[0411] The electronic device in this embodiment may also include a sensor (which has the function of sensing, detecting, and measuring factors such as force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, tilt, vibration, odor, or infrared radiation).

[0412] The electronic device of this embodiment can have various functions. For example, it can have the following functions: displaying various information (static images, dynamic images, text images, etc.) on the display unit; touch panel function; displaying calendar, date, or time, etc.; executing various software (programs); wireless communication function; reading programs or data stored in the storage medium; etc.

[0413] use Figures 21A to 21D This section describes an example of a wearable device that can be worn on the head. These wearable devices have the ability to display AR content and VR content, or both. Furthermore, these wearable devices may also have the ability to display SR or MR content in addition to AR and VR. When an electronic device has the ability to display content of at least one of AR, VR, SR, and MR, the user's sense of immersion can be enhanced.

[0414] Figure 21A The electronic device 700A shown and Figure 21B The electronic devices 700B shown include a pair of display panels 751, a pair of frames 721, a communication unit (not shown), a pair of mounting units 723, a control unit (not shown), an imaging unit (not shown), a pair of optical components 753, a frame 757, and a pair of nose pads 758.

[0415] The display panel 751 can be an embodiment of the display panel of the present invention. Therefore, an electronic device capable of displaying with extremely high clarity can be realized.

[0416] Both electronic devices 700A and 700B can project images displayed on the display panel 751 onto the display area 756 in the optical component 753. Because the optical component 753 is transparent, the user can see the image displayed on the display area by superimposing it with the image seen through the optical component 753. Therefore, both electronic devices 700A and 700B are capable of AR display.

[0417] Both electronic devices 700A and 700B can be equipped with cameras capable of capturing images of the front as imaging units. Furthermore, by incorporating accelerometers such as gyroscopes into both electronic devices 700A and 700B, the orientation of the user's head can be detected, and an image corresponding to that orientation can be displayed on the display area 756.

[0418] The communications section includes a wireless communication device through which image signals can be supplied. Furthermore, in addition to or in addition to the wireless communication device, a connector capable of connecting cables supplying image signals and power potential may also be included.

[0419] In addition, electronic devices 700A and 700B are equipped with batteries that can be charged wirelessly or via wired means, or both.

[0420] The frame 721 may also be equipped with a touch sensor module. The touch sensor module has the function of detecting whether the outer surface of the frame 721 is touched. Through the touch sensor module, various processes can be performed by detecting user tap or swipe operations. For example, a tap operation can perform processing such as temporarily pausing or replaying a moving image, and a swipe operation can perform processing such as fast forward or rewind. Furthermore, by providing a touch sensor module in each of the two frames 721, the operating range can be expanded.

[0421] Various touch sensors can be used as touch sensor modules. For example, capacitive, resistive, infrared, electromagnetic induction, surface acoustic wave, and optical sensors can be employed. In particular, capacitive or optical sensors are preferred for use in touch sensor modules.

[0422] When using optical touch sensors, photoelectric conversion devices (also known as photoelectric conversion elements) can be used as light-receiving devices (also known as light-receiving elements). One or both of inorganic semiconductors and organic semiconductors can be used in the active layer of the photoelectric conversion device.

[0423] Figure 21C The electronic device 800A shown is Figure 21D The electronic devices 800B shown include a pair of display units 820, a frame 821, a communication unit 822, a pair of mounting units 823, a control unit 824, a pair of imaging units 825, and a pair of lenses 832.

[0424] The display unit 820 can utilize a display panel according to one aspect of the present invention. Therefore, an electronic device capable of displaying extremely high clarity can be realized. This allows the user to experience a highly immersive experience.

[0425] The display unit 820 is located inside the housing 821 in a position visible through the lens 832. Furthermore, by displaying different images on each of the pair of display units 820, three-dimensional display utilizing parallax can be achieved.

[0426] Both electronic devices 800A and 800B can be referred to as VR-oriented electronic devices. Users who have installed electronic devices 800A or 800B can see the image displayed on the display unit 820 through the lens 832.

[0427] Electronic devices 800A and 800B preferably have a mechanism in which the left and right positions of the lens 832 and the display unit 820 can be adjusted so that the lens 832 and the display unit 820 are in the most suitable position according to the position of the user's eyes. Furthermore, it is preferable to have a mechanism in which the focus is adjusted by changing the distance between the lens 832 and the display unit 820.

[0428] The user can use the mounting unit 823 to attach electronic device 800A or electronic device 800B to their head. Figure 21C Examples of the mounting part 823 include a shape similar to the temple of an eyeglass (also called a temple wire), but it is not limited to this. As long as the user can attach it, the mounting part 823 can have a helmet-shaped or strap-shaped design, for example.

[0429] The imaging unit 825 has the function of acquiring external information. The data acquired by the imaging unit 825 can be output to the display unit 820. An image sensor can be used in the imaging unit 825. In addition, multiple cameras can be set to support various viewing angles such as telephoto and wide-angle.

[0430] Note that the example shown here includes an imaging unit 825, which can be a ranging sensor (hereinafter also referred to as a detection unit) capable of measuring the distance to an object. In other words, the imaging unit 825 is one type of detection unit. For example, an image sensor or a distance image sensor such as LiDAR (Light Detection and Ranging) can be used as the detection unit. By using images acquired by a camera and images acquired by a distance image sensor, more information can be obtained, enabling more precise attitude control.

[0431] The electronic device 800A may also include a vibration mechanism used as a bone conduction headphone. For example, one or more of the display unit 820, the frame 821, and the mounting unit 823 may adopt a structure including this vibration mechanism. Thus, there is no need to separately install audio equipment such as headphones, earphones, or speakers; one can enjoy images and sound simply by installing the electronic device 800A.

[0432] Electronic devices 800A and 800B may also include input terminals. Cables supplying image signals from image output devices and the like, as well as power for charging batteries installed within the electronic devices, can be connected to the input terminals.

[0433] An electronic device according to one aspect of the present invention may also have the function of wirelessly communicating with the headset 750. The headset 750 includes a communication unit (not shown) and has wireless communication functionality. The headset 750 can receive information (e.g., voice data) from the electronic device via the wireless communication function. For example, Figure 21A The illustrated electronic device 700A has the function of transmitting information to the headset 750 via wireless communication. Furthermore, for example... Figure 21C The electronic device 800A shown has the function of sending information to the headset 750 via wireless communication.

[0434] In addition, electronic devices may also include an earphone unit. Figure 21B The illustrated electronic device 700B includes an earphone unit 727. For example, a structure in which the earphone unit 727 and the control unit are connected by a wire can be adopted. A portion of the wiring connecting the earphone unit 727 and the control unit can also be configured inside the housing 721 or the mounting portion 723.

[0435] same, Figure 21D The illustrated electronic device 800B includes an earphone unit 827. For example, a structure can be adopted in which the earphone unit 827 and the control unit 824 are connected by a wire. A portion of the wiring connecting the earphone unit 827 and the control unit 824 can also be disposed inside the housing 821 or the mounting portion 823. Furthermore, the earphone unit 827 and the mounting portion 823 can also include magnets. Thus, the earphone unit 827 can be magnetically secured to the mounting portion 823, making storage easy, which is preferable.

[0436] Electronic devices may also include an audio output terminal capable of connecting to headphones or headsets. Furthermore, electronic devices may include one or both of an audio input terminal and an audio input mechanism. As an audio input mechanism, a microphone or similar recording device can be used, for example. By incorporating an audio input mechanism into the electronic device, it can be made to function as a so-called headset.

[0437] Thus, as an embodiment of the present invention, both eyeglass type (electronic device 700A and electronic device 700B, etc.) and goggle type (electronic device 800A and electronic device 800B, etc.) are preferred electronic devices.

[0438] Figure 22A The electronic device 6500 shown is a portable information terminal device that can be used as a smartphone.

[0439] Electronic device 6500 includes a frame 6501, a display unit 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and a control device 6509, etc. The display unit 6502 has a touch panel function. The control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a storage device. A semiconductor device according to one aspect of the present invention can be used in the display unit 6502, the control device 6509, etc. Using a semiconductor device according to one aspect of the present invention in the control device 6509 can reduce power consumption, and is therefore preferred.

[0440] The display unit 6502 may use a display panel according to one aspect of the present invention.

[0441] Figure 22B This is a cross-sectional schematic diagram of one end of the microphone 6506, including the frame 6501.

[0442] A light-transmitting protective component 6510 is provided on one side of the display surface of the frame 6501. The space surrounded by the frame 6501 and the protective component 6510 contains a display panel 6511, an optical component 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc.

[0443] The display panel 6511, optical component 6512, and touch sensor panel 6513 are fixed to the protective component 6510 using an adhesive layer (not shown).

[0444] In the area outside the display unit 6502, a portion of the display panel 6511 is folded back, and this folded portion is connected to an FPC 6515. An IC 6516 is mounted on the FPC 6515. The FPC 6515 is connected to terminals disposed on a printed circuit board 6517.

[0445] The display panel 6511 can be used with a display device according to one aspect of the present invention. This allows for the realization of an extremely lightweight electronic device. Furthermore, since the display panel 6511 is extremely thin, a large-capacity battery 6518 can be installed while minimizing the thickness of the electronic device. Additionally, by folding a portion of the display panel 6511 to provide a connection portion with the FPC 6515 on the back of the pixel section, a narrow-bezel electronic device can be achieved.

[0446] Figure 22C An example of a television device is shown. In the television device 7100, a display unit 7000 is assembled in a frame 7101. Here is shown the structure in which the frame 7101 is supported by a bracket 7103.

[0447] It can be operated using the operating switches provided in the housing 7101 and the separately provided remote control 7111. Figure 22C The operation of the television device 7100 shown is illustrated. Alternatively, a touch sensor may be provided in the display unit 7000, allowing operation of the television device 7100 by touching the display unit 7000 with a finger or the like. Furthermore, a display unit for displaying data output from the remote control 7111 may be provided in the remote control 7111. Channel and volume adjustments can be made using the operation keys or touch panel provided in the remote control 7111, and the images displayed on the display unit 7000 can also be manipulated.

[0448] Furthermore, the television device 7100 includes a receiver and a modem. It can receive general television broadcasts using the receiver. Moreover, it can connect to a wired or wireless communication network via the modem to conduct one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication.

[0449] Figure 22D An example of a notebook computer is shown. The notebook computer 7200 includes a chassis 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, a control device 7216, etc. A display unit 7000 is assembled in the chassis 7211. The control device 7216 includes, for example, one or more selected from a CPU, a GPU, and a storage device. A semiconductor device according to one aspect of the present invention can be used in the display unit 7000, the control device 7216, etc. By using a semiconductor device according to one aspect of the present invention in the control device 7216, power consumption can be reduced, and therefore it is preferred.

[0450] Figure 22E and Figure 22F Here is an example of digital signage.

[0451] Figure 22E The digital sign 7300 shown includes a frame 7301, a display unit 7000, and a speaker 7303. It may also include LEDs, operation keys (including a power switch or operation switch), connection terminals, various sensors, a microphone, etc.

[0452] Figure 22F A digital sign 7400 is shown mounted on a cylindrical column 7401. The digital sign 7400 includes a display section 7000 disposed along the curved surface of the column 7401.

[0453] The larger the display unit (7000), the more information it can provide at once. A larger display unit (7000) is also more likely to attract attention, which can improve the effectiveness of advertising.

[0454] By using a touch panel in the display unit 7000, not only can static or dynamic images be displayed on the display unit 7000, but users can also operate it intuitively, making it preferable. Furthermore, when used to provide information such as route information or traffic information, intuitive operation enhances ease of use.

[0455] like Figure 22E and Figure 22F As shown, digital signage 7300 or digital signage 7400 preferably connects wirelessly with information terminal devices 7311 or 7411, such as smartphones carried by the user. For example, advertising information displayed on display unit 7000 can be displayed on the screen of information terminal device 7311 or information terminal device 7411. Furthermore, the display on display unit 7000 can be switched by operating information terminal device 7311 or information terminal device 7411.

[0456] Furthermore, the game can be executed on the digital signage 7300 or 7400 using the screen of information terminal device 7311 or 7411 as the operating unit (controller). Thus, multiple users can participate in the game simultaneously and enjoy the experience.

[0457] exist Figures 22C to 22F In this embodiment, the display panel of one aspect of the present invention can be used in the display unit 7000.

[0458] Figures 23A to 23G The electronic device shown includes a frame 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or operation switch), a connection terminal 9006, a sensor 9007 (which has the function of sensing, detecting, and measuring the following factors: force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, tilt, vibration, odor, or infrared radiation), a microphone 9008, etc.

[0459] Figures 23A to 23GThe electronic device shown has various functions. For example, it may have the following functions: displaying various information (still images, moving images, and text images, etc.) on a display unit; a touch panel function; displaying a calendar, date, or time, etc.; controlling processing using various software (programs); wireless communication function; reading and processing programs or data stored in a storage medium; etc. Note that the functions of the electronic device are not limited to the above functions, but can have various functions. The electronic device may include multiple display units. In addition, a camera or the like may be installed in the electronic device to give it the following functions: capturing still or moving images and storing the captured images in a storage medium (external storage medium or storage medium built into the camera); displaying the captured images on a display unit; etc.

[0460] The following is a detailed explanation. Figures 23A to 23G The electronic device shown.

[0461] Figure 23A This is a perspective view showing a portable information terminal 9101. The portable information terminal 9101 can be used, for example, as a smartphone. Note that a speaker 9003, a connection terminal 9006, a sensor 9007, etc., may also be included in the portable information terminal 9101. Furthermore, as a portable information terminal 9101, text or image information can be displayed on multiple surfaces. Figure 23A The image shows an example displaying three icons 9050. Furthermore, information 9051, shown as a dashed rectangle, can be displayed on other surfaces of the display unit 9001. Examples of information 9051 include notifications of received emails, SNS messages, or phone calls; the subject of the email or SNS message; the sender's name; the date; the time; remaining battery level; and radio wave strength. Alternatively, icons 9050 can be displayed in the same location where information 9051 is displayed.

[0462] Figure 23B This is a perspective view showing a portable information terminal 9102. The portable information terminal 9102 has the function of displaying information on three or more surfaces of the display unit 9001. Here, examples are shown where information 9052, information 9053, and information 9054 are displayed on different surfaces. For example, when the portable information terminal 9102 is placed in a jacket pocket, the user can check the information 9053 displayed in a position seen from above the portable information terminal 9102. For example, the user can check this display without taking the portable information terminal 9102 out of their pocket, thereby determining whether to answer a phone call.

[0463] Figure 23CThis is a perspective view of a tablet terminal 9103. The tablet terminal 9103 can, for example, execute various application software such as mobile phone, email, and article reading and editing, music playback, network communication, and computer games. The tablet terminal 9103 includes a display unit 9001, a camera 9002, a microphone 9008, and a speaker 9003 on the front of the frame 9000; operation keys 9005 serving as operating buttons on the left side of the frame 9000; and a connection terminal 9006 on the bottom surface.

[0464] Figure 23D This is a perspective view showing a watch-type portable information terminal 9200. The portable information terminal 9200 can be used, for example, as a smartwatch (registered trademark). Furthermore, the display surface of the display unit 9001 is curved, allowing display along its curved surface. Additionally, the portable information terminal 9200 can perform hands-free calls, for example, by communicating with a headset capable of wireless communication. Furthermore, by utilizing the connection terminal 9006, the portable information terminal 9200 can transmit data or charge with other information terminals. Charging can also be performed wirelessly.

[0465] Figures 23E to 23G This is a perspective view showing the foldable portable information terminal 9201. Furthermore, Figure 23E This is a 3D view of the portable information terminal 9201 in its unfolded state. Figure 23G It is a 3D image of the folded state. Figure 23F From Figure 23E status and Figure 23G The portable information terminal 9201 is a three-dimensional representation of the state transitioning between different states. In its folded state, it is highly portable, while in its unfolded state, it offers excellent browsing capabilities due to its large, seamlessly integrated display area. The display unit 9001 included in the portable information terminal 9201 is supported by three frames 9000 connected by hinges 9055. The display unit 9001 can be bent, for example, within a radius of curvature of 0.1 mm or more and 150 mm or less.

[0466] At least a portion of this embodiment can be implemented in combination with other embodiments described in this specification.

[0467] (Implementation Method 7)

[0468] In this embodiment, an application example of a semiconductor device according to one aspect of the present invention is described. For example, the semiconductor device according to one aspect of the present invention can be used in electronic components, electronic devices, mainframe computers, space equipment, and data centers (also known as DCs). Electronic components, electronic devices, mainframe computers, space equipment, and data centers using the semiconductor device according to one aspect of the present invention are highly effective in achieving high performance such as low power consumption.

[0469] Electronic components of a semiconductor device using one aspect of the present invention can be applied to the electronic device shown in Embodiment 6.

[0470] [Electronic Components]

[0471] Figure 24A A perspective view of a substrate (circuit board 704) on which electronic components 700 are mounted is shown. Figure 24A The electronic component 700 shown includes a semiconductor device 710 within the mold 711. Figure 24A In this description, a portion of the electronic component 700 is omitted to indicate its internal structure. The electronic component 700 includes a connecting pad 712 on the outside of the mold 711. The connecting pad 712 is electrically connected to an electrode pad 713, which is electrically connected to a semiconductor device 710 via a lead 714. The electronic component 700 is mounted, for example, on a printed circuit board 702. By combining multiple such electronic components and electrically connecting them individually on the printed circuit board 702, a circuit board 704 is completed.

[0472] Furthermore, the semiconductor device 710 includes a driver circuit layer 715 and a memory layer 716. The memory layer 716 has a structure with multiple memory cell arrays stacked on top of each other. The stacked structure of the driver circuit layer 715 and the memory layer 716 can be a monolithic stacked structure. In a monolithic stacked structure, the layers can be connected without through-hole electrode technologies such as TSVs (Through Silicon Vias) or bonding technologies such as Cu-Cu direct bonding. When the driver circuit layer 715 and the memory layer 716 are stacked monolithically, for example, a so-called on-chip memory structure in which memory is directly formed on the processor can be realized. By adopting an on-chip memory structure, high-speed operation of the interface between the processor and the memory can be achieved.

[0473] Furthermore, by employing an on-chip memory structure, the size of interconnect wiring can be reduced compared to techniques using through electrodes such as TSVs, thus allowing for an increase in the number of pins. Increasing the number of pins enables parallel operation, thereby improving the memory's bandwidth.

[0474] Furthermore, it is preferable to use OS transistors to form multiple memory cell arrays in memory layer 716, and to stack these multiple memory cell arrays monolithically. When multiple memory cell arrays are stacked monolithically, one or both of the memory bandwidth and memory access latency can be improved. Bandwidth refers to the amount of data transferred per unit time, and access latency refers to the time between accessing and starting data exchange. When using Si transistors in memory layer 716, it is more difficult to stack them monolithically compared to OS transistors. Therefore, in a monolithically stacked structure, OS transistors are superior to Si transistors.

[0475] Furthermore, the semiconductor device 710 may be referred to as a bare die. In this specification, a bare die refers to a chip obtained by forming a circuit pattern on a disk-shaped substrate (also called a wafer) and cutting it into rectangular pieces during the semiconductor chip manufacturing process. Examples of semiconductor materials that can be used for bare dies include silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a bare die obtained from a silicon substrate (also called a silicon wafer) is sometimes referred to as a silicon wafer.

[0476] then, Figure 24B A perspective view of electronic component 730 is shown. Electronic component 730 is an example of SiP (System in Package) or MCM (Multi-Chip Module). In electronic component 730, an interposer 731 is disposed on a package substrate 732 (printed circuit board), and semiconductor devices 735 and multiple semiconductor devices 710 are disposed on the interposer 731.

[0477] Electronic component 730 illustrates an example of using semiconductor device 710 as a high-bandwidth memory (HBM). Furthermore, semiconductor device 735 can be used in integrated circuits such as CPUs (Central Processing Units), GPUs (Graphics Processing Units), or FPGAs (Field Programmable Gate Arrays).

[0478] The packaging substrate 732 can be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The through-hole plate 731 can be, for example, a silicon through-hole plate or a resin through-hole plate.

[0479] The through-hole board 731 has multiple wirings and multiple integrated circuits with different spacing between their electrical connection terminals. The multiple wirings are composed of a single layer or multiple layers. Furthermore, the through-hole board 731 has the function of electrically connecting the integrated circuits disposed on the through-hole board 731 to electrodes disposed on the package substrate 732. Therefore, the through-hole board is sometimes also referred to as a "rewiring substrate" or "intermediate substrate". Additionally, sometimes a through electrode is provided in the through-hole board 731, through which the integrated circuit is electrically connected to the package substrate 732. Furthermore, in the case of using a silicon through-hole board, a TSV can also be used as the through electrode.

[0480] In HBM, numerous wirings are required to achieve wide memory bandwidth. Therefore, the mounting board for HBM must be capable of forming fine wirings at high density. Consequently, silicon mounting boards are preferred as mounting boards for HBM.

[0481] Furthermore, in SiP and MCM applications using silicon interposers, reliability degradation due to differences in the coefficients of thermal expansion between the integrated circuit and the interposer is less likely to occur. Additionally, due to the high surface flatness of the silicon interposer, poor connection between the integrated circuit and the interposer is less likely to occur. Silicon interposers are particularly preferred for 2.5D packaging (2.5D mounting), where multiple integrated circuits are arranged horizontally on the interposer.

[0482] On the other hand, when multiple integrated circuits with different terminal pitches are electrically connected using silicon interposers and TSVs, space is required for the width of these terminal pitches. Therefore, when the size of the electronic component 730 is to be reduced, the width of the aforementioned terminal pitch becomes a problem, and it is sometimes difficult to set to achieve the required amount of wiring to achieve a wider memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferred. Alternatively, a composite structure combining a memory cell array stacked using TSVs and a monolithic stacked memory cell array can also be used.

[0483] Alternatively, a heat sink (heat plate) may be provided overlapping with the electronic component 730. When a heat sink is provided, it is preferable that the integrated circuits provided on the insert 731 have the same height. For example, in the electronic component 730 shown in this embodiment, it is preferable that the semiconductor device 710 and the semiconductor device 735 have the same height.

[0484] In order to mount the electronic component 730 on other substrates, an electrode 733 may also be provided on the bottom of the package substrate 732. Figure 24BAn example of forming electrode 733 using solder balls is shown. By arranging solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, electrode 733 can also be formed using conductive pins. By arranging conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0485] Electronic component 730 can be mounted on other substrates using various mounting methods, not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0486] [Mainframe Computer]

[0487] then, Figure 25A A perspective view of a mainframe computer 5600 is shown. In the mainframe computer 5600, multiple rack-mounted computers 5620 are housed in racks 5610. Alternatively, the mainframe computer 5600 can also be referred to as a supercomputer.

[0488] Figure 25B A perspective view of an example of a computer 5620 is shown. The computer 5620 includes a motherboard 5630. The motherboard 5630 has a plurality of slots 5631 and a plurality of connection terminals. A personal computer card 5621 is inserted into the slots 5631. Furthermore, the personal computer card 5621 includes connection terminals 5623, 5624, and 5625, which are connected to the motherboard 5630.

[0489] Figure 25C An example of a personal computer card 5621 is shown. The personal computer card 5621 is, for example, a processing board including a CPU, GPU, storage device, etc. The personal computer card 5621 includes a board 5622 and connection terminals 5623, 5624, 5625, electronic components 5626, 5627, 5628, and connection terminals 5629, etc., mounted on the board 5622. Figure 25C Components other than electronic component 5626, electronic component 5627 and electronic component 5628 are also shown.

[0490] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 on the motherboard 5630. The connection terminal 5629 is used as an interface for connecting the personal computer card 5621 to the motherboard 5630. Examples of specifications for the connection terminal 5629 include PCIe.

[0491] Connection terminals 5623, 5624, and 5625 can be used, for example, as interfaces for powering or inputting signals to the personal computer card 5621. Furthermore, they can be used, for example, as interfaces for outputting signals calculated by the personal computer card 5621. Examples of the specifications for connection terminals 5623, 5624, and 5625 include, for example, USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Furthermore, when outputting video signals from connection terminals 5623, 5624, and 5625, examples of the specifications include HDMI (registered trademark).

[0492] Electronic component 5626 includes terminals (not shown) for signal input and output. By inserting these terminals into a socket (not shown) included in board 5622, electronic component 5626 and board 5622 can be electrically connected.

[0493] Electronic components 5627 and 5628 include multiple terminals, which can be mounted, for example, by reflow soldering these terminals to wiring included in board 5622. Examples of electronic components 5627 include, for example, an FPGA, GPU, or CPU. Examples of electronic components 5627 include, for example, electronic component 730. Examples of electronic components 5628 include, for example, a storage device. Examples of electronic components 5628 include, for example, electronic component 700.

[0494] The 5600 mainframe computer can be used as a parallel computer. By using the 5600 mainframe computer as a parallel computer, large-scale computations required for artificial intelligence learning and inference can be performed, for example.

[0495] At least a portion of this embodiment can be implemented in combination with other embodiments described in this specification.

[0496] [Example]

[0497] In this embodiment, a single-crystal oxide semiconductor film is formed on a single-crystal substrate, and its cross-section is observed.

[0498] A single-crystal YSZ substrate is used as the single-crystal substrate. Here, two types of substrates are used: a substrate with a (111) face and a substrate with a (100) face.

[0499] Indium oxide (IO) was used as the oxide semiconductor film. Here, an IO film with a thickness of approximately 5 nm was deposited on a YSZ substrate using the ALD method. Deposition was performed under the following conditions: triethylindium was used as a precursor, ozone was used as an oxidant, and the substrate temperature was set to 200°C.

[0500] Next, cross-sectional observations were performed on the two substrates with indium oxide films. HAADF-STEM was used for the cross-sectional observations.

[0501] Figure 26A A cross-sectional image is shown, including a YSZ substrate with a (111) facet and an indium oxide film (referred to as In2O3) formed thereon. This shows that the indium oxide film is crystallized in a manner reflecting the lattice contained within the YSZ substrate. The right side of the image shows the crystal orientations of the YSZ substrate and the indium oxide film. The cross-sectional image confirms that the crystal orientation of the YSZ substrate is consistent with the crystal orientation of the indium oxide film.

[0502] In addition, a low-contrast layer (buffer layer) was also identified between the YSZ substrate and the indium oxide film.

[0503] Figure 26B Show Figure 26A A magnified image of a portion of the sample. This confirms that the buffer layer is a 2-atom layer. In HAADF-STEM, information in the depth direction is superimposed on the sample surface; therefore, the buffer layer is observed as having lower contrast, indicating the presence of sites where atoms are absent. In other words, the buffer layer can also be considered a region with lower density than other areas.

[0504] Next, we focus on the interatomic distances between the YSZ substrate and the indium oxide film. Figure 26B The interatomic distances of the YSZ substrate and the indium oxide film are shown numerically. The interatomic distances are the average of 100 periods within the observation range. The interatomic distance of the YSZ substrate is 0.313 nm in the in-plane direction and 0.300 nm in the thickness direction, values ​​approximately the same as an ideal YSZ single crystal. On the other hand, the interatomic distance of the indium oxide film is 0.313 nm in the in-plane direction and 0.291 nm in the thickness direction. The interatomic distance in the thickness direction is approximately the same as an ideal indium oxide single crystal, while the interatomic distance in the in-plane direction is greater than that of an ideal single crystal. Therefore, it can be concluded that, at least within the range observed in this embodiment, the crystal structure of the indium oxide film is deformed only in the in-plane direction.

[0505] Figure 27AA cross-sectional image is shown, including a YSZ substrate with a (100) facet and an indium oxide film formed thereon. Additionally, Figure 27B An enlarged view is shown. This demonstrates that well-crystallized indium oxide can be obtained even with different substrate surfaces.

[0506] When considering interatomic distance, the interatomic distance of the YSZ substrate is 0.364 nm in the in-plane direction and 0.258 nm in the thickness direction, which is roughly the same as that of an ideal single crystal. On the other hand, the interatomic distance of the indium oxide film is 0.364 nm in the in-plane direction and 0.252 nm in the thickness direction. The interatomic distance in the thickness direction is roughly the same as that of an ideal indium oxide single crystal, while the interatomic distance in the in-plane direction is greater than that of an ideal single crystal. That is to say, similar to the case where the substrate plane is (111), compared with the ideal single crystal indium oxide, the indium oxide film deforms in the in-plane direction by increasing the interatomic distance, while it hardly deforms in the thickness direction.

[0507] Furthermore, when considering the buffer layer, the buffer layer is 2 atomic layers when the substrate plane is (111), and 1 atomic layer when the substrate plane is (100). This indicates that the stress applied to the indium oxide film varies depending on the crystal orientation of the substrate, and this difference is related to the number of buffer layers. From this result, it can be seen that, regarding the crystal orientation of the YSZ substrate, the (100) plane has a better match with the crystal structure of the indium oxide film compared to the (111) plane.

[0508] According to this embodiment, it can be confirmed that a single-crystal oxide semiconductor film can be formed by epitaxial growth of a single-crystal oxide semiconductor film on a single-crystal substrate. Furthermore, it can be confirmed that a low-density buffer layer can be formed between the single-crystal substrate and the single-crystal oxide semiconductor film. Additionally, it is known that although the crystal structure of the single-crystal oxide semiconductor film exhibits the same degree of distortion as the substrate in the in-plane direction to mitigate lattice mismatch with the substrate, the distortion in the thickness direction is small.

[0509] [Symbol Explanation]

[0510] 10: Transistor, 11: Substrate, 11a: Substrate, 12: Base film, 12a: Layer, 15f: Element, 15m: Element, 15s: Element, 16: Intermediate layer, 21: Semiconductor layer, 21f: Semiconductor film, 22: Insulating layer, 22f: Insulating film, 23: Conductive layer, 24: Conductive layer, 24f: Conductive film, 32: Insulating layer, 33a: Insulating layer, 33b: Insulating layer, 33c: Insulating layer, 33d: Insulating layer, 50: Transistor, 51: Substrate, 51c: Semiconductor region, 52: Insulating layer, 53: Conductive layer, 54: Low resistance region, 61a: Plug, 61b: Plug, 61c: Plug, 61d: Plug, 71a: Conductive layer, 71b: Conductive layer, 71c: Conductive layer 71d: Conductive layer, 81: Element separation layer, 82: Insulating layer, 83a: Insulating layer, 83b: Insulating layer, 83c: Insulating layer, 83d: Insulating layer, 100: Display device, 100a: Display device, 100b: Display device, 101: Substrate, 110: Light-emitting element, 110B: Light-emitting element, 110G: Light-emitting element, 110R: Light-emitting element, 110W: Light-emitting element, 111: Pixel electrode, 111B: Pixel electrode, 111C: Connecting electrode, 111G: Pixel electrode, 111R: Pixel electrode, 112: Organic layer, 112B: Organic layer, 112G: Organic layer, 112R: Organic layer, 112W: Organic layer, 113: Common electrode, 114 115: Common layer; 115B: Conductive layer; 115G: Conductive layer; 115R: Conductive layer; 116B: Colored layer; 116G: Colored layer; 116R: Colored layer; 121: Protective layer; 122: Insulating layer; 123: Insulating layer; 125: Insulating layer; 126: Resin layer; 128: Layer; 140: Connector; 170: Substrate; 171: Adhesive layer; 200: Transistor; 201: Insulating layer; 202: Insulating layer; 205: Conductive layer; 230: Semiconductor layer; 230f: Semiconductor film; 240a: Conductive layer; 240b: Conductive layer; 241a: Insulating layer; 241b: Insulating layer; 242: Conductive layer; 242a: Conductive layer; 242b: Conductive layer. 242f: Conductive film; 250: Insulating layer; 255: Insulating layer; 260: Conductive layer; 260a: Conductive layer; 260b: Conductive layer; 271a: Insulating layer; 271b: Insulating layer; 275: Insulating layer; 280: Insulating layer; 282: Insulating layer; 283: Insulating layer; 285: Insulating layer; 301: Substrate; 310: Transistor; 311: Conductive layer; 312: Low resistance region; 313: Insulating layer; 314: Insulating layer; 315: Element separation layer; 320: Transistor; 350: Insulating layer; 351: Semiconductor layer; 352: Insulating layer; 353: Insulating layer; 354: Conductive layer; 355: Conductive layer; 356: Insulating layer; 357: Conductive layer; 358: Insulating layer.359: Insulating layer, 360: Insulating layer, 361: Wiring layer, 362: Insulating layer, 363: Conductive layer, 364: Conductive layer, 371: Wiring layer, 372: Insulating layer, 373: Conductive layer, 420: Layer, 422: Peripheral circuit, 430[1]: Component layer, 430[2]: Component layer, 430[5]: Component layer, 430[m]: Component layer, 430[m]m: Component layer, 430: Component layer, 432[1,1]: Memory cell, 432[i,j]: Memory cell, 432[m,n]: Memory cell, 432: Memory cell, 437: Transistor, 438: Capacitor, 440: Driver circuit, 442: Row decoder, 443: Row driver, 444: Column Decoder, 445: Column driver, 446 [1]: Sensing amplifier, 446 [2]: Sensing amplifier, 446: Sensing amplifier, 447: Input circuit, 448: Output circuit, 470: Layer, 471: PSW, 472: PSW, 473: Control circuit, 474: Voltage generation circuit, 480: Storage device, 482: Switching circuit, 482_1: Transistor, 482_2: Transistor, 483: Precharge circuit, 483_1: Transistor, 483_3: Transistor, 484: Precharge circuit, 484_1: Transistor, 484_3: Transistor, 485: Amplifier circuit, 485_1: Transistor, 485_2: Transistor, 485_3: Transistor, 485_ 4: Transistor, 500A: Display device, 540: Capacitor, 541: Conductive layer, 543: Insulating layer, 545: Conductive layer, 554: Insulating layer, 555a: Insulating layer, 555b: Insulating layer, 555c: Insulating layer, 556: Connector, 564: Insulating layer, 565: Insulating layer, 574: Connector, 574a: Conductive layer, 574b: Conductive layer, 575: Connector, 575a: Conductive layer, 575b: Conductive layer, 580: Display module, 581: Display section, 582: Circuit section, 583: Pixel circuit section, 583a: Pixel circuit, 584: Pixel section, 584a: Pixel, 585: Terminal section, 586: Wiring section, 590: FPC, 591: Substrate, 59 2: Substrate; 700: Electronic Component; 700A: Electronic Device; 700B: Electronic Device; 702: Printed Circuit Board; 704: Circuit Board; 710: Semiconductor Device; 711: Mold; 712: Connecting Pad; 713: Electrode Pad; 714: Lead Wire; 715: Driver Circuit Layer; 716: Storage Layer; 721: Frame; 723: Mounting Part; 727: Earpiece Part; 730: Electronic Component; 731: Insert Board; 732: Packaging Substrate; 733: Electrode; 735: Semiconductor Device; 750: Earpiece; 751: Display Panel; 753: Optical Component; 756: Display Area; 757: Frame; 758: Nose Pad; 800A: Electronic Device; 800B: Electronic Device; 820: Display Part.821: Frame; 822: Communication Unit; 823: Mounting Unit; 824: Control Unit; 825: Imaging Unit; 827: Earphone Unit; 832: Lens; 5600: Mainframe Computer; 5610: Rack; 5620: Computer; 5621: Personal Computer Card; 5622: Board; 5623: Connecting Terminal; 5624: Connecting Terminal; 5625: Connecting Terminal; 5626: Electronic Component; 5627: Electronic Component; 5628: Electronic Component; 5629: Connecting Terminal; 5630: Motherboard. 5631: Slot; 6500: Electronic device; 6501: Frame; 6502: Display unit; 6503: Power button; 6504: Button; 6505: Speaker; 6506: Microphone; 6507: Camera; 6508: Light source; 6509: Control device; 6510: Protective component; 6511: Display panel; 6512: Optical component; 6513: Touch sensor panel; 6515: FPC; 6516: IC; 6517: Printed circuit board; 6518: Battery; 70 00: Display unit; 7100: Television unit; 7101: Frame; 7103: Stand; 7111: Remote control; 7200: Notebook computer; 7211: Frame; 7212: Keyboard; 7213: Pointing device; 7214: External connection port; 7216: Control device; 7300: Digital signage; 7301: Frame; 7303: Speaker; 7311: Information terminal equipment; 7400: Digital signage; 7401: Column; 7411: Information terminal equipment; 900 0: Frame; 9001: Display unit; 9002: Camera; 9003: Speaker; 9005: Operation keys; 9006: Connection terminal; 9007: Sensor; 9008: Microphone; 9050: Icon; 9051: Information; 9052: Information; 9053: Information; 9054: Information; 9055: Hinge; 9101: Portable information terminal; 9102: Portable information terminal; 9103: Tablet terminal; 9200: Portable information terminal; 9201: Portable information terminal.

Claims

1. A semiconductor device, comprising: A first transistor, a second transistor, a first insulating layer, a second insulating layer, a first single-crystal substrate, and a second single-crystal substrate. The channel of the first transistor is formed in the first single-crystal semiconductor included in the first single-crystal substrate. The second transistor is located above the first transistor, and its channel is formed in a second single-crystal semiconductor in contact with the second single-crystal substrate. The second single-crystal substrate is located above the second transistor. The first insulating layer is located between the first transistor and the second transistor. The second insulating layer is located between the first insulating layer and the second transistor and includes a first bonding surface that contacts the first insulating layer. The first single-crystal semiconductor includes silicon. Furthermore, the second single-crystal semiconductor comprises a metal oxide.

2. The semiconductor device according to claim 1, The second single-crystal substrate has a cubic crystal structure. Furthermore, the second single-crystal semiconductor has a cubic crystal structure.

3. The semiconductor device according to claim 1, The second single-crystal substrate comprises an oxide containing yttrium and zirconium. Furthermore, the second single-crystal semiconductor includes indium oxide.

4. The semiconductor device according to claim 1, The lattice mismatch of the second single-crystal semiconductor relative to the second single-crystal substrate is greater than -5% and less than 5%.

5. The semiconductor device according to claim 1, It also includes a first conductive layer and a second conductive layer. The first conductive layer is connected to one of the source and drain electrodes of the first transistor and is embedded in the first insulating layer. Furthermore, the second conductive layer is connected to one of the source and drain electrodes of the second transistor, embedded in the second insulating layer, and includes a second bonding surface that contacts the first conductive layer.

6. A method for manufacturing a semiconductor device, comprising the following steps: A first single-crystal substrate having a first transistor and a first insulating layer on the first transistor and including a first single-crystal semiconductor is prepared. Prepare the second single-crystal substrate; A semiconductor film comprising a second single-crystal semiconductor is formed on the second single-crystal substrate; The semiconductor film is processed into island shapes to form a semiconductor layer; A second transistor is fabricated by forming a gate insulating layer, a gate electrode, a source electrode, and a drain electrode on the semiconductor layer. A second insulating layer is formed on the second transistor; as well as The top surface of the first insulating layer and the top surface of the second insulating layer are joined together.

7. The method for manufacturing a semiconductor device according to claim 6, The first single-crystal semiconductor includes silicon. Furthermore, the second single-crystal semiconductor comprises a metal oxide.

8. The method for manufacturing a semiconductor device according to claim 6, The second single-crystal substrate has a cubic crystal structure. Furthermore, the second single-crystal semiconductor has a cubic crystal structure.

9. The method for manufacturing a semiconductor device according to claim 6, The second single-crystal substrate comprises an oxide containing yttrium and zirconium. Furthermore, the second single-crystal semiconductor includes indium oxide.

10. The method for manufacturing a semiconductor device according to claim 6, The lattice mismatch of the second single-crystal semiconductor relative to the second single-crystal substrate is greater than -5% and less than 5%.

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