Semiconductor device and power conversion device

Abstract

A semiconductor device includes a gallium oxide semiconductor layer, an impurity layer formed in a surface of a first main surface of the gallium oxide semiconductor layer, having a first impurity of an acceptor type, at least a part of the first impurity being activated, a first recessed groove provided by removing a part of the impurity layer and the gallium oxide semiconductor layer, the first recessed groove being formed shallower than the impurity layer, a first main electrode provided on an upper portion of the first main surface, and a second main electrode provided on an upper portion of a second main surface of the gallium oxide semiconductor layer.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device and a power conversion device, and more particularly to a semiconductor device made of gallium oxide and a power conversion device using the semiconductor device. Background Technology

[0002] Gallium oxide (Ga2O3) has a band gap exceeding that of silicon carbide (SiC) and gallium nitride (GaN), making it a material that is beneficial for high voltage withstand capability and low resistance in power devices. Ga2O3 is highly anticipated as a material for next-generation power devices.

[0003] As a semiconductor device using Ga2O3, for example, as known in Patent Document 1 Figure 4 The DI-MOS (Double Implanted Metal-Oxide-Semiconductor) structure, which is formed by implanting nitrogen (N) into an n-type gallium oxide layer, is disclosed in the paper.

[0004] Patent Document 1: International Publication No. 2018 / 199241 Summary of the Invention

[0005] The problem the invention aims to solve

[0006] Generally, the fabrication of DI-MOS structures requires annealing to recover implanted damage and activate implanted ions. Annealing Ga2O3 can easily introduce surface defects, especially in the region below the gate electrode, known as the JFET region in the DI-MOS structure. This reduces the donor concentration, potentially affecting the rise time of the transistor's Id-Vd characteristic. Even if donor-type elements such as silicon are doped into the JFET region to recover the reduced donor concentration caused by annealing, residual defects remain, potentially lowering the breakdown voltage of the semiconductor device. Furthermore, if the defective areas are etched away completely after annealing, the well layer thickness decreases, potentially further reducing the breakdown voltage of the semiconductor device.

[0007] This disclosure was made to solve the problems described above, and aims to provide a semiconductor device that suppresses the drop in withstand voltage and a power conversion device using the semiconductor device.

[0008] Solution for solving the problem

[0009] The semiconductor device disclosed herein comprises: a gallium oxide semiconductor layer; an impurity layer formed in the surface of a first main surface of the gallium oxide semiconductor layer, having an acceptor-type first impurity, at least a portion of which is activated; a first groove formed by removing the impurity layer and a portion of the gallium oxide semiconductor layer, and being shallower than the impurity layer; a first main electrode disposed on the upper portion of the first main surface; and a second main electrode disposed on the upper portion of a second main surface of the gallium oxide semiconductor layer.

[0010] The effects of the invention

[0011] According to the semiconductor device disclosed herein, the portion where the first groove is provided is defined, and the thickness of the impurity layer is maintained, thereby suppressing the drop in withstand voltage. Attached Figure Description

[0012] Figure 1 This is a cross-sectional view showing the structure of the semiconductor device according to Embodiment 1.

[0013] Figure 2 This is a cross-sectional view illustrating the manufacturing method of the semiconductor device according to Embodiment 1.

[0014] Figure 3 This is a cross-sectional view illustrating the manufacturing method of the semiconductor device according to Embodiment 1.

[0015] Figure 4 This is a cross-sectional view illustrating the manufacturing method of the semiconductor device according to Embodiment 1.

[0016] Figure 5 This is a cross-sectional view illustrating the manufacturing method of the semiconductor device according to Embodiment 1.

[0017] Figure 6 This is a cross-sectional view illustrating the manufacturing method of the semiconductor device according to Embodiment 1.

[0018] Figure 7 This is a cross-sectional view illustrating the manufacturing method of the semiconductor device according to Embodiment 1.

[0019] Figure 8 This is a cross-sectional view illustrating the manufacturing method of the semiconductor device according to Embodiment 1.

[0020] Figure 9 This is a cross-sectional view illustrating the manufacturing method of the semiconductor device according to Embodiment 1.

[0021] Figure 10 This is a diagram illustrating the effects of the semiconductor device according to Embodiment 1.

[0022] Figure 11This is a cross-sectional view showing the structure of the semiconductor device according to Embodiment 2.

[0023] Figure 12 This is a cross-sectional view illustrating the manufacturing method of the semiconductor device according to Embodiment 2.

[0024] Figure 13 This is a cross-sectional view illustrating the manufacturing method of the semiconductor device according to Embodiment 2.

[0025] Figure 14 This is a cross-sectional view showing the structure of the semiconductor device according to Embodiment 3.

[0026] Figure 15 This is a cross-sectional view showing the structure of the semiconductor device according to Embodiment 4.

[0027] Figure 16 This is a cross-sectional view showing the structure of the semiconductor device according to Embodiment 5.

[0028] Figure 17 This is a block diagram illustrating the power conversion device involved in Embodiment 6. Detailed Implementation

[0029] The following description, based on the accompanying drawings, illustrates embodiments of the technology disclosed herein. This technology is not limited to the embodiments shown herein, and appropriate modifications can be made without departing from its spirit. Furthermore, in the following figures, for ease of understanding, the scale of each component or component may sometimes differ from reality, and the same applies between the figures.

[0030] In addition, in the following description, terms such as "up" and "down" are sometimes used to indicate specific positions and directions. These terms are used for convenience in understanding the content of the implementation method and are unrelated to the actual direction during implementation.

[0031] <Implementation Method 1>

[0032] <Device Structure>

[0033] Figure 1 This is a diagram showing the structure of the semiconductor device 100 according to Embodiment 1, and a cross-sectional view showing the structure of the unit cell constituting the semiconductor device. In the active region of the semiconductor device 100, multiple... Figure 1 The unit cell arrangement is shown. In this embodiment, a vertically oriented DI-MOSFET, using gallium oxide (Ga2O3), particularly β-type gallium oxide (β-Ga2O3), as the semiconductor device is exemplified. Here, the crystal structure of gallium oxide is not limited to β-type, and can also be α-type, etc.

[0034] The semiconductor device 100 according to Embodiment 1 is formed using a gallium oxide semiconductor layer 20 made of β-Ga₂O₃. The gallium oxide semiconductor layer 20 is composed of an n-type gallium oxide support layer 1, a first gallium oxide layer 2 disposed on the n-type gallium oxide support layer 1, a second gallium oxide layer 3 disposed on the first gallium oxide layer 2, and a third gallium oxide layer 4 disposed on the second gallium oxide layer 3. Figure 1 The upper surface of the gallium oxide semiconductor layer 20 (the upper surface of the third gallium oxide layer 4) is defined as the "first main surface", and the lower surface of the gallium oxide semiconductor layer 20 (the lower surface of the n-type gallium oxide support layer 1) is defined as the "second main surface".

[0035] The n-type gallium oxide support layer 1 is a conductive semiconductor layer composed of n-type β-Ga₂O₃ with the (001) plane as the main surface. Here, a semiconductor substrate made of gallium oxide can also be used as the n-type gallium oxide support layer 1, but a structure in which a layer of gallium oxide epitaxially grown on a semiconductor substrate of a different material than gallium oxide can also be used. In addition, the crystal surface of the n-type gallium oxide support layer 1 is not limited to the (001) plane, and can be other surface orientations.

[0036] In the first gallium oxide layer 2, at least one of silicon, chlorine, tin, and germanium as n-type dopant is used at a ratio of 1 × 10⁻⁶. 16 cm -3 The concentrations of the left and right were added.

[0037] In the second gallium oxide layer 3 (impurity layer), acceptor-type impurities forming acceptor energy levels are 1×10 18 cm -3 The concentration of impurities is increased to the left and right, and at least a portion of the impurities are activated. Examples of acceptor-type impurities include nitrogen, magnesium, zinc, and phosphorus. In the second gallium oxide layer 3, there may be linear defects extending in the direction including the

[010] direction due to activation annealing, but they may also exist to a degree that does not affect the device characteristics. By not removing these defects, the defect removal process can be omitted to improve productivity.

[0038] In the third gallium oxide layer 4, at least one of silicon, chlorine, tin, and germanium, as an n-type dopant, is used at a concentration of 5 × 10⁻⁶. 19 cm -3 The concentrations of the left and right were added.

[0039] A plurality of gate recesses 5 are formed on the first main surface of the gallium oxide semiconductor layer 20. The gate recesses 5 are recesses formed by partially removing the first gallium oxide layer 2, the second gallium oxide layer 3, and the third gallium oxide layer 4, and are disposed on the first main surface of the gallium oxide semiconductor layer 20. The bottom of the gate recesses 5 is in contact with the first gallium oxide layer 2, and the side surfaces of the gate recesses 5 are in contact with the second gallium oxide layer 3 and the third gallium oxide layer 4.

[0040] A gate insulating film 6 is formed from the inner surface of the gate recess 5 to a portion of the upper surface of the third gallium oxide layer 4. A gate electrode 7 is formed on the gate insulating film 6 in a manner that fills the gate recess 5. The gate electrode 7 is preferably formed of polysilicon, and more preferably of high-concentration p-type silicon. + Polycrystalline silicon (type) is formed.

[0041] An interlayer insulating film 8 is formed on the first main surface of the gallium oxide semiconductor layer 20, covering the gate electrode 7 and its outer side. A source pad electrode 10 is formed on the interlayer insulating film 8. The gate electrode 7 and the source pad electrode 10 are electrically separated by the interlayer insulating film 8.

[0042] A contact hole 9 is formed in the interlayer insulating film 8 to reach the gallium oxide semiconductor layer 20. The source pad electrode 10 is electrically connected to the third gallium oxide layer 4 of the gallium oxide semiconductor layer 20 through the contact hole 9. A source groove 12 is formed in the gallium oxide semiconductor layer 20 (third gallium oxide layer 4) at the bottom of the contact hole 9. The source pad electrode 10 is connected to the third gallium oxide layer 4 in the source groove 12.

[0043] A drain electrode 11 is formed on the second main surface of the gallium oxide semiconductor layer 20. The drain electrode 11 is electrically connected to the n-type gallium oxide support layer 1.

[0044] <Manufacturing Method>

[0045] Next, refer to Figures 2-9 Here is an example of a method for manufacturing the semiconductor device 100 according to Embodiment 1. Figures 2-9 This is a cross-sectional view showing the manufacturing method of the semiconductor device 100 according to Embodiment 1 in the order of process steps.

[0046] First, a conductive n-type gallium oxide support layer 1 with the (001) plane as the main surface is prepared. Then, halide vapor phase growth (HVPE), metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), etc., are used. Figure 2 As shown, a first gallium oxide layer 2 is formed on the n-type gallium oxide support layer 1. Thus, a gallium oxide semiconductor layer 20 composed of the n-type gallium oxide support layer 1 and the first gallium oxide layer 2 is formed.

[0047] The thickness of the n-type gallium oxide support layer 1 can be determined according to the voltage rating of the semiconductor device 100, for example, it can be set to about 10 μm. The donor concentration of the n-type gallium oxide support layer 1 is 1 × 10⁻⁶. 16 cm -3 about.

[0048] Next, based on the implantation mask formed on the first main surface of the gallium oxide semiconductor layer 20 (the upper surface of the first gallium oxide layer 2), at least one dopant selected from nitrogen, zinc, phosphorus, magnesium, and other dopants that form acceptor energy levels is implanted into the gallium oxide semiconductor layer 20. The implantation energy at this time is approximately 20 keV to 500 keV, and the dose is 1 × 10⁻⁶. 14 cm -2 To mitigate damage caused by ion implantation, heated implantation or thermal diffusion methods can also be used.

[0049] After removing the implantation mask, heat treatment is performed to recover from the damage caused by dopant implantation and to activate the dopant. The heat treatment temperature is approximately 800°C to 1200°C, and the heat treatment atmosphere is nitrogen, oxygen, or a mixture thereof. As a result, a second gallium oxide layer 3 with a depth of approximately 700 nm is formed on top of the first gallium oxide layer 2.

[0050] Next, based on the implantation mask formed on the first main surface of the gallium oxide semiconductor layer 20 (the upper surface of the second gallium oxide layer 3), silicon (Si) is ion implanted into the gallium oxide semiconductor layer 20. The implantation energy at this time is approximately 10 keV to 200 keV, and the dose is 1 × 10⁻⁶. 15 cm -2 Approximately 900°C is applied after the implantation mask is removed to recover from damage caused by ion implantation and to activate the dopant. This results in the formation of a third gallium oxide layer 4 with a depth of approximately 200 nm on top of the second gallium oxide layer 3.

[0051] The result, such as Figure 3 In this way, a gallium oxide semiconductor layer 20 is formed, consisting of an n-type gallium oxide support layer 1, a first gallium oxide layer 2, a second gallium oxide layer 3, and a third gallium oxide layer 4.

[0052] Next, a portion of the first main surface of the gallium oxide semiconductor layer 20, including a portion of the second gallium oxide layer 3 and the third gallium oxide layer 4, is removed to form a gate recess 5. As a formation method, an etching mask with openings corresponding to the portion to be removed is formed on the first main surface of the gallium oxide semiconductor layer 20, and dry etching of the gallium oxide semiconductor layer 20 is performed, thereby achieving... Figure 4 In this way, a gate recess 5 is formed in the gallium oxide semiconductor layer 20.

[0053] As the etching gas, chlorine-based gases such as chlorine (Cl) or boron trichloride (BCl3) are preferred. The depth of the gate recess 5 is set to be deeper than the third gallium oxide layer 4 and shallower than the second gallium oxide layer 3. Thus, the corners of the gate recess 5 are protected by the second gallium oxide layer 3, thereby improving the breakdown voltage. More preferably, by etching in a way that rounds the lower corners of the gate recess 5, the electric field is less likely to concentrate, further improving the breakdown voltage.

[0054] Next, the etching mask is removed, and after RCA cleaning of the gallium oxide semiconductor layer 20, as follows: Figure 5 In this way, a gate insulating film 6 composed of an Al2O3 film is formed on the first main surface of the gallium oxide semiconductor layer 20, including the inner surface of the gate recess 5. Atomic layer vapor deposition (ALD) can be used as the method for forming the Al2O3 film. The gate insulating film 6 can also be configured as a multilayer structure; for example, it is conceivable to use a stacked film composed of two or more materials selected from SiO2, HfO2, AlON, AlN, SiN, SiON, and Al2O3 as the gate insulating film 6.

[0055] Next, a gate electrode 7 is formed over the entire surface of the gate insulating film 6. As the material for the gate electrode 7, a high-concentration p-type (p0.05) material formed using a reduced-pressure CVD apparatus is preferred. + Polycrystalline silicon film (type).

[0056] Next, using a chlorine-based gas, the gate electrode 7 is etched through an etching mask, thereby leaving the gate electrode 7 on the gate recess 5 and its outer side. Thus, as... Figure 6 In this way, a gate electrode 7 is formed on and outside the gate recess 5. At this time, the edge of the gate electrode 7 on the outside of the gate recess 5 is retained to a position that extends beyond the edge of the third gallium oxide layer 4. As a result, a gate overlap structure is formed in which the gate electrode 7 overlaps with the edge of the third gallium oxide layer 4, suppressing the increase of on-resistance.

[0057] Next, as Figure 7Thus, an interlayer insulating film 8 is formed on the first main surface of the gallium oxide semiconductor layer 20. It is known that the electric field generated at the interface between the semiconductor and the insulating film is affected by the relative permittivity of both the semiconductor and the insulating film. The relative permittivity of the SiO2 film is 3.9, which is about one-third of the relative permittivity of Ga2O3 (10~12). Therefore, when the interlayer insulating film 8 in contact with the gallium oxide semiconductor layer 20 is composed of a SiO2 film, the interlayer insulating film 8 will be subjected to an electric field nearly three times that of the gallium oxide semiconductor layer 20. Therefore, from the viewpoint of damage resistance, it is preferable that the relative permittivity of the interlayer insulating film 8 is higher than that of the silicon oxide film (SiO2). However, generally speaking, the relative permittivity and band gap are inversely proportional; the higher the relative permittivity, the smaller the band gap. Therefore, if the interlayer insulating film 8 is composed of a material with a high relative permittivity, it is difficult to ensure a sufficient band shift relative to the gallium oxide semiconductor layer 20. Therefore, as the interlayer insulating film 8, a two-layer structure can be used, in which a High-k film with a higher relative permittivity than SiO2 is disposed in the lower layer, and a SiO2 film with a large band gap and low leakage current is disposed in the upper layer. This achieves a balance between high damage resistance and low leakage current. For the High-k film, TiO2, HfO2, Al2O3, BaTiO3, MgF2, etc., can be considered.

[0058] Next, selective dry etching was performed using photolithography techniques, such as... Figure 8 In this way, a contact hole 9 is formed in the interlayer insulating film 8. The contact hole 9 penetrates the interlayer insulating film 8 and the gate insulating film 6, reaching the third gallium oxide layer 4. At this time, a source groove 12 is formed in the gallium oxide semiconductor layer 20 (third gallium oxide layer 4) exposed at the bottom of the contact hole 9.

[0059] Dry etching roughens the surface of the gallium oxide semiconductor layer 20, forming unevenness, thereby increasing the donor-type defects in the β-Ga2O3 constituting the gallium oxide semiconductor layer 20 and decreasing the contact resistance. As a result, the ohmic characteristics between the source pad electrode 10 and the third gallium oxide layer 4 are improved.

[0060] Next, as Figure 9 In this way, a source pad electrode 10 is formed on the interlayer insulating film 8, and a drain electrode 11 is formed on the second main surface of the gallium oxide semiconductor layer 20 (the lower surface of the n-type gallium oxide support layer 1).

[0061] The source pad electrode 10 is formed by forming a metal film on the interlayer insulating film 8 using a sputtering apparatus and then patterning the metal film using selective wet etching with photolithography. A Ti / Al laminated structure is preferred as the material for the source pad electrode 10. Regarding the film thickness of the source pad electrode 10, for example, it is set to 20 nm for Ti and 3 μm for Al.

[0062] The drain electrode 11 is formed after the film wrapped around the second main surface of the gallium oxide semiconductor layer 20 is removed by a dry etching machine or a grinding / polishing machine. The drain electrode 11 is formed by depositing a Ti / Au electrode film on the second main surface of the gallium oxide semiconductor layer 20 using a sputtering machine or an EB evaporation machine. Finally, ohmic sintering is performed, thereby... Figure 1 The semiconductor device 100 is completed.

[0063] <Experimental Results>

[0064] Figure 10 This is a graph showing the experimental results comparing the on-current of a typical DI-MOS structure with that of the semiconductor device 100 with a gate trench 5 in Embodiment 1, i.e., a trench DI-MOS structure. Figure 10 In the diagram, the horizontal axis represents the activation annealing temperature [°C] after the formation of the second gallium oxide layer 3, which is changed in 50°C intervals from 900°C to 1100°C. The vertical axis represents the normalized on-state current, which is normalized with the on-state current at annealing at 900°C as 1.

[0065] exist Figure 10 In the diagram, the on-current of a typical DI-MOS structure is plotted using △, and the on-current of a grooved DI-MOS structure is plotted using □. In a typical DI-MOS structure, the on-current decreases sharply as the annealing temperature increases. In contrast, in a grooved DI-MOS structure, even with higher annealing temperatures, the on-current remains approximately the same as that annealed at 900°C.

[0066] That is, if β-type gallium oxide is annealed at high temperatures, the surface donor concentration decreases. Therefore, in the case of a typical DI-MOS structure, as the temperature of annealing such as RTA (Rapid Thermal Annealing) increases, the potential barrier of the JFET region increases, resulting in a significant decrease in the on-state current. On the other hand, the recessed DI-MOS structure of this disclosure removes the surface modification layer (defect layer) at the bottom of the gate electrode 7 when forming the gate recess 5, thus eliminating the potential barrier. Therefore, the on-state current value is easily maintained even after annealing at high temperatures. In addition, high-temperature annealing can be performed without concern about the degradation of forward characteristics, so the introduced acceptors are easily activated, and reverse leakage decreases. As a result, the trade-off between on-state current and cutoff leakage current is improved.

[0067] Furthermore, the recessed DI-MOS structure of this disclosure removes the surface modification layer at the lower part of the gate electrode 7 during the formation of the gate recess 5, thereby suppressing the decrease in donor concentration at the outermost surface of the first gallium oxide layer 2, which serves as a drift layer. Consequently, the depletion layer is suppressed from extending from the second gallium oxide layer 3, thus eliminating the shift in the rising edge of the transistor's Id-Vd characteristic.

[0068] Furthermore, since the portion forming the gate recess 5 is confined to the lower part of the gate electrode 7, the thickness of the second gallium oxide layer 3 is maintained. Compared to cases where the entire surface modification layer is removed by etching such as CMP (chemical mechanical polishing), punch-through is less likely to occur. Therefore, a semiconductor device 100 that suppresses the drop in breakdown voltage can be obtained.

[0069] <Implementation Method 2>

[0070] <Device Structure>

[0071] Figure 11 This is a diagram showing the structure of the semiconductor device 200 according to Embodiment 2, and a cross-sectional view showing the structure of the unit cell constituting the semiconductor device.

[0072] In the semiconductor device 200 according to Embodiment 2, the source groove 12 formed in the gallium oxide semiconductor layer 20 at the bottom of the contact hole 9 penetrates the third gallium oxide layer 4 and the second gallium oxide layer 3, reaching the first gallium oxide layer 2. Other structures are the same as those of the semiconductor device 100 of Embodiment 1.

[0073] According to the semiconductor device 200 of Embodiment 2, the source pad electrode 10 is connected to the first gallium oxide layer 2 via a Schottky connection. Therefore, a Schottky barrier diode (SBD) is integrated into the MOSFET. Consequently, when assembling the MOSFET into the inverter, an external freewheeling diode is not required. This reduces the component cost of the inverter.

[0074] <Manufacturing Method>

[0075] Next, refer to Figure 12 and Figure 13 An example of the manufacturing method of the semiconductor device 200 according to Embodiment 2 will be described. Furthermore, only the differences from the manufacturing method of the semiconductor device 100 according to Embodiment 1 will be described.

[0076] Figure 12 It is the same as implementation method 1. Figure 3 The corresponding figure is a cross-sectional view of the stage in which the second gallium oxide layer 3 and the third gallium oxide layer 4 are selectively formed on the upper part of the first gallium oxide layer 2 by ion implantation.

[0077] like Figure 12As shown, by changing the opening of the injection mask, the second gallium oxide layer 3, which is in contact with the third gallium oxide layer 4, is configured to include only the two ends of the third gallium oxide layer 4. This is because the third gallium oxide layer 4 is not needed in the portion where the contact hole 9 will be formed later. Alternatively, the second gallium oxide layer 3 can be configured to cover the lower surface of the third gallium oxide layer 4; in this case, the contact hole 9 can simply penetrate the second gallium oxide layer 3 and reach the first gallium oxide layer 2.

[0078] Next, after forming the third gallium oxide layer 4, the first main surface of the gallium oxide semiconductor layer 20, including a portion of the second gallium oxide layer 3 and the third gallium oxide layer 4, is partially removed to form the gate recess 5 and the source recess 12.

[0079] As a formation method, an etching mask with openings corresponding to the portions to be removed is formed on the first main surface of the gallium oxide semiconductor layer 20, and dry etching of the gallium oxide semiconductor layer 20 is performed, thereby achieving... Figure 13 Thus, a gate trench 5 and a source trench 12 are formed in the gallium oxide semiconductor layer 20. Furthermore, the region where the gate trench 5 is formed can be referred to as the MOS region, and the region where the source trench 12 is formed can be referred to as the SBD region.

[0080] <Implementation Method 3>

[0081] Figure 14 This is a diagram showing the structure of the semiconductor device 300 according to Embodiment 3, and a cross-sectional view showing the structure of the unit cell constituting the semiconductor device.

[0082] In the semiconductor device 300 according to Embodiment 3, based on the structure of the semiconductor device 200 of Embodiment 2, where the source groove 12 formed in the gallium oxide semiconductor layer 20 at the bottom of the contact hole 9 penetrates the third gallium oxide layer 4 and the second gallium oxide layer 3 and reaches the first gallium oxide layer 2, an intermediate film 13 as a High-k film is formed between the source groove 12 and the source pad electrode 10, and the source pad electrode 10 is electrically connected to the first gallium oxide layer 2 through the intermediate film 13 in the source groove 12. Other structures are the same as those of the semiconductor device 200 of Embodiment 2.

[0083] Additionally, as a manufacturing process, the following step is added: after forming the contact hole 9, an intermediate film 13 is formed on the entire surface of the gallium oxide semiconductor layer 20, including the source groove 12 and the inner surface of the contact hole 9, for example, by the ALD method. Otherwise, it is the same as in Embodiment 2. Regarding the thickness of the intermediate film 13, it can be appropriately determined according to the material of the source electrode in the MOSFET, the type of donor in the source region, and the donor concentration, etc. Preferably, it is a thickness that suppresses the chemical reaction between the source pad electrode 10 and the first gallium oxide layer 2 without increasing the series resistance component on the forward characteristic of the SBD, preferably about 100 nm or less, particularly preferably about 10 nm or less, and more preferably about 5 nm or less.

[0084] As a High-k film, it is preferred to use a material with a higher relative permittivity than SiO2 and a smaller band gap than β-Ga2O3. For example, TiO2 can be used, but HfO2, Al2O3, BaTiO3, and MgF2 can also be used.

[0085] By making the band gap of the intermediate film 13 smaller than that of β-Ga2O3, no new potential barrier is generated in the conduction band, thus preventing the deterioration of the positive properties of the SBD.

[0086] In addition, the β-Ga2O3 constituting the first gallium oxide layer 2 has the problem that the source pad electrode 10, which functions as the anode electrode of the SBD, is easily oxidized during high-temperature operation. However, by providing an intermediate film 13 between the source groove 12 and the source pad electrode 10, the reaction between the source pad electrode 10 and β-Ga2O3 is suppressed, and the temperature stability is improved.

[0087] According to the semiconductor device 300 of Embodiment 3, in addition to achieving the same effect as the semiconductor device 200 of Embodiment 2 in reducing the component cost of the inverter when assembled into the inverter, by providing the intermediate film 13 as a High-k film, it is also possible to obtain the effect of not degrading the positive characteristics of the SBD and improving temperature stability.

[0088] <Implementation Method 4>

[0089] Figure 15 This is a cross-sectional view showing the structure of the semiconductor device 400 according to Embodiment 4. In this embodiment, a vertical SBD made of β-type gallium oxide is shown.

[0090] The semiconductor device 400 according to Embodiment 4 is formed using a gallium oxide semiconductor layer 30 made of β-Ga₂O₃. The gallium oxide semiconductor layer 30 is composed of an n-type gallium oxide support layer 1, a first gallium oxide layer 2 disposed on the n-type gallium oxide support layer 1, and a second gallium oxide layer 3 (impurity layer) disposed on the first gallium oxide layer 2. Furthermore, these layers are the same as those in the semiconductor device 100 of Embodiment 1, and repeated descriptions of materials, impurities, etc., are omitted.

[0091] A plurality of Schottky recesses 17 are formed on the first main surface of the gallium oxide semiconductor layer 30. Each Schottky recess 17 is a recess formed by partially removing the first gallium oxide layer 2 and the second gallium oxide layer 3, and is disposed on the first main surface of the gallium oxide semiconductor layer 30. The bottom of the Schottky recess 17 is in contact with the first gallium oxide layer 2, and the side of the Schottky recess 17 is in contact with the second gallium oxide layer 3.

[0092] The Schottky recess 17 is formed using dry etching in the same way as the gate recess 5 described in Embodiment 1, and the depth of the Schottky recess 17 is set to be shallower than the second gallium oxide layer 3.

[0093] Thus, the corners of the Schottky recess 17 are protected by the second gallium oxide layer 3, thereby improving the breakdown voltage. More preferably, by etching in a way that rounds the lower corners of the Schottky recess 17, the electric field is less likely to concentrate, further improving the breakdown voltage.

[0094] A Schottky electrode 14 is formed on the entire surface of the first main surface of the gallium oxide semiconductor layer 30, including the inner surface of the Schottky groove 17 and the upper surface of the second gallium oxide layer 3. The preferred material for the Schottky electrode 14 is Ti, Ni, Pt, Au, etc., and the Schottky electrode 14 with a thickness of approximately 200 nm is formed by EB evaporation or sputtering.

[0095] An anode pad electrode 15 is formed on the Schottky electrode 14. The anode pad electrode 15 is formed by forming a metal film on the Schottky electrode 14 using a sputtering apparatus and then patterning the metal film using selective wet etching with photolithography. A Ti / Al laminated structure is preferred as the material for the anode pad electrode 15. The film thickness of the anode pad electrode 15 is, for example, set to 20 nm for Ti and 3 μm for Al.

[0096] A cathode electrode 16 is formed on the second main surface of the gallium oxide semiconductor layer 30. The cathode electrode 16 is electrically connected to the n-type gallium oxide support layer 1. The cathode electrode 16 is formed by depositing a Ti / Au electrode film on the second main surface of the gallium oxide semiconductor layer 20 using a sputtering apparatus or an EB evaporation machine.

[0097] According to the semiconductor device 400 of Embodiment 4, the surface modification layer (defect layer) at the lower part of the Schottky electrode 14 is removed when the Schottky groove 17 is formed, so that a junction barrier Schottky (JBS) structure SBD that does not degrade the positive characteristics can be obtained.

[0098] Furthermore, since the portion forming the Schottky trench 17 is defined, the thickness of the second gallium oxide layer 3 is maintained, making junction breakdown less likely compared to cases where the surface modification layer is completely removed by etching such as CMP. Therefore, a semiconductor device 400 that suppresses the drop in breakdown voltage can be obtained.

[0099] <Implementation Method 5>

[0100] Figure 16 This is a cross-sectional view showing the structure of the semiconductor device 500 according to Embodiment 5. In this embodiment, a vertical SBD made of β-type gallium oxide is shown.

[0101] In the semiconductor device 500 according to Embodiment 5, based on the structure of the semiconductor device 400 of Embodiment 4, an intermediate film 13, serving as a High-k film, is formed on the entire surface of the first main surface of the gallium oxide semiconductor layer 30, including the inner surface of the Schottky recess 17 and the upper surface of the second gallium oxide layer 3. A Schottky electrode 14 is formed on the intermediate film 13. Other structures are the same as those of the semiconductor device 400 of Embodiment 4.

[0102] The High-k film is the same as the intermediate film 13 of the semiconductor device 300 in Embodiment 3. By making the band gap of the intermediate film 13 smaller than that of β-Ga2O3, no new potential barrier is generated in the conduction band, and the positive characteristics of the SBD are not degraded.

[0103] In addition, the β-Ga2O3 constituting the first gallium oxide layer 2 has the problem that the anode pad electrode 15 is easily oxidized during high-temperature operation. However, by providing an intermediate film 13 between the Schottky groove 17 and the Schottky electrode 14, the reaction between the anode pad electrode 15 and β-Ga2O3 is suppressed, and the temperature stability is improved.

[0104] <Implementation Method 6>

[0105] This embodiment applies the semiconductor device described in any one of Embodiments 1 to 5 to a power conversion device. The application of the semiconductor device described in Embodiments 1 to 5 is not limited to a specific power conversion device. Hereinafter, as Embodiment 6, the case of applying the semiconductor device described in any one of Embodiments 1 to 5 to a three-phase inverter will be described.

[0106] Figure 17This is a block diagram illustrating the structure of a power conversion system that utilizes the power conversion device described in this embodiment.

[0107] Figure 17 The power conversion system shown consists of a power source 1000, a power conversion device 2000, and a load 3000. The power source 1000 is a DC power source, supplying DC power to the power conversion device 2000. The power source 1000 can be constructed from various structures, such as a DC system, solar cells, or batteries, or it can be constructed from a rectifier circuit connected to an AC system or an AC / DC converter. Alternatively, the power source 1000 can also be constructed from a DC / DC converter that converts DC power output from a DC system into a specified power.

[0108] The power conversion device 2000 is a three-phase inverter connected between the power source 1000 and the load 3000. It converts the DC power supplied from the power source 1000 into AC power and supplies AC power to the load 3000. Figure 17 As shown, the power conversion device 2000 includes: a main conversion circuit 201 that converts DC power into AC power and outputs it; a drive circuit 202 that outputs drive signals for driving each switching element of the main conversion circuit 201; and a control circuit 203 that outputs control signals for controlling the drive circuit 202 to the drive circuit 202.

[0109] Load 3000 is a three-phase motor driven by AC power supplied from power conversion device 2000. Furthermore, load 3000 is not limited to a specific application; it is a motor mounted on various electrical equipment, such as those used in hybrid vehicles, electric vehicles, railway vehicles, elevators, or air conditioning systems.

[0110] The details of the power conversion device 2000 are described below. The main conversion circuit 201 includes switching elements and freewheeling diodes (not shown). By switching the switching elements, it converts the DC power supplied from the power supply 1000 into AC power and supplies it to the load 3000. Various circuit structures exist for the main conversion circuit 201. The main conversion circuit 201 in this embodiment is a two-level three-phase full-bridge circuit, which can be constructed from six switching elements and six freewheeling diodes connected in anti-parallel to each switching element. At least one of the switching elements and freewheeling diodes in the main conversion circuit 201 is applied to the semiconductor device described in any of embodiments 1 to 5. The six switching elements are connected in series in pairs to form upper and lower arms, and each upper and lower arm constitutes a phase (U phase, V phase, W phase) of the full-bridge circuit. Furthermore, the output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 201, are connected to the load 3000.

[0111] The drive circuit 202 generates drive signals for driving the switching elements of the main converter circuit 201 and supplies them to the control electrodes of the switching elements of the main converter circuit 201. Specifically, according to the control signals from the control circuit 203 (described later), drive signals that turn the switching elements on and drive signals that turn the switching elements off are output to the control electrodes of each switching element. When the switching element is kept in the on state, the drive signal is a voltage signal above the threshold voltage of the switching element (on signal); when the switching element is kept in the off state, the drive signal is a voltage signal below the threshold voltage of the switching element (off signal).

[0112] The control circuit 203 controls the switching elements of the main converter circuit 201 to supply the desired power to the load 3000. Specifically, it calculates the time (on-time) during which each switching element of the main converter circuit 201 should be in the on state based on the power to be supplied to the load 3000. For example, the main converter circuit 201 can be controlled by PWM control that modulates the on-time of the switching elements according to the output voltage. Moreover, it outputs control commands (control signals) to the drive circuit 202 in such a way that it outputs on signals to the switching elements that should be in the on state and off signals to the switching elements that should be in the off state at each time point. The drive circuit 202 outputs on or off signals as drive signals to the control electrodes of each switching element according to the control signals.

[0113] In the power conversion device according to this embodiment, the semiconductor device according to any one of embodiments 1 to 5 is used as the switching element of the main conversion circuit 201, so that a power conversion device using a semiconductor device that suppresses the drop in withstand voltage can be obtained.

[0114] In this embodiment, an example of applying the semiconductor device involved in any of Embodiments 1 to 5 to a 2-level three-phase inverter is described. However, the application of the semiconductor device involved in Embodiments 1 to 5 is not limited to this, and it can be applied to various power conversion devices. In this embodiment, a 2-level power conversion device is used, but it can also be a 3-level or multi-level power conversion device. When supplying power to a single-phase load, the semiconductor device involved in any of Embodiments 1 to 5 can also be applied to a single-phase inverter. In addition, when supplying power to DC loads, the semiconductor device involved in any of Embodiments 1 to 5 can also be applied to DC / DC converters and AC / DC converters.

[0115] Furthermore, the power conversion device that applies any of the semiconductor devices involved in Embodiments 1 to 5 is not limited to the case where the load is an electric motor. For example, it can also be used as a power supply device for a discharge machining machine, a laser machining machine, an induction heating cooker, or a contactless power supply system, and can also be used as a power regulator for a solar power generation system, an energy storage system, etc.

[0116] The above descriptions are all examples and should be understood as allowing for the contemplation of numerous variations not shown.

[0117] Furthermore, the various embodiments can be freely combined, or appropriately modified or omitted. For example, the gate recess 5 is essentially used to remove the surface defect layer caused by annealing. Therefore, if the surface defects are formed at a deep location in the gallium oxide semiconductor layer 20 or the gallium oxide semiconductor layer 30, it is also possible to form the gate recess 5 to be the same as or deeper than the lower end of the second gallium oxide layer 3.

[0118] (Explanation of reference numerals in the attached image)

[0119] 1: n-type gallium oxide support layer; 2: First gallium oxide layer; 3: Second gallium oxide layer; 4: Third gallium oxide layer; 5: Gate trench; 6: Gate insulating film; 7: Gate electrode; 8: Interlayer insulating film; 9: Contact hole; 10: Source pad electrode; 11: Drain electrode; 12: Source trench; 13: Intermediate film; 14: Schottky electrode; 15: Anode pad electrode; 16: Cathode electrode; 17: Schottky trench; 20, 30: Gallium oxide semiconductor layers; 1000: Power supply; 2000: Power conversion device; 201: Main conversion circuit; 202: Drive circuit; 203: Control circuit; 3000: Load.

Claims

1. A semiconductor device comprising: Gallium oxide semiconductor layer; An impurity layer is formed within the surface of the first main surface of the gallium oxide semiconductor layer, having an acceptor-type first impurity, at least a portion of which is activated; The first groove is formed by removing a portion of the impurity layer and the gallium oxide semiconductor layer, and is shallower than the impurity layer. The first main electrode is disposed on the upper part of the first main surface; as well as The second main electrode is disposed on the upper part of the second main surface of the gallium oxide semiconductor layer.

2. The semiconductor device according to claim 1, wherein, The gallium oxide semiconductor layer has: n-type gallium oxide support layer; A first gallium oxide layer is disposed on the n-type gallium oxide support layer; A second gallium oxide layer is disposed on the first gallium oxide layer; as well as A third gallium oxide layer is disposed on the second gallium oxide layer. The impurity layer is the second gallium oxide layer. The first groove is formed by removing the third gallium oxide layer, the second gallium oxide layer, and a portion of the first gallium oxide layer. have: A gate insulating film is disposed on the inner surface of the first groove and on a portion of the upper part of the third gallium oxide layer; and A gate electrode is disposed on the gate insulating film and fills the first groove.

3. The semiconductor device according to claim 2, wherein, In the first gallium oxide layer and the third gallium oxide layer, the donor-type second impurity is contained in greater quantities than the first impurity. In the second gallium oxide layer, the first impurity is contained in greater quantities than the second impurity.

4. The semiconductor device according to claim 2 or 3, wherein, The first groove is formed deeper than the third gallium oxide layer.

5. The semiconductor device according to any one of claims 2 to 4, wherein, The gate electrode is disposed such that it overlaps with the upper edge of the third gallium oxide layer.

6. The semiconductor device according to any one of claims 2 to 5, wherein, The first groove is designed to round off the corners.

7. The semiconductor device according to claim 6, wherein, The first groove is configured such that the corner is in contact with the second gallium oxide layer.

8. The semiconductor device according to any one of claims 2 to 7, wherein, It has a second groove, which is formed by removing a portion of the third gallium oxide layer in the portion where the gate insulating film is not disposed. The second groove is configured such that its bottom does not reach the depth of the second gallium oxide layer. The first main electrode is disposed in such a way that it contacts the third gallium oxide layer via the second groove.

9. The semiconductor device according to claim 2, wherein, The device includes a second groove formed by removing a portion of the third gallium oxide layer, the second gallium oxide layer, and the first gallium oxide layer from the portion where the gate insulating film is not disposed. The second groove is formed deeper than the third gallium oxide layer. The first main electrode is disposed in such a way that it is electrically connected to the first gallium oxide layer via the second groove.

10. The semiconductor device according to claim 9, wherein, It also has an intermediate film, which is disposed between the second groove and the first main electrode, and has a smaller band gap than gallium oxide.

11. The semiconductor device according to claim 1, wherein, The gallium oxide layer has: n-type gallium oxide support layer; A first gallium oxide layer is disposed on the n-type gallium oxide support layer; and A second gallium oxide layer is disposed on the first gallium oxide layer. The impurity layer is the second gallium oxide layer. The first groove is created by removing both the second gallium oxide layer and the first gallium oxide layer. It has a Schottky electrode disposed between the first groove and the first main electrode.

12. The semiconductor device according to claim 11, wherein, In the first gallium oxide layer, the donor-type second impurity is contained in greater quantities than the first impurity. In the second gallium oxide layer, the first impurity is contained in greater quantities than the second impurity.

13. The semiconductor device according to claim 11 or 12, wherein, The first groove is designed to round off the corners.

14. The semiconductor device according to any one of claims 11 to 13, wherein, It also has an intermediate film, which is disposed between the first groove and the Schottky electrode and has a smaller band gap than gallium oxide.

15. The semiconductor device according to claim 10 or 14, wherein, The intermediate film is composed of a High-k film with a higher relative permittivity than that of silicon oxide film.

16. The semiconductor device according to claim 2 or 11, wherein, The second gallium oxide layer includes linear defects extending in a direction including the [010] direction.

17. A power conversion device, comprising: A main conversion circuit having a semiconductor device according to any one of claims 1 to 16, the main conversion circuit converting the input power and outputting it; The driving circuit outputs a driving signal to the semiconductor device to drive the semiconductor device. as well as The control circuit outputs control signals to the drive circuit.

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