Semiconductor device

Abstract

A semiconductor device includes a substrate (10), a first semiconductor layer (31) provided on the substrate and having a first conductivity type, a second semiconductor layer (32) provided on the substrate and having a second conductivity type different from the first conductivity type, a third semiconductor layer (21) provided in contact with the first semiconductor layer and the second semiconductor layer between the first semiconductor layer and the second semiconductor layer and having a third conductivity type same as either one of the first conductivity type and the second conductivity type, and a fourth semiconductor layer (22) provided in contact with the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer between the first semiconductor layer and the second semiconductor layer and having a fourth conductivity type different from the third conductivity type.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device. Background Technology

[0002] It is known that in the formation of FinFET (Field Effect Transistor) or nanosheet transistors and diodes, a semiconductor layer is disposed in the portion of the diode that corresponds to the gate electrode of the transistor. Additionally, CFET (Complementary Field Effect Transistor) technology is known.

[0003] <Prior art documents>

[0004] <Patent Documents>

[0005] Patent Document 1: U.S. Patent Application Publication No. 2023 / 0284427

[0006] Patent Document 2: US Patent No. 10504890

[0007] Patent Document 3: US Patent No. 11,532,607

[0008] Patent Document 4: US Patent No. 11075273

[0009] <Non-Patent Literature>

[0010] Non-patent document 1: H. Mertens et al., "Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle DielectricIsolation to enable CFET Inner Spacer Formation andMulti-VtPatterning" 2023IEEE Symposium on VLSI Technology and Circuits (VLSI Technology andCircuits), 11-16 June 2023, internet<URL:https: / / ieeexplore.ieee.org / document / 10185218>

[0011] Non-patent literature 2: H. Horiguchi et al., “3D Stacked Devices and MOL Innovations for Post-Nanosheet CMOS Scaling” 2023 International ElectronDevices Meeting (IEDM), 09-13 December 2023, Internet <URL:https: / / ieeexplore.ieee.org / abstract / document / 10413701?casa_token=UL8DwJOcPLAAAAAA:MnWiX7kpB3_V0LUFvUSt5lfnm3tRcn2XYE829_oRu4HWdXBXEofP6Jbvdx8jTNI9tWQLomu74YhMTL0> Summary of the Invention

[0012] <Problem to be solved by this invention>

[0013] The specific structure of diodes with large junction areas, when forming nanosheet transistors or CFETs and diodes, has not yet been studied in detail.

[0014] The purpose of this disclosure is to provide a semiconductor device capable of increasing the junction area.

[0015] <Methods for solving problems>

[0016] According to embodiments of this disclosure, a semiconductor device includes: a substrate; a first semiconductor layer disposed on the substrate and having a first conductivity type; a second semiconductor layer disposed on the substrate and having a second conductivity type different from the first conductivity type; a third semiconductor layer disposed between the first semiconductor layer and the second semiconductor layer and in contact with the first semiconductor layer and the second semiconductor layer, and having a third conductivity type of either the first conductivity type or the second conductivity type; and a fourth semiconductor layer disposed between the first semiconductor layer and the second semiconductor layer and in contact with the first semiconductor layer, the second semiconductor layer and the third semiconductor layer, and having a fourth conductivity type different from the third conductivity type.

[0017] <The Effects of the Invention>

[0018] According to the technology disclosed herein, the bonding area can be increased. Attached Figure Description

[0019] Figure 1 (a) to Figure 1(c) is a cross-sectional view of the semiconductor device of the first embodiment.

[0020] Figure 2 (a) to Figure 2 (c) is a cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment.

[0021] Figure 3 (a) to Figure 3 (c) is a cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment.

[0022] Figure 4 (a) and Figure 4 (b) is a cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment.

[0023] Figure 5 (a) and Figure 5 (b) is a cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment.

[0024] Figure 6 This is a cross-sectional view of a semiconductor device of the first modification of the first embodiment.

[0025] Figure 7 (a) to Figure 7 (c) is a cross-sectional view of a semiconductor device of the second variation of the first embodiment.

[0026] Figure 8 (a) and Figure 8 (b) is a cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment.

[0027] Figure 9 This is a circuit diagram of the semiconductor device according to the second embodiment.

[0028] Figure 10 (a) to 10(b) are top views of the semiconductor device of the second embodiment.

[0029] Figure 11 yes Figure 10 (a) and Figure 10 (b) AA section view.

[0030] Figure 12 yes Figure 10 (a) and Figure 10 (b) BB cross section.

[0031] Figure 13 yes Figure 10 (a) and Figure 10 (b) CC section view.

[0032] Figure 14This is a cross-sectional view of the semiconductor device according to the third embodiment.

[0033] Figure 15 This is a cross-sectional view showing the manufacturing method of the third embodiment.

[0034] Figure 16 This is a cross-sectional view showing the manufacturing method of the third embodiment.

[0035] Figure 17 This is a cross-sectional view of the semiconductor device of the first variation of the third embodiment.

[0036] Figure 18 This is a cross-sectional view of the semiconductor device according to the fourth embodiment.

[0037] Figure 19 This is a cross-sectional view of the semiconductor device according to the fourth embodiment.

[0038] Figure 20 This is a cross-sectional view of the semiconductor device according to the fourth embodiment.

[0039] Figure 21 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to the fourth embodiment.

[0040] Figure 22 This is a cross-sectional view of the semiconductor device in the fifth embodiment. Detailed Implementation

[0041] The following describes in detail the methods for implementing this disclosure with reference to the accompanying drawings. The following embodiments are examples used to embody the technical concept of the invention, but this disclosure is not limited to the structures or values ​​described below. Furthermore, in the various drawings, the same symbols are used to label the same structural parts, and repeated descriptions are omitted where appropriate. The size, positional relationships, etc., of the components shown in the various drawings are sometimes exaggerated to facilitate understanding of the invention.

[0042] (First Embodiment)

[0043] Figure 1 (a) to Figure 1 (c) is a cross-sectional view of the semiconductor device of the first embodiment. Figure 1 (a) is Figure 1 (b) and Figure 1 (c) AA section view. Figure 1 (b) and Figure 1 (c) are respectively Figure 1(a) shows the BB and CC cross-sectional views. The thickness direction of the substrate 10 is taken as the Z direction, the direction in which the semiconductor layers 31 and 32 are arranged is taken as the X direction, and the direction orthogonal to the X and Z directions is taken as the Y direction. Furthermore, the viewpoint of the plane formed by the X and Y directions, that is, the viewpoint observed from the Z direction, is sometimes also called the top view.

[0044] Semiconductor device 100 includes a substrate 10, a diode D1, a transistor T1, and an interlayer insulating film 50. An insulating film 12, wirings 14 and 16 are formed on the substrate 10. Wirings 14 and 16 sandwich the diode D1 and transistor T1 in the Y direction and extend in the X direction. Wirings 14 and 16 are, for example, connected to a first power supply VDD and a second power supply VSS, respectively.

[0045] The substrate 10 is, for example, a semiconductor substrate such as a single-crystal silicon substrate. The insulating film 12 is, for example, an insulating film such as a silicon oxide film or a silicon nitride film. The wiring 14 and 16 includes metallic materials such as copper, ruthenium, molybdenum, cobalt, iridium, or tantalum.

[0046] Diode D1 includes semiconductor layers 31, 32, 21, and 22. Semiconductor layers 31 (first semiconductor layer) and 32 (second semiconductor layer) are disposed on substrate 10. Semiconductor layers 31 and 32 have a thickness in the Z direction.

[0047] Semiconductor layer 21 (third semiconductor layer) is disposed between and in contact with semiconductor layers 31 and 32 in the X direction. Semiconductor layer 22 (fourth semiconductor layer) is disposed between and in contact with semiconductor layers 31, 32, and 21 in the X direction. Multiple semiconductor layers 21 and 22 are disposed thereon and are stacked alternately in the Z direction. In the Y direction, semiconductor layer 22 covers the end face of semiconductor layer 21.

[0048] Semiconductor layers 21, 31, and 32 are, for example, silicon layers. Semiconductor layer 22 is, for example, a silicon-germanium (SiGe) layer. Semiconductor layers 31, 32, 21, and 22 are single crystals. Semiconductor layer 21 can be a silicon-germanium layer, and semiconductor layer 22 can be a silicon layer. Semiconductor layers 21, 22, 31, and 32 can be semiconductors other than silicon and silicon-germanium. Semiconductor layers 31 and 21 are, for example, n-type semiconductor layers. Semiconductor layers 32 and 22 are, for example, p-type semiconductor layers. Semiconductor layers 31 and 21 form the cathode region of diode D1, and semiconductor layers 32 and 22 form the anode region of diode D1. Figure 1 (a) and Figure 1 The thick dashed line in (c) is the junction surface 28 between the cathode region and the anode region.

[0049] The conductivity types of semiconductor layers 31, 32, 21, and 22 are respectively set to a first conductivity type, a second conductivity type, a third conductivity type, and a fourth conductivity type, where the second conductivity type is different from the first conductivity type. The third conductivity type is either the first or the second conductivity type. The fourth conductivity type is different from the third conductivity type. That is, the fourth conductivity type is either the first or the second conductivity type. Therefore, semiconductor layers 31, 32, 21, and 22 can function as diode D1.

[0050] Transistor T1 includes semiconductor layers 36, 37, and 21, a gate electrode 41, and a gate insulating film 42. Semiconductor layers 36 (ninth semiconductor layer) and 37 (tenth semiconductor layer) are disposed on substrate 10. Semiconductor layers 36 and 32 have a thickness in the Z direction.

[0051] Semiconductor layer 21 (eleventh semiconductor layer) is disposed between and in contact with semiconductor layers 36 and 37 in the X direction. Gate insulating film 42 is disposed between semiconductor layers 36 and 37 in the X direction and in contact with semiconductor layer 21. Gate electrode 41 is disposed between semiconductor layers 36 and 37 in the X direction and covers the periphery of semiconductor layer 21 and gate insulating film 42. In the Y direction, gate electrode 41 sandwiches gate insulating film 42 and covers the end face of semiconductor layer 21.

[0052] Semiconductor layers 36 and 37 are, for example, silicon layers. Semiconductor layer 21 is, for example, a silicon layer or a silicon-germanium (SiGe) layer. Semiconductor layers 21, 36, and 37 can be semiconductors other than silicon and silicon-germanium. Semiconductor layer 21 is an n-type semiconductor. Semiconductor layers 36 and 37 are p-type semiconductor layers. Gate insulating film 42 is, for example, an insulating film of silicon oxide or hafnium oxide. Gate electrode 41 is a semiconductor layer or metal layer such as polycrystalline silicon.

[0053] The conductivity types of semiconductor layers 36, 37, and 21 are set to the ninth, tenth, and eleventh conductivity types, respectively, with the tenth conductivity type being the same as the ninth. The eleventh conductivity type is different from the ninth and tenth conductivity types. Therefore, semiconductor layers 36 and 37 function as source or drain electrodes, and transistor T1 functions as a MOS (Metal Oxide Semiconductor) FET. When the ninth and tenth conductivity types are p-type and the eleventh conductivity type is n-type, transistor T1 is a PFET. When the ninth and tenth conductivity types are n-type and the eleventh conductivity type is p-type, transistor T1 is an NFET.

[0054] Interlayer insulating film 50 surrounds diode D1 and transistor T1. Interlayer insulating film 50 is an insulating film with a dielectric constant lower than that of silicon oxide film or silicon oxide.

[0055] (Manufacturing method of the first embodiment)

[0056] Figure 2 (a) to Figure 5 (b) is a cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment. Figure 2 As shown in (a), a multilayer film 20 is formed on a substrate 10. Multiple semiconductor layers 21 and multiple semiconductor layers 23 are alternately stacked in the multilayer film 20. Semiconductor layers 23 serve as sacrificial layers, and their etch selectivity differs from that of semiconductor layers 21. When semiconductor layers 21 are silicon layers, semiconductor layers 23 are, for example, silicon-germanium layers. The multilayer film 20 is formed, for example, by epitaxy.

[0057] Next, as Figure 2 As shown in (b), a mask layer 60 is formed on the laminated film 20. The mask layer 60 is, for example, an insulating mask. Using the mask layer 60 as a mask, the laminated film 20 is removed. Thus, laminated films 20A and 20B are formed on the substrate 10. At this time, the upper part of the substrate 10 is also etched. The widths of the laminated films 20A and 20B in the Y direction can be... Figure 1 (b) and Figure 1 In (c), semiconductor layers 21 and 22 have approximately the same width.

[0058] Next, as Figure 2 As shown in (c), the mask layer 60 is removed. An insulating film 12 is formed on the upper part of the substrate 10. The insulating film 12 is, for example, STI (Shallow Trench Isolation). It can be formed before the insulating film 12 is formed. Figure 1 (b) and Figure 1 Wiring 14 and 16 in (c).

[0059] Next, as Figure 3 As shown in (a), a mask layer 62 is formed above the stacked films 20A and 20B. The mask layer 62 is, for example, an insulating mask. The mask layer 62 can be used without removing the mask layer 60. Using the mask layer 62 as a mask, semiconductor layers 31 and 32 are formed on the side surface of the stacked film 20A, and semiconductor layers 36 and 37 are formed on the side surface of the stacked film 20B.

[0060] Next, as Figure 3 As shown in (b), an interlayer insulating film 50 is formed on substrate 10 to cover stacked films 20A and 20B, semiconductor layers 31, 32, 36, and 37, and a mask layer 62. The upper surface of the interlayer insulating film 50 is planarized, and the upper surface of the mask layer 62 is exposed. The mask layer 62 is removed by etching, and openings 51a and 51b are formed in the interlayer insulating film 50 to expose the upper surfaces of the stacked films 20A and 20B, respectively. The widths of openings 51a and 51b in the Y direction are greater than the widths of the stacked films 20A and 20B in the Y direction.

[0061] Next, as Figure 3 As shown in (c), semiconductor layer 23 is removed through openings 51a and 51b. For example, if semiconductor layers 31, 32, 36, 37, and 21 are silicon layers and semiconductor layer 23 is a silicon-germanium layer, semiconductor layer 23 is removed using an etchant that selectively etches silicon onto silicon-germanium. For example, if semiconductor layers 31, 32, 36, 37, and 21 are silicon-germanium layers and semiconductor layer 23 is a silicon layer, semiconductor layer 23 is removed using an etchant that selectively etches silicon onto silicon-germanium. This forms a gap 52a between semiconductor layers 21 within opening 51a. A gap 52b is formed between semiconductor layers 21 within opening 51b. Semiconductor layers 21 are exposed in gaps 52a and 52b.

[0062] Since the width of openings 51a and 51b in the Y direction is greater than the width in the Y direction, the etchant can remove the semiconductor layer 23 in the -Z direction through the openings 51a and 51b on both sides of the stacked films 20A and 20B in the Y direction. As a result, the end face of the semiconductor layer 21 in the Y direction will be exposed in the gaps 52a and 52b.

[0063] Next, as Figure 4 As shown in (a), a mask layer 64 is formed to cover the interlayer insulating film 50. The mask layer 64 covers the opening 51a and exposes the opening 51b. Using the mask layer 64 as a mask, a gate insulating film 42 is formed within the opening 51b. Thus, the gate insulating film 42 is formed on the surfaces of semiconductor layers 36, 37, and 21. Additionally, an insulating film can be formed between semiconductor layers 36 and 37 and the gate insulating film 42. A residual void 52b exists within the gate insulating film 42.

[0064] Next, as Figure 4 As shown in (b), a gate electrode 41 is formed in the void 52b. Therefore, the void 52b is filled by the gate electrode 41. The gate electrode 41, gate insulating film 42, mask layer 64, and interlayer insulating film 50 are planarized in a manner that exposes semiconductor layers 31, 32, 36, and 37. Figure 3 In (c), gaps 52b are provided on both sides of the semiconductor layer 21 in the Y direction, therefore, as Figure 1 As shown in (b), the end face of the semiconductor layer 21 in the Y direction sandwiches the gate insulating film 42 and faces the gate electrode 41.

[0065] Next, as Figure 5 As shown in (a), the mask layer 64 between semiconductor layers 31 and 32 is removed. As a result, the surface of semiconductor layer 21 in the ±Z direction and the end face in the Y direction are exposed to the gap 52a.

[0066] Next, as Figure 5As shown in (b), a mask layer 66 is formed to cover the interlayer insulating film 50. The mask layer 66 covers the gate electrode 41 and exposes the gap 52a. Using the mask layer 66 as a mask, a semiconductor layer 22 is selectively formed within the opening 51a. Epitaxial growth is used to form the semiconductor layer 22. Therefore, the gap 52a is filled by the semiconductor layer 22. The surface of the semiconductor layer 21 in the ±Z direction contacts the semiconductor layer 22. Furthermore, in Figure 3 In (c), gaps 52a are provided on both sides of the semiconductor layer 21 in the Y direction, therefore, as Figure 1 As shown in (c), the end face of semiconductor layer 21 in the Y direction is in contact with semiconductor layer 22.

[0067] Next, by removing mask layer 66, it is possible to manufacture... Figure 1 (a) to Figure 1 (c) Semiconductor device 100.

[0068] According to the first embodiment, semiconductor layer 31 (first semiconductor layer) has a first conductivity type, and semiconductor layer 32 (second semiconductor layer) has a second conductivity type different from the first conductivity type. Semiconductor layer 21 (third semiconductor layer) has a third conductivity type, which is one of the first and second conductivity types, and semiconductor layer 22 (fourth semiconductor layer) has a fourth conductivity type different from the third conductivity type. Therefore, as... Figure 1 (a) and Figure 1 As shown in (c), the area of ​​the junction surface 28 between the cathode region and the anode region can be increased.

[0069] Multiple semiconductor layers 21 and 22 are provided, and the multiple semiconductor layers 21 and 22 are stacked alternately. Therefore, the area of ​​the bonding surface 28 can be increased.

[0070] like Figure 1 As shown in (c), semiconductor layer 22 covers the end face of semiconductor layer 21 in the Y direction (second direction), which is different from the X direction (first direction) in which semiconductor layers 31 and 32 are arranged. Therefore, the area of ​​the bonding surface 28 can be increased.

[0071] The semiconductor layer 21 of transistor T1 and the semiconductor layer 21 of diode D1 are used in Figure 2 (a) The layers that form a film simultaneously. Therefore, as Figure 2 (a) to Figure 5 As shown in (b), transistor T1 and diode D1 can be formed relatively easily on the same substrate 10.

[0072] (First variation of the first embodiment)

[0073] Figure 6 This is a cross-sectional view of a semiconductor device according to a first modification of the first embodiment. Figure 6 As shown, in the semiconductor device 102 of the first modification of the first embodiment, an insulating film 12 is disposed between the substrate 10 and the semiconductor layer 22. For example, in Figure 2 In (a), an insulating film is selectively formed on the substrate 10 before the formation of the lowermost semiconductor layer 23. Alternatively, an SOI (Silicon on Insulator) substrate is used as 10. Therefore, the insulating film 12 can be provided between the substrate 10 and the semiconductor layer 22. This allows for electrical separation between the substrate 10 and the diode D1. Other structures are the same as in the first embodiment, and descriptions are omitted.

[0074] (Second variation of the first embodiment)

[0075] Figure 7 (a) to Figure 7 (c) is a cross-sectional view of a semiconductor device of the second variation of the first embodiment. Figure 7 (a) is Figure 7 (b) and Figure 7 (c) AA section view. Figure 7 (b) and Figure 7 (c) are respectively Figure 7 (a) shows the BB and CC cross sections.

[0076] In the semiconductor device 104 of the second variation of the first embodiment, a semiconductor layer 23 is provided in the diode D1 instead of the semiconductor layer 22. In the Y direction, the end faces of the semiconductor layers 21 and 23 are in contact with the interlayer insulating film 50. Other structures are the same as in the first embodiment, and descriptions are omitted.

[0077] (Manufacturing method of the second variation of the first embodiment)

[0078] Figure 8 (a) and Figure 8 (b) is a cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment. The first embodiment is carried out... Figure 2 (a) to Figure 3 (b) is the process described. At this time, semiconductor layer 23 has a different conductivity type than semiconductor layer 21. For example... Figure 8 As shown in (a), an opening 51b is formed in the interlayer insulating film 50, but an opening 51a is not formed. The width of the opening 51b in the Y direction is greater than the width of the laminated film 20B in the Y direction. Other aspects are similar to... Figure 3 (c) Same.

[0079] like Figure 8 As shown in (b), the semiconductor layer 23 is removed through opening 51b. The semiconductor layer 23 in the -Z direction can also be removed through openings 51b located on both sides of the stacked film 20B in the Y direction. Other than... Figure 4 (a) Same. Then, proceed... Figure 4 (b) and Figure 5 (a) process. Does not form Figure 5 (b) Semiconductor layer 22. Since no semiconductor layer 22 is formed, as... Figure 7 As shown in (c), the semiconductor layer 21 is covered by an interlayer insulating film 50 on both sides in the Y direction. Thus, the semiconductor device 104 of the second modification of the first embodiment is manufactured.

[0080] As in the second variation of the first embodiment, the sacrificial layer of transistor T1 can be used as the semiconductor layer 23 (fourth semiconductor layer) of diode D1. Therefore, the interlayer insulating film 50 covers the end faces of semiconductor layers 21 and 23 in the Y direction. The width of semiconductor layer 21 in the Y direction is the same as the width of semiconductor layer 23 in the Y direction.

[0081] (Second Implementation)

[0082] The second implementation is an example of incorporating a diode in a Sequential CFET. Figure 9 This is a circuit diagram of the semiconductor device according to the second embodiment. Figure 9 The circuit shown is an example of a simple circuit for illustrating the second embodiment; the second embodiment is not limited to this. Figure 9 The circuit.

[0083] like Figure 9 As shown, the semiconductor device 106 includes an inverter INV, diodes D1 and D2. The inverter INV includes transistors T1 and T2. Transistors T1 and T2 are PMOSFET and NMOSFET, respectively. The source, gate, and drain of transistor T1 are electrically connected to a first power supply VDD, input terminal IN, and output terminal OUT, respectively. The source, gate, and drain of transistor T2 are electrically connected to a second power supply VSS, input terminal IN, and output terminal OUT, respectively. The voltage of the first power supply VDD is higher than the voltage of the second power supply VSS.

[0084] Diode D1 is connected to the second power supply VSS and node N1, with node N1 electrically connected to the input terminal IN. Diode D2 is connected to node N1 and the first power supply VDD. In diode D1, the direction from the second power supply VSS towards node N1 is the forward direction. In diode D2, the direction from node N1 towards the first power supply VDD is the forward direction. Diodes D1 and D2 are, for example, part of an electrostatic discharge (ESD) protection circuit.

[0085] Figure 10 (a) and Figure 10 (b) is a top view of the semiconductor device according to the second embodiment. Figure 10 (a) is a top view of the second floor, 72. Figure 10(b) is a top view of the first floor, 70. Figure 11 yes Figure 10 (a) and Figure 10 (b) AA section view. Figure 12 yes Figure 10 (a) and Figure 10 (b) BB cross section. Figure 13 yes Figure 10 (a) and Figure 10 (b) CC section view.

[0086] The semiconductor device 106 of the second embodiment includes a first layer 70, a second layer 72, and a wiring layer 74. The first layer 70 includes a substrate 10, insulating films 12 and 13, wiring 14 and 16, a diode D1, a transistor T1, and an interlayer insulating film 50. A first power supply VDD is provided to wiring 14, and a second power supply VSS is provided to wiring 16. Wiring 14 and 16 may be disposed on the back side (the side in the -Z direction) of the substrate 10. The interlayer insulating film 50 surrounds the diode D1 and the transistor T1. The insulating film 13 is disposed on the diode D1 and the transistor T1. The structures of the other components, such as the substrate 10, the insulating film 12, the wiring 14 and 16, the diode D1, and the transistor T1, are the same as those in the first embodiment and its variations, and are omitted from the description.

[0087] The second layer 72 includes an insulating film 12A, a substrate 10A, a diode D2, a transistor T2, and an interlayer insulating film 53. The substrate 10A is disposed on the insulating film 13. The insulating film 12A is disposed on the substrate 10A. The interlayer insulating film 53 surrounds the diode D2 and the transistor T2. The diode D2 includes semiconductor layers 33, 34, 26, and 27. Semiconductor layers 33 (the fifth semiconductor layer) and 34 (the sixth semiconductor layer) are disposed on the substrate 10A above semiconductor layers 31 and 32, respectively. Semiconductor layers 33 and 34 have a thickness in the Z direction.

[0088] Semiconductor layer 26 (seventh semiconductor layer) is disposed between semiconductor layers 33 and 34 in the X direction and is in contact with semiconductor layers 33 and 34. Semiconductor layer 27 (eighth semiconductor layer) is disposed between semiconductor layers 33 and 34 in the X direction and is in contact with semiconductor layers 33, 34 and 26. Multiple semiconductor layers 26 and 27 are disposed thereon and are stacked alternately in the Z direction. In the Y direction, semiconductor layer 27 covers the end face of semiconductor layer 26.

[0089] Transistor T2 includes semiconductor layers 38, 39, and 26, a gate electrode 43, and a gate insulating film 44. Semiconductor layers 38 and 39 are disposed on substrate 10A above semiconductor layers 36 and 37, respectively. Semiconductor layers 38 and 39 have a thickness in the Z direction.

[0090] Semiconductor layer 26 is disposed between and in contact with semiconductor layers 38 and 39 in the X direction. Gate insulating film 44 is disposed between semiconductor layers 38 and 39 in the X direction and in contact with semiconductor layer 26. Gate electrode 43 is disposed between semiconductor layers 38 and 39 in the X direction and covers the periphery of semiconductor layer 26 and gate insulating film 44. In the Y direction, gate electrode 43 sandwiches the end face of gate insulating film 44 covering semiconductor layer 26.

[0091] The wiring layer 74 is disposed on the second layer 72 and includes an interlayer insulating film 54, wirings 56a, 56b, 58a, and vias 55a-55c, 57a-57b. The interlayer insulating film 54 covers wirings 56a, 56b, 58a, and vias 55a-55c, 57a, and 57b.

[0092] In diode D1, semiconductor layers 31 and 21 are n-type, and semiconductor layers 32 and 22 are p-type. Therefore, semiconductor layers 31 and 21 are the cathode region, and semiconductor layers 32 and 22 are the anode region. In transistor T1, semiconductor layers 36 and 37 are p-type, and semiconductor layer 21 is n-type. Therefore, transistor T1 functions as a PMOSFET. Semiconductor layer 36 is the source region, and semiconductor layer 37 is the drain region.

[0093] In diode D2, semiconductor layers 33 and 26 are p-type, and semiconductor layers 34 and 27 are n-type. Therefore, semiconductor layers 33 and 26 are the anode region, and semiconductor layers 34 and 27 are the cathode region. In transistor T2, semiconductor layers 38 and 39 are n-type, and semiconductor layer 26 is p-type. Therefore, transistor T2 functions as an NMOSFET. Semiconductor layer 38 is the source region, and semiconductor layer 39 is the drain region.

[0094] exist Figure 10 In (a), wirings 46a to 46d are wirings in the second layer 72 that are respectively connected to semiconductor layers 38, 39, 33, and 34. Figure 10 In (b), wirings 45a to 45d are wirings that are respectively connected to semiconductor layers 36, 37, 31 and 32 in the first layer 70.

[0095] exist Figure 10 (a) and Figure 10 In (b), through-hole 47a electrically connects to wiring 45a and wiring 14. Through-hole 47b electrically connects to wiring 46a and wiring 16. Through-hole 47c electrically connects to wiring 46d and wiring 14. Through-hole 47d electrically connects to wiring 45d and wiring 16. Through-hole 48b electrically connects to wiring 45b and 46b. Through-hole 48c electrically connects to wiring 45c and wiring 46c.

[0096] Via 55a electrically connects gate electrode 43 and wiring 56a. Via 55b electrically connects semiconductor layer 33 and wiring 56a. Via 55c electrically connects gate electrode 41 and wiring 56b. (Refer to...) Figure 12 Through hole 57a connects to wiring 56a and 58a. Through hole 57b connects to wiring 56b and 58a.

[0097] The semiconductor layer 38 (source) of transistor T2 (NMOSFET) is electrically connected to wiring 16 (VSS) via wiring 46a and via 47b. The semiconductor layer 36 (source) of transistor T1 (PMOSFET) is electrically connected to wiring 14 (VDD) via wiring 45a and via 47a. The semiconductor layer 39 (drain) of transistor T2 and the semiconductor layer 37 (drain) of transistor T1 are electrically connected via wirings 45b, 46b and via 48b. Via 48b is electrically connected to the output terminal OUT.

[0098] The gate electrode 43 of transistor T2 is electrically connected to wiring 58a through via 55a, wiring 56a, and via 57a. The gate electrode 41 of transistor T1 is electrically connected to wiring 58a through via 55c, wiring 56b, and via 57b. Wiring 58b is electrically connected to the input terminal IN.

[0099] Semiconductor layer 32 (anode) of diode D1 is electrically connected to wiring 16 (VSS) via wiring 45d and via 47d. Semiconductor layer 34 (cathode) of diode D2 is electrically connected to wiring 14 (VDD) via wiring 46d and via 47c. Semiconductor layer 31 (cathode) of diode D1 is electrically connected to semiconductor layer 33 (anode) of diode D1 via wiring 45c, via 48c, and wiring 46c. Semiconductor layer 33 (anode) of diode D1 is electrically connected to wiring 58a (IN) via via 55b, wiring 56b, and via 57a.

[0100] The manufacturing method of semiconductor device 106 will be described. As in the first embodiment, diode D1 and transistor T1 are formed on substrate 10. An insulating film 13 is formed on diode D1 and transistor T1. As in the first embodiment, diode D2 and transistor T2 are formed on substrate 10A. Then, substrate 10A is bonded to the insulating film 13. Then, a wiring layer 74 is formed. Thus, semiconductor device 106 is manufactured.

[0101] In the semiconductor device 106, a p-type semiconductor layer 33 is disposed above an n-type semiconductor layer 31, and an n-type semiconductor layer 34 is disposed above a p-type semiconductor layer 32. A semiconductor layer 33 with the same conductivity type as semiconductor layer 31 can be disposed above semiconductor layer 31, and a semiconductor layer 34 with the same conductivity type as semiconductor layer 32 can be disposed above semiconductor layer 32.

[0102] That is, the fifth conductivity type of semiconductor layer 36 (the fifth semiconductor layer) can be either the first conductivity type of semiconductor layer 31 or the second conductivity type of semiconductor layer 32. The sixth conductivity type of semiconductor layer 37 (the sixth semiconductor layer) can be different from the fifth conductivity type. The seventh conductivity type of semiconductor layer 26 (the seventh semiconductor layer) can be either the fifth or the sixth conductivity type. The eighth conductivity type of semiconductor layer 27 (the eighth semiconductor layer) can be different from the seventh conductivity type.

[0103] The above illustrates an example where transistor T1 is a PMOSFET and transistor T2 is an NMOSFET, but it's also possible for transistor T1 to be an NMOSFET and transistor T2 to be a PMOSFET. Transistors T1 and T2 can be either NMOSFETs or PMOSFETs.

[0104] The above illustrates an example where the layers (first layer 70 and second layer 72) forming diodes and transistors are two layers, but it can also be three or more layers.

[0105] (Third Implementation)

[0106] The third embodiment is an example of incorporating a diode or thyristor in a monolithic CFET. Figure 14 This is a cross-sectional view of the semiconductor device according to the third embodiment. Figure 14 As shown, in the semiconductor device 108 of the third embodiment, the uppermost layer of semiconductor layer 22 in the first layer 70 is in contact with the lowermost layer of semiconductor layer 27 in the second layer 72. The uppermost layer of gate electrode 41 in the first layer 70 is in contact with the lowermost layer of gate electrode 43 in the second layer 72. The interlayer insulating film 50 of the first layer 70 and the second layer 72 is continuously integrated.

[0107] In diode D1, semiconductor layers 31 and 21 are n-type, and semiconductor layers 32 and 22 are p-type. A pn-junction surface 28a is formed between semiconductor layers 32 and 22 and semiconductor layers 31 and 21. In diode D2, semiconductor layers 33 and 26 are p-type, and semiconductor layers 34 and 27 are n-type. A pn-junction surface 28c is formed between semiconductor layers 33 and 26 and semiconductor layers 34 and 27. The uppermost semiconductor layer 22 of semiconductor layers 21 and 22 and the lowermost semiconductor layer 27 of semiconductor layers 26 and 27 have different conductivity types and are in contact with each other. Therefore, a pn-junction surface 28b is formed between semiconductor layers 22 and 27. Therefore, diodes D1 and D2 function as thyristors with n-type and p-type regions, respectively.

[0108] Figure 15 and Figure 16 This is a cross-sectional view showing the manufacturing method of the third embodiment. (Example) Figure 15 As shown, stacked films 20 and 25 are sequentially formed on substrate 10. Stacked film 20 has multiple semiconductor layers 21 and multiple semiconductor layers 22 stacked alternately. Stacked film 25 has multiple semiconductor layers 27 and multiple semiconductor layers 26 stacked alternately.

[0109] Next, as Figure 16 As shown, a mask layer 60 is formed on the stacked films 25. The mask layer 60 is, for example, an insulating mask. Using the mask layer 60 as a mask, the stacked films 20 and 25 are removed. Thus, a structure in which stacked films 20A and 25A are stacked, and a structure in which stacked films 20B and 25B are stacked, can be formed on the substrate 10. Then, similarly to the first embodiment, a first layer 70 including diode D1 and transistor T1 is formed. Furthermore, a second layer 72 including diode D2 and transistor T2 is formed. Thus, the semiconductor device 108 of the third embodiment can be manufactured.

[0110] (First variation of the third embodiment)

[0111] Figure 17 This is a cross-sectional view of the semiconductor device in the first modification of the third embodiment. Figure 17 As shown, in the semiconductor device 110 of the first modification of the third embodiment, the lowermost semiconductor layer 27a of semiconductor layers 26 and 27 in diode D2 and the uppermost semiconductor layer 22a of semiconductor layers 21 and 22 in diode D1 have the same conductivity type and are connected to each other. Semiconductor layers 22a and 27a can be formed continuously under the same film formation conditions. Therefore, no pn junction is formed between diodes D1 and D2. Diodes D1 and D2 are connected in series. Other structures are the same as in the third embodiment, and descriptions are omitted.

[0112] (Fourth implementation)

[0113] The fourth embodiment is an example of providing an insulating film 45 (MDI: Middle Dielectric Isolation) between diodes D1 and D2. Figures 18 to 20 This is a cross-sectional view of the semiconductor device according to the fourth embodiment. Figure 18 yes Figure 19 and Figure 20 AA section view. Figure 19 and Figure 20 They are Figure 18 BB and CC cross-sections in the diagram.

[0114] In the semiconductor device 112 of the fourth embodiment, as Figure 18 and Figure 19As shown, an insulating film 45 is disposed within the interlayer insulating film 50 between diodes D1 and D2. The insulating film 45 is disposed between the uppermost semiconductor layer 22 of semiconductor layers 21 and 22 of diode D1 and the lowermost semiconductor layer 27 of semiconductor layers 26 and 27 of diode D2. Thus, the insulating film 45 enables diodes D1 and D2 to be electrically isolated.

[0115] like Figure 19 and Figure 20 As shown, an insulating film 45 is disposed between the gate electrode 41 of transistor T1 and the gate electrode 43 of transistor T2. In the Z direction, the insulating film 45 does not completely separate the gate electrodes 41 and 43. Therefore, the gate electrode 41 of transistor T1 and the gate electrode 43 of transistor T2 are electrically connected. Other structures are the same as in the third embodiment, and descriptions are omitted.

[0116] Figure 21 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to the fourth embodiment. In the third embodiment... Figure 16 Next, the side surfaces of semiconductor layers 22 and 27 are selectively etched relative to semiconductor layers 21 and 26. This forms protrusions 68 on the side surfaces of semiconductor layers 21 and 26. Then, a mask layer is formed on the side surfaces of the stacked films 20A, 20B, 25A, and 25B. When the mask layer is etched, the mask layer remains in regions with narrow gaps between the side surfaces of the protrusions 68. No mask layer remains in regions 69 between the stacked films 20A and 25A and between the stacked films 20B and 25B, where there are wide gaps between the protrusions 68. Using the mask layer and semiconductor layers 21 and 26 as masks, semiconductor layers 22 and 27 in region 69 are etched. Then, an insulating film 45 is formed in region 69. Then, similar to the third embodiment, a first layer 70 including diode D1 and transistor T1 is formed. Furthermore, a second layer 72 including diode D2 and transistor T2 is formed. Thus, the semiconductor device 112 of the fourth embodiment can be manufactured.

[0117] (Fifth Embodiment)

[0118] The fifth embodiment is an example of extending diodes D1 and D2 along the X direction. Figure 22 This is a cross-sectional view of the semiconductor device in the fifth embodiment. (As shown) Figure 22As shown, in the semiconductor device 114 of the fifth embodiment, in addition to semiconductor layers 31, 32, 21, and 22, diode D1 also includes semiconductor layers 32A, 21A, and 22A. Semiconductor layer 32A (another second semiconductor layer) sandwiches semiconductor layer 31 between semiconductor layer 32. Semiconductor layer 21A (another third semiconductor layer) is disposed between semiconductor layers 31 and 32A, and is in contact with semiconductor layers 31 and 32A, and has the same conductivity type as semiconductor layer 21. Semiconductor layer 22A (a second semiconductor layer) is disposed between semiconductor layers 31 and 32A, and is in contact with semiconductor layers 31, 32A, and 21A, and has the same conductivity type as semiconductor layer 22. Therefore, diode D1 can be extended in the X direction.

[0119] In addition to semiconductor layers 33, 34, 26, and 27, diode D2 also includes semiconductor layers 34A, 26A, and 27A. Semiconductor layer 33 is sandwiched between semiconductor layers 34A and 34A. Semiconductor layer 26A is disposed between and in contact with semiconductor layers 33 and 34A, and has the same conductivity type as semiconductor layer 26A. Semiconductor layer 27A is disposed between and in contact with semiconductor layers 33, 34A, and 26A, and has the same conductivity type as semiconductor layer 27A. This allows diode D2 to extend in the X direction.

[0120] Multiple semiconductor layers 31 and multiple semiconductor layers 32 are alternately arranged in the X direction, and a stacked film of semiconductor layers 21 and 22 is provided between semiconductor layers 31 and 32. This increases the junction area of ​​diode D1. In the first embodiment and its variations, semiconductor layers 32A, 21A, and 22A may also be provided. In the second, third, and fourth embodiments and their variations, semiconductor layers 32A, 21A, 22A, 34A, 26A, and 27A may be provided.

[0121] The present disclosure has been described above with reference to various embodiments, but the present invention is not limited to the requirements shown in the above embodiments. Modifications can be made to these points without prejudice to the spirit of the present disclosure, and appropriate provisions can be made depending on the application.

[0122] Symbol Explanation

[0123] 10, 10A substrate

[0124] 12, 12A, 13, 45 insulating film

[0125] Wiring for 14, 16, 45a, 45b, 45c, 45d, 46a, 46b, 46c, 46d, 56a, 56, 58a, 58b

[0126] 20, 20A, 20B, 25, 25A, 25B laminated films

[0127] Semiconductor layers 21, 21A, 22, 22A, 23, 26, 26A, 27, 27A, 31, 32, 32A, 33, 34, 34A, 36, 37, 38, 39

[0128] 41, 43 Grid electrodes

[0129] 42, 44 Grid insulating film

[0130] Interlayer insulating films: 47a, 47b, 47c, 47d, 48b, 48c, 55a, 55b, 55c, 57a, 57b, 50, 53, 54

Claims

1. A semiconductor device comprising: substrate; A first semiconductor layer is disposed on the substrate and has a first conductivity type; A second semiconductor layer is disposed on the substrate and has a second conductivity type different from the first conductivity type; A third semiconductor layer is disposed between the first semiconductor layer and the second semiconductor layer and in contact with the first semiconductor layer and the second semiconductor layer, and has a third conductivity type of either the first conductivity type or the second conductivity type; and A fourth semiconductor layer is disposed between the first semiconductor layer and the second semiconductor layer, and is in contact with the first semiconductor layer, the second semiconductor layer and the third semiconductor layer, and has a fourth conductivity type different from the third conductivity type.

2. The semiconductor device according to claim 1, wherein, The third semiconductor layer and the fourth semiconductor layer are each provided with multiple layers. The plurality of third semiconductor layers and the plurality of fourth semiconductor layers are stacked alternately.

3. The semiconductor device according to claim 1 or 2, wherein, The first semiconductor layer and the second semiconductor layer are arranged in a first direction. The fourth semiconductor layer covers the end face of the third semiconductor layer in a second direction different from the first direction.

4. The semiconductor device according to claim 1 or 2, wherein, The first semiconductor layer and the second semiconductor layer are arranged in a first direction. The semiconductor device includes an insulating film covering the end faces of the third semiconductor layer and the fourth semiconductor layer in a second direction different from the first direction.

5. The semiconductor device according to claim 1 or 2, comprising: Another second semiconductor layer is disposed on the substrate and has a second conductivity type; Another third semiconductor layer is disposed between the first semiconductor layer and the other second semiconductor layer, and is in contact with the first semiconductor layer and the other second semiconductor layer, and has the third conductivity type; and Another fourth semiconductor layer is disposed between the first semiconductor layer and the other second semiconductor layer, and is in contact with the first semiconductor layer, the other second semiconductor layer and the other third semiconductor layer, and has the fourth conductivity type.

6. The semiconductor device according to claim 1 or 2, comprising: A fifth semiconductor layer is disposed above the first semiconductor layer and has a fifth conductivity type, which is either the first conductivity type or the second conductivity type. A sixth semiconductor layer is disposed above the second semiconductor layer and has a sixth conductivity type different from the fifth conductivity type. A seventh semiconductor layer is disposed between the fifth semiconductor layer and the sixth semiconductor layer, and in contact with the fifth semiconductor layer and the sixth semiconductor layer, and has a seventh conductivity type, which is either the fifth conductivity type or the sixth conductivity type. and An eighth semiconductor layer is disposed between the fifth semiconductor layer and the sixth semiconductor layer, and in contact with the fifth semiconductor layer, the sixth semiconductor layer and the seventh semiconductor layer, and has an eighth conductivity type different from the seventh conductivity type.

7. The semiconductor device according to claim 6, wherein, The uppermost semiconductor layer in the third and fourth semiconductor layers, and the lowermost semiconductor layer in the seventh and eighth semiconductor layers, have the same conductivity type and are in contact with each other.

8. The semiconductor device according to claim 6, wherein, The uppermost semiconductor layer in the third and fourth semiconductor layers, and the lowermost semiconductor layer in the seventh and eighth semiconductor layers, have different conductivity types and are in contact with each other.

9. The semiconductor device according to claim 8, wherein, A thyristor comprising a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a fourth semiconductor layer, a fifth semiconductor layer, a sixth semiconductor layer, a seventh semiconductor layer, and an eighth semiconductor layer.

10. The semiconductor device according to claim 6, wherein, It has an insulating film disposed between the uppermost semiconductor layer in the third semiconductor layer and the fourth semiconductor layer, and between the lowermost semiconductor layer in the seventh semiconductor layer and the eighth semiconductor layer.

11. The semiconductor device according to claim 6, wherein, The first semiconductor layer and the second semiconductor layer are arranged in a first direction. The fifth semiconductor layer and the sixth semiconductor layer are arranged in the first direction. The semiconductor device has an insulating film covering the end faces of the third semiconductor layer, the fourth semiconductor layer, the seventh semiconductor layer, and the eighth semiconductor layer in a second direction different from the first direction.

12. The semiconductor device according to claim 1 or 2, comprising: A ninth semiconductor layer is disposed on the substrate and has a ninth conductivity type, which is either the first conductivity type or the second conductivity type. A tenth semiconductor layer is disposed on the substrate and has the same tenth conductivity type as the ninth conductivity type; The eleventh semiconductor layer is disposed between the ninth semiconductor layer and the tenth semiconductor layer, and is in contact with the ninth semiconductor layer and the tenth semiconductor layer, and has an eleventh conductivity type different from the ninth conductivity type; A gate insulating film is disposed between the ninth semiconductor layer and the tenth semiconductor layer, and in contact with the eleventh semiconductor layer; and A gate electrode is disposed between the ninth semiconductor layer and the tenth semiconductor layer, and covers the eleventh semiconductor layer and the gate insulating film.

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