Semiconductor light-receiving element, method for manufacturing semiconductor light-receiving element, optical line terminal device, multi-stage intensity modulation transceiver device, digital coherent reception device, fiber radio system, spad sensor system, and laser radar device

Abstract

The present disclosure relates to a semiconductor light-receiving element, a manufacturing method of a semiconductor light-receiving element, an optical line terminal device, a multi-level intensity modulation transceiver device, a digital coherent reception device, a fiber radio system, a SPAD sensor system, and a laser radar device. A semiconductor light-receiving element (100) of the present disclosure includes a substrate (1), a first mesa structure (30) having at least an n-type semiconductor layer (2, 3), a multiplication layer (4), a p-type electric field relaxation layer (5), a light absorption layer (6), and an i-type semiconductor layer (8) having a larger band gap than the light absorption layer (6), which are formed in this order on the substrate (1), a second mesa structure (31) formed on the first mesa structure (30) and having at least a window layer (9) having a larger band gap than the light absorption layer (6), and a step portion (40) constituted by the outermost surface of the first mesa structure (30) exposed on the outer peripheral side of the second mesa structure (31).

Description

Technical Field

[0001] This disclosure relates to semiconductor light-receiving elements, methods for manufacturing semiconductor light-receiving elements, optical line termination devices, multi-level intensity modulation transceivers, digital coherent receivers, fiber optic wireless systems, SPAD sensor systems, and lidar devices. Background Technology

[0002] With the development of digital transformation that flexibly utilizes digital information, the development of communication networks for exchanging digital information and data centers for data accumulation and processing has been significant. Optical communication can be used for communication within communication networks and data centers. In recent years, optical communication has made remarkable progress in terms of speed and capacity. In the development of optical communication, the receiver needs photodiodes (PDs) and avalanche photodiodes (APDs) capable of achieving high receiving sensitivity.

[0003] In access networks connecting users to optical communications, Passive Optical Networks (PON) are the primary mode of operation. PON systems originated with G(E)-PON systems transmitting 1-2 Gbps signals, and it is expected that 10G-EPON systems and XG-PON systems transmitting 10 Gbps signals will gradually increase in the future.

[0004] Furthermore, the ITU-T (International Telecommunication Union Telecommunication Standardization Sector) is researching 50G-PON systems as the next generation of high-speed PON systems, and it is expected that 50Gbps-level transmissions will be practically implemented in access networks in the future.

[0005] Patent Document 1: Japanese Patent No. 4609430

[0006] Patent Document 2: Japanese Patent No. 4985298

[0007] Patent Document 3: Japanese Patent No. 5025330

[0008] Patent Document 4: Japanese Patent Application Publication No. 11-354827

[0009] Patent Document 5: Japanese Patent Application Publication No. 3-050875

[0010] Patent Document 6: Japanese Patent Application Publication No. 2002-324911

[0011] Non-patent literature 1: Jiyuan Zheng, et al., “Digital Alloy In AlAs Avalanche Photodiodes”, JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL.36, NO.17, SEPTEMBER 1, pp.3580-3585, 2018

[0012] (1) On the topic of multiplication layers in APD

[0013] For the APD, a semiconductor light-receiving element used in a PON system, its structure consists of a light-absorbing layer (InGaAs), an electric field mitigation layer (InP or InAlAs), and a multiplication layer (InP or InAlAs). A high electric field of approximately 800 kV / cm is applied to the multiplication layer to multiply, i.e., ionize, the electrons and holes generated in the light-absorbing layer. The electric field mitigation layer weakens the electric field to prevent the high electric field of the multiplication layer from being applied to the light-absorbing layer. The ionization coefficient of electrons is denoted as α, and the ionization coefficient of holes is denoted as β.

[0014] In an APD (Active Power Detector), the greater the difference in ionization coefficients between electrons and holes, the less excess noise is generated during multiplication and the higher the receiver sensitivity. Furthermore, since a greater difference in ionization coefficients between electrons and holes results in a shorter multiplication time in the multiplication layer, the response bandwidth becomes wider.

[0015] The electron-to-hole ionization coefficient ratio k is defined by k = β / α. When electrons are injected into the multiplication layer, a smaller ionization coefficient ratio k results in improved performance of the APD. The multiplication layer of an APD used in optical communication can be made of compound semiconductor materials such as InAlAs or InP.

[0016] When InAlAs is chosen as the material for the multiplication layer, the difference in ionization coefficients between electrons and holes increases compared to InP. Specifically, in InP, the ionization coefficient of holes is greater than that of electrons, approximately twice that of electrons. Conversely, when InAlAs is chosen as the material for the multiplication layer, the ionization coefficient of electrons is greater than that of holes, approximately five times that of holes. Therefore, since using InAlAs as the multiplication layer results in higher receiver sensitivity, InAlAs is a more suitable material than InP for the multiplication layer of an APD.

[0017] In PON systems, as mentioned above, the APD, as a semiconductor light-receiving element, is required to have a wide response bandwidth and high receiving sensitivity. However, unlike the PD, the APD suffers from a reduced response bandwidth at high multiplication rates because the multiplication time required for doubling increases with increasing multiplication rate.

[0018] While APDs with InAlAs as the constituent material used in optical communication have a wider response bandwidth than APDs made of other semiconductor materials, their response bandwidth remains around 20 GHz when the multiplication rate is above 6. In other words, there is a problem that it is difficult to achieve the wide response bandwidth of 37.5 GHz or more required for 50G-PON systems when using existing APDs.

[0019] As mentioned above, APDs, which are semiconductor light-receiving elements used in optical communication, are required to operate over a wider response bandwidth. Patent Document 5 describes an APD using a superlattice as the multiplication layer, but since the thickness of each layer of the superlattice is 5 to 10 nm, it functions as a quantum well reflecting the band gap of each layer. If the thickness of each stacked layer is several nm or more, the energy unevenness reflecting the band gap of each layer will hinder the transit of charge carriers, resulting in a decrease in transit velocity.

[0020] In 50G-PON systems, the response bandwidth of semiconductor light-emitting elements and semiconductor light-receiving elements, as well as the light output of semiconductor light-emitting elements and the receiving sensitivity of semiconductor light-receiving elements, are insufficient. Therefore, it is advisable to consider setting up a digital bandwidth compensation circuit composed of a digital signal processor (DSP) after the APD in the optical network unit (ONU), i.e., the receiving device on the user side.

[0021] In addition, in the optical line terminal (OLT), i.e. the receiving device on the central office side, in order to compensate for the insufficient receiving sensitivity of the semiconductor light receiving element, a semiconductor optical amplifier (SOA) is required, or an electro-absorption modulated laser diode (EML) needs to be integrated into the transmitting side of the ONU to increase the optical output.

[0022] However, concerns are raised that the replacement of existing PON systems with 50G-PON systems will be difficult to proceed due to the high power consumption of DSPs and SOA, which are the main reasons for rising costs.

[0023] In existing PON systems beyond next-generation high-speed PON systems, research is underway to increase the number of branches of the optical signal output from the OLT in order to reduce costs. However, in this case, it is also necessary to integrate SOA into the EML on the transmitting side of the OLT and ONU to increase the optical output, which leads to increased power consumption and cost of the transmitter.

[0024] As mentioned above, in order to compensate for the limitations of the receiving sensitivity and response bandwidth of semiconductor light-receiving elements, a transceiver design was carried out that incorporates expensive and power-consuming DSPs and SOAs into ONUs and OLTs. However, this design has the problem of increased power consumption and cost.

[0025] To address the aforementioned issues related to the multiplication layer in APDs, non-patent literature 1, for example, is investigating the application of digital alloy structures with significantly lower ionization coefficient ratios (k) compared to random alloy structures to multiplication layers. However, there are still challenges to be solved in applying digital alloy structure multiplication layers to APDs with highly reliable p-type impurity diffusion structures.

[0026] (2) Issues related to the formation of p-type impurity regions in APDs with p-type impurity diffusion structures

[0027] Patent document 1, etc., describes an APD with a p-type impurity diffusion structure. In an APD with a p-type impurity diffusion structure, an electric field is concentrated in the light-receiving region by forming a convex p-type impurity diffusion region, i.e., a p-type region, on the lower side, suppressing local multiplication (edge ​​breakdown) at the outer periphery of the light-receiving region. Since the APD with a p-type impurity diffusion structure does not experience edge breakdown, it is an excellent structure with low dark current and high reliability. In an APD with a p-type impurity diffusion structure, a p-type region is formed in the i-type InP window layer through Zn diffusion, and a pn junction is formed to apply a reverse bias, thereby applying an electric field to the light-absorbing layer, the electric field mitigation layer, and the multiplication layer. The area from the deepest part of the p-type region to the n-type semiconductor layer becomes a depletion layer due to the applied electric field.

[0028] In a wide-response APD, a short transit time for carriers transiting in the depletion layer is a necessary condition. The 3dB band ftr, which is determined by the transit time of carriers in the depletion layer within the optical absorption layer, is represented by the following equation (1).

[0029] ftr=3.5Vav / (2πW) (1)

[0030] In equation (1), W is the thickness of the depletion layer formed within the light-absorbing layer, and Vav is the average saturation drift velocity of electrons and holes. Besides the transit time of the depletion layer formed within the light-absorbing layer, the overall response bandwidth of the APD is determined by the RC time constant, doubling time, and the diffusion time of charge carriers in the p-type region within the light-absorbing layer. According to equation (1), since ftr is inversely proportional to the thickness of the depletion layer, to achieve a wide response bandwidth, the depletion layer needs to be thinned to a p-type region midway through the light-absorbing layer.

[0031] Therefore, thermal diffusion of p-type impurities such as Zn needs to be carried out at high temperatures for extended periods, with the deepest part of the p-type impurity diffusion region reaching the light-absorbing layer. However, with long diffusion times for Zn at high temperatures, the dopants contained in the p-type InP electric field mitigation layer diffuse upwards and downwards, failing to achieve the required electric field mitigation. As a result, applying a high electric field to the light-absorbing layer leads to tunnel breakdown, resulting in the loss of multiplication. Alternatively, even if multiplication occurs, excessively high dark current may result. Particularly when the multiplication layer is a digital alloy structure, the digital alloy structure becomes disordered due to the thermal diffusion of p-type impurities into the multiplication layer, leading to increased multiplication noise.

[0032] Thus, if the thermal diffusion of p-type impurities is carried out for a long time in order to shorten the transit time of charge carriers, and the deepest part of the p-type impurity diffusion region is formed inside the light absorption layer, then the problem of no longer multiplying, increased dark current, or increased multiplication noise will occur. Summary of the Invention

[0033] This disclosure was made to solve the problems mentioned above, and its purpose is to obtain a semiconductor light-receiving element having excellent element characteristics such as operation over a wide response bandwidth, a method for manufacturing the same, and an apparatus using the semiconductor light-receiving element.

[0034] The semiconductor light-receiving element disclosed herein includes:

[0035] substrate;

[0036] The first mesa structure has at least an n-type semiconductor layer, a multiplication layer, a p-type electric field mitigation layer, a light absorption layer, and an i-type semiconductor layer with a band gap larger than that of the light absorption layer, which are sequentially formed on the substrate.

[0037] The second mezzanine structure, formed on the first mezzanine structure, has at least a window layer with a band gap larger than the light absorption layer; and

[0038] The step portion is formed by the outermost surface of the first platform structure that is exposed on the outer periphery of the second platform structure.

[0039] The method for manufacturing the semiconductor light-receiving element disclosed herein includes:

[0040] The process of epitaxially growing an n-type semiconductor layer, a multiplication layer, a p-type electric field mitigation layer, a light absorption layer, an i-type semiconductor layer with a band gap larger than the light absorption layer, a window layer with a band gap larger than the light absorption layer, and a p-type contact layer on a substrate in at least sequential order.

[0041] On the surface of the aforementioned p-type contact layer, a selective diffusion mask consisting of an insulating film with approximately circular openings is formed.

[0042] The process of forming a p-type impurity diffusion region from the above-mentioned opening, with the bottom extending at least to the interior of the above-mentioned light absorption layer;

[0043] Excluding the above-mentioned process of selecting a diffusion mask;

[0044] The process of processing the above-mentioned p-type contact layer into a ring shape along the outer periphery of the light-receiving area;

[0045] The process of forming a second mesa structure by etching the outer periphery of the aforementioned light-receiving area until at least the type I semiconductor layer is exposed on the surface; and

[0046] The process of forming the first mezzanine structure by etching the portion of the second mezzanine structure from the outer periphery, excluding the pre-defined area.

[0047] The optical line terminal device disclosed herein includes:

[0048] The aforementioned semiconductor light-receiving element;

[0049] A light-splitter allows the optical signal to be incident on the aforementioned semiconductor light-receiving element;

[0050] An amplifier circuit amplifies the electrical signal output from the aforementioned semiconductor light-receiving element;

[0051] A clock data recovery circuit, connected to the aforementioned amplification circuit, recovers clock data from the amplified electrical signal; and

[0052] The forward error correction circuit is connected to the aforementioned clock data recovery circuit to correct errors in the clock data.

[0053] The multi-level intensity modulation transceiver device disclosed herein includes:

[0054] The aforementioned semiconductor light-receiving element receives light signals modulated by multiple intensity levels;

[0055] An amplifier circuit amplifies the electrical signal output from the aforementioned semiconductor light-receiving element;

[0056] An analog-to-digital converter circuit, connected to the aforementioned amplifier circuit, converts the amplified electrical signal into a digital signal; and

[0057] A digital signal processing circuit, connected to the aforementioned analog-to-digital conversion circuit, processes the aforementioned digital signal.

[0058] The fiber optic wireless system disclosed herein has the following features:

[0059] The light source emits a simulated modulated light signal;

[0060] The aforementioned semiconductor light-receiving element receives the aforementioned light signal after it has been analog-modulated;

[0061] The transmission path transmits the analog electrical signal output from the aforementioned semiconductor light-receiving element to the antenna; and

[0062] The antenna is connected to the aforementioned transmission path and radiates the aforementioned analog electrical signal as a radio wave signal.

[0063] The digital coherent receiving device disclosed herein includes:

[0064] The aforementioned semiconductor light-receiving element;

[0065] A polarization separator separates the polarization of a polarization-multiplexed optical signal that has been modulated in intensity and phase.

[0066] A 90-degree mixer performs wavelength division and synthesis on the optical signal output from the aforementioned polarization separator; and

[0067] The digital signal processing circuit is connected to the aforementioned 90-degree mixer to process the digital signals.

[0068] The SPAD (Single Photon Avalanche Diode) sensor system disclosed herein features:

[0069] The SPAD sensor is composed of the aforementioned semiconductor light-receiving element;

[0070] The quenching circuit repeatedly applies voltages above and below the breakdown voltage to the aforementioned SPAD sensor; and

[0071] The optoelectronic measurement circuit measures the electrical signal output from the aforementioned SPAD sensor.

[0072] The lidar device disclosed herein includes:

[0073] The light source emits light in a pulsed manner;

[0074] The aforementioned semiconductor light-receiving element receives light emitted from the aforementioned light source that is reflected back by the object;

[0075] An amplifier circuit amplifies the electrical signal output from the aforementioned semiconductor photosensitive element; and

[0076] The ranging circuit calculates the distance based on the electrical signal amplified by the aforementioned amplifier circuit.

[0077] According to the semiconductor light-receiving element and the manufacturing method of the semiconductor light-receiving element disclosed herein, the step portion provides an effect that enables the semiconductor light-receiving element and the manufacturing method of the semiconductor light-receiving element to have excellent element characteristics such as operation over a wide response bandwidth.

[0078] According to the optical line terminal device, multi-level intensity modulation transceiver device, digital coherent receiver device, fiber optic wireless system, SPAD sensor system and lidar device involved in this disclosure, since the semiconductor light-receiving element of this disclosure is used as the semiconductor light-receiving element, it achieves the effect of obtaining various devices and systems with excellent performance. Attached Figure Description

[0079] Figure 1 This is a cross-sectional view showing the element structure of a back-illuminated APD, which is an example of a semiconductor light-receiving element according to Embodiment 1.

[0080] Figure 2 This is a cross-sectional view after epitaxial crystal growth in a manufacturing method of a back-illuminated APD, which is an example of a semiconductor light-receiving element according to Embodiment 1.

[0081] Figure 3 This is a cross-sectional view of the p-type impurity diffusion process in a method for manufacturing a back-illuminated APD, which is an example of a semiconductor light-receiving element according to Embodiment 1.

[0082] Figure 4 This is a cross-sectional view of the contact layer patterned in a manufacturing method of a back-illuminated APD, which is an example of a semiconductor light-receiving element according to Embodiment 1.

[0083] Figure 5 This is a cross-sectional view of the window layer patterned in a manufacturing method of a back-illuminated APD, which is an example of a semiconductor light-receiving element according to Embodiment 1.

[0084] Figure 6A This is a cross-sectional view showing the patterned mesa groove in a manufacturing method of a back-illuminated APD, which is an example of a semiconductor light-receiving element according to Embodiment 1. Figure 6B It is a top view.

[0085] Figure 7This is a cross-sectional view after a surface protective film is formed and patterned in a manufacturing method of a back-illuminated APD, which is an example of a semiconductor light-receiving element according to Embodiment 1.

[0086] Figure 8 This is a cross-sectional view after the surface-side electrode is formed and patterned in the manufacturing method of a back-illuminated APD, which is an example of a semiconductor light-receiving element according to Embodiment 1.

[0087] Figure 9 This is a cross-sectional view showing the element structure of a back-incident type APD, which is a comparative example of Embodiment 1.

[0088] Figure 10A This is a cross-sectional view after epitaxial crystal growth in a manufacturing method of a back-illuminated APD, which is an example of a semiconductor light-receiving element according to Embodiment 1. Figure 10B This is a cross-sectional view of the epitaxial crystal growth process in the manufacturing method of a back-incidence type APD, which serves as a comparative example.

[0089] Figure 11A This is a cross-sectional view after the p-type impurity diffusion process in the manufacturing method of a back-illuminated APD, which is an example of a semiconductor light-receiving element according to Embodiment 1. Figure 11B This is a cross-sectional view after the p-type impurity diffusion process in the manufacturing method of a back-incidence type APD, which serves as a comparative example.

[0090] Figure 12 This is a cross-sectional view showing the element structure of a back-illuminated APD, which is an example of a semiconductor light-receiving element according to Embodiment 2.

[0091] Figure 13 This is a diagram showing the electric field dependence of the dead zone of electrons in the InAlAs multiplication layer.

[0092] Figures 14A to 14C This is a schematic diagram representing the ionization coefficients of electrons and holes.

[0093] Figure 15 This is a graph showing the dependence of the ionization coefficient ratio and the layer thickness of the tunnel current multiplication layer.

[0094] Figures 16A to 16D This is a schematic diagram showing the ionization coefficients in the multiplication layer and the electric field mitigation layer. Figure 16A This is a graph representing the ionization coefficients in the case of a random alloy structure multiplication layer. Figure 16B This is a graph representing the ionization coefficient in the case of digital alloy multiplication layers. Figure 16C This is a graph representing the ionization coefficients of a partially disordered digital alloy multiplication layer. Figure 16DThis is a graph showing the ionization coefficient when a thick electric field mitigation layer is combined with a digital alloy structure multiplication layer.

[0095] Figure 17 This is a cross-sectional view showing the element structure of a back-illuminated APD, which is an example of a semiconductor light-receiving element according to Embodiment 2, Variation 1.

[0096] Figure 18 This is a cross-sectional view showing the element structure of a back-illuminated APD, which is an example of a semiconductor light-receiving element according to Embodiment 2, Modification 2.

[0097] Figure 19 This is a cross-sectional view showing the element structure of a back-illuminated APD, which is an example of a semiconductor light-receiving element according to Embodiment 2, Modification 3.

[0098] Figure 20 This is a cross-sectional view showing the element structure of a back-incident type APD, which is an example of a semiconductor light-receiving element according to Embodiment 2, Variation 4.

[0099] Figure 21 This is a cross-sectional view showing the element structure of a back-illuminated APD, which is an example of a semiconductor light-receiving element according to Embodiment 2, Variation 5.

[0100] Figure 22 This is a cross-sectional view after the formation of the second terrace in the manufacturing process of a back-illuminated APD, which is an example of a semiconductor light-receiving element according to Embodiment 2, Variation 5.

[0101] Figure 23 This is a cross-sectional view showing the element structure of a surface-incident type APD, which is an example of a semiconductor light-receiving element according to Embodiment 3.

[0102] Figure 24 This is a configuration diagram showing the optical line terminal (OLT) of the 50G-PON system according to Embodiment 4.

[0103] Figure 25 This is a configuration diagram of the optical line terminal unit (ONU) of the 50G-PON system according to Embodiment 4.

[0104] Figure 26 This is a diagram showing the configuration of the optical line terminal (OLT) of a 50G-PON system as a comparative example.

[0105] Figure 27 This is a diagram showing the configuration of the optical line terminal (OLT) of the 50G-PON system according to Embodiment 4.

[0106] Figure 28 This is a diagram showing the configuration of the optical line terminal unit (ONU) of the 50G-PON system according to Embodiment 4.

[0107] Figure 29 This is a diagram illustrating the configuration of the multi-level intensity modulation transceiver device according to Embodiment 5.

[0108] Figure 30A and Figure 30B This is a schematic diagram showing the received waveform of the multi-level intensity modulation transceiver device according to Embodiment 5.

[0109] Figure 31A and Figure 31B This is a schematic diagram illustrating the operation of the PD during highlight input.

[0110] Figure 32 This is a diagram illustrating the operation of the APD during highlight input.

[0111] Figure 33 It is a graph representing the residence time of electrons and holes in each material that makes up the multiplication layer.

[0112] Figure 34 This is a diagram illustrating the configuration of the fiber optic wireless system according to Embodiment 6.

[0113] Figure 35 This is a diagram showing the configuration of a fiber optic wireless system as a comparative example.

[0114] Figure 36 This is a diagram illustrating the configuration of the digital coherent receiving device according to Embodiment 7.

[0115] Figure 37A This is a schematic diagram showing the waveforms of a digital coherent receiving device used as a comparative example. Figure 37B This is a schematic diagram showing the waveform of the digital coherent receiving device according to Embodiment 7.

[0116] Figure 38 This is a diagram showing the configuration of the SPAD sensor system according to Embodiment 8.

[0117] Figure 39A This is a schematic diagram illustrating the multiplication characteristics of the SPAD sensor system used as a comparative example. Figure 39B This is a schematic diagram illustrating the multiplication characteristics of the SPAD sensor system according to Embodiment 8.

[0118] Figure 40 It is a graph that calculates the difference between the quenching electric field of each component of the multiplication layer and the electric field of the Geiger mode.

[0119] Figure 41 This is a diagram showing the configuration of the lidar device according to Embodiment 9.

[0120] Figure 42A This is a schematic diagram showing the received waveform of the APD mounted on the lidar device used as a comparative example. Figure 42B This is a schematic diagram showing the received waveform of the APD mounted on the lidar device according to Embodiment 9. Detailed Implementation

[0121] Implementation method 1.

[0122] Figure 1 This is a cross-sectional view showing the element structure of a back-illuminated APD, which is an example of the semiconductor light-receiving element 100 according to Embodiment 1. In the following description, the upper side refers to the direction in which the semiconductor layer is stacked from the surface of the semiconductor substrate, i.e., the stacking direction, and the lower side refers to the direction opposite to the stacking direction, in other words, the direction from the surface side where the semiconductor layer is formed in the semiconductor substrate toward the back side.

[0123] <Component Structure of Semiconductor Photodetector (APD) According to Embodiment 1>

[0124] As an example of the semiconductor light-receiving element 100 according to Embodiment 1, the back-incident type APD is composed of an Fe-doped InP substrate 1, a first mesa structure 30, a second mesa structure 31, a p-type impurity diffusion region 20, a step portion 40, a surface protective film 11, a surface-side anti-reflection film 15, an n-type electrode 50, a p-type electrode 51, a back-side anti-reflection film 16, and a back electrode 52. The first mesa structure 30 has a carrier concentration of 5 × 10⁻⁶ sequentially formed on the Fe-doped InP substrate 1. 17 ~8×10 18 cm －3 Furthermore, the n-type InP conductive layer has a thickness of 0.1–1.0 μm and a carrier concentration of 5 × 10⁻⁶. 17 ~8×10 18 cm －3 Furthermore, it consists of an n-type InAlAs conductive layer 3 with a thickness of 0.1–1.0 μm, an i-type InAlAs multiplication layer 4, and a carrier concentration of 1 × 10⁻⁶. 16 ~5×10 18 cm －3The structure comprises a p-type InAlAs electric field mitigation layer 5 with a thickness of 10–100 nm, an i-type InGaAs light-absorbing layer 6 with a thickness of 0.1–2.0 μm, an i-type InAlGaAs gradient layer 7 with a thickness of 5–100 nm and progressively shorter component wavelengths, and an i-type InAlAs surface protective layer 8 with a thickness of 10–200 nm. An n-type InP conductive layer 2 is exposed as a semiconductor layer on its outer periphery and has a roughly circular surface when viewed from above. The second mesa structure 31 has a carrier concentration of 5 × 10⁻⁶ formed sequentially on the first mesa structure 30. 17 ~8×10 18 cm －3 Furthermore, it consists of a p-type InP window layer with a thickness of 0.1–3.0 μm and a carrier concentration of 5 × 10⁹ / L. 17 ~8×10 18 cm －3 The p-type InGaAs contact layer 10 has a thickness of 0.05 to 0.5 μm and is annular along the outer periphery of the light-receiving area 60, which is approximately circular when viewed from above. The p-type impurity diffusion region 20 is disposed on a portion of the p-type InP window layer 9 and the i-type InGaAs light-absorbing layer 6 on the inner periphery of the annular p-type InGaAs contact layer 10. The step portion 40 is formed by the outermost surface of the first mesa structure 30 exposed on the outer periphery of the second mesa structure 31 and has a width of 0.5 μm or more in the outer periphery direction. The surface protective film 11 is formed by an insulating film covering the first mesa structure 30, the side surface of the first mesa structure 30, and the step portion 40. A side antireflective film 15 is formed on the inner periphery of the annular p-type InGaAs contact layer 10, that is, on the surface of the p-type InP window layer 9 corresponding to the approximately circular light-receiving area 60, and is made of SiN film; an n-type electrode 50 is formed on the surface of the n-type InP conductive layer 2 exposed as a semiconductor layer on the outer periphery of the first mesa structure 30; a p-type electrode 51 is disposed on the surface of the annular p-type InGaAs contact layer 10 and the surface of the surface-side antireflective film 15; a back-side antireflective film 16 is disposed on the back side of the Fe-doped InP substrate 1 at a position opposite to the p-type electrode 51; and a back-side electrode 52 is disposed on the outer periphery of the back-side antireflective film 16 on the back side of the Fe-doped InP substrate 1.

[0125] In this disclosure, type i refers to undoped or p-type impurity concentration or n-type impurity concentration of 5 × 10⁻⁶. 17 cm －3 The following situations apply.

[0126] As described above, the step portion 40 is formed by the outermost surface of the first mesa structure 30 exposed on the outer periphery of the second mesa structure 31, and has a width of 0.5 μm or more in the outer periphery direction. In the above configuration, the outermost surface of the first mesa structure 30 exposed on the outer periphery becomes the upper surface of the i-type InAlAs surface protective layer 8. In the following description, the surface exposed as a semiconductor layer in the step portion 40 will be referred to as the step surface 41. For example, in the above configuration, the upper surface of the i-type InAlAs surface protective layer 8, i.e., the upper side surface, is the step surface 41. Here, the upper surface refers to, for example, the upper side of the two surfaces of the i-type InAlAs surface protective layer 8, i.e., the side opposite to the Fe-doped InP substrate 1.

[0127] The p-type electrode 51 also functions as a reflective film, which is used to return the incident light 90 that is not absorbed by the i-type InGaAs light absorption layer 6 and is transmitted to the surface side from the back side of the Fe-doped InP substrate 1 to the i-type InGaAs light absorption layer 6.

[0128] The p-type InP window layer 9 can also be replaced by a p-type InAlAs layer, a p-type InAlGaAs layer, or a p-type InGaAsP layer. Alternatively, the window layer can be composed of multiple layers formed by stacking any two or more of the p-type InP, p-type InAlAs, p-type InAlGaAs, and p-type InGaAsP layers. The i-type InAlAs surface protective layer 8 also functions as a gradient layer to smooth the bandgap step difference between the two layers positioned vertically in the i-type InAlAs surface protective layer 8.

[0129] Alternatively, an i-type InP layer can be used as a surface protective layer to replace the i-type InAlAs surface protective layer 8. By using an i-type InP layer as a surface protective layer, oxidation of the step surface 41 of the step portion 40 can be prevented, which results in the extension of the lifespan of the semiconductor photosensitive element.

[0130] When an i-type InP layer is used as a surface protective layer, by making the window layer a p-type InAlAs layer, the step portion 40 can be easily formed by selective etching. When an i-type InP layer is used as a surface protective layer, an i-type InAlAs layer can also be placed between the i-type InAlGaAs gradient layer 7 and the i-type InP surface protective layer to mitigate the bandgap step difference between them.

[0131] Here, a gradient layer is used to mitigate the step difference between the valence band and conduction band when semiconductor materials of different materials or compositions are stacked. Specifically, examples include multiple layers having an intermediate band gap between the two layers to be stacked, layers with material compositions that can form intermediate energy steps in the valence band and conduction band even if they do not have an intermediate band gap, and layers in which the two layers to be stacked are stacked alternately with short periods of a few nm or less.

[0132] The p-type InAlAs electric field mitigation layer 5 can also be composed of any structure, either a random alloy structure or a digital alloy structure. Alternatively, it can be composed of a p-type InP layer. A gradient layer composed of an i-type InAlGaAs layer or an i-type InGaAsP layer can also be placed between the p-type InAlAs electric field mitigation layer 5 and the i-type InGaAs light-absorbing layer 6.

[0133] <Method for manufacturing a semiconductor light-receiving element according to Embodiment 1>

[0134] Appropriate reference Figures 2 to 8 The following describes a method for manufacturing a back-illuminated APD, which is an example of the semiconductor light-receiving element 100 according to Embodiment 1.

[0135] First, starting from the Fe-doped InP substrate 1, an n-type InP conductive layer 2, an n-type InAlAs conductive layer 3, an i-type InAlAs multiplication layer 4, a p-type InAlAs electric field mitigation layer 5, an i-type InGaAs light absorption layer 6, an i-type InAlGaAs gradient layer 7, an i-type InAlAs surface protection layer 8, a p-type InP window layer 9, and a p-type InGaAs contact layer 10 are epitaxially grown sequentially. Figure 2 This is a cross-sectional view showing the epitaxial crystal growth layers in the manufacturing method of the back-incident type APD according to Embodiment 1.

[0136] Examples of epitaxial crystal growth methods include metal-organic vapor phase epitaxy (MOVPE) and molecular beam epitaxy (MBE).

[0137] The preferred n-type impurity (n-type dopant) for the epitaxial crystal growth layer is sulfur (S) or silicon (Si). The preferred p-type impurity (p-type dopant) is zinc (Zn), beryllium (Be), carbon (C), cadmium (Cd), or magnesium (Mg). In the case of the MOVPE method, the crystal growth temperature during epitaxial crystal growth is preferably in the range of 450°C to 800°C, and in the case of the MBE method, this temperature is preferably in the range of 500°C to 800°C.

[0138] As a feature of the wafer after epitaxial crystal growth of the back-incident type APD involved in Embodiment 1, the following can be cited: the presence of an i-type InAlAs surface protective layer 8, and the fact that the InP window layer and InGaAs contact layer are not i-type but p-type.

[0139] A selective diffusion mask 12, composed of insulating films such as SiN or SiO2, is formed on the surface of the p-type InGaAs contact layer 10, with an opening provided in the portion that becomes the light-receiving region 60. A p-type impurity diffusion region 20 is formed by thermally diffusing p-type impurities such as Zn, Cd, or Mg into the semiconductor layer using gas-phase diffusion or solid-phase diffusion. The diffusion temperature is set within a range of 400°C to 800°C. During thermal diffusion, the thermal diffusion is controlled so that the deepest part of the p-type impurity diffusion region 20 is located inside the i-type InGaAs light-absorbing layer 6. Figure 3 This is a cross-sectional view after the p-type impurity diffusion process in the manufacturing method of the back-incident type APD according to Embodiment 1.

[0140] The depth to which p-type impurities diffuse into the interior of the i-type InGaAs light-absorbing layer 6 is controlled to be below 0.3 μm. If the p-type impurities diffuse too deeply into the interior of the i-type InGaAs light-absorbing layer 6, the receiver sensitivity will decrease due to the recombination of carriers in the p-typed i-type InGaAs light-absorbing layer 6. Therefore, the optimal depth for p-type impurities to diffuse into the interior of the i-type InGaAs light-absorbing layer 6 is within the range of 0.05–0.3 μm.

[0141] In the back-incident type APD described in Embodiment 1, the p-type InP window layer 9 and the p-type InGaAs contact layer 10 are pre-doped with p-type impurities such as Zn, Be, C, Cd or Mg during epitaxial crystal growth.

[0142] For example, such as Figure 3 As shown, if solid-state diffusion of Zn is performed on the p-type InGaAs contact layer 10 and p-type InP window layer 9 doped with Zn or Be, the pre-doped Zn or Be will begin to thermally diffuse downwards, i.e. to the Fe-doped InP substrate 1, without waiting for the arrival of newly added Zn from the outside. Therefore, the p-type impurities thermally diffuse to the i-type InGaAs light-absorbing layer 6 in a short time.

[0143] Especially when Zn is thermally diffused into the pre-doped Be p-type InGaAs contact layer 10 and p-type InP window layer 9, inter-diffusion or mutual diffusion of Be and Zn occurs, i.e., the rapid substitution of Be with existing impurity atoms in the semiconductor layer. Through this inter-diffusion, the atoms that become the diffusion source, i.e., Zn, reach the deepest part of the p-type impurity diffusion region 20 in a very short time. Since the diffusion rate of Zn is greater than that of Be, Zn inter-diffusion into the interior of the i-type InGaAs light-absorbing layer 6 in a short time, thus greatly reducing the diffusion time.

[0144] On the other hand, for the outer periphery of the light-receiving region 60, i.e. the region covered by the selective diffusion mask 12, it is preferable to maintain a thick depletion layer to minimize the entry of p-type impurities into the interior of the i-type InGaAs light-absorbing layer 6. Since it is inherently difficult for vacancies to be generated in the region covered by the selective diffusion mask 12, p-type impurities are difficult to thermally diffuse into the interior of the i-type InGaAs light-absorbing layer 6.

[0145] Especially when the pre-doped p-type impurity is Be, since the diffusion rate of Be is less than that of Zn as described above, the interdiffusion of Be into the i-type InGaAs light-absorbing layer 6 is difficult to occur, thus the depletion layer can be kept thick. Therefore, it is preferable to use a combination of impurities in which Be is used as the p-type impurity during the epitaxial growth of the p-type InGaAs contact layer 10 and the p-type InP window layer 9, and Zn is used as the p-type impurity thermally diffused in the subsequent p-type impurity diffusion process.

[0146] After the above-mentioned p-type impurity diffusion process, the p-type InGaAs contact layer 10 is processed into a ring shape when viewed from above. Figure 4 This is a cross-sectional view of the p-type InGaAs contact layer 10 after it has been machined into an annular shape in the manufacturing method of the back-facing incident APD according to Embodiment 1. The inner diameter of the annular p-type InGaAs contact layer 10 is machined to be approximately the same as or smaller than the p-type impurity diffusion region 20. On the other hand, the outer diameter of the annular p-type InGaAs contact layer 10 can be either smaller or larger than the p-type impurity diffusion region 20.

[0147] Next, the p-type InP window layer 9 exposed on the outer peripheral surface of the annular p-type InGaAs contact layer 10 is removed by etching until the surface of the i-type InAlAs surface protective layer 8 is reached. Figure 5 This is a cross-sectional view of the p-type InP window layer 9 after patterning in the manufacturing method of the back-incidence type APD according to Embodiment 1.

[0148] However, it is not necessary to etch until the p-type InP window layer 9 is completely removed. That is, it is sufficient to remove the p-type InP window layer 9 by etching. If the p-type window layer 9 on the surface of the i-type InAlAs surface protective layer 8 is about 100 nm thick, it can remain. The reason is that if the remaining p-type InP window layer 9 is a thin layer, it will be depleted when a voltage is applied to the APD, and will function in a way that mitigates the electric field of the step portion 40.

[0149] Furthermore, the etching depth can be increased to approximately 100 nm from the lower surface of the i-type InAlAs surface protective layer 8, allowing the etched surface to reach the interior of the i-type InAlGaAs gradient layer 7 or the interior of the i-type InGaAs light-absorbing layer 6. The reason for this is that even during the heat treatment for thermal diffusion, p-type impurities diffuse downwards from the p-type InP window layer 9; by removing the area after thermal diffusion of p-type impurities in a subsequent process, the electric field of the step portion 40 can be mitigated.

[0150] Both the p-type InP window layer 9 and the i-type InAlAs surface protective layer 8 can be composed of InP layers. Alternatively, the p-type InP window layer 9 can be composed of a p-type InAlAs layer, and the i-type InAlAs surface protective layer 8 can be composed of an i-type InP layer. In the latter case, it facilitates selective etching of the window layer.

[0151] The second mesa structure 31 is formed by etching the p-type InP window layer 9 as described above. The second mesa structure 31 has a p-type InP window layer 9 formed sequentially on the first mesa structure 30 described later, and a p-type InGaAs contact layer 10 in an annular shape along the outer periphery of the light-receiving area 60 which is approximately circular when viewed from above, and the surface is approximately circular when viewed from above.

[0152] On the outer periphery of the roughly circular second mesa structure 31, i.e., on the outer periphery of the etched p-type InP window layer 9, a step portion 40 with a width of more than 1 μm is left in the outer periphery direction of the step surface 41, with the upper surface of the i-type InAlAs surface protective layer 8 as the outermost surface. The semiconductor layer on the outer periphery is then etched until the etched surface reaches the n-type InAlAs conductive layer 3 or the n-type InP conductive layer 2, thereby forming a mesa trench 35. The depth of the mesa trench 35 is only required to allow the i-type InAlAs multiplication layer 4 to be physically separable and to ensure that the etched bottom surface does not reach the Fe-doped InP substrate 1. Figure 6A and Figure 6B These are cross-sectional and top views of the back-incident type APD manufacturing method according to Embodiment 1, after the formation of the mesa trench 35 where the etched bottom surface reaches the n-type InP conductive layer 2.

[0153] The order can also be arbitrarily changed to implement the following: Figure 4 The process involves patterning the p-type InGaAs contact layer 10 in a ring shape up to the formation of the mesa trench in FIG6. For example, the p-type InGaAs contact layer 10 can be patterned into a ring shape by etching the p-type InP window layer 9 to a roughly circular shape when viewed from above, leaving the outer periphery of the roughly circular p-type InGaAs contact layer 10, and etching away the inner periphery of the p-type InGaAs contact layer 10. Alternatively, the p-type InP window layer 9 and the p-type InGaAs contact layer 10 can be patterned after the mesa trench 35 has been formed.

[0154] The first mesa structure 30 is formed by etching the semiconductor layers on the outer periphery of the second mesa structure 31 and the step portion 40. The first mesa structure 30 has an n-type InP conductive layer 2, an n-type InAlAs conductive layer 3, an i-type InAlAs multiplication layer 4, a p-type InAlAs electric field mitigation layer 5, an i-type InGaAs light-absorbing layer 6, an i-type InAlGaAs gradient layer 7, and an i-type InAlAs surface protection layer 8 sequentially formed on an Fe-doped InP substrate 1. The n-type InP conductive layer 2 is exposed as a semiconductor layer on the outer periphery and has a roughly circular surface when viewed from above. That is, the outermost surface of the first mesa structure 30 is exposed as a semiconductor layer at the step portion 40.

[0155] After the first mesa structure 30 is formed on the wafer, a surface protective film 11 and a surface-side anti-reflective film 15, both composed of SiN films, are formed. Openings are provided on the surface of the annular p-type InGaAs contact layer 10 and on the surface of the n-type InP conductive layer 2 exposed at the bottom of the mesa trench 35 by the aforementioned etching. Alternatively, SiO2 films, SiON films, BCB (benzocyclobutene) films, or insulating films composed of organic materials such as polyimide can be used instead of SiN films. Figure 7 This is a cross-sectional view of the back-incident type APD manufacturing method according to Embodiment 1, after forming a surface protective film 11 and a surface-side anti-reflective film 15 made of SiN film and patterning the opening.

[0156] Next, a p-type electrode 51 is formed on the annular p-type InGaAs contact layer 10 and on the insulating film composed of SiN film in the light-receiving region 60, and an n-type electrode 50 is formed on the surface of the n-type InP conductive layer 2 exposed on the outer periphery of the first mesa structure 30. Figure 8 This is a cross-sectional view showing the component structure after the p-type electrode 51 and n-type electrode 50 are formed in the manufacturing method of the back-incident type APD according to Embodiment 1.

[0157] The p-type electrode 51 and n-type electrode 50 are composed of a combination of multiple metal films, such as Ti / Au, Ti / Pt / Au, Pt / Ti / Pt / Au, and Pt / Ti / Au / Ti / Pt / Au, arranged from bottom to top. When the back-incident APD is mounted with the junction face downwards, the p-type electrode 51 can also be composed of multiple metal films formed from Ti / Au / Ti / Pt / Au arranged from bottom to top. The reason for inserting Pt into a portion of the multiple metal films is that Pt acts as a barrier metal to prevent solder material from diffusing into the back-incident APD.

[0158] In this example of the semiconductor light-receiving element 100 according to Embodiment 1, the reason for using Fe-doped InP substrate 1 as the semiconductor substrate in a back-illuminated APD is that if an n-type InP substrate is used in the case of a back-illuminated APD, the light absorption loss caused by the n-type InP substrate would be slightly greater. However, even if an n-type InP substrate is used instead of Fe-doped InP substrate 1, it will not cause any particular obstacle to the operation of the APD. When an n-type InP substrate is applied to a back-illuminated APD, an n-type electrode can be provided on the back side of the n-type InP substrate so that the back electrode of the back-illuminated APD can be used as an n-type electrode.

[0159] <Function of the semiconductor light-receiving element involved in Implementation Method 1>

[0160] The following is about... Figure 1 The function of a back-incident type APD in an example of the semiconductor light-receiving element 100 according to Embodiment 1 will be explained.

[0161] For the back-incident APD according to Embodiment 1, during epitaxial crystal growth, p-type impurities such as Zn and Be are pre-doped in the p-type InGaAs contact layer 10 and the p-type InP window layer 9. For example, if solid-phase diffusion or gas-phase diffusion of Zn is performed on the p-type InGaAs contact layer 10 and the p-type InP window layer 9, which are Be-doped semiconductor layers, from the outside, the Be, which is pre-presented as a p-type impurity, begins to diffuse downwards without waiting for the arrival of Zn based on solid-phase diffusion or gas-phase diffusion. Through the interdiffusion of Be and Zn, Zn reaches the deepest part of the p-type impurity diffusion region 20 in a very short time. That is, the p-type impurities, namely Zn and Be, interdiffuse into the interior of the i-type InGaAs light-absorbing layer 6 in a short time.

[0162] Due to the relationship between diffusion depth and (diffusion time) 0.5The diffusion time is proportional to the diffusion depth. Therefore, if the required diffusion depth is halved, the diffusion time becomes 1 / 4, thus enabling p-type impurities to thermally diffuse into the i-type InGaAs light-absorbing layer 6 in a short time. By shortening the diffusion time, the p-type impurities pre-contained in the p-type InAlAs electric field mitigation layer 5 diffuse into the i-type InGaAs light-absorbing layer 6, thereby preventing adverse conditions such as increased dark current.

[0163] In the back-illuminated APD according to Embodiment 1, the inner peripheral side of the annular p-type InGaAs contact layer 10 functions as a light-receiving region 60. In the light-receiving region 60, electrons generated by the light absorbed by the i-type InGaAs light-absorbing layer 6 are multiplied by crossing to the i-type InAlAs multiplication layer 4.

[0164] The deepest part of the p-type impurity diffusion region 20 extends into the interior of the i-type InGaAs light-absorbing layer 6 by about 0.2 μm. Since the thickness of the i-type InGaAs light-absorbing layer 6 in the 50 Gbps APD is about 0.6 μm, the thickness of the depletion layer inside the i-type InGaAs light-absorbing layer 6 is about 0.4 μm. As shown in equation (1) above, since the response bandwidth determined by the transit time of the depletion layer inside the i-type InGaAs light-absorbing layer 6 is inversely proportional to the thickness of the depletion layer, the receiving sensitivity is improved in the APD according to Embodiment 1 with a wide response bandwidth.

[0165] On the other hand, since the portion below the p-type InGaAs contact layer 10, starting from the lower surface of the p-type InP window layer 9, becomes a depletion layer, the thickness of the depletion layer increases. Since the capacitance of the pn junction of the APD is inversely proportional to the thickness of the depletion layer, the capacitance decreases, thus improving the response bandwidth determined by the RC time constant in the back-incident APD according to Embodiment 1.

[0166] For example, the sum of the layer thicknesses from the lower surface of the p-type InP window layer 9 to the upper surface of the n-type InAlAs conductive layer 3, i.e. Figure 1 The DL1 is 0.9 μm and is the sum of the layer thicknesses from the deepest part of the p-type impurity diffusion region 20 to the upper surface of the n-type InAlAs conductive layer 3, i.e. Figure 1 When the DL2 is 0.6 μm, the capacitance per unit area on the underside of the p-type InGaAs contact layer 10 is 2 / 3 of the capacitance per unit area of ​​the light-receiving region 60 (=0.6 μm / 0.9 μm).

[0167] Regarding the back-incidence APD described in Embodiment 1, where p-type impurities only diffuse thermally to the inner periphery of the annular p-type InGaAs contact layer 10, and the back-incidence APD described later as a comparative example where p-type impurities diffuse thermally to the outer periphery of the p-type InGaAs contact layer 10, a comparison is made between the back-incidence APD and the APD used for setting the capacitance of the pn junction to 50 Gbps. The capacitance Cpn of the pn junction is expressed by the following equation (2).

[0168] Cpn=εr·ε0·S / Wt (2)

[0169] In equation (2), εr represents the relative permittivity, and ε0 represents the permittivity of vacuum (=8.85×10). －18 F / μm), S represents the area of ​​the pn junction, and Wt represents the thickness of the depletion layer. The relative permittivity εr varies depending on the composition of the semiconductor material but is around 13.5. Although the actual permittivity is slightly different for each semiconductor layer, for the sake of simplifying the calculation, the relative permittivity εr of all semiconductor layers is uniformly set to 13.5.

[0170] In 50Gbps APDs, to reduce capacitance, the diameter of the light-receiving area (the inner periphery of the annular contact layer) needs to be miniaturized to approximately 10μmΦ, and the diameter of the window layer (the outer periphery of the annular contact layer) needs to be miniaturized to approximately 16μmΦ. The surface area of ​​the light-receiving area with a diameter of 10μmΦ is 78.5μm². 2 The surface area of ​​the window layer with a diameter of 16 μmΦ is 201.0 μm. 2 The surface area of ​​the light-receiving area, i.e., the surface area of ​​the annular contact layer, is 122.5 μm after deducting the surface area of ​​the window layer. 2 The pn junction capacitance Cpn of the APD involved in the comparative example described later is calculated using the following equation (3).

[0171] 13.5×8.85×10 －18 F / μm×201.0μm 2 / 0.6μm=40fF (3)

[0172] On the other hand, the pn junction capacitance Cpn of the back-incident type APD involved in Embodiment 1 is calculated by the following equation (4).

[0173] 13.5×8.85×10 －18 F / μm×(78.5μm) 2 / 0.6μm+122.5μm 2 / 0.9μm)=32fF (4)

[0174] That is, the pn junction capacitance Cpn of the comparative example back-illuminated APD is 40 fF, while the pn junction capacitance Cpn of the back-illuminated APD according to Embodiment 1 is 32 fF, a reduction of 8 fF. In other words, in the back-illuminated APD according to Embodiment 1, the pn junction capacitance Cpn can be reduced by 20% compared to the comparative example. Therefore, the bandwidth fcr (=1 / (2πCR)) determined by the capacitance C and the load resistance R is increased by 20%. For example, if the load resistance R is set to 50 Ω, then in the back-illuminated APD according to Embodiment 1, the bandwidth fcr determined solely by the pn junction capacitance Cpn is 100 GHz.

[0175] In addition to the pn junction capacitance Cpn, the response bandwidth of the APD is also affected by the transit time of electrons and holes, multiplication time, parasitic capacitance, and component resistance. Therefore, in the APD used for 50Gbps, the response bandwidth determined by the pn junction capacitance Cpn and the load resistance R needs to be about twice the transmission speed, around 100GHz.

[0176] As described above, by reducing the thickness of the depletion layer in the light-receiving region where electrons and holes transit in the depletion layer, and increasing the thickness of the depletion layer below the p-type contact layer in the region where electrons and holes do not transit in the depletion layer, the pn junction capacitance Cpn of the APD can be reduced, resulting in an improved response bandwidth.

[0177] The disadvantage of making the entire window layer p-type is that the electric field applied to the side surface of the first mesa structure 30 increases during APD operation. When the electric field applied to the exposed side surfaces of the i-type InAlAs multiplication layer 4, p-type InAlAs electric field mitigation layer 5, and i-type InGaAs light absorption layer 6 of the first mesa structure 30 is large, there is a concern that the dark current may change over time and impair the reliability of the APD.

[0178] In the back-illuminated APD according to Embodiment 1, by providing a step portion 40 between the side portion of the second mezzanine structure 31 and the side portion of the first mezzanine structure 30, the distance between the side portions of the second mezzanine structure 31 and the side portions of the first mezzanine structure 30 is increased (hereinafter referred to as the step width Lt). Therefore, since the electric field applied to the side portion of the first mezzanine structure 30 is mitigated, a back-illuminated APD with high reliability can be obtained.

[0179] As a lower limit for the step width Lt, a width of 1 μm or more is preferred, which facilitates the processing of forming the step portion 40 and mitigates the electric field applied to the mesa trench 35. On the other hand, if the step width Lt is too long, i.e., the area of ​​the step portion 40 is too wide, an increase in dark current occurs due to the increased area of ​​the i-type InAlAs multiplication layer 4 and the i-type InGaAs light-absorbing layer 6. Therefore, as an upper limit for the step width Lt, 300 μm or less is preferred. Furthermore, considering that the element resistance increases if the distance between the light-receiving area 60 and the n-type electrode 50 becomes longer, a step width Lt of 50 μm or less is preferred. That is, the step width Lt is preferably in the range of 1 μm or more and 50 μm or less.

[0180] <Effects of Implementation Method 1>

[0181] As described above, the semiconductor light-receiving element according to Embodiment 1 adopts an element structure in which a second mesa structure and a step portion are provided on the first mesa structure, and a p-type impurity region is formed only in the light-receiving region. Therefore, the pn junction capacitance can be reduced, and the thermal diffusion of p-type impurities outside the light-receiving region can be suppressed. Thus, the semiconductor light-receiving element that operates with high reliability over a wide response bandwidth is obtained.

[0182] According to the semiconductor light-receiving element manufacturing method of Embodiment 1, since p-type impurities are pre-doped in the contact layer and window layer during the epitaxial crystal growth process, and the p-type impurities are selectively diffused into the light-absorbing layer only in the light-receiving region during the p-type impurity diffusion process after epitaxial crystal growth, the diffusion time of p-type impurities can be shortened. Furthermore, the time required for high-temperature heat treatment during p-type impurity diffusion can be shortened. As a result, since thermal diffusion of p-type impurities contained in the electric field mitigation layer into the light-absorbing layer and multiplication layer can be prevented, the dark current is reduced, resulting in the ability to easily manufacture semiconductor light-receiving elements with high receiving sensitivity.

[0183] Furthermore, as an advantage of pre-doping p-type impurities in the contact layer and window layer during the epitaxial crystal growth process, and selectively diffusing p-type impurities into the interior of the light-absorbing layer only in the light-receiving region during the p-type impurity diffusion process after epitaxial crystal growth, it can be cited that the depletion layer formed on the lower side of the annular p-type InGaAs contact layer can be thicker than the depletion layer formed in the light-receiving region on the inner periphery of the p-type InGaAs contact layer. Based on this advantage, since the capacitance of the pn junction can be reduced, a semiconductor light-receiving device with a wide response bandwidth can be realized.

[0184] Comparative example of implementation method 1.

[0185] Figure 9This is a cross-sectional view of the element structure of a back-illuminated APD, which is an example of the semiconductor light-receiving element 200 according to Embodiment 1 as a comparative example. The semiconductor light-receiving element 200 according to the comparative example differs from the semiconductor light-receiving element 100 according to Embodiment 1 in that it does not have a second mesa structure, an i-type InAlAs surface protective layer and a step portion, and p-type impurities are not pre-doped in the contact layer and window layer during the epitaxial crystal growth process.

[0186] <Component structure of the semiconductor photodetector (APD) involved in the comparative example of Embodiment 1>

[0187] As an example of the semiconductor light-receiving element 200 according to Embodiment 1, the back-incident type APD is composed of an Fe-doped InP substrate 1, a mesa structure 33, a surface protective film 11, a surface-side antireflective film 15, an n-type electrode 50, a p-type electrode 51, a back-side antireflective film 16, and a back electrode 52. The mesa structure 33 has a carrier concentration of 5 × 10⁻⁶ sequentially formed on the Fe-doped InP substrate 1. 17 ~8×10 18 cm －3 Furthermore, the n-type InP conductive layer has a thickness of 0.1–1.0 μm and a carrier concentration of 5 × 10⁻⁶. 17 ~8×10 18 cm －3 Furthermore, it consists of an n-type InAlAs conductive layer 3 with a thickness of 0.1–1.0 μm, an i-type InAlAs multiplication layer 4, and a carrier concentration of 1 × 10⁻⁶. 16 ~5×10 18 cm －3The structure includes a p-type InAlAs electric field mitigation layer 5 with a thickness of 10–100 nm, an i-type InGaAs light-absorbing layer 6 with a thickness of 0.1–2.0 μm, an i-type InAlGaAs gradient layer 7 with a thickness of 5–100 nm and progressively shorter wavelengths, an undoped i-type InP window layer 9a with a thickness of 0.1–3.0 μm, an undoped i-type InGaAs contact layer 10a with a thickness of 0.05–0.5 μm and annular along the outer periphery of a roughly circular light-receiving region 60 when viewed from above, and a p-type impurity diffusion region 20a disposed on the outer periphery of the annular i-type InGaAs contact layer 10a and a portion of the i-type InGaAs light-absorbing layer 6. The i-type InP window layer 9a is exposed as a semiconductor layer on the outer periphery of the annular i-type InGaAs contact layer 10a. The surface is protected. The protective film 11 is composed of an insulating film covering the surface of the i-type InP window layer 9a exposed on the outer periphery of the annular i-type InGaAs contact layer 10a; the surface-side antireflective film 15 is formed on the inner periphery of the annular i-type InGaAs contact layer 10a, that is, on the surface of the i-type InP window layer 9a corresponding to the approximately circular light-receiving area 60, and is composed of a SiN film; the n-type electrode 50 is formed on the surface of the n-type InP conductive layer 2 exposed on the outer periphery of the mesa structure 33 as a semiconductor layer; the p-type electrode 51 is disposed on the surface of the annular i-type InGaAs contact layer 10a and the surface-side antireflective film 15; the back-side antireflective film 16 is disposed on the back side of the Fe-doped InP substrate 1 at a position opposite to the p-type electrode 51; the back-side electrode 52 is disposed on the outer periphery of the back-side antireflective film 16 on the back side of the Fe-doped InP substrate 1.

[0188] Figure 10A This is a cross-sectional view of the epitaxial crystal grown in the manufacturing method of the semiconductor light-receiving element 100, i.e., the back-incident type APD, according to Embodiment 1. Figure 10B This is a cross-sectional view after epitaxial crystal growth in the manufacturing method of the back-incident type APD according to the comparative example of Embodiment 1.

[0189] like Figure 10B As shown, in the back-illuminated APD of the comparative example of Embodiment 1, the wafer after epitaxial crystal growth is composed of a series of semiconductor layers on the Fe-doped InP substrate 1, starting from one side of the Fe-doped InP substrate 1: an n-type InP conductive layer 2, an n-type InAlAs conductive layer 3, an i-type InAlAs multiplication layer 4, a p-type InAlAs electric field mitigation layer 5, an i-type InGaAs light absorption layer 6, an i-type InAlGaAs gradient layer 7, an i-type InP window layer 9a, and an i-type InGaAs contact layer 10a.

[0190] By comparison Figure 10A and Figure 10B It can be seen that the back-illuminated APD described in the comparative example of Embodiment 1 differs structurally from the back-illuminated APD described in Embodiment 1 in that it lacks an i-type InAlAs surface protective layer in its stacked semiconductor layer structure, and that the InP window layer 9a and the InGaAs contact layer 10a are both i-type in conductivity. That is, in the comparative example, the i-type InP window layer 9a and the i-type InGaAs contact layer 10a are i-type regions.

[0191] Figure 11A This is a cross-sectional view after the p-type impurity diffusion process in the manufacturing method of the back-incidence type APD according to Embodiment 1. Figure 11B This is a cross-sectional view after the p-type impurity diffusion process in the manufacturing method of the back-incident type APD involved in the comparative example.

[0192] exist Figure 11B In the case of the back-attribution APD involved in the comparative example shown, since it takes a long time for Zn to reach the i-type InGaAs light-absorbing layer 6 from the outermost surface of the semiconductor layer, Be, which is pre-contained as a p-type impurity in the p-type InAlAs electric field mitigation layer 5, thermally diffuses to the i-type InGaAs light-absorbing layer 6, resulting in an increase in dark current. Furthermore, because Be also thermally diffuses to the i-type InAlAs multiplication layer 4, partially p-typening of the multiplication layer occurs, an electric field distribution is generated within the multiplication layer, resulting in problems such as deterioration of multiplication noise.

[0193] On the other hand, Figure 11A In the case of the back-illuminated APD according to Embodiment 1, due to the short diffusion time, the thermal diffusion of Be, which is pre-contained as a p-type impurity in the p-type InAlAs electric field mitigation layer 5, can be suppressed. Therefore, the p-type impurity in the p-type InAlAs electric field mitigation layer 5 does not undergo thermal diffusion. Consequently, adverse conditions such as increased dark current and deterioration of multiplication noise, which are common in back-illuminated APDs, are not observed.

[0194] Implementation method 2.

[0195] <Features of the semiconductor photodetector (APD) involved in Embodiment 2>

[0196] Figure 12This is a cross-sectional view showing the element structure of a back-illuminated APD, an example of the semiconductor light-receiving element 110 according to Embodiment 2. The semiconductor light-receiving element 110 according to Embodiment 2 differs structurally from the semiconductor light-receiving element 100 according to Embodiment 1 in that the multiplication layer of the semiconductor light-receiving element 100 according to Embodiment 1 is composed of an i-type InAlAs layer, i.e., a random alloy structure, while the multiplication layer of the semiconductor light-receiving element 110 according to Embodiment 2 is composed of an i-type InAs / AlAs digital alloy structure. That is, the semiconductor light-receiving element 110 according to Embodiment 2 has an i-type InAs / AlAs digital alloy structure multiplication layer 4a.

[0197] As an example, the i-type InAs / AlAs digital alloy structure multiplication layer 4a is composed of semiconductor layers stacked alternately in the order of InAs layer (with a thickness of two atomic layers, approximately 0.6 nm) and AlAs layer (with a thickness of two atomic layers, approximately 0.6 nm).

[0198] However, the thickness of the InAs and AlAs layers only needs to be between two and six atomic layers, respectively. The requirement of six atomic layers or less is because the stacked InAs and AlAs layers are preferred not to function as a quantum well structure. That is, the digital alloy structure consists of two semiconductor layers made of different semiconductor materials, stacked alternately in a periodic pattern of two to six atomic layers.

[0199] Furthermore, it is preferable that the number of atomic layers in each layer of the i-type InAs / AlAs digital alloy structure multiplication layer 4a is two to four atomic layers, with two atomic layers being the most preferred. The reason for this is that the thinner the atomic layers, the greater the reduction in the ionization coefficient ratio k based on the digital alloy structure. Additionally, considering not only the performance as a semiconductor light-receiving element but also productivity, a layer thickness of four to six atomic layers, which reduces the number of shutter switches during crystal growth via the MBE method, is also preferred.

[0200] Considering the above important factors, for the number of atomic layers in each layer of the type i InAs / AlAs digital alloy structure multiplication layer 4a, a period of two to six atomic layers is considered the preferred range. Alternatively, from a productivity perspective, it is also possible to make a portion of the multiplication layer an InAs / AlAs digital alloy structure and the remainder an InAlAs random alloy structure, rather than making the entire multiplication layer an InAs / AlAs digital alloy structure.

[0201] The thickness of the i-type InAs / AlAs digital alloy structure multiplication layer 4a is preferably in the range of 40 nm to 170 nm, but it can be as short as 300 nm. For example, if the thickness of the i-type InAs / AlAs digital alloy structure multiplication layer 4a is 100 nm, the number of repetitions of the InAs layer (two atomic layers) / AlAs layer (two atomic layers) is 85.

[0202] The conductivity type of the i-type InAs / AlAs digital alloy multiplication layer 4a is i-type. As an example, the carrier concentration is 1×10⁻⁶. 17 cm －3 Below. However, the conductivity type of the InAs / AlAs digital alloy structure multiplication layer can also be a carrier concentration of 5 × 10⁻⁶. 17 cm －3 The following are p-type or n-type.

[0203] In addition to the multiplication layer composed of InAs / AlAs digital alloy structure, a digital alloy structure composed of InAlAsSb, which is a material system with added antimony (Sb), can also be used as the multiplication layer of the semiconductor photoreceiving element disclosed herein.

[0204] In the semiconductor light-receiving element 110 according to Embodiment 2, since, as in Embodiment 1, the diffusion depth and (diffusion time) are the same. 0.5 The diffusion time is proportional to the depth required for thermal diffusion. Therefore, if the depth required for thermal diffusion is halved, the diffusion time becomes 1 / 4, allowing p-type impurities to thermally diffuse into the interior of the i-type InGaAs light-absorbing layer 6 in a short time. By shortening the diffusion time, it is possible to prevent the increase in dark current caused by the thermal diffusion of p-type impurities pre-contained in the p-type InAlAs electric field mitigation layer 5 into the i-type InGaAs light-absorbing layer 6, and to prevent adverse conditions such as disordering of the digital alloy structure multiplication layer and deterioration of multiplication noise caused by the thermal diffusion of p-type impurities from the p-type InAlAs electric field mitigation layer 5 to the i-type InAs / AlAs digital alloy structure multiplication layer 4a.

[0205] In the semiconductor photodetector 110 according to Embodiment 2, as in Embodiment 1, the p-type impurity diffusion region 20 is provided only in the photodetector region 60, which affects the transit time of charge carriers, to deepen the p-type region. Therefore, the depth of the p-type region formed on the outer periphery of the second mesa structure 31, i.e., below the step portion 40, is 0.3 μm shallower than the photodetector region 60. Thus, even if the step width Lt is 0 μm, the distance between the p-type region and the i-type InAs / AlAs digital alloy multiplication layer 4a increases by 0.3 μm. As a result, in the back-illuminated APD according to Embodiment 1, even when the step width Lt is 0 μm, i.e., the step portion 40 is not provided, the thickness of the depletion layer below the p-type InGaAs contact layer 10 is increased by 0.3 μm compared to the semiconductor photodetector 200 as a comparative example, thus reducing capacitance.

[0206] The semiconductor light-receiving element 110 according to Embodiment 2 is characterized in that the multiplication layer is composed of an i-type InAs / AlAs digital alloy structure. Hereinafter, one of the structural features of the semiconductor light-receiving element of this disclosure, which also includes the semiconductor light-receiving elements described later, namely the digital alloy structure multiplication layer, will be described in detail.

[0207] If a wideband APD (Active Detector) with a response bandwidth exceeding 37.5 GHz can be achieved, then a next-generation high-speed PON system can be realized even without using DSP (Digital Signal Processor) and SOA (Service-Oriented Architecture). In the case of PDs where wideband response is relatively easy to achieve, the response bandwidth is limited by:

[0208] (1) RC time constant (R is the resistance of the component, C is the capacitance of the component)

[0209] (2) Transit time of charge carriers (the time that electrons or holes transit within the depletion layer).

[0210] In APD, further limitations include:

[0211] (3) Multiplication time (the time for electrons and holes to multiply in the multiplication layer, which increases proportionally to the multiplication rate).

[0212] The 37.5 GHz band mentioned above can be achieved in PD, but in APD, due to the need for doubling time, it is difficult to achieve the desired band if the doubling rate is increased. The doubling time TM is represented by the following equations (5) to (7).

[0213] Doubling time TM = Doubling rate M / GB product (5)

[0214] GB product = 1 / (2πNkτav) (6)

[0215] That is, the doubling time TM = 2πNkMτav (7).

[0216] Here, the GB product is the product of the multiplication rate and the response bandwidth, k is the ionization coefficient ratio, N is a coefficient that varies slowly with the ionization coefficient ratio k, and τav is the average transit time of electrons and holes in the multiplication layer. Therefore, by reducing the ionization coefficient ratio k, the multiplication time TM can be shortened. In particular, to realize a high-speed PON system, the multiplication time TM needs to be close to zero, that is, the ionization coefficient ratio k needs to be close to zero.

[0217] To achieve a zero ionization coefficient ratio k, various compound semiconductors have been proposed as materials for the multiplication layer. Furthermore, while digital alloy structures have been proposed to reduce the ionization coefficient ratio k by periodically stacking semiconductor layers of different compositions in alternating periods of 1 to 6 atomic layers, it is difficult to achieve a zero ionization coefficient ratio k unless the structure is optimized within the digital alloy structure. Regarding digital alloy structures, non-patent literature 1 describes such structures.

[0218] In view of this, the inventors fabricated an APD with a digital alloy structure multiplication layer to reduce the ionization coefficient ratio k of the digital alloy structure. This digital alloy structure multiplication layer uses a multiplication layer consisting of alternating layers of two atomic layers of InAs and two atomic layers of AlAs. Analysis of the multiplication characteristics revealed that the distance to which the charge carriers translocate and ionize within the multiplication layer is longer than that of an APD with a typical bulk InAlAs structure, i.e., an InAlAs random alloy structure multiplication layer. This distance to which the charge carriers translocate and ionize within the multiplication layer is referred to as the dead zone.

[0219] Regarding the length of the dead region (hereinafter referred to as the dead region length), since holes are longer than electrons, in the case of a typical bulk InAlAs random alloy structure, if the thickness of the multiplication layer is reduced to the tens of nm level, the ionization coefficient ratio k decreases because holes cannot be ionized. However, when the thickness of the multiplication layer is reduced to the tens of nm level, a new problem arises: a higher electric field needs to be applied to the multiplication layer to obtain the desired multiplication rate, leading to an increase in leakage current, such as tunneling current. That is, if the tunneling current increases, the noise generated in the APD increases. On the other hand, through the inventors' analysis, it was found that in the digital alloy structure, because the dead region is exceptionally large compared to the random alloy structure, even multiplication layers with a thickness of 100 nm or more can achieve an ionization coefficient ratio k = 0.

[0220] In other words, the inventors have discovered for the first time that by constructing a multiplication layer for an APD with a digital alloy structure, it is possible to suppress tunneling current while achieving an ionization coefficient ratio (k) of 0. Specifically, it was found that in the multiplication layer constructed with a digital alloy structure disclosed in this invention, the ionization coefficient ratio (k) decreases sharply at layer thicknesses below 170 nm, particularly in the range of 60 to 130 nm where the dead zone effect is significantly improved. That is, the inventors have demonstrated that by applying the multiplication layer constructed with a digital alloy structure disclosed in this invention, an ionization coefficient ratio (k) of 0 can be achieved that is impossible with multiplication layers constructed with random alloy structures or with thick digital alloy structures. Currently, no research institution has reported that thinning the multiplication layer of an APD with a digital alloy structure multiplication layer has a higher effect on reducing the ionization coefficient ratio (k) than thinning the multiplication layer of an APD based on existing materials.

[0221] The thickness of the i-type InAs / AlAs digital alloy structure multiplication layer 4a is in the range of 40 nm to 1000 nm. However, in order to increase the dead zone effect in the i-type InAs / AlAs digital alloy structure multiplication layer 4a, the thickness of the i-type InAs / AlAs digital alloy structure multiplication layer 4a can also be in the range of 40 nm to 170 nm. Furthermore, considering the typical deviation of the layer thickness during the fabrication of the semiconductor light-receiving element 110, i.e., 20%, it is more preferable that the thickness of the i-type InAs / AlAs digital alloy structure multiplication layer 4a is in the range of 50 nm to 140 nm.

[0222] The following explains the function of the APD with an i-type InAs / AlAs digital alloy structure multiplication layer. The inventors discovered that if a digital alloy structure multiplication layer is used as in the back-incident APD described in Embodiment 2, the dead zone effect, i.e., the reduction effect of the ionization coefficient ratio k, can be enhanced.

[0223] Figure 13 This is a graph (estimated value) showing the electric field dependence of the dead zone of electrons in the InAlAs multiplication layer. The inventors analyzed the electron multiplication characteristics in the digital alloy structure multiplication layer, and the results are as follows: Figure 17 As shown in the diagram, it is clear that the InAs / AlAs digital alloy structure multiplication layer of this disclosure has a longer dead zone compared to the existing InAlAs random alloy structure multiplication layer.

[0224] Figures 14A to 14C These are schematic diagrams representing the ionization coefficients of electrons and holes. Figure 14A This is a schematic diagram illustrating the ionization of electrons. Figure 14B This is a schematic diagram illustrating the ionization of holes. Figure 14CThis is a schematic diagram illustrating the ionization coefficient when the multiplication layer is thinned. In existing InAlAs random alloy structure multiplication layers, it possesses... Figure 13 As shown in the chart, the dead region length is approximately 45 nm, so the thickness of the multiplication layer needs to be reduced to about 1.5 times the dead region (approximately 70 nm). However, if the multiplication layer is reduced to 70 nm, the electric field of the multiplication layer becomes higher, which leads to a sharp increase in tunneling current and thus increased noise.

[0225] On the other hand, in the i-type InAs / AlAs digital alloy structure multiplication layer 4a of the back-incidence type APD according to embodiment 2, due to... Figure 13 As shown in the graph, when the reciprocal of the applied electric field is 1.47 × 10⁻⁶, －6 At cm / V, the dead zone length is approximately 85 nm. Therefore, even if the layer thickness of the multiplication layer is approximately 1.5 times the thickness of the dead zone (approximately 130 nm), the ionization coefficient ratio k can be made close to zero. Thus, the influence of tunneling current is small in the back-incident type APD involved in Embodiment 2.

[0226] Furthermore, in InAs / AlAs digital alloy multiplication layers, the dead zone exhibits a high dependence on the applied electric field. For example, when the reciprocal of the applied electric field is 1.27 × 10⁻⁶, the dead zone becomes highly dependent on the applied electric field. －6 In the case of cm / V, due to... Figure 13 As shown in the chart, the dead zone length is approximately 50 nm, so the multiplication layer needs to be thinned to 75 nm. That is, the layer thickness of the InAs / AlAs digital alloy structure multiplication layer can be thicker than that of the InAlAs random alloy structure multiplication layer.

[0227] Figure 15 This is a graph showing the dependence of the ionization coefficient ratio and tunneling current multiplication layer thickness on the layer thickness (experimental and literature values). The inventors fabricated APDs with InAs / AlAs digital alloy structure multiplication layers and InAlAs random alloy structure multiplication layers, respectively, and measured the ionization coefficient ratio k, and then compared it with... Figure 15 The measurement results from references 1 and 2 recorded in the document are plotted together. Figure 15 In the middle. Among them, Figure 15 References 1 and 2 are shown below.

[0228] (1) Reference 1

[0229] Yuan Yuan,et al.,“Temperature dependence of the ionizationcoefficients of InAlAs and AlGaAs digital alloys” pp.794, Vol.6, No.8 / August2018 / Photonics Research

[0230] (2) Reference 2

[0231] Wenyang Wang, et al., “Characteristics of thin InAlAs digital alloyavalanche photodiodes” pp.3841, Vol.46, No.16 / 15 August 2021 / Optics Letters

[0232] like Figure 15 As shown, in InAlAs random alloy structure multiplication layers, the reduction in ionization coefficient ratio k due to the dead zone is not achieved unless the layer thickness is below 80 nm. On the other hand, if the layer thickness is reduced to less than 80 nm, the tunneling current increases sharply, leading to tunnel breakdown. When the layer thickness is around 60 nm, the reduction in ionization coefficient ratio k and the limitation on tunneling current can be barely balanced, but the thickness margin is only a few nm, making it extremely difficult to stably manufacture APDs. Furthermore, the ionization coefficient ratio k becomes as large as 0.12. In other words, in existing InAlAs random alloy structure multiplication layers, it is difficult to apply the reduction in ionization coefficient ratio k resulting from thinning to APDs.

[0233] On the other hand, in the InAs / AlAs digital alloy structure multiplication layer disclosed herein, due to the large dead zone as discovered by the inventors, therefore... Figure 15 As shown, if the multiplication layer is thinned, the ionization coefficient ratio k decreases to below 0.1 starting from a layer thickness of 170 nm. Here, the ionization coefficient ratio k is determined based on the measured value of the multiplication noise and is the minimum value of the ionization coefficient ratio within the range of multiplication rates of 1 to 10. With the same ionization coefficient ratio k, the layer thickness of the InAs / AlAs digital alloy structure multiplication layer is more than twice that of the InAlAs random alloy structure multiplication layer.

[0234] like Figure 15As shown, in an APD with a pn junction diameter of 20 μm, if 40 nm is set as the lower limit for the layer thickness as the multiplication layer thickness with a tunnel current of 1 μA, then the layer thickness in the range of 40 nm to 170 nm becomes the optimal range for the InAs / AlAs digital alloy structure multiplication layer. Layer thicknesses within this range can be manufactured with sufficiently good reproducibility.

[0235] Because the InAs / AlAs digital alloy multiplication layer can achieve a significant reduction in the ionization coefficient ratio k through the dead-zone effect, the layer thickness is 1.47 × 10⁻⁶ times the inverse of the applied electric field. －6 In the case of cm / V, it can be considered to be approximately twice the dead zone length, so if considering as Figure 15 As shown, the dead zone length is 85nm. Therefore, twice the dead zone length, i.e., 170nm, is a suitable upper limit for the layer thickness of the InAs / AlAs digital alloy structure multiplication layer.

[0236] Furthermore, in order to control the ionization coefficient ratio k to below 0.05 in the InAs / AlAs digital alloy multiplication layer, according to Figure 15 The preferred thickness of the multiplication layer is 150 nm or less. Furthermore, to ensure a tunneling current of 1 μA or less and an ionization coefficient ratio k approximately zero, a thickness of 60 nm to 130 nm is optimal for the multiplication layer. With a margin of 10 nm during APD fabrication, a thickness of 70 nm to 120 nm is preferred.

[0237] In addition, the length of the dead zone is determined according to Figure 13 It is known that the optimal dead zone length is between 50 nm and 90 nm. The preferred ratio of the dead zone length to the multiplication layer thickness is the value obtained by dividing the minimum dead zone length (50 nm) by the maximum multiplication layer thickness (170 nm), i.e., 29% or higher. A higher ratio results in a smaller ionization coefficient ratio k, but it cannot exceed 100%. This is because if the ionization coefficient ratio k exceeds 100%, multiplication will no longer occur. Therefore, in principle, the ratio of the dead zone length to the multiplication layer thickness is preferably 29% or higher and less than 100%. Furthermore, since the multiplication layer thickness in this prototype is 120 nm, 42% (=50 nm / 120 nm) to 75% (=90 nm / 120 nm) is the optimal range confirmed through experiments.

[0238] The inventors investigated the reasons why the ionization coefficient ratio k=0 could not be achieved in existing InAlAs random alloy structure multiplication layers, but could be achieved in the InAs / AlAs digital alloy structure multiplication layer of this disclosure.

[0239] If the dead zone length of electrons is set as De and the dead zone length of holes is set as Dh, then the following equations (8) and (9) represent the conditions for achieving the ionization coefficient ratio k=0. Among them, equation (8) represents the condition for the difference in dead zone lengths, and equation (9) represents the condition for tunneling current.

[0240] Dhe=Dh-De>0 (8)

[0241] Dh>Tmin (9)

[0242] Here, Dhe is the difference in dead zone length between holes and electrons. Tmin is the minimum layer thickness of the multiplication layer for which the tunneling current is sufficiently small to not affect the noise level; the thicker the multiplication layer, the lower the tunneling current. Regarding the condition for the difference in dead zone length, since... Figure 14C As shown in the schematic diagram, if the thickness of the multiplication layer is below the dead zone length of the hole, the hole will no longer multiply and the ionization coefficient ratio k=0, so it is set as in the above equation (8).

[0243] according to Figure 13 and Figure 15 In the case of InAlAs random alloy structure multiplication layers, the ionization coefficient ratio k begins to decrease at approximately 40 nm for De and approximately 80 nm for Dh as the multiplication layer is gradually thinned. Since the minimum layer thickness Tmin is 90 nm when the pn junction diameter is 20 μm and the tunneling current is below 100 nA, the InAlAs random alloy structure does not meet the tunneling current condition, therefore it is impossible to achieve an ionization coefficient ratio k = 0.

[0244] On the other hand, in the case of InAs / AlAs digital alloy structure multiplication layers, for the value at which the ionization coefficient ratio k begins to decrease as the multiplication layer is gradually thinned, De is approximately 80 nm and Dh is approximately 170 nm. Since the minimum layer thickness Tmin is 90 nm when the pn junction diameter is 20 μm and the tunneling current is below 100 nA, there exists a multiplication layer thickness that satisfies the condition that the ionization coefficient ratio k = 0. Regarding the minimum layer thickness Tmin, it is the same in both InAs / AlAs digital alloy structure multiplication layers and InAlAs random alloy structure multiplication layers, since the band gap remains unchanged.

[0245] Specifically, the inventors discovered that in the case of a random alloy structure, De is approximately 40 nm and Dh is approximately 80 nm. In contrast, in the case of a digital alloy structure, De is approximately 80 nm and Dh is approximately 170 nm.

[0246] In the InAs / AlAs digital alloy multiplication layer, the difference in lattice constant between InAs (lattice constant = 0.606 nm) and AlAs (lattice constant = 0.566 nm), which constitute the superlattice, is extremely large, at 6.55%. Therefore, it is possible that dopants, i.e., impurities, in the electric field mitigation layer during the fabrication process diffuse into the InAs / AlAs digital alloy multiplication layer, resulting in disorder within the multiplication layer.

[0247] Figures 16A to 16D This is a schematic diagram showing the ionization coefficients in the multiplication layer and the electric field mitigation layer. Figure 16A This is a schematic diagram showing the ionization coefficient in the case of InAlAs random alloy structure multiplication layers. Figure 16B This is a schematic diagram showing the ionization coefficient in the case of InAs / AlAs digital alloy multiplication layers. Figure 16C This is a schematic diagram representing the ionization coefficient in the case of a partially disordered InAs / AlAs digital alloy multiplication layer. Figure 16D This is a schematic diagram illustrating the ionization coefficient when a thick electric field mitigation layer is combined with an InAs / AlAs digital alloy multiplication layer. Figure 16A Compared to the InAlAs random alloy structure multiplication layer shown, Figure 16B The InAs / AlAs digital alloy multiplication layer shown has a long dead zone length, but in the InAs / AlAs digital alloy multiplication layer that is partially disordered due to dopant diffusion from the electric field mitigation layer, such as... Figure 16C As shown, the dead zone length becomes shorter.

[0248] To avoid the effects of disorder in the InAs / AlAs digital alloy multiplication layer, the selection of materials and dopants for the electric field mitigation layer, as well as the doping concentration, become important. The impurity diffusion equation is represented by the following equation (10).

[0249] dN / dt=D(d 2 N / d 2 x)-F (10)

[0250] In equation (10), N is the impurity concentration, t is time, D is the diffusion constant, x is the position, and F is the external force acting on the diffusion. Materials that can be used as the electric field mitigation layer include InP, InAlAs random alloy structures, and InAs / AlAs digital alloy structures. Additionally, p-type dopants that can be used as the electric field mitigation layer include Be and Zn. Considering p-type dopants, the combination of a Be-doped p-type InP electric field mitigation layer and an InAs / AlAs digital alloy structure multiplication layer is preferred. The reason is that Be, in addition to having a small diffusion constant D, also forms a potential barrier with the InAs / AlAs digital alloy structure multiplication layer. This potential barrier is equivalent to F in equation (10).

[0251] To prevent the deviation in the electric field mitigation amount (i.e., the product of layer thickness and carrier concentration) from increasing even when the layer thickness of the electric field mitigation layer deviates, the preferred carrier concentration for the electric field mitigation layer is 2 × 10⁻⁶. 18 cm －3 Below, when InAlAs is used as the constituent material of the electric field mitigation layer, Zn doping is optimal, with an optimal carrier concentration of 2 × 10⁻⁶. 18 cm －3 The following. Among them, if the impurity concentration is higher than 2×10... 18 cm －3 This increases the likelihood of inactive impurities diffusing, therefore the carrier concentration must be 5 × 10⁻⁶. 18 cm －3 the following.

[0252] The electric field mitigation amount ΔE is represented by the following equation (11).

[0253] ΔE=W·q·N / ε (11)

[0254] In equation (11), W is the thickness of the electric field mitigation layer, q is the elementary charge, N is the carrier concentration of the electric field mitigation layer, and ε is the dielectric constant. When the electric field mitigation amount ΔE is constant, if the carrier concentration of the electric field mitigation layer is increased, the thickness of the electric field mitigation layer needs to be reduced inversely proportional to the carrier concentration.

[0255] If the carrier concentration N in the electric field buffer layer is 5 × 10 18 cm －3 The electric field mitigation layer is approximately 10 nm thick. To prevent the shortening of the dead zone length caused by impurity diffusion into the multiplication layer, the carrier concentration of the electric field mitigation layer is set to 5 × 10⁻⁶. 18 cm －3 The following methods are used for control. Additionally, the electric field mitigation layer requires a thickness of at least 10 nm.

[0256] On the other hand, such as Figure 16D As shown, if the thickness of the electric field mitigation layer is more than 1.5 times the dead zone length of the electric field mitigation layer, a multiplication effect occurs within the electric field mitigation layer. Figure 13 As shown, since the dead zone length in the random alloy structure is less than 45 nm, the thickness of the electric field mitigation layer composed of the random alloy structure needs to be less than 70 nm. On the other hand, since the dead zone length in the InAs / AlAs digital alloy structure is less than 85 nm, the thickness of the electric field mitigation layer of the digital alloy structure needs to be less than 130 nm.

[0257] in, Figures 16A to 16D The lengths of the dead zones shown are the dead zone lengths ( Figure 16A Dead Zone ( Figure 16DDead Zone ( Figure 16C Dead Zone ( Figure 16B The relationship between ).

[0258] <Effects of the digital alloy structure multiplication layer of the semiconductor photodetector (APD) according to Embodiment 2>

[0259] First, the first effect of the semiconductor light-receiving element 110 according to Embodiment 2 will be explained quantitatively below. If the bandwidth limitation based on the RC time constant is set as frc, the bandwidth limitation based on the transit time of the charge carrier is set as ftr, and the bandwidth limitation based on the doubling time is set as fm, then the 3dB bandwidth fc of the existing APD is represented by the following equation (12).

[0260] fc_APD = 1 / ((1 / frc)) 2 +(1 / ftr) 2 +(1 / fm) 2 ) 0.5 (12)

[0261] On the other hand, the 3dB band fc of the APD with the InAs / AlAs digital alloy structure multiplication layer involved in embodiments 1 and 2 is limited only by the RC time constant and the transit time of the carriers according to equations (7) and (12) since the ionization coefficient ratio k is close to zero, and can therefore be expressed by the following equation (13).

[0262] fc_APD = 1 / ((1 / frc)) 2 +(1 / ftr) 2 ) 0.5 (13)

[0263] In equation (13), the transit time of the charge carrier, ftr, is the transit time in the light absorption layer plus the transit time in the multiplication layer.

[0264] Since the RC time constant is inversely proportional to the sum of the thickness of the light-absorbing layer and the thickness of the multiplication layer, and on the other hand, the transit time is directly proportional to it, equation (13) has a maximum value. That is, the maximum bandwidth is reached when frc = ftr. If we substitute frc = ftr, then equation (13) can be expressed by the following equation (14).

[0265] fc = ftr / √2 (14)

[0266] In addition, the 3dB band ftr, which is determined by the transit time, is represented by the following equation (15).

[0267] ftr=3.5Vav / (2πWt) (15)

[0268] In equation (15), Vav is the average saturation drift velocity of electrons and holes, and Wt is the sum of the thicknesses of the light-absorbing layer and the multiplication layer. For example, in the case of InGaAs, Vav is 5.35 × 10⁻⁶. 6 cm / s. Furthermore, if the thickness of the multiplication layer is 100 nm and the thickness of the light-absorbing layer is 400 nm, then Wt = 500 nm.

[0269] If Vav = 5.35 × 10 6 Substituting cm / s and Wt=500nm into equation (15), we get ftr=59.6GHz. Furthermore, if we substitute the calculated ftr into equation (14), the 3dB bandwidth of the APD with the InAs / AlAs digital alloy structure multiplication layer of Embodiment 2 is 42.2GHz. Therefore, based on the above analysis, it can be seen that the APD with the InAs / AlAs digital alloy structure multiplication layer according to Embodiment 2 can meet the bandwidth requirement of 37.5GHz for a 50G-PON system. In the following description of the apparatus, system, etc., the APD with the InAs / AlAs digital alloy structure multiplication layer according to Embodiment 2 of this disclosure will be referred to as the DA-APD of this disclosure.

[0270] <Effects of Implementation Method 2>

[0271] As described above, the semiconductor light-receiving element according to Embodiment 2 further has a digital alloy structure multiplication layer with a layer thickness controlled within a predetermined range, thus achieving the effect of obtaining a semiconductor light-receiving element that operates in a wider response frequency band and has high receiving sensitivity.

[0272] Variation 1 of Implementation Method 2.

[0273] <Features of the semiconductor photodetector (APD) involved in Variation 1 of Embodiment 2>

[0274] Figure 17 This is a cross-sectional view of the element structure of a back-incident type APD, which is an example of the semiconductor light-receiving element 120 according to Embodiment 2, Variation 1. The semiconductor light-receiving element 120 according to Embodiment 2 differs structurally from the semiconductor light-receiving element 110 according to Embodiment 2 in that the window layer of the semiconductor light-receiving element 110 according to Embodiment 2 is a p-type InP window layer 9, while the window layer of the semiconductor light-receiving element 110 according to Embodiment 2 is composed of two layers: an i-type InP first window layer 9b and a p-type InAlAs second window layer 9c, which extend from the i-type InAlAs surface protective layer 8 side.

[0275] In the configuration of the back-illuminated APD according to Variation 1 of Embodiment 2, since each semiconductor layer from the n-type InP conductive layer 2 to the i-type InAlAs surface protective layer 8 is the same as that of the back-illuminated APD according to Embodiment 2, the description is omitted.

[0276] In the back-incident type APD described in Variation 1 of Embodiment 2, an i-type InP first window layer 9b with a thickness of 0.1 to 1 μm and a carrier concentration of 5 × 10⁻⁶ is formed on the i-type InAlAs surface protective layer 8. 17 ~8×10 18 cm －3 Furthermore, the p-type InAlAs second window layer 9c has a thickness of 0.1–2.0 μm and a carrier concentration of 5 × 10⁻⁶. 17 ~8×10 18 cm －3 It consists of a p-type InGaAs contact layer 10 with a thickness of 0.05 to 0.5 μm and annular shape along the outer periphery of the light-receiving area 60, which is roughly circular when viewed from above.

[0277] Similar to the back-incident APD described in Embodiment 2, the i-type InAlAs surface protective layer 8 can also be an i-type InP layer. Furthermore, the first window layer can also be composed of an InAlAs layer, and the second window layer can also be composed of a p-type InP layer.

[0278] <Function of the semiconductor photodetector (APD) involved in Variation 1 of Embodiment 2>

[0279] The back-illuminated APD described in Variation 1 of Embodiment 2 has the same function and effect as the back-illuminated APD described in Embodiment 2. In the back-illuminated APD described in Variation 1 of Embodiment 2, since an i-type InP first window layer 9b is provided as described above, the thickness of the depletion layer on the underside of the annular p-type InGaAs contact layer 10 is increased by the thickness of the i-type InP first window layer 9b. When the thickness of the i-type InP first window layer 9b is 0.3 μm, equation (4) becomes equation (16).

[0280] 13.5×8.85×10 －18 F / μm×(78.5μm) 2 / 0.6μm+122.5μm 2 / (0.9μm+0.3μm))=28fF(16)

[0281] Since the pn junction capacitance is reduced from 32 fF (Cpn) of the back-illuminated APD in Embodiment 1 calculated according to Equation (4) to 28 fF (Cpn) of the back-illuminated APD in Modified Example 1 of Embodiment 2 calculated according to Equation (16), the RC time constant can be reduced in the back-illuminated APD in Modified Example 1 of Embodiment 2. On the other hand, since the thickness of the depletion layer in the light-receiving region 60 of the back-illuminated APD in Modified Example 1 of Embodiment 2 remains unchanged, the transit time of the charge carriers does not increase. As a result, the overall response bandwidth of the APD is improved, and a wide response bandwidth is obtained.

[0282] <Effects of Variation 1 of Implementation Method 2>

[0283] The semiconductor light-receiving element according to the modified example 1 of embodiment 2, since the window layer is composed of two layers, i-type InP first window layer and p-type InAlAs second window layer, can reduce the pn junction capacitance, thus achieving the effect of obtaining a semiconductor light-receiving element that can operate with a wider response bandwidth and has high reliability.

[0284] Variation 2 of Implementation Method 2.

[0285] <Characteristics of the semiconductor photodetector (APD) involved in Variation 2 of Embodiment 2>

[0286] Figure 18 This is a cross-sectional view of the element structure of a back-incident type APD, which is an example of a semiconductor light-receiving element 130 according to Embodiment 2, Modification 2. The semiconductor light-receiving element 130 according to Embodiment 2 differs structurally from the semiconductor light-receiving element 110 according to Embodiment 2 in that: in the semiconductor light-receiving element 110 according to Embodiment 2, the upper surface of the i-type InAlAs surface protective layer 8 directly below the p-type InP window layer 9 becomes the step surface 41 in the step portion 40, and the i-type InAlAs surface protective layer 8 mitigates the electric field applied to the side portion of the i-type InAs / AlAs digital alloy structure multiplication layer 4a exposed in the mesa trench 35; while in the semiconductor light-receiving element 130 according to Embodiment 2, the upper surface of the p-type InAlAs electric field mitigation layer 5 directly below the i-type InGaAs light-absorbing layer 6 becomes the step surface 41a in the step portion 40a. That is, by etching the outer periphery of the p-type InGaAs contact layer 10, which is annular when viewed from above, to the p-type InAlAs electric field mitigation layer 5, the step surface 41a is formed by the upper surface of the p-type InAlAs electric field mitigation layer 5.

[0287] In the back-illuminated APD according to Embodiment 2, the i-type InAlAs surface protective layer 8 formed between the i-type InAlGaAs gradient layer 7 and the p-type InP window layer 9 functions as both a surface protective layer and a gradient layer. On the other hand, in the back-illuminated APD according to Modification 2 of Embodiment 2, the i-type InAlAs layer formed between the i-type InAlGaAs gradient layer 7 and the p-type InP window layer 9 functions specifically as the i-type InAlAs gradient layer 8a.

[0288] The p-type InAlAs electric field mitigation layer 5 can be any of a random alloy structure or a digital alloy structure. Alternatively, it can be composed of a p-type InP layer. A gradient layer composed of an i-type InAlGaAs layer or an i-type InGaAsP layer can also be provided between the p-type InAlAs electric field mitigation layer 5 and the i-type InGaAs light-absorbing layer 6.

[0289] In addition to the step surface 41a being formed by the upper surface of the p-type InAlAs electric field mitigation layer 5, the step surface 41a can also be formed by the middle surface of the p-type InAlAs electric field mitigation layer 5 or the middle surface of the i-type InAs / AlAs digital alloy structure multiplication layer 4a.

[0290] When a gradient layer is provided between the p-type InAlAs electric field mitigation layer 5 and the i-type InGaAs light-absorbing layer 6, the step surface 41a in the step portion 40a can be formed from the upper surface or a middle surface of the gradient layer. Furthermore, even if the step surface 41a is formed from the surface of the i-type InGaAs light-absorbing layer 6 with a thickness of less than 100 nm remaining on the p-type InAlAs electric field mitigation layer 5, there is no problem because the electric field is mitigated by the step portion 40a. That is, in the back-illuminated APD according to the variation 2 of Embodiment 2, the step surface 41a can be formed simply by using the upper surface of the p-type InAlAs electric field mitigation layer 5 or a layer thickness of 100 nm in the vertical direction based on the upper surface of the p-type InAlAs electric field mitigation layer 5.

[0291] <The function and effect of the semiconductor photodetector (APD) involved in variation 2 of embodiment 2>

[0292] In the back-incident type APD described in Embodiment 2, such as Figure 12 As shown, an i-type InGaAs light-absorbing layer 6 exists on the lower side of the step surface 41, but in the back-incident APD involved in the variation 2 of embodiment 2, as... Figure 18As shown, the i-type InGaAs light-absorbing layer 6 is absent on the underside of the step surface 41a. The small bandgap of the i-type InGaAs light-absorbing layer 6 contributes to dark current, but in the back-illuminated APD described in Variation 2 of Embodiment 2, the semiconductor layers other than the light-receiving region 60 and the p-type InGaAs contact layer 10 are removed by etching up to the upper surface of the p-type InAlAs electric field mitigation layer 5. As a result, the area of ​​the i-type InGaAs light-absorbing layer 6 is reduced, thus reducing dark current.

[0293] In the back-incident type APD described in Embodiment 2, such as Figure 12 As shown, if incident light 90 is incident on an Fe-doped InP substrate 1 with a thickness of 100 μm or more, the light beam diffuses as it propagates within the Fe-doped InP substrate 1. Even in the i-type InGaAs light-absorbing layer 6 outside the light-receiving region 60, light is absorbed, generating electrons and holes. Electrons and holes generated in the step portion 40 and other areas outside the light-receiving region travel a longer distance to the p-type region, resulting in a longer transit time and a concern about frequency response degradation. Therefore, in the case of a back-incident APD, it is necessary to consider preventing beam diffusion and the optical axis from deviating from the light-receiving region.

[0294] On the other hand, in the back-illuminated APD according to Variation 2 of Embodiment 2, since the i-type InGaAs light-absorbing layer 6 on the lower side of the step portion 40a is removed in order to reduce light absorption outside the light-receiving area 60, even if the incident light diffuses in the direction of the step portion 40a and is incident on the step portion 40a, it will not be absorbed. That is, it achieves the effect that even if the incident light beam 90 diffuses inside the back-illuminated APD, the response frequency band will not degrade.

[0295] Since the p-type impurity diffusion region 20 is deepened by thermally diffusing p-type impurities only in the light-receiving region 60, while the p-type region on the underside of the annular p-type InGaAs contact layer 10 remains shallow, the electric field applied to the side portion of the i-type InGaAs light-absorbing layer 6 is reduced, thus enabling a back-incident APD with high reliability.

[0296] Furthermore, since the side portion of the i-type InAs / AlAs digital alloy structure multiplier layer 4a, which is subjected to a high electric field, is located further outward than the step portion 40a on the side of the mesa groove 35, and is further away from the p-type InP window layer 9, the electric field applied to the side portion of the i-type InAs / AlAs digital alloy structure multiplier layer 4a is reduced when the APD operates, resulting in a back-incident APD with high reliability.

[0297] As a lower limit for the step width Lt, a step width Lt of 1 μm or more is preferred, which facilitates the processing of the step portion 40a and mitigates the electric field applied to the side surface exposed on the mesa groove 35. On the other hand, if the step width Lt is too long, i.e., if the area of ​​the step portion 40a is too large, an increase in dark current will occur due to the increased area of ​​the i-type InAs / AlAs digital alloy structure multiplication layer 4a. Therefore, as an upper limit for the step width Lt, 300 μm or less is preferred. Furthermore, considering that the element resistance increases if the distance between the light-receiving area 60 and the n-type electrode 50 becomes longer, a step width Lt of 50 μm or less is more preferred. Thus, it can be said that the step width Lt is preferably in the range of 1 μm or more and 50 μm or less.

[0298] When SiN or SiO2 films are formed on a semiconductor layer using chemical vapor deposition (CVD) with hydrogen-containing feed gas, hydrogen is introduced into the semiconductor layer and combines with impurities (dopants) and vacancies. If impurities combine with hydrogen, the impurities become inactive, and the carrier concentration decreases. This phenomenon is called hydrogen passivation. To efficiently generate the film reaction, heat, light, or plasma are used; plasma-enhanced chemical vapor deposition (PECVD) is commonly employed. In PECVD, hydrogen passivation is particularly easy to occur due to the high reaction energy. If the upper surface or intermediate surface of the electric field mitigation layer composed of a p-type InAlAs layer or a p-type InP layer is taken as the step surface 41a, the activation rate of p-type impurities such as Zn and Be contained in the p-type electric field mitigation layer 5 is reduced due to hydrogen passivation generated during the deposition of the surface protective film 11 composed of an insulating film by plasma-enhanced CVD. Consequently, the carrier concentration of the p-type electric field mitigation layer 5 located below the step 40a is reduced. That is, a hydrogen passivation region 45 is formed inside the p-type electric field mitigation layer 5 located below the step 40a. As a result of the formation of the hydrogen passivation region 45, the electric field concentration in the multiplication layer located below the step 40a is mitigated, preventing edge breakdown, i.e., preventing local multiplication in the exposed side portion of the mesa trench 35. Therefore, the low-noise characteristics characteristic of digital alloy structure multiplication layers can be obtained.

[0299] <Effects of Variation 2 of Implementation Method 2>

[0300] According to the above, the semiconductor light-receiving element according to the modified example 2 of embodiment 2, since the upper surface of the p-type electric field mitigation layer is a step surface in the step portion, the electric field applied to the side portion of the i-type InGaAs light-absorbing layer can be suppressed to a small extent. Therefore, it can achieve the effect of realizing a semiconductor light-receiving element with low dark current, low noise, high reliability, and no degradation of the diffusion response band of the incident light beam inside the semiconductor light-receiving element.

[0301] Variation 3 of Implementation Method 2.

[0302] <Features of the semiconductor photodetector (APD) involved in Variation 3 of Embodiment 2>

[0303] Figure 19 This is a cross-sectional view showing the element structure of a back-attribution type APD, which is an example of a semiconductor light-receiving element 140 according to Embodiment 2, Modification 3. The semiconductor light-receiving element 140 according to Embodiment 2, Modification 3 differs structurally from the semiconductor light-receiving element 130 according to Embodiment 2, Modification 2 in that, in the semiconductor light-receiving element 130 according to Embodiment 2, both the i-type InAlGaAs gradient layer 7 and the i-type InGaAs light-absorbing layer 6 below the p-type InP window layer 9 have an i-type conductivity. In contrast, in the semiconductor light-receiving element 140 according to Embodiment 2, Modification 3 has a p-type conductivity of the p-type InAlGaAs gradient layer 7a and the upper part of the InGaAs light-absorbing layer. That is, the InGaAs light-absorbing layer consists of two layers, an i-type InGaAs first light-absorbing layer 6a and a p-type InGaAs second light-absorbing layer 6b, starting from the side in contact with the p-type InAlAs electric field mitigation layer 5.

[0304] A carrier concentration of 5 × 10⁻⁶ is formed on the upper side of the first light-absorbing layer 6a of type i InGaAs. 17 ~8×10 18 cm －3 Furthermore, a p-type InGaAs second light-absorbing layer 6b with a thickness of 0.4 μm or less is formed. Above the p-type InGaAs second light-absorbing layer 6b, a p-type InAlGaAs graded layer 7a with a thickness of 5 to 100 nm and a phased decrease in component wavelength is formed, and a p-type InAlAs graded layer 7b with a thickness of 10 to 200 nm is formed. The semiconductor layers after the p-type InP window layer 9 above the p-type InAlAs graded layer 7b are the same as the semiconductor light-receiving element 130 involved in the variation 2 of Embodiment 2.

[0305] Here, when the upper part of the light absorption layer is a p-type semiconductor layer, that is, when a p-type InGaAs second light absorption layer 6b is provided, holes can easily flow from the p-type InGaAs second light absorption layer 6b to the p-type InP window layer 9, so it is not necessary to have a p-type InAlGaAs gradient layer 7a and a p-type InAlAs gradient layer 7b.

[0306] <The function and effect of the semiconductor photodetector (APD) involved in variation 3 of embodiment 2>

[0307] According to the semiconductor light-receiving element 140 of the modified embodiment 2, since the p-type InGaAs second light-absorbing layer 6b located on the upper side of the entire light-absorbing layer is p-type, the diffusion time is further shortened. Therefore, it can prevent the increase of dark current caused by the thermal diffusion of p-type impurities contained in the p-type InAlAs electric field mitigation layer 5, and the degradation of multiplication noise caused by the disordering of the i-type InAs / AlAs digital alloy structure multiplication layer 4a due to the thermal diffusion of p-type impurities.

[0308] Variation 4 of Implementation Method 2.

[0309] <Characteristics of the semiconductor photodetector (APD) involved in Variation 4 of Embodiment 2>

[0310] Figure 20 This is a cross-sectional view showing the element structure of a back-attribution type APD, as an example of the semiconductor light-receiving element 150 according to Embodiment 2, Variation 4. The semiconductor light-receiving element 150 according to Embodiment 2, Variation 4, is structurally similar to... Figure 19 The difference between the semiconductor light-receiving element 140 in the modified example 3 of embodiment 2 shown is that the semiconductor light-receiving element 140 in the modified example 3 of embodiment 2 has a p-type electric field mitigation layer formed by a p-type InAlAs layer and a p-type impurity diffusion region 20 provided. In contrast, the semiconductor light-receiving element 150 in the modified example 4 of embodiment 2 has a p-type electric field mitigation layer formed by a p-type InP layer and no p-type impurity diffusion region provided.

[0311] When the electric field mitigation layer is composed of a p-type InP layer, examples of p-type impurities that can be pre-doped into the p-type InP layer include Zn, C, Be, and Mg. In variation 4 of embodiment 2, as described above, no p-type impurity diffusion region is provided on the inner periphery of the p-type InGaAs contact layer 10. Therefore, the boundary between the i-type and p-type regions inside the InGaAs light-absorbing layer composed of the i-type InGaAs first light-absorbing layer 6a and the p-type InGaAs second light-absorbing layer 6b, i.e., the interface where the i-type InGaAs first light-absorbing layer 6a and the p-type InGaAs second light-absorbing layer 6b contact, is uniform in the horizontal direction, i.e., in the direction parallel to the surface of the Fe-doped InP substrate 1.

[0312] <The function and effect of the semiconductor photodetector (APD) involved in variation 4 of embodiment 2>

[0313] For p-type InP layers, during the formation of insulating films such as SiN and SiO2 films, hydrogen can be introduced into the semiconductor layer during processes such as plasma processing performed in an atmosphere containing hydrogen. If hydrogen is introduced into the interior of the p-type semiconductor layer, it deactivates p-type impurities. This phenomenon is called hydrogen passivation.

[0314] Because the p-type impurities contained in the p-type InP field mitigation layer 5a are deactivated due to hydrogen passivation, the carrier concentration of the p-type InP field mitigation layer 5a decreases. In the p-type InP field mitigation layer 5a exposed on the outer periphery of the step portion 40, the carrier concentration is easily reduced due to hydrogen passivation. That is, a hydrogen passivation region 45a is formed inside the p-type InP field mitigation layer 5a located below the step portion 40a. Furthermore, a carrier concentration reduction region is formed inside the i-type InAs / AlAs digital alloy structure multiplication layer 4a located below the hydrogen passivation region 45a.

[0315] In the hydrogen passivation region 45a, which is the area where the carrier concentration is reduced in the p-type InP electric field mitigation layer 5a, i.e., the region where the electric field mitigation amount is reduced, it is difficult for multiplication to occur in the i-type InAs / AlAs digital alloy structure multiplication layer 4a that is connected to the hydrogen passivation region 45a. Therefore, it can suppress edge breakdown in the side portion of the i-type InAs / AlAs digital alloy structure multiplication layer 4a.

[0316] Hydrogen introduced into the semiconductor layer due to hydrogen passivation during the formation of the insulating film is reduced by desorption during high-temperature heat treatment processes following the formation of the insulating film. Actual measurements show that hydrogen decreases by 2 × 10⁻⁶. 17 ~1×10 18 cm －3The carrier concentration remains in the p-type InP layer. This is because the carrier concentration in the p-type InP electric field mitigation layer 5a before hydrogen passivation is 5 × 10⁻⁶. 17 ~2×10 18 cm －3 Therefore, since the concentration is 2×10 17 ~1×10 18 cm －3 Hydrogen is introduced into the p-type InP electric field mitigation layer 5a, and the carrier concentration of the p-type InP electric field mitigation layer 5a is reduced to about half. Therefore, since the carrier concentration of the p-type InP electric field mitigation layer 5a located on the lower side of the step portion 40 can be reduced by forming the hydrogen passivation region 45a, the edge breakdown suppression effect is enhanced.

[0317] Hydrogen is also introduced into the semiconductor layer during epitaxial crystal growth. However, the hydrogen concentration is 5 × 10⁻⁶ in semiconductor materials with lattice-matched InP substrates where hydrogen passivation does not occur. 16 cm －3 Below, relative to the 5×10 of the p-type InP electric field mitigation layer 5a 17 ~2×10 18 cm －3 The carrier concentration is an order of magnitude lower. If hydrogen is used to mitigate the carrier concentration in the p-type InP electric field-modulated layer 5a, that is, 5 × 10⁻⁶... 17 ~2×10 18 cm －3 If the same order of magnitude of hydrogen concentration exists in the p-type InP electric field mitigation layer 5a, it can be considered that hydrogen passivation will occur. Therefore, it is preferable that the hydrogen concentration introduced into the p-type InP electric field mitigation layer 5a exposed at the step portion 40, i.e., the hydrogen concentration in the hydrogen passivation region 45a, is 2 × 10⁻⁶. 17 ~1×10 18 cm －3 Within the range.

[0318] Here, the carrier concentration based on p-type impurities in the aforementioned p-type InP electric field mitigation layer 5a is 5 × 10⁻⁶. 17 ~2×10 18 cm －3 The optimal electric field mitigation layer thickness under certain conditions will be explained. The electric field mitigation amount is expressed as elementary charge × carrier concentration × layer thickness of the multiplication layer / (relative permittivity · vacuum permittivity). To obtain the required electric field mitigation amount of 700 kV / cm, if the relative permittivity of the electric field mitigation layer is assumed to be 13, then the carrier concentration based on p-type impurities is 5 × 10⁻⁶. 17 cm －3 The electric field mitigation layer has a thickness of 100 nm and a carrier concentration of 2 × 10⁻⁶. 18 cm －3The electric field mitigation layer thickness is 25 nm in the case of p-type InP electric field mitigation layer 5a. Therefore, in the p-type InP electric field mitigation layer 5a, the carrier concentration based on p-type impurities is 5 × 10⁻⁶. 17 ~2×10 18 cm －3 Within the specified range, the preferred layer thickness is 25–100 nm.

[0319] For example, in Patent Document 6, in order to reduce the amount of electric field mitigation on the outer periphery of the electric field mitigation layer, the thickness of the electric field mitigation layer on the outer periphery is reduced by etching. On the other hand, in Modification 4 of Embodiment 2, by simply forming a surface protective film 11 made of SiN film on the step surface 41 of the step portion 40, the amount of electric field mitigation of the step portion 40 can be reduced by hydrogen passivation effect, and as a result, excessive noise caused by edge breakdown can be suppressed. As described above, in Modification 4 of Embodiment 2, since the manufacturing process of the structure for suppressing edge breakdown is simplified and the etching of the poorly controllable electric field mitigation layer is not performed, the deviation of the device characteristics is also small. In addition, in Modification 4 of Embodiment 2, since the thermal diffusion of p-type impurities, which is a high-temperature heat treatment, is not performed, disordering of the digital alloy structure multiplication layer does not occur, and therefore an APD with low noise characteristics can be easily realized.

[0320] In variations 2, 3, and 5 of Embodiment 2 (described later), the electric field mitigation layer is also constructed from a p-type InP layer to achieve the same effect as in variation 4 of Embodiment 2. Similar to variation 4 of Embodiment 2, the preferred range for the p-type impurity-based carrier concentration and layer thickness of the electric field mitigation layer is a p-type impurity-based carrier concentration of 5 × 10⁻⁶. 17 ~2×10 18 cm －3 Within the range, the layer thickness is in the range of 25 to 100 nm.

[0321] Variation 5 of Implementation Method 2.

[0322] <Features of the semiconductor photodetector (APD) involved in Variation 5 of Embodiment 2>

[0323] Figure 21 This is a cross-sectional view of the element structure of a back-illuminated APD, which is an example of a semiconductor light-receiving element 160 according to Embodiment 2, Modification 5. The semiconductor light-receiving element 160 according to Embodiment 2 is characterized by having a first step portion 42a with the p-type InAlAs electric field mitigation layer 5 below the i-type InGaAs light-absorbing layer 6 as the outermost surface, and a second step portion 42b with the i-type InAlAs surface protection layer 8 below the p-type InP window layer 9 as the outermost surface.

[0324] The semiconductor light-receiving element 160 according to the variation 5 of embodiment 2 includes at least: an Fe-doped InP substrate 1; a first mesa structure 30 having an n-type InP conductive layer 2, an n-type InAlAs conductive layer 3, an i-type InAs / AlAs digital alloy structure multiplication layer 4a, and a p-type InAlAs electric field mitigation layer 5 sequentially formed on the Fe-doped InP substrate 1; a second mesa structure 31 formed on the first mesa structure 30 and having an i-type InGaAs light-absorbing layer 6, a p-type InAlGaAs gradient layer 7a, and an i-type InAlAs surface protection layer 8; a first step portion 42a formed by the outermost surface of the first mesa structure 30 exposed on the outer periphery of the second mesa structure 31; a third mesa structure 32 formed on the second mesa structure 31 and having a p-type InP window layer 9 with a band gap larger than that of the i-type InGaAs light-absorbing layer 6; and a second step portion 42b formed by the outermost surface of the second mesa structure 31 exposed on the outer periphery of the third mesa structure 32.

[0325] As an example of the manufacturing method of the semiconductor light-receiving element 160 according to Variation 5 of Embodiment 2, the following manufacturing method can be listed: In Embodiment 2 Figure 5 After etching the p-type InP window layer 9 as shown to form the second step portion 42b, as indicated... Figure 22 As shown, the first step portion 42a is formed by etching away the i-type InAlAs surface protective layer 8, the p-type InAlGaAs gradient layer 7a, and the i-type InGaAs light-absorbing layer 6. After forming the first step portion 42a, a mesa trench 35 is formed with the etched surface reaching the n-type InP conductive layer 2, and a surface protective film 11, an n-type electrode 50, a p-type electrode 51, and a back-side anti-reflective film 16 are formed in the same manner as in Embodiment 2.

[0326] The preferred step width Lt for both the first step portion 42a and the second step portion 42b is preferably 1 μm or more, which is easy to process and can mitigate the electric field applied to the mesa trench 35. On the other hand, if the step width Lt is too wide, the dark current increases due to the increased area of ​​the i-type InGaAs light-absorbing layer 6 and the i-type InAs / AlAs digital alloy structure multiplication layer 4a. In view of the above, the combined step width Lt of the first step portion 42a and the second step portion 42b is preferably 300 μm or less, and when considering that the element resistance increases if the distance between the light-receiving area 60 and the n-type electrode 50 becomes longer, it is preferably 50 μm or less. Based on the above, it can be said that the step width Lt of both the first step portion 42a and the second step portion 42b is preferably in the range of 1 μm or more and 50 μm or less.

[0327] <The function and effect of the semiconductor photodetector (APD) involved in variation 5 of embodiment 2>

[0328] When the electric field applied to the exposed side portions of the i-type InAs / AlAs digital alloy multiplication layer 4a, the p-type InAlAs electric field mitigation layer 5, and the i-type InGaAs light-absorbing layer 6 is large, a problem arises where dark current changes over time, impairing reliability. Therefore, in the semiconductor light-receiving element 160 according to Modification 5 of Embodiment 2, since a second step portion 42b is provided in addition to the first step portion 42a, the distance from the p-type InP window layer 9 to the exposed side portion of the i-type InGaAs light-absorbing layer 6 can be increased, thus mitigating the electric field applied to the side portions of the i-type InGaAs light-absorbing layer 6.

[0329] Furthermore, similar to Variation 2 of Embodiment 2, since the first step portion 42a can mitigate the electric field concentration in the side portion of the i-type InAs / AlAs digital alloy structure multiplication layer 4a without causing edge breakdown, i.e., local multiplication in the side portion, it achieves the effect of stably obtaining the low noise characteristic of the digital alloy structure multiplication layer. As described above, by forming the first step portion 42a and the second step portion 42b, the effect of achieving a highly reliable APD with long-term stable dark current and multiplication noise is achieved.

[0330] Implementation method 3.

[0331] <Features of the semiconductor photodetector (APD) involved in Embodiment 3>

[0332] Figure 23 This is a cross-sectional view showing the element structure of a surface-incident type APD, an example of the semiconductor light-receiving element 170 according to Embodiment 3. Figure 12 The difference between the semiconductor light-receiving element 110 in Embodiment 2 is that the semiconductor light-receiving element 110 in Embodiment 2 is a back-incident type APD in which light is incident from the back side of the semiconductor substrate, while the semiconductor light-receiving element 170 in Embodiment 3 is a surface-incident type APD in which light is incident from the surface side of the semiconductor substrate.

[0333] As an example of the semiconductor light-receiving element 170 according to Embodiment 3, the surface-incident type APD is composed of an n-type InP substrate 1a, a first mesa structure 30, a second mesa structure 31, a p-type impurity diffusion region 20, a step portion 40, a surface-side anti-reflection film 15, a mesa trench 35, a light-shielding metal film 66, a p-type electrode 51a, and an n-type electrode 50a. The first mesa structure 30 has a carrier concentration of 5 × 10⁻⁶ sequentially formed on the n-type InP substrate 1a. 17 ~8×1018 cm －3 Furthermore, it consists of an n-type InAlAs conductive layer 3 with a thickness of 0.1–1.0 μm, an i-type InAs / AlAs digital alloy multiplication layer 4a, and a carrier concentration of 1 × 10⁻⁶. 16 ~5×10 18 cm －3 The structure comprises a p-type InAlAs electric field mitigation layer 5 with a thickness of 10–100 nm, an i-type InGaAs light absorption layer 6 with a thickness of 0.1–2.0 μm, an i-type InAlGaAs gradient layer 7 with a thickness of 5–100 nm and progressively shorter component wavelengths, and an i-type InAlAs surface protection layer 8 with a thickness of 10–200 nm. The n-type InP substrate 1a is exposed as a semiconductor layer on its outer periphery, and its surface is approximately circular when viewed from above. The second mesa structure 31 has a carrier concentration of 5 × 10⁻⁶ formed sequentially on the first mesa structure 30. 17 ~8×10 18 cm －3 Furthermore, it consists of a p-type InP window layer with a thickness of 0.1–3.0 μm and a carrier concentration of 5 × 10⁹ / L. 17 ~8×10 18 cm －3 The p-type InGaAs contact layer 10, with a thickness of 0.05–0.5 μm, is annular along the outer periphery of the approximately circular light-receiving area 60 when viewed from above, and its surface is approximately circular when viewed from above. A p-type impurity diffusion region 20 is disposed on a portion of the p-type InP window layer 9 and the i-type InGaAs light-absorbing layer 6 on the inner periphery of the annular p-type InGaAs contact layer 10. The step portion 40 is formed by the first mesa structure 30 exposed on the outer periphery of the second mesa structure 31, and has a step surface 41 with a width of 1.0 μm or more in the outer periphery direction. Surface-side anti-reflection... The photoresist film 15 is formed on the inner peripheral side of the annular p-type InGaAs contact layer 10, that is, on the surface of the p-type InP window layer 9 corresponding to the approximately circular light-receiving area 60, and is made of SiN film; the mesa trench 35 reaches the n-type InP substrate 1a on the outer peripheral side of the first mesa structure 30; the light-shielding metal film 66 covers the step surface 41 of the step portion 40 and the side surface of the first mesa structure 30 and is made of metal film; the p-type electrode 51a is disposed on the surface of the annular p-type InGaAs contact layer 10; and the n-type electrode 50a is disposed on the back side of the n-type InP substrate 1a.

[0334] The light-shielding metal film 66 is made of the same material as the p-type electrode 51a, such as Ti / Au or Ti / Pt / Au, starting from the contact surface. As described above, a p-type impurity diffusion region 20, which is formed to reach the i-type InGaAs light-absorbing layer 6, is provided on the inner peripheral side of the annular p-type InGaAs contact layer 10.

[0335] Here, i-type refers to undoped, p-type, or n-type carriers with a carrier concentration of 5 × 10⁻⁶. 17 cm －3 The following situation applies. Since the Fe-doped InP substrate 1 is used in the semiconductor light-receiving element 110 according to Embodiment 2, it is necessary to form an n-type electrode 50 on the surface side of the Fe-doped InP substrate 1. On the other hand, in the semiconductor light-receiving element 170 according to Embodiment 3, since... Figure 23 As shown, an n-type InP substrate 1a is used, so an n-type electrode 50a can be formed on the back side of the n-type InP substrate 1a.

[0336] <Function and Effect of the Semiconductor Photodetector (APD) Involved in Implementation Method 3>

[0337] In the case of a back-incident type APD, which is an example of the semiconductor light-receiving element 110 according to Embodiment 2, if the light beam diffuses and is incident on the Fe-doped InP substrate 1 having a layer thickness of 100 μm or more after being incident on it, and is incident on the i-type InGaAs light-absorbing layer 6 outside the light-receiving region 60, then the light outside the light-receiving region 60 is also absorbed, generating electrons and holes.

[0338] In the portion outside the light-receiving region 60, such as the step portion 40 and the underside of the p-type InGaAs contact layer 10, the transit time of charge carriers such as electrons and holes is longer due to the thickness of the depletion layer. Therefore, in the case of a back-incident APD, it is necessary to avoid beam diffusion and optical axis deviation from the light-receiving region 60.

[0339] On the other hand, in the surface-incident APD according to Embodiment 3, since a light-shielding metal film 66 is disposed outside the light-receiving area 60 such as the step portion 40, even if incident light is incident on the step portion 40, it will not be absorbed by the i-type InGaAs light-absorbing layer 6. In addition, since the surface of the annular p-type InGaAs contact layer 10 is covered by the p-type electrode 51, light will not be incident on the i-type InGaAs light-absorbing layer 6 located below the p-type InGaAs contact layer 10. As a result, even if the beam diffuses and the optical axis shifts inside the surface-incident APD, a carrier component with a slow response speed will not be generated, thus achieving the effect of obtaining a semiconductor photodetector (APD) with a wide response bandwidth.

[0340] Implementation method 4.

[0341] Figure 24This is a configuration diagram showing the optical line termination device (OLT) 260 of the 50G-PON system according to Embodiment 3. The optical line termination device 260 includes an FEC 261 (Forward Error Correction), a driver amplifier 262, a light source 263, a WDM 264 (Wavelength Division Multiplexing), a CDR 265 (Clock Data Recovery) as a clock data recovery circuit, a limiting amplifier 266, a burst TIA 267, and the DA-APD 268 of this disclosure.

[0342] In this disclosure, DA-APD refers to the APD with an InAs / AlAs digital alloy structure as the multiplication layer described in Embodiment 2, Variations 1 to 5 of Embodiment 2, and Embodiment 3.

[0343] Figure 25 This is a configuration diagram showing the optical line termination device (ONU) of the 50G-PON system according to Embodiment 4. The optical line termination device 270 includes: WDM 271, light source 272, driver amplifier 273, FEC 274, DA-APD 275 of this disclosure, TIA 276, limiting amplifier 277, and CDR 278.

[0344] Figure 26 This is a configuration diagram of an optical line termination device (OLT) 250a for a comparative example of a 50G-PON system. The comparative example OLT 250a includes a forward error correction circuit (FEC251), a driver amplifier 252, a light source 253, a wavelength division multiplexing (WDM) circuit (WDM254), a digital signal processing circuit (DSP255), an analog-to-digital converter (ADC256), a burst amplifier (TIA257), and a conventional APD258.

[0345] like Figure 26 As shown in the optical line termination device 250a of the 50G-PON system as a comparative example, the 50G-PON system as a comparative example requires digital band compensation, i.e., DSP255. On the other hand, in the 50G-PON system using the DA-APD of this disclosure, digital band compensation is not required. That is, if... Figure 25If the DA-APD of this disclosure is used in the 50G-PON system optical line terminal unit (ONU) of the embodiment 4 shown, a wide response bandwidth and high receiving sensitivity can be achieved, thus simplifying and saving power of the DSP circuit and reducing the output power of the SOA.

[0346] To enable multi-branching of PON systems and eliminate SOA, the receiver's SN ratio needs to be improved to enhance receiver sensitivity. For example, if an additional optical splitter is added to increase the number of branches compared to the current situation, the SN ratio needs to be improved by at least 3dB because the light quantity is halved. The SN ratio of a receiver using an APD is represented by the following equation (17).

[0347] SN ratio = Iph 2 ·M 2 / (2q(Iph+Id)M 2 ·F·B+4Kb·T·Ft·B / Rt) (17)

[0348] In equation (17), Iph represents the photocurrent of the APD, M represents the multiplication rate, q represents the unit charge, Id represents the multiplied dark current, F represents the excess noise figure of the APD, B represents the frequency band, Kb represents the Boltzmann constant, T represents the absolute temperature, Ft represents the noise figure of the amplifier, and Rt represents the input resistance. The left-hand side of the denominator represents the shot noise of the APD, and the right-hand side of the denominator represents the thermal noise of the amplifier.

[0349] To simplify equation (17), it is assumed that the shot noise term of the APD is equal to the thermal noise term of the amplifier when Id is sufficiently smaller than Iph and the SN ratio is at its maximum multiplication rate. If the shot noise term of the APD is used to replace the thermal noise term of the amplifier, the SN ratio is expressed by the following equation (18).

[0350] SN ratio = Iph / (4q·F·B) (18)

[0351] In addition, the excess noise figure F is given by the following equation (19).

[0352] F=M(1-(1-k)·((M-1) 2 / M 2 )(19)

[0353] In the case of existing InAlAs random alloy structure multiplication layers, if the thickness is reduced to the point of dead zone effect (approximately 70 nm), the tunneling current increases and noise deteriorates as described above. To minimize the tunneling current, the pn junction diameter needs to be reduced to below a few μm, but this increases the alignment precision required for focusing onto the APD. Although the performance is inferior to that of digital alloy multiplication layers in terms of noise, this method of thinning the multiplication layer can still achieve a certain degree of noise reduction, even for random alloy multiplication layers. On the other hand, the small diameter of the pn junction imposes limitations on productivity and other aspects. Therefore, the ionization coefficient ratio k is set to 0.2 for the case of an unthinned InAlAs multiplication layer in the system design. With an ionization coefficient ratio k = 0.2 and a multiplication rate of 12x, the excess noise figure F = 3.9.

[0354] On the other hand, in the 50G-PON system according to Embodiment 4, an APD with an InAs / AlAs digital alloy structure as a multiplication layer, namely the DA-APD of this disclosure, is used as a semiconductor light-receiving element. In the case of the InAs / AlAs digital alloy structure multiplication layer of this disclosure, since a dead zone effect can be achieved even with a layer thickness of 100 nm or more, it can be applied to an APD. In this case, the ionization coefficient ratio k=0, and when the multiplication rate is 12 times, the excess noise figure F=1.9. Therefore, it is about half the excess noise of conventional APDs. As a result, if the DA-APD of this disclosure is applied, the signal-to-noise ratio is improved by 3 dB.

[0355] In a typical 50G-PON system, inserting a second-level splitter to increase the number of branches increases the loss by 3dB. Therefore, by using the DA-APD disclosed herein as a semiconductor light-receiving element, it is possible to insert an additional second-level splitter in a 50G-PON system.

[0356] Figure 27 This diagram illustrates the configuration of the optical line termination device (OLT) of the 50G-PON system according to Embodiment 4. The optical line termination device 260a of the 50G-PON system includes an FEC 261, a driver amplifier 262, a light source 263, a WDM 264, a DSP 265a, an ADC 266a, a burst TIA 267, and the DA-APD 268 of this disclosure.

[0357] Figure 28 This diagram illustrates the configuration of the optical line termination unit (ONU) of the 50G-PON system according to Embodiment 4. The optical line termination unit 260b of the 50G-PON system includes an FEC 261, a driver amplifier 262, a light source 263, a WDM 264, a DSP 265a, an ADC 266a, a TIA 267a, and the DA-APD 268 of this disclosure.

[0358] The effects of the semiconductor light-receiving element involved in this disclosure are further explained. The DA-APD of this disclosure, with its InAs / AlAs digital alloy structure multiplication layer, achieves a zero ionization coefficient ratio k by controlling the layer thickness within a predetermined range, thus making the multiplication time in equation (7) almost zero. As a result, the response bandwidth of the APD does not degrade even when the multiplication rate is increased. That is, in the DA-APD of this disclosure, similar to existing PDs, the response bandwidth is limited only by the RC time constant and the carrier transit time. Therefore, the required broadband response bandwidth can be achieved in a 50G-PON system, enabling reception even without DSP-based digital bandwidth compensation.

[0359] Furthermore, if the ionization coefficient ratio k is close to zero, the excessive noise that degrades receiver sensitivity is suppressed, thus eliminating the need for optical signal amplification via SOA. Moreover, in PON systems beyond 50G-PON systems, more branching can be achieved than in existing systems. As a result, lower cost and lower power consumption can be realized in PON systems.

[0360] <Effects of Implementation Method 4>

[0361] As described above, the optical line termination device according to Embodiment 4 uses the DA-APD of this disclosure as a semiconductor light-receiving element, thus achieving the effect of increasing the transmission distance of optical signals and reducing power consumption.

[0362] Implementation method 5.

[0363] Figure 29 This is a diagram illustrating the configuration of the multi-level intensity modulation transceiver 300 according to Embodiment 5. Additionally, Figure 30A and Figure 30B This is a schematic diagram showing the received waveform envisioned in the multi-level intensity modulation transceiver 300 according to Embodiment 4.

[0364] The multi-level intensity modulation transceiver 300 is a multi-level intensity modulation transceiver using PAM (Pulse Amplitude Modulation) as the multi-level intensity modulation method. In the transmitting section, the digital signal generated by the DSP 301 is converted into an analog signal by the DAC 302a, amplified by the driver amplifier 303, and then drives the light source 304, which is composed of a DFB laser or an EML, to emit an optical signal into the optical fiber cable 310.

[0365] On the other hand, in the receiving section, light from the optical fiber cable 310 is incident on the DA-APD305, which is a semiconductor light-receiving element of the present disclosure, through the optical system. The light signal is converted into current and multiplied, and then amplified in the Linear-TIA306. After that, it is converted into a digital signal in the ADC302b and processed by the DSP301.

[0366] <Function and Effects of the Multi-Level Intensity Modulation Transceiver Device in Implementation Method 5>

[0367] In the PAM-based multi-level intensity modulation transceiver 300, not only are binary signals of 1 and 0 such as NRZ (None Return to Zero) and RZ (Return to Zero) required, but also, for example, in PAM4 (Pulse Amplitude Modulation-4), four values ​​with different light signal intensities need to be received. Figure 30A The schematic diagram shows a hypothetical example of the received waveform in PAM4. The TDECQ (Transmitter Dispersion and Eye Closure Quaternary) index can be used to determine the quality of the received waveform in PAM4. TDECQ is calculated using the following equation (20).

[0368] TDECQ(dB)=10·log(OMA / (6·Qt·R))(20)

[0369] In equation (20), the optical modulation amplitude (OMA) is the total amplitude from level 0 to level 3, Qt is a value dependent on the SER (Symbol Error Rate) specified by the IEEE (Institute of Electrical and Electronics Engineers), and R is the additional noise value required to achieve the SER value. TDECQ (dB) is specified, for example, to be below 3dB. To reduce TDECQ (dB), the following is required:

[0370] (1) The eye diagrams of each level have uniform openings.

[0371] (2) There is little noise at each level.

[0372] To ensure uniform eye diagram openings for the four levels representing different light signal intensities, the semiconductor light-receiving element requires excellent linearity. Here, good linearity of the semiconductor light-receiving element means that the photocurrent Iph increases proportionally to the optical input power Pin. That is, even if the optical input power Pin changes, good linearity can be considered achieved if Iph / Pin remains constant.

[0373] Furthermore, in PAM (Power Amplifier), excellent dynamic range is required because it needs to receive signals ranging from low to high intensity. That is, even if the optical input power (Pin) increases, a good dynamic range can be considered achieved if the decrease in Iph / Pin is small. (See the schematic diagram for illustration.) Figure 30B As with the received waveform, if the linearity and dynamic range deteriorate, the eye diagram opening between level 2 and level 3 will deteriorate.

[0374] In the case of PD and APD, one reason for the deterioration of linearity is that as the photocurrent increases with the increase of light input, the number of holes and electrons crossing in the multiplication layer and the light absorption layer increases, thus changing the electric field distribution in the multiplication layer and the light absorption layer. This phenomenon is called the space charge effect.

[0375] The inventors studied a model of linearity degradation in APD. Figure 31A and Figure 31B This is a diagram illustrating the operation of the PD during highlight input. For example... Figure 31A As shown, if the light input increases and the photocurrent increases, the space charge effect will act as if a voltage drop caused by the series resistance no longer applies a voltage to the pn junction. The multiplication rate decreases due to this voltage drop. This is because... Figure 31B The electrons and holes generated as shown affect the electric field distribution. The series resistance Rli that degrades the linearity of the APD is shown in the following equation (21).

[0376] Rli = Rsc + Rd + Rlo (21)

[0377] In equation (21), Rsc is the resistance caused by the space charge effect, Rd is the element resistance, and Rlo is the load resistance. Rd and the load resistance are usually tens of Ω, but Rsc sometimes reaches hundreds of Ω or more.

[0378] The inventors discovered that if the time for electrons and holes generated by light absorption to pass through the depletion layer is set as Td, then Rsc is represented by the following equation (22).

[0379] Rsc=W·Td / (2εS) (22)

[0380] In equation (22), W is the thickness of the depletion layer, ε is the dielectric constant, and S is the area of ​​the pn junction.

[0381] The resistance Rsc caused by the space charge effect is proportional to the transit time Td of electrons and holes in the depletion layer. Therefore, increasing the transit velocity of electrons and holes to reduce Td can decrease the resistance Rsc.

[0382] In the DA-APD disclosed herein, due to the short doubling time, the response bandwidth does not degrade even when used at high doubling rates. Therefore, since the light absorption in the light absorption layer is small, the receiver sensitivity can be improved even when operating at high doubling rates, allowing for thinning of the light absorption layer, which in turn reduces the resistance Rsc. As a result, the TDECQ meets the specified value because the eye diagram opening becomes more uniform. Furthermore, it enables the transmission distance to be increased and the drive current of the transmitting laser to be reduced.

[0383] The following explains the use of the DA-APD disclosed herein. First, the operation of the APD during highlight input will be explained. Figure 32 This is a schematic diagram illustrating the operation of the APD during high-light input. If many electrons and holes are generated in the multiplication layer, the electric field in the multiplication layer of the APD changes, i.e., the so-called space charge effect occurs. Due to the occurrence of this space charge effect, the multiplication rate of the APD decreases and the linearity deteriorates. As mentioned above, since the deterioration of the linearity of the APD is caused by the series resistance Rsc, it is necessary to reduce the residence time Tdm of electrons and holes in the depletion layer. In particular, if the multiplication rate increases, the residence time Tdm in the multiplication layer increases. Tdm is the same as the so-called multiplication time, and is represented by the following equation (23).

[0384] Residence time Tdm = doubling time = 2πNkMτav (23)

[0385] In equation (23), N is the Emmons coefficient (which varies slowly with the ionization coefficient ratio k), M is the multiplication rate, and τav is the average transit time of electrons and holes in the multiplication layer. The one-way transit time of carriers across the multiplication layer is subtracted from the residence time Tdm. N is 0.55, 0.83, 1.1, and 2.0 for ionization coefficient ratios k = 0.5 (InP), 0.2 (InAlAs), 0.1 (Si), and 0–0.001 (InAs / AlAs digital alloy structure), respectively.

[0386] Figure 33 The table shows the estimated residence time (Tdm) of electrons and holes for each material constituting the multiplication layer. In the InAs / AlAs digital alloy multiplication layer, the residence time (Tdm) within the multiplication layer is significantly reduced. That is, due to the rapid expulsion of electrons and holes from the multiplication layer, the space charge effect in the multiplication layer can be suppressed, resulting in improved linearity and dynamic range in the InAs / AlAs digital alloy multiplication layer.

[0387] As a result, in existing APDs, such as Figure 30B As shown in the schematic diagram, the eye diagram opening of PAM4 is uneven, but in the DA-APD of this disclosure, due to... Figure 30A As shown in the schematic diagram, the eye diagram opening becomes uniform, so TDECQ can meet the specified value. Therefore, if the DA-APD of this disclosure is used, since the APD can be used even in transceivers for PAM, the transmission distance of the optical signal can be increased and the drive current of the transmitting laser can be reduced.

[0388] <Effects of Implementation Method 5>

[0389] As described above, the multi-level intensity modulation transceiver device according to Embodiment 5 uses the DA-APD of this disclosure as a semiconductor light-receiving element, thus achieving the effect of increasing the transmission distance of the optical signal and reducing power consumption.

[0390] Implementation method 6.

[0391] Figure 34 This is a schematic diagram illustrating the configuration of the fiber optic wireless system 400 (Radio on fiber: RoF) according to Embodiment 6. Additionally, Figure 35 This is a schematic diagram illustrating the configuration of a fiber optic wireless system 450 as a comparative example. The fiber optic wireless system 400 includes a light source 401, a transmission path 402 such as a fiber optic cable, a DA-APD 403 of this disclosure, and an antenna 404.

[0392] In the fiber optic wireless system 400 according to Embodiment 6, an analog electrical amplitude signal is input to a light source 401 such as an LD and converted into an optical amplitude signal. The converted optical amplitude signal is transmitted through an optical fiber cable, i.e., transmission path 402. The DA-APD 403 of this disclosure is used to multiply the transmitted optical amplitude signal and convert it into an electrical amplitude signal. The converted electrical amplitude signal is transmitted to an antenna 404 and radiated as a radio wave signal.

[0393] The fiber optic wireless system 400 described in Embodiment 6 can efficiently supply signals to an antenna 404 located at a distance from the electrical signal source. Furthermore, since no analog-to-digital or digital-to-analog conversion is performed during transmission, it features a simple system configuration and low power consumption.

[0394] <The function and effects of the fiber optic wireless system involved in Implementation Method 6>

[0395] exist Figure 35In the comparative example of the fiber optic wireless system 450 shown, if the signal attenuates during transmission through the fiber optic cable, there is a problem that the antenna cannot radiate a sufficient amount of radio wave signal because the signal cannot be multiplied in the PD406.

[0396] Alternatively, if using an existing APD, then as follows Figure 31A and Figure 31B As illustrated in the diagram, the electric field distribution changes as the number of electrons and holes in the multiplication layer increases, causing the multiplication rate to saturate and making it impossible to ensure the dynamic range. Therefore, not only is it impossible to obtain sufficient electrical signal amplitude, but there is also the problem of analog signal distortion. Consequently, it is difficult to apply existing APDs to fiber optic wireless systems like the comparative example 450.

[0397] On the other hand, in the DA-APD of this disclosure used in the fiber optic wireless system 400 according to Embodiment 6, the response bandwidth does not degrade even when used at a high doubling rate due to the short doubling time. Therefore, since the receiving sensitivity can be improved even when operating at a high doubling rate, even if the amount of light absorbed in the light absorption layer is small, the light absorption layer can be thinned, and the resistance Rsc can be reduced by thinning the light absorption layer. As a result, a response with good linearity can be obtained over a wide dynamic range, and a large current amplitude can be obtained. Thus, since the fiber optic wireless system 400 is constructed using the DA-APD of this disclosure, a strong radio signal can be output with good linearity even when the optical transmission distance is increased.

[0398] Furthermore, in the DA-APD403 disclosed herein, such as Figure 33 As shown, due to the short residence time Tdm of electrons and holes in the multiplication layer, changes in the electric field distribution within the multiplication layer can be suppressed. As a result, a response with excellent linearity can be obtained over a wide dynamic range. That is, by multiplying the signal using the DA-APD403 of this disclosure, the original signal can be reproduced and a large current amplitude can be obtained.

[0399] The multiplication rate of the DA-APD403 disclosed herein can be used in the range of 1.2 to 10. However, since signal distortion occurs if the multiplication rate increases, it is preferable to use it at a multiplication rate in the range of 1.2 to 5. Furthermore, considering the fiber loss and the fact that the quantum efficiency of the APD is not 100% but approximately 80%, it is best to use it at a multiplication rate of 2 to 3 to compensate for this loss.

[0400] <Effects of Implementation Method 6>

[0401] According to the fiber optic wireless system described in Embodiment 6, since the fiber optic wireless system is constructed using the DA-APD disclosed herein, it achieves the effect of providing a fiber optic wireless system that can output strong radio wave signals even when the optical transmission distance is increased.

[0402] Implementation method 7.

[0403] Figure 36 This is a schematic diagram illustrating the configuration of the digital coherent receiving apparatus 500 according to Embodiment 7. The digital coherent receiving apparatus 500 according to Embodiment 7 is characterized by using the DA-APD505a of this disclosure.

[0404] In digital coherent communication, optical signals modulated in both phase and intensity within an optical fiber are transmitted via polarization multiplexing. In the digital coherent receiving device 500, the optical signal input from the optical fiber cable 501 is first polarized by a polarization separator 502. After polarization separation, each polarized signal light is incident on 90-degree mixers 503a and 503b, respectively. Meanwhile, the local oscillator laser emitted from the semiconductor laser 504 is separated into two signals with a 90-degree phase offset.

[0405] The signal light is combined with the laser beam, and then the signal light is separated into orthogonal components (I, Q) and output. Four optical signals, namely, four optical signals with orthogonal I and Q components for each polarization wave, are respectively incident on four balanced detectors 505. These four balanced detectors 505 are connected in series as a pair via two DA-APDs 505a disclosed herein and are configured within 90-degree mixers 503a and 503b. The electrical signals output from the balanced detectors 505 are input to the DSP 506. The digital coherent receiving apparatus 500 according to Embodiment 7 has the above configuration.

[0406] <Function of the digital coherent receiving device involved in Implementation Method 7>

[0407] Figure 37A This is a schematic diagram used to illustrate a waveform conceived in a digital coherent receiving device used as a comparative example. Figure 37B This is a schematic diagram illustrating a waveform envisioned in the digital coherent receiving apparatus according to Embodiment 7.

[0408] In existing balanced detectors, a photodiode (PD) is used as the semiconductor light-receiving element to receive the signal light. On the other hand, since the signal can be multiplied by using the DA-APD505a disclosed herein, the local oscillator light can be suppressed to a small extent. Furthermore, if a conventional APD is used, as... Figure 32As shown in the schematic diagram, the electric field distribution changes as the number of electrons and holes in the multiplication layer increases, leading to multiplication rate saturation and inability to ensure dynamic range. Therefore, not only is sufficient electrical signal amplitude not obtained, but analog signal distortion also occurs. The result is as follows... Figure 37A As shown in the schematic diagram, in the comparative example, the interval between waveforms A1 and B1 becomes narrower, and due to the distortion of the intensity signal of the constellation waveform, it is difficult to apply the APD.

[0409] On the other hand, in the DA-APD of this disclosure used in the digital coherent receiving apparatus 500 according to Embodiment 7, since the doubling time is short, the response bandwidth does not degrade even when using a high doubling rate. Therefore, since the receiving sensitivity can be improved as long as it operates at a high doubling rate, even if the light absorption in the light absorption layer is small, the light absorption layer can be thinned. By thinning the light absorption layer, it is less susceptible to the influence of resistance Rsc caused by the space charge effect, and thus a constellation waveform with excellent linearity can be obtained over a wide dynamic range.

[0410] Furthermore, in the DA-APD505a disclosed herein, as Figure 33 As shown, due to the short residence time Tdm of electrons and holes in the multiplication layer, changes in the electric field distribution within the multiplication layer can be suppressed. The result is, as... Figure 37B As shown in the schematic diagram, when using the DA-APD505a of this disclosure, the interval between waveform A and waveform B becomes wider, enabling the acquisition of a constellation waveform with excellent linearity over a wide dynamic range. That is, even when the signal is multiplied by the APD, the original signal can be reproduced, and a large current amplitude can be obtained.

[0411] The DA-APD505a disclosed herein can also be used in the range of 1.2 to 10 times. However, since the signal will be distorted if the multiplication rate is too high, it is preferable to use it in the range of 1.2 to 5 times.

[0412] <Effects of Implementation Method 7>

[0413] According to the above, the digital coherent receiving device according to Embodiment 7 uses the DA-APD of this disclosure as a semiconductor light-receiving element for receiving optical signals, thus achieving the effect of reducing the driving current of the local oscillator (laser) and reducing the power consumption of the digital coherent receiving device.

[0414] Implementation method 8.

[0415] Figure 38 This is a schematic diagram showing the configuration of the SPAD sensor system according to Embodiment 8. The SPAD sensor system 600 includes a photoelectronic measurement circuit 601, a SPAD sensor 602 composed of the DA-APD disclosed herein, and a quenching circuit 603.

[0416] SPADs can be used not only for photon counting but also as highly sensitive light-receiving elements. However, they require continuous switching between the quenching voltage (A) and the Geiger mode voltage (B), described later. The repetition period is on the order of nanoseconds to microseconds. Shortening the repetition period of the quenching and Geiger mode voltages can improve the SPAD's response speed.

[0417] That is, if the DA-APD of this disclosure is applied to SPAD, it is possible to achieve fast switching between A: Quenching voltage and B: Geiger mode voltage, thereby improving the response bandwidth of SPAD sensor 602.

[0418] Furthermore, if the DA-APD505a of this disclosure is used in the SPAD sensor system 600, the photons incident on the SPAD sensor system 600 are absorbed in the light absorption layer of the SPAD sensor 602 composed of the DA-APD of this disclosure, generating electron-hole pairs, with the electrons flowing into the multiplication layer. An electric field approximately 10% higher than the avalanche breakdown electric field is applied to the multiplication layer.

[0419] This state is called Geiger mode. In Geiger mode, the number of electrons multiplies to 10. 6 The generated electrons flow as an electric current to the photoelectron measurement circuit 601. If the current generated by a photon is known in advance, the number of photons incident on the SPAD sensor system 600 can be counted.

[0420] Figure 39A This is a schematic diagram illustrating the multiplication characteristics envisioned in the SPAD sensor system used as a comparative example. Figure 39B This is a schematic diagram illustrating the anticipated multiplication characteristics in the SPAD sensor system according to Embodiment 8. Since an excess current would flow if an electric field exceeding the avalanche breakdown electric field were continuously applied to the multiplication layer, the voltage applied to the SPAD sensor 602 is rapidly reduced after a photon is detected to weaken the electric field of the multiplication layer. This is called quenching. That is, as based on... Figure 39A and Figure 39B The diagram illustrates a comparison of the multiplication characteristics of a SPAD sensor. The chain multiplication is stopped by reducing the voltage from B: Geiger mode voltage to A: quench voltage, and then increasing the voltage from A: quench voltage to B: Geiger mode voltage again, resulting in a state where incident photons can be received with high sensitivity.

[0421] The quenching circuit 603 for controlling the voltage contains both passive and active circuits. In the passive circuit, if a current flows due to photons incident on the SPAD sensor 602, a voltage drop occurs in the resistor connected in series with the SPAD sensor 602, thus reducing the voltage applied to the SPAD sensor 602. In other words, the quenching circuit 603 operates by repeatedly applying voltages above and below the breakdown voltage to the SPAD sensor 602.

[0422] <Function and Effects of the SPAD Sensor System in Implementation Method 8>

[0423] The SPAD sensor system 600 described in Embodiment 8 can be used not only for photon counting but also as a highly sensitive semiconductor light-receiving element. However, it requires continuous repetition from the B: Geiger mode voltage to the A: quenching voltage. If the difference between the A: quenching voltage and the B: Geiger mode voltage, which has a repetition period on the order of nanoseconds to microseconds, can be reduced, the response speed of the SPAD sensor system 600 can be improved by shortening the repetition period.

[0424] In the passive quenching circuit 603, the resistance value connected in series with the SPAD sensor 602 can be reduced, thus increasing the response speed of the SPAD sensor 602. Furthermore, in the active quenching circuit 603, the voltage amplitude is reduced, which simplifies the drive circuit, saves power, and widens the response bandwidth.

[0425] In the DA-APD of this disclosure, due to the short doubling time, the response bandwidth does not degrade even when using high doubling rates. Therefore, since the light absorption in the light absorption layer is small, the receiver sensitivity can be improved as long as it operates at a high doubling rate, thus allowing the light absorption layer to be thinned. Since the resistance Rsc is reduced by thinning the light absorption layer, the breakdown voltage can also be reduced. If the DA-APD of this disclosure is used in a SPAD, the difference between the quenching voltage and the Geiger mode voltage, i.e., the applied voltage difference, can be reduced, thereby improving the response bandwidth and simplifying and saving power in the quenching circuit.

[0426] The following explains the function of the InAs / AlAs digital alloy structure disclosed herein as a multiplication layer. In the InAs / AlAs digital alloy structure multiplication layer of this disclosure, as... Figure 14A and Figure 14BAs shown in the schematic diagram, due to the long dead zone length, no multiplication occurs under low electric fields. However, since the dead zone length shortens as the electric field is gradually increased, the multiplication rate increases sharply, leading to breakdown. In the APD with InAlAs random alloy structure multiplication layer and the APD with InAs / AlAs digital alloy structure multiplication layer having a thick multiplication layer, if the voltage with a dark current exceeding 10 μA is set as the breakdown voltage, the multiplication rate at 90% of the breakdown voltage exceeds 10 times. On the other hand, in the InAs / AlAs digital alloy structure multiplication layer of this disclosure, the multiplication rate at 90% of the breakdown voltage is less than 10 times.

[0427] Since the breakdown voltage depends on the component structure, such as the thickness of the light-absorbing layer and the carrier concentration of the electric field mitigation layer, the effect is verified here using the electric field of the multiplication layer, which can be quantified. Specifically, above the punch-through voltage (~12V), the voltage applied to the SPAD sensor 602 is proportional to the electric field of the multiplication layer.

[0428] Figure 40 This is a graph showing the difference between the quenching electric field and the Geiger mode electric field of each constituent material in the multiplication layer. In the InAs / AlAs digital alloy structure multiplication layer of this disclosure, it can be seen that the difference between the quenching electric field and the Geiger mode electric field of each multiplication layer is usually low, at 170 kV / cm. For an InAs / AlAs digital alloy structure multiplication layer with a layer thickness of more than 200 nm that has not been thinned, although it has the same superlattice structure as the InAs / AlAs digital alloy structure multiplication layer of this disclosure, the electric field is as low as 120 kV / cm.

[0429] <Effects of Implementation Method 8>

[0430] According to the SPAD sensor system of Embodiment 8, since the DA-APD of this disclosure is used in the SPAD sensor, the difference between the quenching electric field and the Geiger mode electric field, i.e. the applied voltage difference, can be reduced. Therefore, the SPAD sensor system that can achieve the effects of improving the response bandwidth, simplifying the quenching circuit, and saving power can be obtained.

[0431] Implementation method 9.

[0432] Figure 41 This diagram illustrates the configuration of the LiDAR (Light Detection and Ranging) device according to Embodiment 9. Figure 42A This is a schematic diagram illustrating the received waveform envisioned in the APD of a lidar device used as a comparative example. Figure 42B This is a schematic diagram showing the expected received waveform in the APD of the lidar device 700 according to Embodiment 9.

[0433] The lidar device 700 according to Embodiment 9 includes a light source 701, a DA-APD 702 and a TIA 703 of this disclosure, and a ranging circuit 704. The light source 701 emits pulsed light (hereinafter referred to as pulsed light) or light modulated by frequency.

[0434] In the lidar device 700 according to Embodiment 9, the distance to the object 705 is calculated by measuring the time until the pulsed light emitted from the light source illuminates the object 705 and returns to the semiconductor light-receiving element. The light source 701 can be an LD or the like. In order to measure distant objects, it is necessary to increase the light intensity of the LD, but from the viewpoint of eye safety, an upper limit is set on the light intensity emitted from the LD. Therefore, it is necessary to improve the receiving sensitivity of the semiconductor light-receiving element. In view of this, in the lidar device 700 according to Embodiment 9, the DA-APD 702 of this disclosure is used as the semiconductor light-receiving element with a high magnification rate.

[0435] The detected light pulse is multiplied by the DA-APD702 of this disclosure and converted into a current pulse. Then, it is amplified by the TIA703 and input to the ranging circuit 704, as shown below. Figure 42A and Figure 42B As shown in the schematic diagram, the arrival time is determined by the point at which the intensity of the pulse signal exceeds a preset recognition line. The timing of the light pulse emitted from the light source 701 is input to the ranging circuit 704 as a signal. By multiplying the time difference between the two by the speed of light and then dividing by 2, the distance to the object 705 can be calculated. Alternatively, the distance can also be calculated using frequency-modulated light and the frequency difference between the emitted wave and the returned reflected wave.

[0436] <Function and Effects of the LiDAR Device According to Embodiment 9>

[0437] Because the reflectivity of object 705 may not be high and the reflection direction is diverse, it is necessary to detect small amounts of light using an APD. In existing APDs, such as... Figure 42A As shown in the diagram, if the voltage is set and activated in a high-multiplication manner, the multiplication time becomes longer, and the width of the current pulse output from the APD becomes wider. Furthermore, the tunneling current increases, making it difficult to identify the optical pulse. In methods that calculate distance based on the frequency difference between the emitted and reflected waves, frequency identification also becomes difficult.

[0438] On the other hand, in the DA-APD of this disclosure used in the lidar device 700 according to Embodiment 9, high sensitivity can be obtained even when the receiving sensitivity of existing APDs is insufficient. As a result, not only can the distance of distant objects 705 be measured, but also power saving can be achieved by reducing the light output of the light source 701, and eye safety is also improved.

[0439] Furthermore, in the DA-APD505a disclosed herein, even with a high multiplication rate of 20x or higher, it is as follows: Figure 15 As described in the instructions, the tunneling current does not increase, making it easy to detect faint light. Additionally, as... Figure 33 As shown, due to the short residence time in the multiplication layer, therefore... Figure 42B As shown in the schematic diagram, a current pulse with a high peak intensity can be obtained, resulting in high recognition sensitivity. Consequently, it not only enables distance measurement of distant objects, but also saves power by reducing the light output of the light source, and improves eye safety.

[0440] <Effects of Implementation Method 9>

[0441] According to the above, the lidar device according to Embodiment 9, since it receives reflected light from an object through the DA-APD of this disclosure, it achieves the effect of obtaining a lidar device that can measure the distance of distant objects, saves power of the light source, and is safe for the eyes.

[0442] This disclosure describes a variety of exemplary embodiments and examples, but the various features, methods and functions described in one or more embodiments are not limited to the application of a specific embodiment, and can be applied to the embodiment alone or in various combinations.

[0443] Therefore, numerous variations not illustrated are conceivable within the scope of this disclosure. These include variations on at least one constituent element, additions, omissions, and extraction of at least one constituent element combined with constituent elements of other embodiments.

[0444] Explanation of reference numerals in the attached figures

[0445] 1…Fe-doped InP substrate, 2…n-type InP conductive layer, 3…n-type InAlAs conductive layer, 4…i-type InAlAs multiplication layer, 4a…i-type InAs / AlAs digital alloy structure multiplication layer, 5…p-type InAlAs electric field mitigation layer, 5a…p-type InP electric field mitigation layer, 6…i-type InGaAs light absorption layer, 6a…i-type InGaAs first light absorption layer, 6b…p-type InGaAs second light absorption layer, 7…i-type InAlGaAs graded layer, 7a…p-type InAlGaAs graded layer, 8…i-type InAlAs surface protective layer, 8a…i-type InAlAs graded layer, 9…p-type InP window layer, 9a…i-type InP window layer, 9b…i-type… InP first window layer, 9c…p-type InAlAs second window layer, 10…p-type InGaAs contact layer, 10a…i-type InGaAs contact layer, 11…surface protective film, 12…selective diffusion mask, 15…surface-side antireflective film, 16…backside antireflective film, 20, 20a…p-type impurity diffusion region, 30…first mesa structure, 31…second mesa structure, 32…third mesa structure, 33…mesa structure, 35…mesa trench, 40, 40a…step portion, 41, 41a…step surface, 42a…first step portion, 42b…second step portion, 45, 45a…hydrogen passivation region, 50, 50a…n-type electrode, 51, 51a…p-type electrode, 52…backside electrode, 60 …Light-receiving area, 66…Light-shielding metal film, 100, 110, 120, 130, 140, 150, 160, 170, 200…Semiconductor light-receiving element, 250a, 260, 260a, 260b, 270…Optical line termination device, 251, 261, 274…FEC, 252, 262, 273, 303…Driver amplifier, 253, 263, 272, 304, 401, 701…Light source, 254, 264, 271…WDM, 255, 265a, 301, 506…DSP, 256, 266a, 302b…ADC, 258…APD, 257, 267…Burst TIA, 265, 278…CDR, 266… 277… Limiting amplifier; 267a, 276, 703… TIA; 268, 275, 305, 403, 505a, 702… DA-APD; 300… Multi-level intensity modulation transceiver; 302a… DAC; 310, 501… Fiber optic cable; 306… Linear-TIA; 400, 450… Fiber optic wireless system; 402… Transmission path; 404… Antenna; 406… PD; 500… Digital coherent receiver; 501… Fiber optic cable; 502… Polarization separator; 503a, 503b… 90-degree mixer; 504… Semiconductor laser; 505… Balance detector; 600… SPAD sensor system; 601… Optoelectronic measurement circuit.602…SPAD sensor, 603…quenching circuit, 700…LiDAR device, 704…ranging circuit, 705…object.

Claims

1. A semiconductor light-receiving element, characterized in that, have: substrate; The first mesa structure has at least an n-type semiconductor layer, a multiplication layer, a p-type electric field mitigation layer, a light absorption layer, and an i-type semiconductor layer with a band gap larger than that of the light absorption layer, which are sequentially formed on the substrate. The second mezzanine structure is formed on the first mezzanine structure and has at least a window layer with a band gap larger than the light absorption layer. as well as The step portion is formed by the outermost surface of the first platform structure that is exposed on the outer periphery of the second platform structure.

2. The semiconductor light-receiving element according to claim 1, characterized in that, The aforementioned window layer consists of two layers, an i-type first window layer and a p-type second window layer, starting from the side that contacts the first tabletop structure.

3. A semiconductor light-receiving element, characterized in that, have: substrate; The first mesa structure has at least an n-type semiconductor layer, a multiplication layer and an electric field mitigation layer formed sequentially on the substrate. The second mezzanine structure is formed on the first mezzanine structure and has at least a light absorption layer and a window layer with a band gap larger than the light absorption layer. as well as The step portion is formed by the outermost surface of the first platform structure that is exposed on the outer periphery of the second platform structure.

4. The semiconductor light-receiving element according to claim 3, characterized in that, The light absorption layer consists of two layers, an i-type first light absorption layer and a p-type second light absorption layer, starting from the side that contacts the first mesa structure.

5. The semiconductor light-receiving element according to claim 3 or 4, characterized in that, The aforementioned electric field mitigation layer is composed of a p-type InAlAs layer.

6. The semiconductor light-receiving element according to claim 3 or 4, characterized in that, The aforementioned electric field mitigation layer is composed of a p-type InP layer.

7. A semiconductor light-receiving element, characterized in that, have: substrate; The first mesa structure has at least an n-type semiconductor layer, a multiplication layer and a p-type electric field mitigation layer formed sequentially on the substrate. The second mezzanine structure is formed on the first mezzanine structure and has at least a light-absorbing layer and an i-type surface protective layer. The first step portion is formed by the outermost surface of the first platform structure that is exposed on the outer periphery of the second platform structure. The third mezzanine structure is formed on the second mezzanine structure and has at least a window layer with a band gap larger than the light absorption layer. as well as The second step portion is formed by the outermost surface of the second platform structure that is exposed on the outer periphery of the third platform structure.

8. The semiconductor light-receiving element according to claim 7, characterized in that, The second mesa structure described above also has an i-type semiconductor layer with a larger band gap than the light absorption layer described above.

9. The semiconductor light-receiving element according to any one of claims 1, 3 to 8, characterized in that, It also has a p-type impurity diffusion region disposed in part of the above-mentioned window layer and the above-mentioned light absorption layer.

10. The semiconductor light-receiving element according to claim 9, characterized in that, The thickness of the aforementioned p-type impurity diffusion region within the aforementioned light-absorbing layer is between 0.1 μm and 0.3 μm.

11. The semiconductor light-receiving element according to claim 9 or 10, characterized in that, The p-type impurities contained in the aforementioned p-type impurity diffusion region are any one of zinc, cadmium, magnesium, and beryllium.

12. The semiconductor light-receiving element according to any one of claims 1, 3 to 7, characterized in that, The conductivity type of the aforementioned window layer is p-type.

13. The semiconductor light-receiving element according to any one of claims 1 to 12, characterized in that, The aforementioned multiplication layer is composed of a digital alloy structure.

14. The semiconductor light-receiving element according to claim 13, characterized in that, The aforementioned digital alloy structure is formed by alternating layers of InAs and AlAs.

15. The semiconductor light-receiving element according to any one of claims 1 to 6, characterized in that, It also has a surface protective film made of an insulating film, which covers at least the side surface of the first platform structure, the side surface of the second platform structure, and the surface of the step portion.

16. The semiconductor light-receiving element according to claim 15, characterized in that, A light-shielding metal film is provided on the surface of the surface protective film covering the aforementioned step portion and the surface protective film covering the side portion of the aforementioned first countertop structure.

17. The semiconductor light-receiving element according to any one of claims 1 to 6, characterized in that, A hydrogen passivation region is formed inside the semiconductor layer that is in contact with the lower side of the aforementioned step portion.

18. The semiconductor light-receiving element according to claim 17, characterized in that, The hydrogen concentration in the aforementioned hydrogen passivation region is 2 × 10⁻⁶. 17 cm －3 Above 1×10 18 cm －3 Within the following range.

19. A method for manufacturing a semiconductor light-receiving element, characterized in that, have: The process of epitaxially growing an n-type semiconductor layer, a multiplication layer, a p-type electric field mitigation layer, a light absorption layer, an i-type semiconductor layer with a band gap larger than the light absorption layer, a window layer with a band gap larger than the light absorption layer, and a p-type contact layer on a substrate in at least sequential order. A process of forming a film on the surface of the above-mentioned p-type contact layer using a selective diffusion mask consisting of an insulating film with an opening of approximately circular shape; The process of forming a p-type impurity diffusion region from the above-mentioned opening, with the bottom extending at least to the interior of the above-mentioned light absorption layer; Excluding the above-mentioned process of selecting a diffusion mask; The process of processing the above-mentioned p-type contact layer into a ring shape along the outer periphery of the light-receiving area; The process of forming a second mesa structure by etching the outer periphery of the aforementioned light-receiving area until at least the type I semiconductor layer is exposed on the surface; and The process of forming the first mezzanine structure by etching the portion other than the pre-defined area from the outer periphery of the second mezzanine structure.

20. The method for manufacturing a semiconductor light-receiving element according to claim 19, characterized in that, The aforementioned p-type impurity diffusion region is formed by gas-phase diffusion or solid-phase diffusion.

21. An optical line terminal device, characterized in that, have: The semiconductor light-receiving element according to any one of claims 1 to 20; A light-splitter allows the optical signal to be incident on the aforementioned semiconductor light-receiving element; An amplifier circuit amplifies the electrical signal output from the aforementioned semiconductor light-receiving element; A clock data recovery circuit, connected to the aforementioned amplifier circuit, recovers clock data from the amplified electrical signal. as well as The forward error correction circuit is connected to the aforementioned clock data recovery circuit to correct errors in the clock data.

22. An optical line terminal device, characterized in that, have: The semiconductor light-receiving element according to any one of claims 1 to 20; A light-splitter allows the optical signal to be incident on the aforementioned semiconductor light-receiving element; An amplifier circuit amplifies the electrical signal output from the aforementioned semiconductor light-receiving element; An analog-to-digital converter circuit, connected to the aforementioned amplifier circuit, converts the amplified electrical signal into a digital signal. A digital signal processing circuit, connected to the aforementioned analog-to-digital conversion circuit, processes the aforementioned digital signals; as well as A forward error correction circuit is connected to the aforementioned digital signal processing circuit to correct errors in the digital signal.

23. A multi-level intensity modulation transceiver, characterized in that, have: The semiconductor light-receiving element according to any one of claims 1 to 20 receives an optical signal modulated by multiple levels of intensity; An amplifier circuit amplifies the electrical signal output from the aforementioned semiconductor light-receiving element; An analog-to-digital converter circuit, connected to the aforementioned amplifier circuit, converts the amplified electrical signal into a digital signal; and A digital signal processing circuit, connected to the aforementioned analog-to-digital conversion circuit, processes the aforementioned digital signal.

24. A fiber optic wireless system, characterized in that, have: The light source emits a simulated modulated light signal; The semiconductor light-receiving element according to any one of claims 1 to 20 receives the above-mentioned optical signal after being simulated and modulated; The transmission path will transmit the analog electrical signal output from the aforementioned semiconductor light-receiving element to the antenna; as well as The antenna is connected to the aforementioned transmission path and radiates the aforementioned analog electrical signal as a radio wave signal.

25. A digital coherent receiving device, characterized in that, have: The semiconductor light-receiving element according to any one of claims 1 to 20; A polarization separator separates the polarization of a polarization-multiplexed optical signal that has been modulated in intensity and phase. A 90-degree mixer performs wavelength division and synthesis on the optical signal output from the aforementioned polarization separator; and The digital signal processing circuit is connected to the aforementioned 90-degree mixer to process the digital signals.

26. A SPAD sensor system, characterized in that, have: The SPAD sensor is composed of a semiconductor light-receiving element as described in any one of claims 1 to 20; The quenching circuit repeatedly applies voltages above and below the breakdown voltage to the aforementioned SPAD sensor; as well as The optoelectronic measurement circuit measures the electrical signal output from the aforementioned SPAD sensor.

27. A lidar device, characterized in that, have: A light source that emits pulsed light or light modulated by frequency; The semiconductor light-receiving element according to any one of claims 1 to 20 receives light emitted from the light source and reflected back by an object; An amplifier circuit amplifies the electrical signal output from the aforementioned semiconductor light-receiving element; as well as The ranging circuit calculates the distance based on the electrical signal amplified by the aforementioned amplifier circuit.

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