encapsulation

Abstract

The present technology improves heat dissipation on the back surface side of a chip while reducing interconnection constraints on the back surface side of the chip. The package includes a chip whose front surface is formed with external terminals for signal transmission, a substrate on which the chip is mounted through the back surface of the chip, a plurality of thermally conductive layers arranged in mutually different layers of the substrate and having higher thermal conductivity than the substrate, and a via interconnecting the plurality of thermally conductive layers. The external terminals include first bonding pads, the substrate includes second bonding pads arranged around the chip, and the first bonding pads and the second bonding pads can be connected to each other by bonding wires.

Description

Technical Field

[0001] This technology relates to packaging. More specifically, this technology relates to packaging capable of dissipating heat from the back side of a substrate on which a chip is mounted. Background Technology

[0002] To improve heat dissipation from the back side of the chip, there is a technique for providing heat dissipation components on the back side of the chip. For example, there is a technique in which a bonding component is formed in the region overlapping with the MOSFET region, which is used solely for heat dissipation and not for transmitting electrical signals (see, for example, Patent Document 1).

[0003] Citation List

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2007-53148 Summary of the Invention

[0006] The problem to be solved by the present invention

[0007] However, in the aforementioned conventional technology, the bonding member that does not form an electrical signal path is separately disposed from the bonding member used to connect the electrical signal path from the active region to the interconnect substrate via a signal line. Therefore, the heat dissipation path from the back side of the chip may be limited by the bonding member connecting the electrical signal path.

[0008] In view of this situation, this technology was developed, and therefore the purpose of this technology is to improve heat dissipation on the back side of the chip while reducing interconnect constraints on the back side of the chip.

[0009] Solution to the problem

[0010] This technology was developed to address the aforementioned problems, and a first aspect of this technology is a package comprising: a chip having external terminals for signal transmission formed on the front side of the chip; a substrate on which the chip is mounted via a back side; a plurality of thermally conductive layers disposed in mutually different layers of the substrate and having a higher thermal conductivity than the substrate; and vias interconnecting the plurality of thermally conductive layers. This allows the thermally conductive layers to be disposed on the back side of the chip while reducing constraints on the placement of the external terminals on the chip.

[0011] Furthermore, in the first aspect, vias can be arranged at locations overlapping with the chip. This allows interconnects to be formed in the substrate while improving heat dissipation from the chip's mounting surface to the back of the substrate.

[0012] Furthermore, in the first aspect, vias can be arranged at equal intervals across the entire back side of the chip. This allows for the formation of interconnects in the substrate while improving heat dissipation across the entire back side of the chip.

[0013] Furthermore, in the first aspect, vias can be arranged according to the heat distribution of the chip. This allows interconnects to be formed in the substrate while improving heat dissipation from high-temperature areas.

[0014] In addition, in the first aspect, the external terminal may include a first bonding pad, the substrate may include a second bonding pad arranged around the chip, and the first and second bonding pads may be connected to each other via bonding wires. This provides the effect of allowing the chip to be electrically connected to the outside via the substrate while allowing heat dissipation from the entire back side of the chip.

[0015] Furthermore, in the first aspect, the plurality of thermally conductive layers may include an upper thermally conductive layer and a lower thermally conductive layer, and the upper thermally conductive layer and the bonding pads may be disposed in a common layer of the substrate. This allows bonding wires to be connected to the bonding pads while reducing the thermal resistance between the upper thermally conductive layer and the chip.

[0016] Furthermore, in the first aspect, it may further include solder pad electrodes formed on the back side of the substrate, and a lower thermally conductive layer may be disposed above the layer forming the solder pad electrodes. This results in a reduction of the thermal resistance on the back side of the substrate.

[0017] Furthermore, in the first aspect, the plurality of thermally conductive layers can be formed in a location that completely overlaps with the back surface of the chip. This results in a reduction of the thermal resistance between the upper thermally conductive layer and the chip across the entire back surface.

[0018] Additionally, in the first aspect, the upper thermal conductive layer may extend beyond the back side of the chip to surround the second bonding pad. This results in an extended heat dissipation path from the back side of the chip to the outside of the chip.

[0019] Furthermore, in the first aspect, a terminal may be further included, disposed on the side of the substrate and having a higher thermal conductivity than the substrate, and a thermally conductive layer may be connected to the terminal. This allows heat generated by the chip to dissipate not only from the back side of the substrate but also from the side side of the substrate.

[0020] Additionally, in the first aspect, a housing may be further included, which is joined to the terminal via a bonding member. This allows heat generated by the chip to dissipate from the housing via the sides of the substrate.

[0021] Additionally, in the first aspect, the chip may include a light-receiving portion configured to receive light, and may further include a lens supported above the light-receiving portion via a housing. This provides the effect of allowing heat generated by the chip to dissipate from the housing via the sides of the substrate while simultaneously allowing the lens to be supported above the light-receiving portion via the housing.

[0022] Furthermore, in the first aspect, a sealant may be included to seal the chip and bonding wires on the substrate. This provides protection for the chip and bonding wires while improving heat dissipation from the back side of the substrate.

[0023] Furthermore, in the first aspect, it may further include a transparent substrate disposed above the chip and ribs supporting the transparent substrate above the chip. This provides the effect of protecting the chip and bonding wires while allowing optical operation of the chip.

[0024] Furthermore, in the first aspect, a heat sink may be further included, which is bonded to the back side of the substrate. This results in improved heat dissipation from the back side of the substrate. Attached Figure Description

[0025] Figure 1 This is a diagram illustrating an example configuration of the package according to the first embodiment.

[0026] Figure 2 This is a plan view illustrating another configuration example of the package according to the first embodiment.

[0027] Figure 3 This is a plan view illustrating yet another configuration example of the package according to the first embodiment.

[0028] Figure 4 This is a cross-sectional view showing an example configuration of the package according to the second embodiment.

[0029] Figure 5 This is a cross-sectional view showing an example configuration of the package according to the third embodiment.

[0030] Figure 6 This is a cross-sectional view showing an example configuration of the package according to the fourth embodiment.

[0031] Figure 7 This is a cross-sectional view showing an example configuration of the package according to the fifth embodiment.

[0032] Figure 8 This is a cross-sectional view showing an example configuration of the package according to the sixth embodiment.

[0033] Figure 9 This is a block diagram illustrating a schematic configuration example of a vehicle control system.

[0034] Figure 10This is an illustrative diagram showing an example of the mounting location of the imaging section. Detailed Implementation

[0035] The following describes the methods used to implement this technology (hereinafter referred to as embodiments). The descriptions will be given in the following order.

[0036] 1. A first embodiment (in which a plurality of thermally conductive layers having a higher thermal conductivity than the substrate are disposed on a ball grid array (BGA) on which a sensor chip is mounted, the plurality of thermally conductive layers being interconnected through vias, and bonding lines being arranged inside a rib supporting the transparent substrate above a light-receiving element)

[0037] 2. Second embodiment (in which a plurality of thermally conductive layers having a higher thermal conductivity than the substrate are disposed on the BGA on which the sensor chip is mounted, the plurality of thermally conductive layers being interconnected through vias, and bonding lines being covered by ribs supporting a transparent substrate above the light-receiving element)

[0038] 3. A third embodiment (in which a plurality of thermally conductive layers having a higher thermal conductivity than the substrate are disposed on a ceramic substrate on which the sensor chip is mounted, and the plurality of thermally conductive layers are interconnected through vias)

[0039] 4. Fourth embodiment (an example in which a plurality of thermally conductive layers having a higher thermal conductivity than the substrate are disposed on a BGA on which a semiconductor chip is mounted, the plurality of thermally conductive layers being interconnected through vias, and the semiconductor chip and bonding wires being covered with a sealant)

[0040] 5. Fifth embodiment (an example of a BGA on which a sensor chip is mounted having multiple thermally conductive layers with a thermal conductivity higher than that of the substrate, the multiple thermally conductive layers being interconnected via vias, and a heat sink being attached to the back side of the package substrate)

[0041] 6. Sixth embodiment (an example in which a BGA on which a sensor chip is mounted has multiple thermally conductive layers with a thermal conductivity higher than that of the substrate, the multiple thermally conductive layers are interconnected via through-holes, and thermally conductive terminals disposed on the side of the substrate are connected to a housing supporting a lens)

[0042] 7. Examples of application to moving bodies

[0043] <1. First Embodiment>

[0044] Figure 1This is a diagram illustrating an example configuration of the package according to the first embodiment. Note that a in the figure is a cross-sectional view of an example configuration of the package 100A taken along a vertical direction, and b in the figure is a plan view illustrating an example configuration of the package 100A. In the figure, a shows a cross-section taken along line A1-A2 in figure b. In the figure, b shows an example of the planar pattern of the upper thermally conductive layer 106A. It should be noted that in the figures used below, for ease of understanding of each configuration, scale, shape, etc., may differ from the actual structure.

[0045] In the figure, package 100A includes package substrate 101A, chip 111, and transparent substrate 122. In this configuration, package 100A can form a hollow package in which chip 111 is mounted.

[0046] Multilayer substrates can be used as the packaging substrate 101A. BGAs can be used as the packaging substrate 101A. For example, a pin grid array (PGA) or a pad grid array (LGA) can be used as the packaging substrate 101A. Chip 111 is mounted on the packaging substrate 101A. In this configuration, the packaging substrate 101A can dissipate heat generated by chip 111. To improve heat dissipation from chip 111, the packaging substrate 101A includes multiple thermally conductive layers with a thermal conductivity higher than that of the substrate of the packaging substrate 101A. These thermally conductive layers are arranged in different layers and connected via vias. The substrate of the packaging substrate 101A can be, for example, ceramic or resin. Interconnects 102A, bonding pads 105A, and land electrodes 109 are formed in the packaging substrate 101A. Interconnects 102A can be used as signal lines, power lines, or ground lines. Bonding pads 105A are arranged on the front side of the packaging substrate 101A. In this configuration, bonding pads 105A can be arranged along the four sides of chip 111. Solder electrodes 109 are arranged on the back side of package substrate 101A. Furthermore, through-holes 103A are formed in package substrate 101A to interconnect the layers of package substrate 101A. In this configuration, through-holes 103A allow interconnects 102A, bonding pads 105A, and solder electrodes 109 to interconnect.

[0047] Furthermore, the packaging substrate 101A includes an upper thermally conductive layer 106A and a lower thermally conductive layer 107 as thermally conductive layers. The upper thermally conductive layer 106A and the bonding pads 105A are disposed in a common layer of the packaging substrate 101A. In this configuration, the upper thermally conductive layer 106A and the bonding pads 105A can be disposed in the uppermost layer of the packaging substrate 101A. A protective film can be formed on the front side of the packaging substrate 101A. In this configuration, the protective film on the upper thermally conductive layer 106A and the bonding pads 105A can be removed to expose the upper thermally conductive layer 106A and the bonding pads 105A on the front side. The lower thermally conductive layer 107 can be disposed above the layer where the solder pads 109 are located. It should be noted that the lower thermally conductive layer 107 and the solder pads 109 can be disposed in a common layer of the packaging substrate 101A. In this configuration, the lower thermal conductive layer 107 and the solder electrode 109 can be arranged in the bottom layer of the packaging substrate 101A.

[0048] The upper thermal conductive layer 106A and the lower thermal conductive layer 107 can be formed at a location that completely overlaps with the back surface of the chip 111. The upper thermal conductive layer 106A extends outward beyond the back surface of the chip 111 to surround the bonding pad 105A. The lower thermal conductive layer 107 extends outward beyond the back surface of the chip 111. In this configuration, the upper thermal conductive layer 106A and the lower thermal conductive layer 107 can reach all four sides of the outer periphery of the package substrate 101A. Here, the upper thermal conductive layer 106A and the lower thermal conductive layer 107 can be used only for heat dissipation and not for signal lines or power lines. Therefore, the upper thermal conductive layer 106A and the lower thermal conductive layer 107 can be continuously formed on the entire surface of the package substrate 101A. Here, in the upper thermal conductive layer 106A, an opening KA1 can be formed around the bonding pad 105A to separate the bonding pad 105A from the upper thermal conductive layer 106A within a common layer. In the lower thermal conductive layer 107, an opening KA2 can be formed around the via 103A to separate the via 103A from the lower thermal conductive layer 107. The upper thermal conductive layer 106A and the lower thermal conductive layer 107 are interconnected via heat dissipation vias 108A. In this configuration, the heat dissipation vias 108A can penetrate the package substrate 101A between the upper thermal conductive layer 106A and the lower thermal conductive layer 107. The heat dissipation vias 108A can be arranged at equal intervals on the back side of the entire chip 111.

[0049] Thermally conductive terminals 104 are formed on the side of the packaging substrate 101A. The thermally conductive terminals 104 can be arranged at equal intervals along the four sides of the outer periphery of the packaging substrate 101A. The thermally conductive terminals 104 can be connected to the upper thermally conductive layer 106A and the lower thermally conductive layer 107.

[0050] The interconnect 102A, through-hole 103A, bonding pad 105A, solder pad electrode 109, upper thermally conductive layer 106A, lower thermally conductive layer 107, heat dissipation through-hole 108A, and thermally conductive terminal 104 may be made of the same material. The interconnect 102A, through-hole 103A, bonding pad 105A, solder pad electrode 109, upper thermally conductive layer 106A, lower thermally conductive layer 107, heat dissipation through-hole 108A, and thermally conductive terminal 104 may be made of metals such as Cu. Platings of Ni, Au, etc., may be formed on the bonding pad 105A and solder pad electrode 109.

[0051] Chip 111 is mounted face-up on package substrate 101A. Chip 111 can be bonded to upper thermal conductive layer 106A via solder material or via a paste material such as Ag paste. Chip 111 and upper thermal conductive layer 106A can be directly bonded. In this configuration, a Cu film can be formed on the entire back surface of chip 111, upper thermal conductive layer 106A can include Cu, and chip 111 and upper thermal conductive layer 106A can be directly bonded based on Cu-Cu bonding.

[0052] Chip 111 is connected to package substrate 101A via bonding wire 116. In this configuration, bonding pads 113 connected to bonding wire 116 can be formed on chip 111. Here, connecting chip 111 to package substrate 101A via bonding wire 116 eliminates the need to form bump electrodes on chip 111. As the material of bonding wire 116, metals such as Au or Al can be used.

[0053] Semiconductor elements, optical elements, or microelectromechanical systems (MEMS) can be formed in chip 111. The substrate used for chip 111 can be a semiconductor substrate, a dielectric substrate, or an organic substrate.

[0054] The light-receiving element can be an image sensor such as a charge-coupled device (CCD) sensor, a complementary metal-oxide-semiconductor (CMOS) sensor, or a single-photon avalanche diode (SPAD) sensor. The light received by the image sensor can be visible light, near-infrared light (NIR), short-wavelength infrared light (SWIR), ultraviolet light, X-rays, etc. The optical element can be a light-receiving element such as a photodiode (PD) or a light-emitting element such as a laser diode (LD), a light-emitting diode (LED), or a vertical-cavity surface-emitting laser (VCSEL). The optical element can be an optical switch, a digital micromirror device (DMD), etc. The optical element can be a display element such as a liquid crystal element or an organic electroluminescent (EL) element. The materials used for the optical element can be semiconductors such as Si, GaAs, or InGaAs, or dielectrics such as LiNbO3, glass, or transparent resin.

[0055] Semiconductor components can include integrated circuits (ICs), transistors, resistors, capacitors, etc. They can form memory, processors, signal processing circuits, data processing circuits, or interface circuits. For example, they can form hardware circuits such as field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs). Materials used for semiconductor components can be Si, GaAs, SiC, GaN, InGaAs, InP, InGaAsP, etc.

[0056] For example, a CMOS image sensor can be formed in chip 111. In this configuration, chip 111 is provided with a light-receiving portion 112. In the light-receiving portion 112, pixels and pixel transistors are arranged in a matrix along the row and column directions. In each pixel, a photodiode can be formed. For each pixel, a color filter 114 is formed on the light-receiving portion 112. For each pixel, an on-chip lens 115 is formed on the color filter 114. As materials for the color filter 114 and the on-chip lens 115, for example, insulating films such as SiO2, SiN, or SiCN, or transparent resins such as acrylic or polycarbonate can be used. The color filter 114 may contain pigment. For example, the color filter 114 may be formed as a Bayer array or a quad-Bayer array. The color filter 114 may include an RGB color filter, a complementary color filter, or a white color filter. Lenses, dichroists, or deflectors configured to have a metasurface can be formed on the light receiving portion 112.

[0057] A transparent substrate 122 is disposed on the chip 111. In this configuration, the transparent substrate 122 is supported on and bonded to the packaging substrate 101A via ribs 121. The transparent substrate 122 may be a glass substrate, a quartz substrate, or a transparent resin substrate such as acrylic or polycarbonate. The transparent substrate 122 may contain Al2O3, CaF2, MgF2, LiF, etc., depending on the wavelength of the light received by the chip 111.

[0058] Rib 121 is located between chip 111 and transparent substrate 122. In this configuration, rib 121 can support transparent substrate 122 on top of chip 111. Rib 121 can be continuously arranged along the outer periphery of packaging substrate 101A. In this configuration, rib 121 can be arranged outside bonding pad 105A. The material of rib 121 can be thermosetting resin or UV-curable resin. For example, resins such as siloxane resin, acrylic resin, or epoxy resin can be used as the material of rib 121. To improve reliability, rib 121 can contain fillers including inorganic or organic materials. The filler material can be glass. To reduce flares on light-receiving portion 112, rib 121 can be blackened or may include an opaque layer. For example, rib 121 can contain black pigments such as carbon black, or it can contain fillers such as carbon fibers.

[0059] Here, heat generated by chip 111 is conducted from the back side of chip 111 to the upper thermal conductive layer 106A. The heat conducted to the upper thermal conductive layer 106A is then conducted through the heat dissipation via 108A to the lower thermal conductive layer 107, and dissipates from the back side of the packaging substrate 101A. Additionally, heat conducted to the upper thermal conductive layer 106A and the lower thermal conductive layer 107 is conducted to the thermal conductive terminal 104, and dissipates from the side side of the packaging substrate 101A. This configuration allows heat generated by chip 111 to be conducted to the upper thermal conductive layer 106A across the entire back side of chip 111, thereby improving the dissipation of heat generated by chip 111.

[0060] Figure 2 This is a plan view illustrating another configuration example of the package according to the first embodiment. Note that the drawing shows an example of the planar pattern of the upper thermally conductive layer 106B.

[0061] In the accompanying drawings, package 100B includes package substrate 101B, replacing the package substrate 101A described above. Other components of package 100B are similar to those of package 100A described above.

[0062] The packaging substrate 101B includes interconnects 102B, through-holes 103B, bonding pads 105B, and an upper thermally conductive layer 106B, replacing the interconnects 102A, through-holes 103A, bonding pads 105A, and upper thermally conductive layer 106A described above. Other components of the packaging substrate 101B are similar to those of the packaging substrate 101A described above.

[0063] Bonding pads 105B are arranged along two opposite sides of the outer periphery of the package substrate 101B. In this configuration, bonding pads 113 of the chip 111 can also be arranged along two opposite sides of the outer periphery of the chip 111. Bonding pads 105B are connected to vias 103B via interconnects 102B.

[0064] The upper thermal conductive layer 106B can be formed on the back side of the entire overlaid chip 111. Furthermore, the upper thermal conductive layer 106B extends outward beyond the back side of the chip 111 to surround the bonding pad 105B. Here, an opening KB1 can be formed around the bonding pad 105B in the upper thermal conductive layer 106B to separate the bonding pad 105B from the upper thermal conductive layer 106A within a common layer.

[0065] Figure 3 This is a plan view illustrating yet another configuration example of the package according to the first embodiment. Note that the drawing shows an example of the planar pattern of the upper thermally conductive layer 106C.

[0066] In the accompanying drawings, package 100C includes package substrate 101C, replacing the package substrate 101A described above. Other components of package 100C are similar to those of package 100A described above.

[0067] The packaging substrate 101C includes a heat dissipation via 108C, replacing the heat dissipation via 108A. Other components of the packaging substrate 101C are similar to those of the packaging substrate 101A described above.

[0068] A heat dissipation via 108C interconnects the upper thermally conductive layer 106A and the lower thermally conductive layer 107. The heat dissipation via 108C can be arranged according to the heat distribution of the chip 111. In this configuration, the arrangement density of the heat dissipation via 108C can be higher in the portions of the chip 111 with higher heat generation than in the portions with lower heat generation. Note that the diameter of the heat dissipation via 108C can vary according to the heat distribution of the chip 111. In this configuration, the diameter of the heat dissipation via 108C can be larger in the portions of the chip 111 with higher heat generation than in the portions with lower heat generation.

[0069] As described above, in the first embodiment, an upper thermally conductive layer 106A and a lower thermally conductive layer 107, having a higher thermal conductivity than the packaging substrate 101A, are provided and interconnected via a heat dissipation via 108C. Therefore, the heat generated by the chip 111 can be dissipated to the packaging substrate 101A through the entire back side of the chip 111, thereby improving the heat dissipation of the chip 111.

[0070] <2. Second Embodiment>

[0071] In the first embodiment described above, an upper thermally conductive layer 106A and a lower thermally conductive layer 107, both having higher thermal conductivity than the package substrate 101A, are provided and interconnected via heat dissipation vias 108A, and ribs 121 are arranged on the outer side of the bonding pads 105A. In the second embodiment, an upper thermally conductive layer and a lower thermally conductive layer, both having higher thermal conductivity than the package substrate, are provided and interconnected via heat dissipation vias, and ribs are arranged at locations covering the bonding pads.

[0072] Figure 4 This is a cross-sectional view showing an example configuration of the package according to the second embodiment.

[0073] In the accompanying drawings, package 200 includes a package substrate 201, a chip 211, a transparent substrate 222, and a sealant 224. In this configuration, package 200 can form a hollow package on which the chip 211 is mounted.

[0074] A multilayer substrate can be used as the packaging substrate 201. A chip 211 is mounted on the packaging substrate 201. Interconnects 202, bonding pads 205, and land electrodes 209 are formed in the packaging substrate 201. The interconnects 202 can serve as signal lines, power lines, or ground lines. The bonding pads 205 are arranged on the front side of the packaging substrate 201. The land electrodes 209 are arranged on the back side of the packaging substrate 201. Furthermore, vias 203 are formed in the packaging substrate 201 to interconnect the layers of the packaging substrate 201. In this configuration, the vias 203 can interconnect the interconnects 202, bonding pads 205, and land electrodes 209.

[0075] Furthermore, the packaging substrate 201 includes an upper thermally conductive layer 206 and a lower thermally conductive layer 207 as thermally conductive layers. The upper thermally conductive layer 206 and the bonding pads 205 are disposed in a common layer of the packaging substrate 201. In this configuration, the upper thermally conductive layer 206 and the bonding pads 205 may be disposed in the top layer of the packaging substrate 201. The lower thermally conductive layer 207 may be disposed above the layer containing the solder pads 209. Note that the lower thermally conductive layer 207 and the solder pads 209 may be disposed in a common layer of the packaging substrate 201. In this configuration, the lower thermally conductive layer 207 and the solder pads 209 may be disposed in the bottom layer of the packaging substrate 201.

[0076] An upper thermal conductive layer 206 and a lower thermal conductive layer 207 can be formed at a location where they overlap the entire back surface of the chip 211. The upper thermal conductive layer 206 extends beyond the back surface of the chip 211 to surround the bonding pad 205. The lower thermal conductive layer 207 extends beyond the back surface of the chip 211. Here, in the upper thermal conductive layer 206, an opening KD1 can be formed around the bonding pad 205 to separate the bonding pad 205 from the upper thermal conductive layer 206 within a common layer. In the lower thermal conductive layer 207, an opening KD2 can be formed around the via 203 to separate the via 203 from the lower thermal conductive layer 207. The upper thermal conductive layer 206 and the lower thermal conductive layer 207 are interconnected via a heat dissipation via 208.

[0077] Thermally conductive terminals 204 are formed on the side of the packaging substrate 201. The thermally conductive terminals 204 can be arranged at equal intervals along the four sides of the outer periphery of the packaging substrate 201. The thermally conductive terminals 204 can be connected to the upper thermally conductive layer 206 and the lower thermally conductive layer 207.

[0078] Chip 211 is mounted face up on the packaging substrate 201. Chip 211 can be bonded to the upper thermal conductive layer 206 by solder material or by a paste material such as Ag paste, or chip 211 and the upper thermal conductive layer 206 can be directly bonded.

[0079] Chip 211 is connected to package substrate 201 via bonding wire 216. In this configuration, bonding pads 213 connected to bonding wire 216 can be formed on chip 211.

[0080] For example, a CMOS image sensor can be formed in chip 211. In this configuration, chip 211 is provided with a light receiving section 212. In the light receiving section 212, pixels and pixel transistors are arranged in a matrix along the row and column directions. For each pixel, a color filter 214 is formed on the light receiving section 212. For each pixel, an on-chip lens 215 is formed on the color filter 214.

[0081] A transparent substrate 222 is disposed on the chip 211. In this configuration, the transparent substrate 222 is supported on and bonded to the packaging substrate 201 via ribs 221.

[0082] Rib 221 is located between chip 211 and transparent substrate 222. In this configuration, rib 221 can support transparent substrate 222 on top of chip 211. Rib 221 can be continuously arranged along the outer periphery of packaging substrate 201.

[0083] The chip 211 and bonding wires 216 on the packaging substrate 201 are sealed with a sealant 224. The sealant 224 is formed on the exterior of the chip 211 and ribs 221 on the packaging substrate 201. In this configuration, the sealant 224 can be continuously arranged to surround the chip 211 and ribs 221. The sealant 224 can be positioned at the rear end of the bonding wire 216. The sealant 224 can contact the side of the transparent substrate 222. The material of the sealant 224 can be a thermosetting resin or a UV-curable resin. For example, resins such as siloxane resins, acrylic resins, or epoxy resins can be used as the material of the sealant 224. To improve reliability, the sealant 224 can contain fillers including inorganic or organic materials. The filler material can be glass. To reduce flares and the like on the light-receiving portion 212, the sealant 224 can be blackened or may include an opaque layer. For example, the sealant 224 can contain a black pigment such as carbon black, or it can contain fillers such as carbon fibers. The material of sealant 224 can be the same as or different from the material of rib 221. In this configuration, the material of sealant 224 can be selected to reduce warping of the encapsulation substrate 201 or to reduce stress applied to the transparent substrate 222.

[0084] As described above, in the second embodiment, an upper thermally conductive layer 206 and a lower thermally conductive layer 207, having a higher thermal conductivity than the packaging substrate 201, are provided and interconnected via heat dissipation vias 208, and ribs 224 are arranged at locations covering the bonding pads 213. This configuration eliminates the need to form a space between the bonding pads 213 and the ribs 224 on the chip 211, thereby enabling a reduction in chip size and improved heat dissipation from the chip 211 without reducing the light-receiving area.

[0085] <3. Third Embodiment>

[0086] In the first embodiment described above, an upper thermally conductive layer 106A and a lower thermally conductive layer 107, having higher thermal conductivity than the BGA package substrate 101A, are provided and interconnected via a heat dissipation via 108A. In the third embodiment, an upper thermally conductive layer and a lower thermally conductive layer, having higher thermal conductivity than the cavity-containing ceramic package substrate, are provided and interconnected via a heat dissipation via.

[0087] Figure 5 This is a cross-sectional view showing an example configuration of the package according to the third embodiment.

[0088] In the accompanying drawings, package 300 includes a package substrate 301 and a transparent substrate 322, instead of the package substrate 101A and transparent substrate 122 of the first embodiment described above. Other components of the package 300 of the third embodiment are similar to those of the package 100A of the first embodiment described above.

[0089] In the accompanying drawings, a ceramic substrate can be used as the packaging substrate 301. The packaging substrate 301 is provided with a cavity CAV capable of accommodating the chip 111. The cavity CAV may be provided with steps. In this configuration, the chip 111 is mounted on the lowest level of the cavity CAV. Interconnects 302, bonding pads 305, and solder pads 309 are formed in the packaging substrate 301. The interconnects 302 can be used as signal lines, power lines, or ground lines. The bonding pads 305 can be arranged on the second level of the cavity CAV. The solder pads 309 are arranged on the back side of the packaging substrate 301. In addition, through-holes 303 are formed in the packaging substrate 301 to interconnect the layers of the packaging substrate 301. In this configuration, the through-holes 303 can interconnect the interconnects 302, bonding pads 305, and solder pads 309.

[0090] Furthermore, the packaging substrate 301 includes an upper thermally conductive layer 306 and a lower thermally conductive layer 307 as thermally conductive layers. The upper thermally conductive layer 306 is disposed on the lowest level of the cavity CAV. The lower thermally conductive layer 307 may be disposed above the layer in which the solder pad electrodes 309 are disposed. Note that the lower thermally conductive layer 307 and the solder pad electrodes 309 may be disposed in a common layer of the packaging substrate 301. In this configuration, the lower thermally conductive layer 307 and the solder pad electrodes 309 may be disposed in the lowest layer of the packaging substrate 301.

[0091] The upper thermal conductive layer 306 and the lower thermal conductive layer 307 can be formed at a location that completely overlaps with the back surface of the chip 111. Furthermore, the upper thermal conductive layer 306 and the lower thermal conductive layer 307 extend beyond the back surface of the chip 311. Here, in the upper thermal conductive layer 306, an opening KE1 can be formed around a via 303 to separate the via 303 from the upper thermal conductive layer 306. In the lower thermal conductive layer 307, an opening KE2 can be formed around a via 303 to separate the via 303 from the lower thermal conductive layer 307. The upper thermal conductive layer 306 and the lower thermal conductive layer 307 are interconnected via a heat dissipation via 308.

[0092] Thermally conductive terminals 304 are formed on the side of the packaging substrate 301. The thermally conductive terminals 304 can be arranged at equal intervals along the four sides of the outer periphery of the packaging substrate 301. The thermally conductive terminals 304 can be connected to the upper thermally conductive layer 306 and the lower thermally conductive layer 307.

[0093] A transparent substrate 322 is disposed above the chip 111. In this configuration, the transparent substrate 322 can be bonded to the uppermost layer of the encapsulation substrate 301 via an adhesive layer 321. The adhesive layer 321 can be, for example, an epoxy resin.

[0094] As described above, in the third embodiment, an upper thermally conductive layer 306 and a lower thermally conductive layer 307 are provided, having a higher thermal conductivity than the ceramic package substrate 301 with a cavity CAV, and are interconnected via a heat dissipation via 308. Therefore, the heat dissipation generated by the chip 311 can be improved while enhancing the hermeticity of the package 300.

[0095] <4. Fourth Embodiment>

[0096] In the first embodiment described above, an upper thermally conductive layer 106A and a lower thermally conductive layer 107, both having higher thermal conductivity than the packaging substrate 101A, are interconnected via a heat dissipation via 108A, and a transparent substrate 122 is disposed above the chip 111. In this fourth embodiment, an upper thermally conductive layer 106A and a lower thermally conductive layer 107, both having higher thermal conductivity than the packaging substrate 101A, are interconnected via a heat dissipation via 108A, and the chip is encapsulated with an encapsulant.

[0097] Figure 6 This is a cross-sectional view showing an example configuration of the package according to the fourth embodiment.

[0098] In the accompanying drawings, package 400 includes a chip 411 and a sealant 421, replacing the chip 111, rib 121, and transparent substrate 122 in the first embodiment described above. Other components of package 400 in the fourth embodiment are similar to those in package 100A of the first embodiment described above.

[0099] Chip 411 is mounted on package substrate 101A with its front surface facing upwards. Chip 411 can be bonded to the upper thermal conductive layer 106A using solder material, or using a paste-like material such as Ag paste. Chip 411 and the upper thermal conductive layer 106A can be directly bonded.

[0100] Chip 411 is connected to package substrate 101A via bonding wire 116. In this configuration, bonding pad 413 (on which bonding wire 116 is connected) can be formed on chip 411.

[0101] A circuit portion 412 is formed on the chip 411. Semiconductor elements can be formed in the circuit portion 412. Semiconductor elements may include integrated circuits (ICs), transistors, resistors, capacitors, etc. Among the semiconductor elements, memory, processors, signal processing circuits, data processing circuits, interface circuits, or power semiconductor elements such as inverters can be formed. The semiconductor substrate used for the chip 411 may include Si, GaAs, SiC, GaN, InGaAs, InP, InGaAsP, etc.

[0102] The chip 411 and bonding wire 116 on the packaging substrate 101A are encapsulated by a sealant 421. In this configuration, the chip 411 and bonding wire 116 on the packaging substrate 101A can be covered by the sealant 421. The surface of the sealant 421 can be planarized. The material of the sealant 421 can be a thermosetting resin or a UV-curable resin. For example, resins such as siloxane resins, acrylic resins, or epoxy resins can be used as the material of the sealant 421. The sealant 421 can be formed by molding or potting.

[0103] A protruding electrode 110 is formed on the solder pad electrode 109. The protruding electrode 110 can be used as an external connection terminal for connecting the package 400 to the mother substrate, etc. The protruding electrode 110 can be, for example, a solder ball or a conductive pillar electrode. In this configuration, the package 400 can be mounted on the mother substrate via the protruding electrode 110 by, for example, reflow soldering.

[0104] As described above, in the fourth embodiment, an upper thermally conductive layer 106A and a lower thermally conductive layer 107, having a higher thermal conductivity than the packaging substrate 101A, are provided and interconnected via a heat dissipation via 108A, and the chip 411 is encapsulated by a sealant 421. Therefore, the chip 411 can be encapsulated in the sealant 421 without eliminating the need for a cavity above the chip 411, thereby simplifying the manufacturing process while improving the dissipation of heat generated by the chip 411.

[0105] <5. Fifth Embodiment>

[0106] In the first embodiment described above, an upper thermally conductive layer 106A and a lower thermally conductive layer 107, both having higher thermal conductivity than the packaging substrate 101A, are provided and interconnected via a heat dissipation via 108A. In this fifth embodiment, an upper thermally conductive layer 106A and a lower thermally conductive layer 107, both having higher thermal conductivity than the packaging substrate 101A, are provided and interconnected via a heat dissipation via 108A, and a heat sink is attached to the back side of the packaging substrate 101A.

[0107] Figure 7 This is a cross-sectional view showing an example configuration of the package according to the fifth embodiment.

[0108] In the accompanying drawings, package 500 corresponds to package 100 of the first embodiment described above, which further includes a heat sink 503. Other components of package 500 of the fifth embodiment are similar to those of package 100A of the first embodiment described above.

[0109] Package 500 is mounted on mother substrate 501. In this configuration, protruding electrode 110 is formed on solder pad electrode 109. Solder pad electrode 502 is formed on mother substrate 501. Package 500 can be mounted on mother substrate 501 by bonding protruding electrode 110 to solder pad electrode 502.

[0110] The heat sink 503 is bonded to the back side of the package substrate 101A. Here, the heat sink 503 can be bonded to the back side of the package substrate 101A, with its distal end extending through the mother substrate 501. In this configuration, solder electrodes 109 and 502 can be arranged around the heat sink 503. The heat sink 503 can be provided with heat dissipation fins. Metals such as Cu or Al can be used as the material for the heat sink 503. Note that the heat sink 503 can be directly bonded to the lower thermally conductive layer 107. In this configuration, a protective film such as solder resist can be removed from the lower thermally conductive layer 107.

[0111] Furthermore, the housing 505 is mounted on the mother substrate 501. The housing 505 is joined to the thermally conductive terminals 104 of the packaging substrate 101A via the joining member 504. The housing 505 may have a rectangular tubular shape. In this configuration, the housing 505 may be joined to the thermally conductive terminals 104 arranged along the four sides of the outer periphery of the packaging substrate 101A. To improve heat dissipation from the housing 505, the material of the housing 505 is ideally a metal such as Cu, Al, or stainless steel.

[0112] As described above, in the fifth embodiment, an upper thermally conductive layer 106A and a lower thermally conductive layer 107 with higher thermal conductivity than the packaging substrate 101A are provided and interconnected through a heat dissipation via 108A, and a heat sink 503 is attached to the back side of the packaging substrate 101A. Therefore, the dissipation of heat generated by the chip 111 can be improved while eliminating the need to modify the configuration of the packaging substrate 101A.

[0113] It should be noted that in the fifth embodiment described above, the thermally conductive terminal 104 of the package substrate 101A is bonded to the housing 505; however, the housing 505 can be the casing of an electronic device such as a smartphone or camera. Therefore, heat generated by the chip 111 can be dissipated to the outside of the electronic device while suppressing an increase in its size. Additionally, the housing 505 can be a lens barrel supporting an optical component such as a lens or filter, located above the package 500.

[0114] <6. Sixth Embodiment>

[0115] In the fifth embodiment described above, the housing 505 is joined to the thermally conductive terminal 104 of the encapsulation substrate 101A via the joining member 504. In the sixth embodiment, the thermally conductive terminal 104 of the encapsulation substrate 101A is joined to the housing supporting the lens.

[0116] Figure 8 This is a cross-sectional view showing an example configuration of the package according to the sixth embodiment.

[0117] In the figure, package 100A is mounted on mother substrate 601. In this configuration, protruding electrode 110 is formed on solder pad electrode 109. Solder pad electrode 602 is formed on mother substrate 601. Package 100A can then be mounted on mother substrate 601 by bonding protruding electrode 110 to solder pad electrode 602.

[0118] A housing 605 is mounted on a mother substrate 601. The housing 605 supports a lens 603 above a light-receiving portion 112. The lens 603 focuses incident light onto the light-receiving portion 112. The housing 605 is bonded to a thermally conductive terminal 104 of a packaging substrate 101A via a bonding member 604. The housing 605 may have a rectangular tubular shape. In this configuration, the housing 605 may be bonded to thermally conductive terminals 104 on four surfaces of the periphery of the packaging substrate 101A. The material of the housing 605 may be, for example, stainless steel or die-cast aluminum.

[0119] As described above, in this sixth embodiment, the thermally conductive terminal 104 of the packaging substrate 101A is bonded to the housing 605 that supports the lens 603. Therefore, while supporting the lens 603 above the light receiving portion 112 via the housing 605, the heat generated by the chip 111 can be dissipated from the housing 605 via the side of the packaging substrate 101A.

[0120] <7. Examples of application to moving bodies>

[0121] The technology disclosed herein (the Technology) can be applied to a variety of products. For example, the Technology disclosed herein can also be implemented as a device installed on any type of mobile body such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, or robots.

[0122] Figure 9 This is a block diagram illustrating a schematic configuration example of a vehicle control system, which is an example of a mobile body control system to which the technology according to this disclosure can be applied.

[0123] The vehicle control system 12000 includes multiple electronic control units, which are interconnected via a communication network 12001. Figure 9In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. Furthermore, a microcomputer 12051, an audio / image output section 12052, and an in-vehicle network interface (I / F) 12053 are shown as functional components of the integrated control unit 12050.

[0124] The drive system control unit 12010 controls the operation of equipment related to the vehicle's drive system according to various programs. For example, the drive system control unit 12010 is used as a control device for drive force generating equipment (such as an internal combustion engine, drive motor, etc.) for generating vehicle driving force, drive force transmission mechanism for transmitting driving force to the wheels, steering mechanism for adjusting vehicle steering angle, braking equipment for generating vehicle braking force, etc.

[0125] The body system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the body system control unit 12020 is used as a control device for keyless entry systems, smart key systems, power window devices, or various lights such as headlights, reversing lights, brake lights, turn signals, fog lights, etc. In this case, radio waves or signals from various switches sent from mobile devices used as key replacements can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals and controls the vehicle's door locking devices, power window devices, lights, etc.

[0126] The exterior information detection unit 12030 detects information about the exterior of the vehicle, including the vehicle control system 12000. For example, the exterior information detection unit 12030 is connected to the imaging unit 12031. The exterior information detection unit 12030 causes the imaging unit 12031 to capture images of the exterior of the vehicle and receives the captured images. Based on the received images, the exterior information detection unit 12030 can perform detection processing of objects such as people, vehicles, obstacles, signs, and text on the road surface, or perform distance detection processing.

[0127] The imaging section 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging section 12031 can output the electrical signal as an image, or it can output the electrical signal as information about the measured distance. Furthermore, the light received by the imaging section 12031 can be visible light or invisible light, such as infrared light.

[0128] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. The in-vehicle information detection unit 12040 is connected, for example, to a driver state detection section 12041 that detects the driver's state. The driver state detection section 12041 includes, for example, a camera that captures images of the driver. Based on the detection information input from the driver state detection section 12041, the in-vehicle information detection unit 12040 can calculate the driver's level of fatigue or concentration, or determine whether the driver is drowsy.

[0129] The microcomputer 12051 can calculate target control values ​​for the drive force generation device, steering mechanism, or braking device based on information about the vehicle's interior or exterior obtained by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform coordinated control to achieve functions of an advanced driver assistance system (ADAS), including collision avoidance or impact mitigation, following distance-based driving, vehicle speed maintenance, collision warning, lane departure warning, etc.

[0130] In addition, the microcomputer 12051 can control the drive force generation device, steering mechanism, braking device, etc., based on information about the exterior or interior of the vehicle obtained by the external information detection unit 12030 or the internal information detection unit 12040, thereby performing cooperative control aimed at enabling the vehicle to drive automatically without relying on driver operation.

[0131] Additionally, the microcomputer 12051 can output control commands to the body system control unit 12020 based on information about the exterior of the vehicle obtained by the exterior information detection unit 12030. For example, the microcomputer 12051 can perform coordinated control aimed at preventing glare by controlling the headlights to switch from high beams to low beams based on the position of the vehicle ahead or oncoming vehicle detected by the exterior information detection unit 12030.

[0132] The sound / image output section 12052 transmits at least one output signal, either sound or image, to an output device capable of conveying information to vehicle occupants or outside the vehicle in a visual or auditory manner. Figure 9 In the example, audio speaker 12061, display portion 12062, and dashboard 12063 are shown as output devices. For example, display portion 12062 may include at least one of an in-vehicle display and a head-up display.

[0133] Figure 10 This is a diagram showing an example of the mounting location of the imaging section 12031.

[0134] exist Figure 10In the imaging section 12031, imaging sections 12101, 12102, 12103, 12104 and 12105 are included.

[0135] For example, imaging units 12101, 12102, 12103, 12104, and 12105 are positioned on the upper part of the windshield, such as the front nose, side mirrors, rear bumper, rear door, and interior of the vehicle 12100. Imaging unit 12101 on the front nose and imaging unit 12105 on the upper part of the windshield inside the vehicle primarily acquire images of the front of the vehicle 12100. Imaging units 12102 and 12103 on the side mirrors primarily acquire images of the sides of the vehicle 12100. Imaging unit 12104 on the rear bumper or rear door primarily acquires images of the rear of the vehicle 12100. Imaging unit 12105 on the upper part of the windshield inside the vehicle is mainly used to detect vehicles, pedestrians, obstacles, signals, traffic signs, lanes, etc., ahead.

[0136] It should be noted that, Figure 10 Examples of the imaging ranges of imaging portions 12101 to 12104 are shown. Imaging range 12111 represents the imaging range of imaging portion 12101 located at the front nose. Imaging ranges 12112 and 12113 represent the imaging ranges of imaging portions 12102 and 12103 located at the side mirrors, respectively. Imaging range 12114 represents the imaging range of imaging portion 12104 located at the rear bumper or rear door. For example, a top-view image of the vehicle 12100 viewed from above is obtained by superimposing image data captured by imaging portions 12101 to 12104.

[0137] At least one of the imaging portions 12101 to 12104 may have the function of acquiring distance information. For example, at least one of the imaging portions 12101 to 12104 may be a stereo camera composed of multiple imaging elements, or may be an imaging element having pixels for phase difference detection.

[0138] For example, the microcomputer 12051 can determine the distance to each three-dimensional object within the imaging range 12111 to 12114 and the time change of that distance (relative speed relative to the vehicle 12100) based on distance information acquired from imaging portions 12101 to 12104, and thereby extract the nearest three-dimensional object, especially located on the driving path of the vehicle 12100 and traveling substantially in the same direction as the vehicle 12100 at a predetermined speed (e.g., equal to or greater than 0 km / h), as the vehicle ahead. Furthermore, the microcomputer 12051 can preset a following distance to be maintained relative to the vehicle ahead and execute automatic braking control (including follow-stop control), automatic acceleration control (including follow-start control), etc. Therefore, cooperative control aimed at enabling the vehicle to drive automatically without relying on driver operation can be performed.

[0139] For example, microcomputer 12051 can classify three-dimensional object data about three-dimensional objects into three-dimensional object data of two-wheeled vehicles, standard-sized vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information acquired from imaging units 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic obstacle avoidance. For example, microcomputer 12051 identifies obstacles around vehicle 12100 as obstacles that can be visually recognized by the driver of vehicle 12100 and obstacles that are difficult for the driver of vehicle 12100 to visually recognize. Then, microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle. If the collision risk is equal to or higher than a set value and therefore there is a possibility of collision, microcomputer 12051 outputs a warning to the driver via audio speaker 12061 or display unit 12062, and performs forced deceleration or evasive steering via drive system control unit 12010. Microcomputer 12051 can thus assist driving to avoid collisions.

[0140] At least one of the imaging units 12101 to 12104 can be an infrared camera that detects infrared light. For example, the microcomputer 12051 can identify a pedestrian by determining whether a pedestrian exists in the images captured by the imaging units 12101 to 12104. Such pedestrian identification is performed, for example, by: extracting feature points from the images captured by the imaging units 12101 to 12104, which are infrared cameras; and determining whether an object is a pedestrian by performing pattern matching processing on a series of feature points representing the outline of an object. When the microcomputer 12051 determines that a pedestrian exists in the images captured by the imaging units 12101 to 12104 and thus identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 such that a square outline for emphasis is displayed superimposed on the identified pedestrian. The sound / image output unit 12052 can also control the display unit 12062 such that an icon representing a pedestrian, etc., is displayed at a desired location.

[0141] The above has described an example of a vehicle control system to which the technology according to this disclosure can be applied. The technology according to this disclosure can be applied to the drive system control unit 12010, body system control unit 12020, external information detection unit 12030, internal information detection unit 12040, integrated control unit 12050, and imaging section 12031 in the above configuration. Specifically, the packaging of the fourth embodiment described above can be applied to, for example, the drive system control unit 12010, body system control unit 12020, external information detection unit 12030, internal information detection unit 12040, and integrated control unit 12050. The packaging of any of the first to third, fifth, and sixth embodiments described above can be applied to the imaging section 12031. By applying the technology according to this disclosure to the vehicle control system 12000, the heat dissipation of the package can be improved while suppressing the increase in package size, thereby improving the reliability of the package.

[0142] It should be noted that the above embodiments are merely examples of implementing this technology, and the matters in the embodiments correspond to the matters defined in the claims. Similarly, the matters defined in the claims correspond to the matters with the same names in the embodiments of this technology. However, this technology is not limited to the embodiments and can be implemented with various modifications without departing from the spirit of this technology. In addition, the effects described herein are merely examples and are not intended to be limiting; other effects can also be achieved.

[0143] It should be noted that this technology can also have the following configurations.

[0144] (1) A package comprising: A chip having external terminals for signal transmission formed on its front side; A substrate on which the chip is mounted via the back side of the chip; Multiple thermally conductive layers, wherein the multiple thermally conductive layers are arranged in mutually different layers of the substrate and have a higher thermal conductivity than the substrate; and Through holes interconnect the plurality of thermally conductive layers.

[0145] (2) The packaging according to (1) above, wherein, The via is arranged at a position overlapping with the chip.

[0146] (3) The packaging according to (1) or (2) above, wherein, The vias are arranged at equal intervals on the entire back side of the chip.

[0147] (4) The packaging according to (1) or (2) above, wherein, The vias are arranged according to the heat distribution of the chip.

[0148] (5) The packaging according to any one of (1)-(4) above, wherein, The external terminal includes a first bonding pad. The substrate includes a second bonding pad arranged around the chip, and The first bonding pad and the second bonding pad are connected to each other via bonding lines.

[0149] (6) The packaging according to (5) above, wherein, Multiple thermally conductive layers include an upper thermally conductive layer and a lower thermally conductive layer, and The upper thermal conductive layer and bonding pads are arranged in a common layer of the substrate.

[0150] (7) The packaging according to (6) above further includes: Solder electrode formed on the back side of the substrate, wherein The lower heat-conducting layer is arranged on top of the layer that forms the solder area electrode.

[0151] (8) The packaging according to any one of (5) to (7) above, wherein

[0152] Multiple thermally conductive layers are formed at locations that completely overlap with the back of the chip.

[0153] (9) The packaging according to (8) above, wherein

[0154] The upper thermal conductive layer extends beyond the back side of the chip to surround the second bonding pad.

[0155] (10) The packaging according to (9) above further includes: Terminals disposed on the side of the substrate and having a higher thermal conductivity than the substrate, wherein The thermally conductive layer is connected to the terminal.

[0156] (11) The packaging according to (10) above further includes: A housing that is engaged with terminals via a connecting member.

[0157] (12) The packaging according to (11) above, wherein

[0158] The chip includes a light receiver configured to receive light, and the package also includes: A lens supported above the light-receiving part by the housing.

[0159] (13) The packaging according to any one of (5) to (12) above further includes: Sealant for sealing chips and bonding lines on a substrate.

[0160] (14) The packaging according to any one of (1) to (12) above further includes: A transparent substrate positioned above the chip; and Ribs that support the transparent substrate above the chip.

[0161] (15) The packaging according to any one of (1) to (14) above further includes: A heat sink that is bonded to the back of the substrate.

[0162] List of reference numerals

[0163] 100A package

[0164] 101A Package Substrate

[0165] 102 Interconnectors

[0166] 103 Through Hole

[0167] 104 thermally conductive terminal

[0168] 105, 113 joint pads

[0169] 106A Upper Thermal Conductive Layer

[0170] 107 Lower heat-conducting layer

[0171] 108A heat dissipation holes

[0172] 109 Solder Zone Electrode

[0173] 111 Sensor Chip

[0174] 112 Optical Receiver Section

[0175] 114 Color Filter

[0176] 115 On-plate lens

[0177] 116 Joint Line

[0178] 121 Sealant

[0179] 122 Transparent substrate

Claims

1. A package, comprising: The chip has external terminals for signal transmission formed on the front side of the chip; A substrate on which the chip is mounted via the back side of the chip; Multiple thermally conductive layers are arranged in different layers of the substrate and have a higher thermal conductivity than the substrate. as well as Through holes interconnecting the multiple thermally conductive layers.

2. The packaging according to claim 1, wherein The via is positioned to overlap with the chip.

3. The packaging according to claim 1, wherein The vias are arranged at equal intervals on the entire back side of the chip.

4. The packaging according to claim 1, wherein The vias are arranged according to the heat distribution of the chip.

5. The packaging according to claim 1, wherein The external terminal includes a first bonding pad. The substrate includes a second bonding pad arranged around the chip, and The first bonding pad and the second bonding pad are connected to each other via bonding lines.

6. The packaging according to claim 5, wherein The plurality of thermally conductive layers include an upper thermally conductive layer and a lower thermally conductive layer, and The upper thermally conductive layer and the bonding pads are arranged in a common layer of the substrate.

7. The packaging according to claim 6, further comprising: Solder electrode formed on the back side of the substrate, wherein The lower thermally conductive layer is disposed on top of the layer forming the solder area electrode.

8. The packaging according to claim 5, wherein The plurality of thermally conductive layers are formed at locations that completely overlap with the back side of the chip.

9. The packaging according to claim 8, wherein The upper thermal conductive layer extends beyond the back side of the chip to surround the second bonding pad.

10. The packaging according to claim 9, further comprising: Terminals disposed on the side surface of the substrate and having a higher thermal conductivity than the substrate, wherein The thermally conductive layer is connected to the terminal.

11. The packaging according to claim 10, further comprising: The housing is engaged with the terminal by a coupling member.

12. The packaging according to claim 11, wherein The chip includes a light receiving portion configured to receive light, and the package further includes: The lens is supported above the light receiving portion via the housing.

13. The packaging according to claim 5, further comprising: A sealant is used to seal the chip and the bonding lines on the substrate.

14. The packaging according to claim 1, further comprising: A transparent substrate disposed above the chip; as well as Ribs that support the transparent substrate above the chip.

15. The packaging according to claim 1, further comprising: A heat sink that is coupled to the back side of the substrate.

Images