Active charge balancing device, method and chip

Abstract

This application provides an active charge balancing device, method, and chip. The device includes: a voltage change sensing circuit configured to sense the magnitude change of the electrode voltage of a target electrode, and to output an enable signal in response to the electrode voltage change exceeding expectations; a voltage-to-time conversion circuit configured to start operating according to the enable signal, and to convert the electrode voltage and a preset threshold voltage into an electrode time-domain signal and a threshold time-domain signal; a time-to-digital conversion circuit configured to convert the electrode time-domain signal and the threshold time-domain signal into a digital signal with a preset number of bits; and a digital-to-analog conversion circuit configured to convert the digital signal into a current signal and feed it back to the stimulation current source of the target electrode. This application converts the measured electrode voltage from voltage to time domain to avoid the problems faced by high-precision ADCs, and can achieve low power consumption while maintaining the accuracy of electrode voltage detection.

Description

Technical Field

[0001] This application belongs to the technical field of integrated circuit design, and relates to an active charge balancing device, method and chip. Background Technology

[0002] Traditional charge balancing techniques primarily employ an ADC (Analog-to-Digital Converter) to sample the electrode voltage. After obtaining the correction code, a feedback loop is used to reduce the residual voltage on the electrodes. Therefore, the effectiveness of charge balancing largely depends on the accuracy of the ADC. A charge-balancing ADC is essentially an integral Σ-Δ architecture, its core being the maintenance of charge conservation at the input node. During the integration phase, the input electrode voltage, after being buffered by a high impedance, charges the internal integrating capacitor, generating an integral voltage that varies linearly with time. During the feedback balancing phase, when the integral voltage reaches the comparator threshold, digital logic controls a precision current source (or switched capacitor network) to inject or extract a fixed amount of charge (Q = I × Δt) into or from the integrating node, causing the integral voltage to fall back. In the counting output phase, the number of feedback operations per unit time (i.e., pulse frequency) is proportional to the input voltage, and a counter accumulates the data to obtain the digital output.

[0003] However, as manufacturing processes become more advanced and power supply voltages are designed to be smaller to achieve low power consumption, the minimum effective bits (LSB) of high-precision ADCs are easily overwhelmed by noise in low power supply voltage scenarios, making them difficult to implement. Summary of the Invention

[0004] This application provides an active charge balancing device, method, and chip to solve the problem of achieving low power consumption while maintaining the accuracy of electrode voltage detection.

[0005] In a first aspect, this application provides an active charge balancing device, comprising: a voltage change sensing circuit configured to sense the magnitude change of the electrode voltage of a target electrode, and to output an enable signal in response to the electrode voltage change exceeding expectations; a voltage-time conversion circuit configured to start working according to the enable signal, and to convert the electrode voltage and a preset threshold voltage into an electrode time-domain signal and a threshold time-domain signal; a time-to-digital conversion circuit configured to convert the electrode time-domain signal and the threshold time-domain signal into a digital signal with a preset number of bits; and a digital-to-analog conversion circuit configured to convert the digital signal into a current signal and feed it back to the stimulation current source of the target electrode.

[0006] In one implementation of the first aspect, the voltage change sensing circuit includes a comparator; the first input terminal of the comparator receives the electrode voltage, and the second input terminal receives the preset threshold voltage; the comparator compares the detected electrode voltage with the preset threshold voltage, and in response to the electrode voltage being greater than the preset threshold voltage, outputs the enable signal through its output terminal.

[0007] In one implementation of the first aspect, the first input terminal is a positive input terminal and the second input terminal is a negative input terminal; the enable signal output by the output terminal of the comparator is a high level; or the first input terminal is a negative input terminal and the second input terminal is a positive input terminal; the enable signal output by the output terminal of the comparator is a low level.

[0008] In one implementation of the first aspect, the voltage-time conversion circuit includes a symmetrically distributed first charging / discharging unit and a second charging / discharging unit; the input terminal of the first charging / discharging unit receives the electrode voltage, and the output terminal reflects the charging / discharging status of the first charging / discharging unit; the input terminal of the second charging / discharging unit receives the preset threshold voltage, and the output terminal reflects the charging / discharging status of the second charging / discharging unit; the voltage-time conversion circuit utilizes the voltage difference between the electrode voltage and the preset threshold voltage to cause different discharge rates in the discharge circuits within the two units, thereby converting it into a time difference signal between the output terminals of the first charging / discharging unit and the second charging / discharging unit; the time difference signal output by the output terminal of the first charging / discharging unit is an electrode time-domain signal, and the time difference signal output by the output terminal of the second charging / discharging unit is a threshold time-domain signal.

[0009] In one implementation of the first aspect, the time-to-digital conversion circuit includes: multiple levels of delay chains, registers one level higher than the number of delay chain levels, and a binary encoder; each level of the register uses the threshold time-domain signal as a clock trigger signal to sample the nodes of the corresponding level circuit on the delay chain to obtain a first target code; wherein, the last level of the register samples the output of the last level on the delay chain to obtain a second target code; the binary encoder converts the multi-level target codes into binary output of the digital signal.

[0010] In one implementation of the first aspect, the delay chain includes: a plurality of inverters connected in series; each stage of the register samples the input of the corresponding stage inverter in the delay chain to obtain the first target code; and the last stage of the register samples the output of the last stage inverter in the delay chain to obtain the second target code.

[0011] In one implementation of the first aspect, the registers at each level include: each flip-flop having one more stage than the number of stages in the delay chain; the clock terminal of the flip-flop uses the threshold time-domain signal as the clock trigger signal, and samples the nodes of the corresponding level circuits in the delay chain through the data trigger terminal to obtain the first target code; the last stage of the flip-flop samples the output terminal of the last stage in the delay chain to obtain the second target code.

[0012] In one implementation of the first aspect, the binary encoder includes: a logic operation device; the logic operation device is configured to perform logical operations on the target codes output from all levels to achieve position compression and output the digital signal.

[0013] Secondly, this application provides an active charge balancing method, comprising: sensing the magnitude change of the electrode voltage of a target electrode; responding to the electrode voltage change exceeding expectations by outputting an enable signal; starting operation according to the enable signal; converting the electrode voltage and a preset threshold voltage into an electrode time-domain signal and a threshold time-domain signal; converting the electrode time-domain signal and the threshold time-domain signal into a digital signal with a preset number of bits; and converting the digital signal into a current signal and feeding it back to the stimulation current source of the target electrode.

[0014] Thirdly, this application provides a chip, including: the aforementioned device.

[0015] As described above, the active charge balancing device, method, and chip of this application have the following beneficial effects:

[0016] This application provides a time-domain-based charge balancing technique that converts the measured electrode voltage from voltage to time domain to avoid the problems faced by high-precision ADCs. The circuit is simple to implement and can be flexibly configured, achieving low power consumption and improved system safety while maintaining the accuracy of electrode voltage detection.

[0017] The charge balancing circuit designed in this application employs an active correction technique, utilizing a comparator for online detection to improve the effectiveness and timeliness of charge balancing. In terms of innovation, the voltage-to-time conversion circuit utilizes a dynamic comparator architecture, thus eliminating additional static power consumption and achieving low power requirements. The voltage-to-time conversion circuit converts the voltage signal into a pair of pseudo-differential signals in the time domain (VTC_outp / VTC_outn), suppressing some common-mode noise and improving the measurement accuracy of the entire charge balancing circuit. The time-to-digital converter primarily performs subtraction and data conversion, simplifying the overall circuit design. Finally, the charge balancing circuit designed in this application allows for programmable adjustment of the threshold voltage, addressing key pain points in electrochemical interfaces and clinical applications, including the water window effect and the overall safety of electrostimulation systems. Attached Figure Description

[0018] Figure 1 The diagram shown is a structural schematic of the active charge balancing device described in an embodiment of this application.

[0019] Figure 2 The diagram shown is a schematic diagram of the circuit structure of the active charge balancing device described in the embodiments of this application.

[0020] Figure 3 The diagram shown is a schematic diagram of the voltage-time conversion circuit of the active charge balancing device described in the embodiments of this application.

[0021] Figure 4 The diagram shown is a schematic of the time-to-digital conversion circuit of the active charge balancing device described in this application embodiment.

[0022] Figure 5 The diagram shows the electrode voltage waveforms of the active charge balancing device described in this application embodiment.

[0023] Figure 6 The diagram shows the signal waveform output of the voltage-time conversion circuit of the active charge balancing device described in this application embodiment.

[0024] Figure 7 The image shown is a waveform diagram of the electrical stimulation current change of the active charge balancing device described in the embodiments of this application.

[0025] Figure 8 The diagram shown is a time-to-digital conversion timing diagram of the active charge balance device described in the embodiments of this application.

[0026] Figure 9 The diagram shown is a flowchart illustrating the principle of the active charge balance method described in this application embodiment.

[0027] Figure 10 The diagram shown is a schematic representation of the chip described in an embodiment of this application.

[0028] Figure 11 The diagram shown is a structural schematic of the implantable system described in an embodiment of this application.

[0029] Component designation explanation

[0030] 1 Active charge balance device 11 Voltage change sensing circuit 12 Voltage-time conversion circuit 121 First charging and discharging unit 122 Second charging and discharging unit 13 Time-to-digital converter circuit 14 Digital-to-analog converter circuit S91~S94 step Detailed Implementation

[0031] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0032] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. Therefore, the illustrations only show the components related to this application and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0033] The technical solutions in the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0034] Example 1

[0035] Please see Figure 1 The image shown is a schematic diagram of the active charge balancing device described in an embodiment of this application. Figure 1 As shown, this embodiment provides an active charge balancing device 1, which specifically includes: a voltage change sensing circuit 11, a voltage-time conversion circuit 12, a time-to-digital conversion circuit 13, and a digital-to-analog conversion circuit 14.

[0036] The voltage change sensing circuit 11 is configured to sense the magnitude change of the electrode voltage of the target electrode, and output an enable signal in response to the electrode voltage change exceeding the expectation.

[0037] The voltage-time conversion circuit 12 is configured to start working according to the enable signal and convert the electrode voltage and the preset threshold voltage into an electrode time domain signal and a threshold time domain signal respectively.

[0038] The time-to-digital converter circuit 13 is configured to convert the electrode time-domain signal and the threshold time-domain signal into a digital signal with a preset number of bits.

[0039] The digital-to-analog conversion circuit 14 is configured to convert the digital signal into a current signal and feed it back to the stimulation current source of the target electrode.

[0040] In one embodiment, the voltage change sensing circuit includes a comparator.

[0041] The comparator receives the electrode voltage at its first input terminal and the preset threshold voltage at its second input terminal; the comparator compares the detected electrode voltage with the preset threshold voltage, and outputs the enable signal through its output terminal in response to the electrode voltage being greater than the preset threshold voltage.

[0042] Please see Figure 2 The diagram shows a schematic of the circuit structure of the active charge balancing device described in an embodiment of this application. Figure 2 As shown, the voltage change sensing circuit 11 includes a comparator. The first input terminal of the comparator receives the electrode voltage VE0, and the second input terminal receives the preset threshold voltage Vth. The comparator compares the detected electrode voltage VE0 with the preset threshold voltage Vth. In response to the electrode voltage VE0 being greater than the preset threshold voltage Vth, the comparator outputs the enable signal VTC_EN through its output terminal.

[0043] Therefore, the voltage change sensing circuit 11 described in this application mainly functions as an analog amplitude decision unit, responsible for sensing changes in the strength of external analog signals. When the comparator detects that the electrode voltage (analog signal) exceeds a certain threshold, the comparator output changes from a low potential to a high potential (digital level signal), driving the voltage-time converter to operate. This invention primarily focuses on the comparator's propagation delay, which determines the response speed of the entire charge balance circuit.

[0044] In one embodiment, the first input terminal is a positive input terminal, and the second input terminal is a negative input terminal; the enable signal output by the output terminal of the comparator is a high level.

[0045] In another embodiment, the first input terminal is a negative input terminal, and the second input terminal is a positive input terminal; the enable signal output by the comparator is a low level.

[0046] like Figure 2As shown, the core of the charge balancing architecture in this embodiment takes a single-channel form as an example. The first input terminal is a positive phase input terminal, and the second input terminal is a negative phase input terminal; the enable signal output by the comparator is high level. The charge balancing circuit mainly consists of a comparator, a voltage-to-time conversion circuit, a time-to-digital conversion circuit, and a current-based digital-to-analog converter. The entire workflow is as follows: when the comparator detects that the voltage of electrode VE0 is greater than the system's designed threshold voltage Vth, the comparator outputs VTC_EN as high level, and the voltage-to-time conversion circuit starts working, converting the electrode voltage VE0 and the threshold voltage Vth into time-domain signals VTC_outp and VTC_outn. Then, the time-to-digital conversion circuit subtracts VTC_outp and VTC_outn and converts them into a 6-bit digital signal TDC_out<5:0>. Finally, the current-based digital-to-analog converter circuit converts TDC_out<5:0> back into a current signal Icom0 and feeds it back to the single-channel stimulation current source.

[0047] In practical applications, the threshold voltage Vth of this application can be adjusted by programming according to the specific application scenario of the device and different actual charge balance requirements.

[0048] In different implementations, the voltage-time conversion circuit of this application can be implemented using one of the following: current-starved inverter type, ring oscillator type, capacitor charge-discharge integral type, and delay chain type. The current-starved inverter type refers to connecting a MOS transistor (as a variable resistor / current source) controlled by the input voltage in series in the pull-up or pull-down path of a CMOS (Complementary Metal-Oxide-Semiconductor) inverter. By changing the charge-discharge current rate, the charge-discharge time of the load capacitor is adjusted, thereby generating a rise / fall delay or pulse width proportional to the input voltage. The ring oscillator type refers to a ring composed of an odd number of inverter stages, where one or more stages employ a current-starved structure. The delay chain type refers to the input voltage controlling the drive strength of transistors in a multi-stage delay unit, where the total propagation time of the signal through a fixed-stage delay chain is related to the input voltage.

[0049] Please see Figure 3 The diagram shows a schematic representation of the voltage-time conversion circuit of the active charge balancing device described in this embodiment. Figure 3 As shown, taking the capacitor charge-discharge integral type as an example, the voltage-time conversion circuit 12 includes a first charge-discharge unit 121 and a second charge-discharge unit 122 that are symmetrically distributed.

[0050] The input terminal of the first charging and discharging unit 121 receives the electrode voltage, and the output terminal reflects the charging and discharging status of the first charging and discharging unit 121; the input terminal of the second charging and discharging unit 122 receives the preset threshold voltage, and the output terminal reflects the charging and discharging status of the second charging and discharging unit 122.

[0051] The voltage-time conversion circuit 12 utilizes the voltage difference between the electrode voltage VE0 and the preset threshold voltage Vth to cause different discharge rates in the discharge circuits within the two units, thereby converting it into a time difference signal between the output terminals of the first charge-discharge unit 121 and the second charge-discharge unit 122; the time difference signal output by the output terminal of the first charge-discharge unit 121 is an electrode time domain signal, and the time difference signal output by the output terminal of the second charge-discharge unit 122 is a threshold time domain signal.

[0052] like Figure 2 As shown, when the enable signal VTC_EN is valid, the voltage-time conversion circuit 12 uses the voltage difference between the electrode voltage VE0 and the preset threshold voltage Vth to cause different discharge rates in the discharge circuits within the two units, thereby converting it into a time difference signal between the output terminals of the first charge-discharge unit 121 and the second charge-discharge unit 122; the time difference signal output by the output terminal of the first charge-discharge unit 121 is the electrode time domain signal VTC_outp, and the time difference signal output by the output terminal of the second charge-discharge unit 122 is the threshold time domain signal VTC_outn.

[0053] Therefore, the voltage-to-time conversion circuit 12 of this application acts as a modulator for analog-to-time quantities, mapping the voltage amplitudes (analog signals) of the electrodes and reference electrodes, which are difficult to measure directly, into time pulse widths (time signals) that are easy for digital circuits to measure. This application focuses on the linearity and adjustable conversion gain of the voltage-to-time converter, thereby determining the input range and detection accuracy of the charge balance circuit. By converting the voltage signal into a pair of pseudo-differential signals in the time domain (VTC_outp / VTC_outn), the voltage-to-time conversion circuit 12 can suppress some common-mode noise and improve the measurement accuracy of the entire charge balance circuit.

[0054] In one embodiment, the time-to-digital conversion circuit includes: multiple levels of delay chains, registers one level higher than the number of delay chain levels, and a binary encoder.

[0055] Each level of the register uses the threshold time-domain signal as a clock trigger signal to sample the nodes of the corresponding level circuit on the delay chain to obtain the first target code; wherein, the last level of the register samples the output of the last level on the delay chain to obtain the second target code; the binary encoder converts the multi-level target codes into binary output digital signals.

[0056] The delay chain includes multiple inverters connected in series.

[0057] Each stage of the register samples the input of the corresponding level inverter in the delay chain to obtain the first target code, and the last stage of the register samples the output of the last stage inverter in the delay chain to obtain the second target code.

[0058] Please see Figure 4 The diagram shows the time-to-digital conversion circuit schematic of the active charge balancing device described in this application embodiment. Figure 4 As shown, the delay chain includes multiple inverters TD0, TD1...TD61 connected in series. Each stage of the register samples the input of the corresponding inverter in the delay chain to obtain the first target code, and the last stage of the register samples the output of the last inverter in the delay chain to obtain the second target code.

[0059] Furthermore, the registers at each level include each flip-flop that has one more stage than the number of stages in the delay chain.

[0060] The clock terminal of the trigger uses the threshold time domain signal as the clock trigger signal, and samples the nodes of the corresponding level circuit on the delay chain through the data trigger terminal to obtain the first target code. The last stage of the trigger samples the output terminal of the last stage on the delay chain to obtain the second target code.

[0061] like Figure 4As shown, the registers at each level include flip-flops D0, D1, D2...D61, D62, each one level higher than the number of stages in the delay chain. The clock input of each flip-flop uses the threshold time-domain signal VTC_outn as the clock trigger signal. After the electrode time-domain signal VTC_outp is input, the data trigger terminal D samples the nodes of the corresponding level circuits in the delay chain to obtain the first target code. The last flip-flop samples the output of the last stage in the delay chain to obtain the second target code. For example, the clock input of flip-flop D0 uses the threshold time-domain signal VTC_outn as the clock trigger signal, and the data trigger terminal D samples the input of TD0 in the delay chain to obtain the target code Dout. <0> The clock input of trigger D1 uses the threshold time-domain signal VTC_outn as the clock trigger signal, and samples the input of TD1 on the delay chain through the data trigger input D to obtain the target code Dout. <1> The clock input of trigger D2 uses the threshold time-domain signal VTC_outn as the clock trigger signal, and samples the input of TD2 on the delay chain through the data trigger input D to obtain the target code Dout. <2> The clock input of trigger D61 uses the threshold time-domain signal VTC_outn as the clock trigger signal, and samples the input of TD61 on the delay chain through the data trigger input D to obtain the target code Dout. <61> The clock input of trigger D62 uses the threshold time-domain signal VTC_outn as the clock trigger signal, and samples the output of TD61 on the delay chain through the data trigger input D to obtain the target code Dout. <62> The target encoding includes the use of thermometer code, which is a numerical encoding method that uses multiple "1"s to represent values. If the value is N, the corresponding code consists of N "1"s and the remaining "0".

[0062] Furthermore, the binary encoder includes: a logic operation device.

[0063] The logic processing device is configured to perform logical operations on the target codes of all levels of output, achieve position compression, and output the digital signal.

[0064] like Figure 4 As shown, the encoder includes a logic processing device. The logic processing device is configured to output the target code Dout for all stages. <0> Dout <1> Dout <2> …Dout <61> Dout <62> Perform logical operations to achieve position compression and output the digital signal TDC_out<5:0>.

[0065] In different implementations, the logic operation device can be a subtractor, an adder, a combination of addition and subtraction logic devices, or any other device or combination of devices capable of bit compression.

[0066] like Figure 4 As shown, the time-to-digital converter circuit described in this application is mainly based on a traditional flash time-to-digital converter (Flash TDC) architecture plus an encoder to obtain a 6-bit time-to-digital converter circuit. When the rising edge of the VTC differential outputs (VTC_outp and VTC_outn) is detected, the time-to-digital converter circuit is triggered and begins to work, converting the time difference between the two rising edges of the VTC outputs into a digital signal. However, the output of the traditional flash time-to-digital converter architecture is represented in the form of a target code, therefore an additional encoder is needed to convert the target code into binary code for input to the next stage current-mode digital-to-analog converter. For example, this study designs a 63-stage flash time-to-digital converter based on time accuracy and input range requirements, with an output of Dout. <0> To Dout <62> The total is 63 bits. However, without an encoder, the direct serial output of 63 bits of data by the time-to-digital converter would limit the signal bandwidth of the entire charge-balance circuit. Therefore, a binary encoder is designed to convert the 63 bits of data into 6 bits, i.e., output TDC_out<5:0>, to solve the potential signal bandwidth limitation problem.

[0067] In different implementations, a bit depth of 6 bits is only one implementation method. Other reasonable bit depth settings based on design requirements and circuit area considerations are also within the scope of protection of this application.

[0068] Therefore, the time-to-digital converter circuit 13 of this application mainly consists of a delay chain composed of inverters and D-type flip-flops. Compared with traditional analog-to-digital converters that require operational amplifiers and capacitors, which consume a large amount of chip area and power, the time-to-digital converter circuit requires a small area and has near-zero static power consumption, thus possessing energy efficiency and being very suitable for low-power implantable systems with energy constraints and high-density multi-channel acquisition. As a high-precision time interval quantizer, it is responsible for quantizing pulse time (time signal) into binary or target code (digital signal) so that the microcontroller can process it. This application mainly focuses on the time resolution of the time-to-digital converter, which determines the detection accuracy of the charge balance circuit.

[0069] The current-type digital-to-analog converter 14 in this application serves as a converter that converts digital signals into analog signals. It is responsible for restoring the error (digital signal) detected by the charge balance circuit into a current form (analog signal) and feeding it back to the current source. This invention focuses on whether the current-type digital-to-analog converter maintains its monotonic characteristic. This indicator mainly affects the magnitude of the error in the feedback current of the charge balance, which in turn leads to the failure of the charge balance circuit.

[0070] Please see Figure 5 The image shows the electrode voltage waveforms of the active charge balancing device described in the embodiments of this application. Figure 5 As shown, VE is the electrode voltage, and the horizontal line in the VE waveform is the detection threshold voltage Vth set in this application.

[0071] Please see Figure 6 The image shows the signal waveform output by the voltage-time conversion circuit of the active charge balancing device described in this application embodiment. Figure 6 As shown, VTC is the pulse difference between the two outputs VTC_outp and VTC_outn of the voltage-time conversion circuit.

[0072] Please see Figure 7 The image shows a waveform diagram of the electrical stimulation current change of the active charge balancing device described in the embodiments of this application. Figure 7 As shown, Istim is the output of the stimulation current source, i.e. Figure 2 Output of a single-channel current source.

[0073] Combination Figures 5 to 7 As shown, when the electrode voltage VE exceeds the detection threshold, VTC_output starts working, converting the difference between the electrode voltage and the reference voltage into a pulse. This pulse then passes through a time-to-digital converter and a current-to-digital converter to generate a feedback current that returns to the stimulation current source. Therefore, it can be seen that Istim changes at 0.03 seconds, and finally, VE stabilizes near the threshold voltage at approximately 0.03 seconds. Figure 5 Middle electrode voltage (VE) Figure 6 Medium Voltage Time Converter Output (VTC output) and Figure 7 The change in electrical stimulation current (Istim) illustrates the process of the entire charge balance operation.

[0074] Please see Figure 8 The image shows a time-to-digital conversion timing diagram of the active charge balancing device described in the embodiments of this application. Figure 8As shown, VTC_outp and VTC_outn are the inputs of the time-to-digital converter circuit, and Tin is the time difference between VTC_outp and VTC_outn. The main function of the time-to-digital converter circuit is to convert the time difference Tin into a digital output TDCout<5:0>. TD0~TD62 are the delay chains of the time-to-digital converter circuit, combined with... Figure 4 As can be seen, VTC_outn serves as the clock trigger signal for each stage of the register, sampling each stage of the delay chain to obtain the target code Dout<62:0>. Finally, the encoder converts Dout<62:0> into a binary output TDCout<5:0>. The encoder circuit can be composed of adders, which sum the signals from the 62 register stages to obtain the final output TDCout<5:0>.

[0075] It should be noted that the conversion of the 63-bit target code to a 6-bit digital signal in the time-to-digital converter circuit of this application is only one implementation method of this application, utilizing 2^6 - 1 = 63. Furthermore, the number of stages in the time-to-digital converter circuit directly determines the number of output bits, and the number of stages needs to be determined based on the input range, precision, and area of ​​the time-to-digital converter. Any other reasonable conversion relationships, such as 127 to 7 or 255 to 8, are within the scope of protection of this application.

[0076] Example 2

[0077] Please see Figure 9 The diagram shows a schematic flowchart of the active charge balance method described in an embodiment of this application. Figure 9 As shown, this embodiment provides an active charge balancing method, applied to the active charge balancing device described in this application, specifically including the following steps S91 to S94.

[0078] S91, sense the magnitude change of the electrode voltage of the target electrode, and output an enable signal in response to the electrode voltage change exceeding the expectation.

[0079] Specifically, in combination Figure 2 The system senses the magnitude change of the electrode voltage VE0 of the target electrode. In response to the electrode voltage change exceeding expectations, i.e., detecting that the voltage of electrode VE0 is greater than the system preset threshold voltage Vth, the system outputs the enable signal VTC_EN as high level.

[0080] S92, start working according to the enable signal, and convert the electrode voltage and the preset threshold voltage into electrode time domain signal and threshold time domain signal respectively.

[0081] Specifically, when the enable signal VTC_EN is high, the voltage-time conversion circuit starts working, converting the electrode voltage VE0 and the preset threshold voltage Vth into the electrode time-domain signal VTC_outp and the threshold time-domain signal VTC_outn.

[0082] S93 converts the electrode time-domain signal and the threshold time-domain signal into a digital signal with a preset number of bits.

[0083] Specifically, the 63-bit electrode time-domain signal VTC_outp and the threshold time-domain signal VTC_outn are subtracted by a time-to-digital converter circuit and converted into a 6-bit digital signal TDC_out<5:0>.

[0084] S94, the digital signal is converted into a current signal and fed back to the stimulation current source of the target electrode.

[0085] Specifically, the current signal TDC_out<5:0> is converted back into the current signal Icom0 through a current-type digital-to-analog converter circuit and fed back to the single-channel stimulation current source.

[0086] Example 3

[0087] Please see Figure 10 The image shown is a schematic diagram of the chip structure described in an embodiment of this application. Figure 10 As shown, this embodiment provides a chip including the aforementioned active charge balancing device.

[0088] In one embodiment, the active charge balancing device includes: a voltage change sensing circuit configured to sense the magnitude change of the electrode voltage of the target electrode, and to output an enable signal in response to the electrode voltage change exceeding expectations; a voltage-time conversion circuit configured to start working according to the enable signal, and to convert the electrode voltage and a preset threshold voltage into an electrode time-domain signal and a threshold time-domain signal; a time-to-digital conversion circuit configured to convert the electrode time-domain signal and the threshold time-domain signal into a digital signal with a preset number of bits; and a digital-to-analog conversion circuit configured to convert the digital signal into a current signal and feed it back to the stimulation current source of the target electrode.

[0089] In one embodiment, the voltage change sensing circuit includes a comparator; the first input terminal of the comparator receives the electrode voltage, and the second input terminal receives the preset threshold voltage; the comparator compares the detected electrode voltage with the preset threshold voltage, and in response to the electrode voltage being greater than the preset threshold voltage, outputs the enable signal through the output terminal.

[0090] In one embodiment, the first input terminal is a positive input terminal, and the second input terminal is a negative input terminal; the enable signal output by the output terminal of the comparator is a high level.

[0091] In one embodiment, the first input terminal is a negative input terminal, and the second input terminal is a positive input terminal; the enable signal output by the comparator's output terminal is a low level.

[0092] In one embodiment, the voltage-time conversion circuit includes a symmetrically distributed first charging / discharging unit and a second charging / discharging unit; the input terminal of the first charging / discharging unit receives the electrode voltage, and the output terminal reflects the charging / discharging status of the first charging / discharging unit; the input terminal of the second charging / discharging unit receives the preset threshold voltage, and the output terminal reflects the charging / discharging status of the second charging / discharging unit; the voltage-time conversion circuit utilizes the voltage difference between the electrode voltage and the preset threshold voltage to cause different discharge rates in the discharge circuits within the two units, thereby converting it into a time difference signal between the output terminals of the first charging / discharging unit and the second charging / discharging unit; the time difference signal output by the output terminal of the first charging / discharging unit is an electrode time-domain signal, and the time difference signal output by the output terminal of the second charging / discharging unit is a threshold time-domain signal.

[0093] In one embodiment, the time-to-digital conversion circuit includes: multiple levels of delay chains, registers one level higher than the number of delay chain levels, and a binary encoder; each level of the register uses the threshold time-domain signal as a clock trigger signal to sample the nodes of the corresponding level circuit on the delay chain to obtain a first target code; wherein, the last level of the register samples the output of the last level on the delay chain to obtain a second target code; the binary encoder converts the multi-level target codes into binary output of the digital signal.

[0094] In one embodiment, the delay chain includes: a plurality of inverters connected in series; each stage of the register samples the input of the corresponding stage inverter in the delay chain to obtain the first target code, and the last stage of the register samples the output of the last stage inverter in the delay chain to obtain the second target code.

[0095] In one embodiment, the registers at each level include: each flip-flop having one more level than the delay chain stage; the clock terminal of the flip-flop uses the threshold time domain signal as the clock trigger signal, and samples the nodes of the corresponding level circuits on the delay chain through the data trigger terminal to obtain the first target code; the last flip-flop samples the output terminal of the last stage on the delay chain to obtain the second target code.

[0096] In one embodiment, the encoder includes: a logic operation device; the logic operation device is configured to perform logic operations on the target codes output from all levels to achieve position compression and output the digital signal.

[0097] Example 4

[0098] Please see Figure 11 The image shown is a schematic diagram of the implantable system described in an embodiment of this application. Figure 11 As shown, the active charge balancing device of this application can be applied in various scenarios such as implantable systems or high-speed ADCs. This embodiment takes an implantable system as an example and provides an implantable system, including: the active charge balancing device, a stimulation current source, and implantable electrodes.

[0099] The electrode voltage of the implanted electrode is transmitted to the circuit, which converts the electrode voltage from the voltage domain to the time domain, and then feeds the output current signal back to the stimulation current source after time-to-digital conversion and digital-to-analog conversion, so that the implanted electrode adjusts the stimulation pulse generated according to the stimulation current source.

[0100] In one embodiment, the active charge balancing device includes: a voltage change sensing circuit configured to sense the magnitude change of the electrode voltage of the target electrode, and to output an enable signal in response to the electrode voltage change exceeding expectations; a voltage-time conversion circuit configured to start working according to the enable signal, and to convert the electrode voltage and a preset threshold voltage into an electrode time-domain signal and a threshold time-domain signal; a time-to-digital conversion circuit configured to convert the electrode time-domain signal and the threshold time-domain signal into a digital signal with a preset number of bits; and a digital-to-analog conversion circuit configured to convert the digital signal into a current signal and feed it back to the stimulation current source of the target electrode.

[0101] In one embodiment, the implantable system includes an implantable brain-spinal interface system.

[0102] In practical applications, the active charge balancing device can be used in implantable systems (such as nerve stimulators and cardiac pacemakers). The operating principle is to actively control the direction and duration of the current to ensure that the amount of positive charge injected into the tissue in each stimulation cycle is strictly equal to the amount of reverse charge, thereby maintaining the electrical neutrality of the electrode-tissue interface and preventing tissue damage or electrode corrosion caused by charge accumulation.

[0103] The scope of protection of the active charge balancing method described in this application is not limited to the order of steps listed in this embodiment. Any solution implemented by adding, subtracting, or replacing steps in the prior art based on the principles of this application is included within the scope of protection of this application.

[0104] This application also provides an active charge balancing device, which can implement the active charge balancing method described in this application. However, the implementation device of the active charge balancing method described in this application includes, but is not limited to, the structure of the active charge balancing device listed in this embodiment. All structural modifications and substitutions of the prior art made based on the principles of this application are included within the protection scope of this application.

[0105] In the several embodiments provided in this application, it should be understood that the disclosed apparatus or method can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For instance, the division of circuit modules / units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or units may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection of apparatuses or modules or units may be electrical, mechanical, or other forms.

[0106] The modules / units described as separate components may or may not be physically separate. The components shown as modules / units may or may not be physical modules; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules / units can be selected to achieve the objectives of the embodiments of this application, depending on actual needs. For example, the functional modules / units in the various embodiments of this application may be integrated into one processing module, or each module / unit may exist physically separately, or two or more modules / units may be integrated into one module / unit.

[0107] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0108] The descriptions of the processes or structures corresponding to the above figures each have their own emphasis. For parts of a process or structure that are not described in detail, please refer to the relevant descriptions of other processes or structures.

[0109] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. An active charge balancing device, characterized in that, include: A voltage change sensing circuit is configured to sense the magnitude change of the electrode voltage of the target electrode, and output an enable signal in response to the electrode voltage change exceeding the expectation. The voltage-time conversion circuit is configured to start working according to the enable signal and convert the electrode voltage and the preset threshold voltage into an electrode time-domain signal and a threshold time-domain signal, respectively. A time-to-digital conversion circuit is configured to convert the electrode time-domain signal and the threshold time-domain signal into a digital signal with a preset number of bits. A digital-to-analog conversion circuit is configured to convert the digital signal into a current signal and feed it back to the stimulation current source of the target electrode.

2. The apparatus according to claim 1, characterized in that, The voltage change sensing circuit includes a comparator; The first input terminal of the comparator receives the electrode voltage, and the second input terminal receives the preset threshold voltage. The comparator compares the detected electrode voltage with the preset threshold voltage, and outputs the enable signal through the output terminal in response to the electrode voltage being greater than the preset threshold voltage.

3. The apparatus according to claim 2, characterized in that, The first input terminal is a positive input terminal, and the second input terminal is a negative input terminal; the enable signal output by the comparator is high level; or the first input terminal is a negative input terminal, and the second input terminal is a positive input terminal; the enable signal output by the comparator is low level.

4. The apparatus according to claim 1, characterized in that, The voltage-time conversion circuit includes a symmetrically distributed first charge-discharge unit and a second charge-discharge unit. The input terminal of the first charging and discharging unit receives the electrode voltage, and the output terminal reflects the charging and discharging status of the first charging and discharging unit; the input terminal of the second charging and discharging unit receives the preset threshold voltage, and the output terminal reflects the charging and discharging status of the second charging and discharging unit. The voltage-time conversion circuit utilizes the voltage difference between the electrode voltage and the preset threshold voltage to cause different discharge rates in the discharge circuits within the two units, thereby converting it into a time difference signal between the output terminals of the first charge-discharge unit and the second charge-discharge unit. The time difference signal output by the output terminal of the first charge-discharge unit is an electrode time domain signal, and the time difference signal output by the output terminal of the second charge-discharge unit is a threshold time domain signal.

5. The apparatus according to claim 1, characterized in that, The time-to-digital conversion circuit includes: multiple levels of delay chains, registers that have one more level than the delay chains, and a binary encoder; Each level of the register uses the threshold time-domain signal as a clock trigger signal to sample the nodes of the corresponding level circuit on the delay chain to obtain the first target code; wherein, the last level of the register samples the output of the last level on the delay chain to obtain the second target code; The binary encoder converts the multi-level target encoding into binary output of the digital signal.

6. The apparatus according to claim 5, characterized in that, The delay chain includes: multiple inverters connected in series; Each stage of the register samples the input of the corresponding level inverter in the delay chain to obtain the first target code, and the last stage of the register samples the output of the last stage inverter in the delay chain to obtain the second target code.

7. The apparatus according to claim 5, characterized in that, Each level of register includes: each flip-flop that is one level higher than the number of stages in the delay chain; The clock terminal of the trigger uses the threshold time domain signal as the clock trigger signal, and samples the nodes of the corresponding level circuit on the delay chain through the data trigger terminal to obtain the first target code. The last stage of the trigger samples the output terminal of the last stage on the delay chain to obtain the second target code.

8. The apparatus according to claim 5, characterized in that, The binary encoder includes: a logic operation device; The logic processing device is configured to perform logical operations on the target codes of all levels of output, achieve position compression, and output the digital signal.

9. An active charge balancing method, characterized in that, include: The magnitude of the change in the electrode voltage of the target electrode is sensed, and an enable signal is output in response to the change in the electrode voltage exceeding the expectation. The system starts working according to the enable signal, and converts the electrode voltage and the preset threshold voltage into electrode time-domain signal and threshold time-domain signal respectively. Convert the electrode time-domain signal and the threshold time-domain signal into a digital signal with a preset number of bits; The digital signal is converted into a current signal and fed back to the stimulation current source of the target electrode.

10. A chip, characterized in that, include: The apparatus according to any one of claims 1 to 8.

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