A method for path optimization of integrated circuit test cost
By using a multi-station vision camera and encoder integrated circuit testing method, the problems of high false negative rate, low detection accuracy and measurement drift in chip sorting and inspection have been solved, achieving efficient and accurate three-dimensional defect detection, reducing costs and improving production efficiency.
Patent Information
- Application Number
- CN202611545248.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-10-08
- Publication Date
- 2026-11-06
AI Technical Summary
Existing chip sorting and inspection solutions suffer from problems such as high false negative rate, low inspection accuracy, long processing time due to lack of process grading, poor parameter control capability, and easy drift in measurement accuracy. In particular, they are difficult to identify three-dimensional defects and achieve efficient inspection in 3D inspection.
The sorting equipment uses a multi-station vision camera and encoder. It uses a 2D camera to establish a template positioning model for error-proof detection and initial inspection of the plastic packaging appearance. Combined with the encoder to record the material position in real time, it skips the 3D scanning of defective products and uses a 3D camera to perform precise three-dimensional size detection, dynamically compensating for measurement errors caused by temperature drift and mechanical offset.
It significantly reduces the overall testing cost and cycle time, improves the coverage and accuracy of defect detection, and ensures the high stability and high precision of the system in mass production.
Smart Images
Figure CN123039082A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor packaging and testing, and specifically relates to a path optimization method for integrated circuit testing costs. Background Technology
[0002] In the back-end packaging and sorting inspection of semiconductor integrated circuits, the quality of chip pins and appearance directly determines the device mounting yield and reliability. Existing chip sorting and inspection solutions are mainly divided into two categories: pure 2D vision inspection and simple single-line 3D inspection, both of which have the following significant drawbacks: 1. Limitations of pure 2D vision inspection: It can only acquire planar grayscale images and cannot identify three-dimensional defects such as poor coplanarity of pins, pin warping, height difference, three-dimensional burrs, and dents. The detection rate of three-dimensional defects is high. 2. Traditional single 3D detection and positioning has low accuracy: Without 2D image-assisted positioning, when the chip is shifted or rotated during transmission, it is impossible to accurately lock the pin detection ROI, resulting in misalignment of the 3D scanning area and large measurement deviation. 3. Lack of process hierarchy leads to long CT time: Conventional 3D inspection uses a single station for acquisition, without segmented error prevention and pre-inspection. Invalid materials such as reverse material, broken plastic seal, and defective characters flow into the 3D inspection station, wasting 3D scanning capacity and extending the overall machine cycle time (CT). 4. Precision is prone to drift: The existing 3D calibration mechanism lacks standard calibration block multi-baseline calibration. After long-term operation, it is affected by temperature drift and mechanical offset, and the measurement accuracy of pin height and coplanarity drifts, resulting in batch misjudgment. 5. Poor parameter control capability: It lacks the logic for splitting pins in different regions. Multiple pins on the left and right / top and bottom share the same set of detection parameters, making it impossible to control dimensional tolerances by region. Summary of the Invention
[0003] To address the above shortcomings, this invention provides a path optimization method for integrated circuit testing costs. This method is applied to sorting equipment equipped with encoders and multi-station vision cameras, and includes the following steps: S1. Error-proof detection of feeding direction: The chip image is acquired by the first 2D camera, a template positioning model is established and the chip matching parameters are obtained to determine whether the chip feeding direction is abnormal; if abnormal, the first NG mark is generated and the rejection signal is output. S2. Initial inspection of the molded body appearance: The second 2D camera is used to detect the molded body and characters of the chip with the correct feeding orientation; the outer contour of the molded body is fitted to determine the reference area, and surface defects and character defects are identified. If defects are present, a second NG mark is generated and a rejection signal is output. S3, 3D pin solid dimension precision detection: The encoder records the physical position of the material in real time. If the material has the first NG mark or the second NG mark, the 3D camera is controlled to skip scanning the material. For materials without NG marks, the pin reference coordinates are locked by the template positioning model. The chip pin is divided into multiple independent detection areas and different detection parameters are configured. 3D point cloud data is collected and the pin solid dimension features are calculated. S4. Full re-inspection of finished tape and reel products: The material that has passed the 3D inspection is inspected by a fourth 2D camera to check the layered pin dimensions, secondary plastic packaging appearance and secondary character matching to determine the quality of the final product. S5. Dynamic drift compensation: During system calibration or operation, the global accuracy coefficient and mirror compensation coefficient matrix are calculated based on the standard calibration block. When temperature drift or mechanical offset deviation is detected, the encoder pulse count and 3D measurement calibration matrix are corrected in real time.
[0004] Furthermore, the determination logic in step S1 is as follows: The chip rotation angle is obtained by matching the template positioning model and comparing it with the preset reference angle. If the X / Y pixel deviation or angle deviation exceeds the set threshold, it is determined to be a reverse defect.
[0005] Furthermore, the determination logic in step S1 is as follows: Using the template positioning model as the positioning follower, a region of interest (ROI) is drawn in the plastic seal hypotenuse area. The hypotenuse angle is fitted and compared with a preset reference angle range to complete the orientation determination.
[0006] Furthermore, the skip scan and rejection control mechanism in step S3 is as follows: S301, the assembly line synchronous encoder records the number of pulses of the material on the conveying medium in real time; S302. When it is determined in step S1 or S2 that the first NG mark or the second NG mark is generated, the main control system marks the encoder pulse position register corresponding to the material as NG. S303. When the pulse position reaches the 3D workstation, the main control system sends a skip instruction to the PLC, and the 3D camera does not trigger acquisition. S304. When the pulse position reaches the physical rejection position, the PLC reads the mark and controls the actuator to reject the NG material.
[0007] Furthermore, the pin splitting and 3D feature calculation in step S3 includes: Region splitting: The chip pins are independently split into six independent detection regions: middle left pin, middle right pin, outer left pin, outer right pin, outer upper pin, and outer lower pin. Each region is configured with a threshold and region of interest (ROI). Standing height calculation: Using the lower surface of the chip's plastic package or the reference carrier surface as the point cloud reference plane, calculate the vertical distance from the lowest point cloud coordinate of each pin to the reference plane. Coplanarity calculation: The least squares method is used to fit a virtual least squares plane in space where the lowest point of all pins is located. The absolute distance difference from the lowest point of each pin to the virtual plane is calculated, and the maximum difference is used as the coplanarity value. Collinearity calculation: Fit the same straight line on the outer edge of a single pin on a 2D projection plane, and calculate the orthogonal deviation distance from the feature points on the edge of each pin to the fitted straight line.
[0008] Furthermore, step S3 also includes a pre-process 3D calibration and correction procedure: Collect point clouds of calibration blocks with standard reflectivity and known micrometer-level step height; By comparing the actual height of the collected point cloud with the standard step height, the light intensity distortion difference is calculated, and a spatially gridded mirror compensation coefficient matrix is generated. During mass production testing, the mirror compensation coefficient matrix is used to perform real-time interpolation noise reduction and truncation repair on the point cloud height value of the highly reflective area on the pin surface. Multiple sets of reference lines are laid out on the calibration block, and pixel-to-micron conversion coefficients are calculated based on the standard physical dimensions of the calibration block.
[0009] Furthermore, the dynamic drift compensation in step S5 includes: S501. Place a standard square calibration block and draw the pixel dimensions of the length caliper and width caliper. S502, Input the actual physical size of the calibration block and calculate the global accuracy coefficient of CCD pixels-micrometers; S503. Compare the currently measured global accuracy coefficient with the factory reference coefficient, and add the deviation value as a real-time dynamic correction factor to the encoder pulse count and 3D measurement calibration matrix to automatically compensate for measurement errors caused by temperature drift and mechanical offset.
[0010] Compared with the prior art, the present invention has the following advantages: 1. Implemented path optimization by eliminating prerequisites, significantly reducing overall system testing costs and cycle time (CT): This invention uses a synchronous encoder on the production line to track the material position in real time. It binds the defective product marks determined by the error-proof process in the feeding direction (S1) and the initial inspection process of the plastic packaging appearance (S2) to the encoder pulse register. Before the preceding NG material reaches the 3D inspection station, the main control system automatically issues a skip instruction to control the 3D laser camera not to trigger acquisition and scanning. Since the acquisition of 3D point cloud data and the calculation of complex three-dimensional geometric features take the longest time in the inspection process, this invention eliminates the invalid inspection time of defective products by intercepting and skipping the 3D scanning of the preceding NG material in advance. It significantly shortens the average cycle time (CT) of the whole machine in terms of logic and timing, reduces the hardware wear and inspection cost of the sorting equipment, and improves the overall inspection throughput. 2. It achieves deep integration of 2D visual positioning and 3D stereoscopic inspection, significantly improving defect detection coverage: Traditional inspection methods rely on a single visual dimension, which can easily lead to missed detections of defects in the height direction (Z-axis), such as pin coplanarity, warping, height, and three-dimensional burrs. This invention first uses a 2D template positioning model to complete high-precision planar coordinate tracking and pin independent region segmentation. Then, it combines 3D laser point cloud measurement and spatial mirror compensation repair algorithm to accurately calculate three-dimensional features such as height, coplanarity, and collinearity. This architecture overcomes the blind spots of three-dimensional defect omission caused by the lack of depth data in traditional pure 2D inspection, and greatly improves the accuracy and reliability of pin defect detection for complex packaged chips. 3. Possesses robust calibration denoising and dynamic drift compensation capabilities: By generating a spatially gridded mirror compensation coefficient matrix, the light intensity distortion and point cloud noise caused by the high reflectivity of the chip's metal pins are effectively eliminated. At the same time, combined with the dynamic drift compensation step (S5), the measurement deviation caused by temperature drift or mechanical micro-displacement during long-term operation of the equipment can be automatically corrected, ensuring the high precision and high stability of the system in the process of large-scale continuous production. Attached Figure Description
[0011] Figure 1 This is a flowchart of the present invention.
[0012] Figure 2 This is a detailed flowchart of the skip control and 3D detection process in step S3 of the present invention. Detailed Implementation
[0013] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0014] Example
[0015] like Figure 1 As shown, this embodiment provides a path optimization method for integrated circuit testing costs, applied to a sorting device equipped with encoders and multi-station vision cameras. The sorting device's hardware is based on four CCD cameras for station-specific acquisition: a first 2D camera (CCD1, feeding direction station), a second 2D camera (CCD2, B-disc packaging appearance station), a 3D laser contour camera (CCD3, 3D precision measurement station), and a fourth 2D camera (CCD4, tape and reel finishing station), along with supporting vision software and a production line synchronous encoder.
[0016] The path optimization method utilizes the aforementioned hardware to implement the following four-stage detection steps: S1. Error-proof detection for feed direction The first 2D camera acquires a grayscale image of the chip, draws a global search area for the product, selects the pins to establish a template positioning model, limits the search to a full-angle range of -180° to 180° and obtains chip matching parameters, and determines whether the chip feeding orientation is abnormal. Judgment Logic Scheme A: Match the template positioning model to obtain the chip rotation angle, compare it with the preset reference angle (0° / 90° / 180° / 270°), limit the X / Y pixel deviation and angle deviation thresholds, if it exceeds the set threshold, it is judged as reverse defect, and the first NG mark is generated; Judgment Logic Scheme B: Using the template positioning model as the positioning follower, draw the region of interest (ROI) for finding the line in the plastic seal slant area, fit the slant angle and compare it with the preset benchmark angle range to complete the orientation determination; if they do not match, it is judged as a reverse defect and a first NG mark is generated; The correct material flows into the next station, while the defective material generates the first NG mark and directly outputs a rejection signal. S2. Initial inspection of the appearance of the encapsulated body The second 2D camera detects the encapsulation and characters on the chip with the correct feed orientation. A template positioning model is used to lock the encapsulation, and a rectangular caliper is used to fit the outer contour of the encapsulation to determine the reference area. S201, Laser Engraved Character Detection: Draw the character search area and character segmentation area, train standard character templates, set character similarity and minimum area threshold for scratches, and identify missing characters, blurred characters and surface scratches. S202, Plastic Seal Damage Detection: Using a rectangular fitting area as the outer surface detection ROI, setting the grayscale range of black and white defects and the area tolerance of fragments, to identify plastic seal chipping, missing material, dents and foreign objects; S203. For chips with defective characters or damaged plastic packaging, a second NG mark is generated and a rejection signal is output; good materials flow into the 3D pin inspection station. S3, 3D pin stereoscopic dimension precision inspection This step utilizes the encoder and the preceding workstation in series to achieve path optimization and 3D precision measurement, eliminating the previous steps. The specific implementation process is executed sequentially as follows: S301, the assembly line synchronous encoder records the number of pulses representing the physical position of materials on the conveying medium (such as a belt) in real time; S302. When it is determined in step S1 or step S2 that a first NG mark or a second NG mark is generated, the main control system marks the encoder pulse position register corresponding to the material as NG. S303. Before the encoder pulse position reaches the 3D workstation (CCD3), the main control system queries the material marking status at that position and processes it accordingly: S3031, Skip Control Branch: If the material has a first NG mark or a second NG mark, the main control system sends a skip instruction to the PLC, controlling the 3D camera not to trigger acquisition and directly skipping the 3D point cloud scan of the NG material, thereby greatly shortening the overall cycle time (CT). S3032, Pre-processing 3D Calibration and Noise Reduction: For good materials without NG marks, the main control system controls the 3D camera to trigger acquisition. Before mass production testing, the equipment collects a point cloud of a calibration block with standard reflectivity and known micron-level step height. The actual point cloud height is compared with the standard height, and the light intensity distortion difference is calculated to generate a spatially gridded mirror compensation coefficient matrix. Multiple sets of reference lines (center 1 / center 2 / center 3 and left and right side reference lines) are laid on the calibration block. The pixel-to-micron conversion coefficient is calculated in combination with the standard physical dimensions. When the S3032 triggers acquisition, the mirror compensation coefficient matrix is used to perform real-time interpolation noise reduction and truncation repair on the point cloud height value of the high reflectivity area on the pin surface. In addition, the above standard calibration block can be replaced with a ceramic standard package of the same material as the chip under test. The ceramic standard package can be used directly for 3D calibration and compensation coefficient matrix generation to eliminate the material reflectivity difference between the metal pins and the ordinary calibration block. S3033, 2D Template Following and Independent Pin Partitioning: Utilizing a template positioning model to lock the pin reference coordinates (limited to ±25° small angle search). The chip pins are independently divided into six detection regions: middle left pin, middle right pin, outer left pin, outer right pin, outer upper pin, and outer lower pin; each region is plotted as a separate region of interest (ROI), and each region is configured with its own pin grayscale threshold, segmentation threshold, glitch filter value, and tolerance. S3034, 3D Feature Calculation and Judgment: Collect the repaired point cloud data and calculate the following respectively: Standoff: Using the lower surface of the chip's plastic package or the reference carrier surface as the reference reference plane for the point cloud, calculate the vertical distance from the lowest point cloud coordinate of each pin to this reference reference plane; Coplanarity: The least squares method is used to fit a virtual least squares plane in space containing the lowest points of all pins. The absolute distance difference from the lowest point of each pin to the virtual plane is calculated, and the maximum difference is used as the coplanarity value of the entire chip. Collinearity: Fits the same straight line on the outer edge of a single pin on a 2D projection plane, and calculates the orthogonal deviation distance from the feature points of each pin edge to the fitted straight line; If any of the above dimensions exceeds the preset tolerance, the main control system will update and mark the material as a 3D NG material. In addition, the geometric feature judgment logic based on size threshold can be replaced by PointNet point cloud AI deep learning model. The 3D point cloud data after S3032 repair is directly input into the pre-trained PointNet model to realize intelligent classification and recognition of pin micro three-dimensional burrs, bending and surface micro pit defects. S304. When the encoder pulse position with an NG mark (including the NG mark generated in the preceding S1 / S2 or the 3D NG mark determined in S3034) reaches the physical rejection position, the PLC reads the NG mark and controls the actuator (such as the pneumatic rejection valve to close) to physically reject the corresponding NG material. S4. Complete re-inspection of finished tape and ribbon products. The fourth 2D camera performs final quality control on materials that have passed 3D inspection: S401. Use the template positioning model and rectangular calipers again to lock the plastic-sealed body; S402, Layered Pin Inspection: Differentiate between upper and lower pin areas, and re-measure the plane pin dimensions, missing pins, and plane damage; S404. Secondary Appearance and Character Re-inspection: Use the rectangular area of the plastic seal to detect surface scratches and corner defects, and perform secondary matching and verification of laser-engraved characters; S404, OK materials after re-inspection flow into the receiving box; materials deemed NG by any workstation output IO signals and are graded and rejected by the PLC; S5, Dynamic Drift Compensation During system periodic calibration or pre-mass production calibration, the following sub-steps automatically compensate for measurement errors caused by temperature drift or mechanical offset: S501. Place a standard square calibration block, turn on calibration mode, draw a length caliper (arrow to the right) and a width caliper (arrow to the up) respectively, and collect pixel length and width values; S502: Input the actual physical size of the calibration block (mm / µm), calculate the global accuracy coefficient of CCD pixel-µm, and unify the measurement units of all dimensions of the whole machine; S503. Compare the currently measured global accuracy coefficient with the system's factory reference coefficient. If there is a deviation, use the deviation value as a real-time dynamic correction factor and add it to the encoder pulse count and 3D measurement calibration matrix to automatically compensate for image distortion and dimensional measurement errors caused by temperature drift and mechanical displacement.
[0017] It should be noted that the 3D laser camera and the second 2D camera can be coaxially integrated, merging the plastic packaging appearance inspection station and the 3D precision measurement station, thus reducing the number of CCD hardware components.
[0018] If the production line only needs to detect the pin size, the S2 station can be omitted, and only the orientation error prevention in S1, the 3D detection in S3, and the tape re-inspection in S4 need to be retained.
[0019] It should be noted that the structure described in this invention can be implemented in many different forms and is not limited to the embodiments described. Any equivalent transformations made by those skilled in the art based on the description and drawings of this invention, or direct or indirect applications in other related technical fields, such as the loading and unloading of other items, are included within the protection scope of this invention.
Claims
1. A method of path optimization for integrated circuit test cost, characterized by, This method is applied to sorting equipment equipped with encoders and multi-station vision cameras, and includes the following steps: S1. Error-proof detection of feeding direction: The chip image is acquired by the first 2D camera, a template positioning model is established and the chip matching parameters are obtained to determine whether the chip feeding direction is abnormal; if abnormal, the first NG mark is generated and the rejection signal is output. S2. Initial inspection of the molded body appearance: The second 2D camera is used to detect the molded body and characters of the chip with the correct feeding orientation; the outer contour of the molded body is fitted to determine the reference area, and surface defects and character defects are identified. If defects are present, a second NG mark is generated and a rejection signal is output. S3, 3D pin solid dimension precision detection: The encoder records the physical position of the material in real time. If the material has the first NG mark or the second NG mark, the 3D camera is controlled to skip scanning the material. For materials without NG marks, the pin reference coordinates are locked by the template positioning model. The chip pin is divided into multiple independent detection areas and different detection parameters are configured. 3D point cloud data is collected and the pin solid dimension features are calculated. The skip scan and rejection control mechanism in step S3 is as follows: S301, the assembly line synchronous encoder records the number of pulses of the material on the conveying medium in real time; S302. When it is determined in step S1 or S2 that the first NG mark or the second NG mark is generated, the main control system marks the encoder pulse position register corresponding to the material as NG. S303. When the pulse position reaches the 3D workstation, the main control system sends a skip instruction to the PLC, and the 3D camera does not trigger acquisition. S304. When the pulse position reaches the physical rejection position, the PLC reads the mark and controls the actuator to reject the NG material. S4. Full re-inspection of finished tape and reel products: The material that has passed the 3D inspection is inspected by a fourth 2D camera to check the layered pin dimensions, secondary plastic packaging appearance and secondary character matching to determine the quality of the final product. S5. Dynamic drift compensation: During system calibration or operation, the global accuracy coefficient and mirror compensation coefficient matrix are calculated based on the standard calibration block. When temperature drift or mechanical offset deviation is detected, the encoder pulse count and 3D measurement calibration matrix are corrected in real time.
2. The method of claim 1, wherein: The determination logic in step S1 is as follows: The chip rotation angle is obtained by matching the template positioning model and comparing it with the preset reference angle. If the X / Y pixel deviation or angle deviation exceeds the set threshold, it is determined to be a reverse defect.
3. The method for optimizing the path of integrated circuit testing costs as described in claim 1, characterized in that: The determination logic in step S1 is as follows: Using the template positioning model as the positioning follower, a region of interest (ROI) is drawn in the plastic seal hypotenuse area. The hypotenuse angle is fitted and compared with a preset reference angle range to complete the orientation determination.
4. The method for optimizing the path of integrated circuit testing costs as described in claim 1, characterized in that: The pin splitting and 3D feature calculation in step S3 include: Region splitting: The chip pins are independently split into six independent detection regions: middle left pin, middle right pin, outer left pin, outer right pin, outer upper pin, and outer lower pin. Each region is configured with a threshold and region of interest (ROI). Standing height calculation: Using the lower surface of the chip's plastic package or the reference carrier surface as the point cloud reference plane, calculate the vertical distance from the lowest point cloud coordinate of each pin to the reference plane. Coplanarity calculation: The least squares method is used to fit a virtual least squares plane in space where the lowest point of all pins is located. The absolute distance difference from the lowest point of each pin to the virtual plane is calculated, and the maximum difference is used as the coplanarity value. Collinearity calculation: Fit the same straight line on the outer edge of a single pin on a 2D projection plane, and calculate the orthogonal deviation distance from the feature points on the edge of each pin to the fitted straight line.
5. The method for optimizing the path of integrated circuit testing costs as described in claim 1, characterized in that: Step S3 also includes a pre-process 3D calibration and correction: Collect point clouds of calibration blocks with standard reflectivity and known micrometer-level step height; By comparing the actual height of the collected point cloud with the standard step height, the light intensity distortion difference is calculated, and a spatially gridded mirror compensation coefficient matrix is generated. During mass production testing, the mirror compensation coefficient matrix is used to perform real-time interpolation noise reduction and truncation repair on the point cloud height value of the highly reflective area on the pin surface. Multiple sets of reference lines are laid out on the calibration block, and pixel-to-micron conversion coefficients are calculated based on the standard physical dimensions of the calibration block.
6. The method for optimizing the path of integrated circuit testing costs as described in claim 1, characterized in that: The dynamic drift compensation in step S5 includes: S501. Place a standard square calibration block and draw the pixel dimensions of the length caliper and width caliper. S502, Input the actual physical size of the calibration block and calculate the global accuracy coefficient of CCD pixels-micrometers; S503. Compare the currently measured global accuracy coefficient with the factory reference coefficient, and add the deviation value as a real-time dynamic correction factor to the encoder pulse count and 3D measurement calibration matrix to automatically compensate for measurement errors caused by temperature drift and mechanical offset.