Parallel silicon carbide MOSFET current sharing screening method

Abstract

The application provides a parallel silicon carbide MOSFET current sharing screening method, comprising screening threshold voltages based on voltage intervals in a device set to be screened, obtaining a classified device set screened based on distance threshold voltage, and respectively obtaining a threshold voltage variation and a voltage tolerance curve variation of each device in the classified device set; based on the working condition, the threshold voltage variation and the voltage tolerance curve variation, using clustering analysis to classify the devices in the classified device set to obtain a parallel device group. The device screened by the method has low discrete degradation degree, good sorting matching effect, and can reduce the parallel current imbalance and the device current overshoot caused by uneven transient current distribution when used in parallel application, reduce the risk of the device exceeding the safe operation area, and reduce the risk of thermal runaway caused by the inconsistent temperature rise of the parallel devices due to the difference in current distribution.

Description

Technical Field

[0001] This application relates to the technical field, specifically to a method for screening current sharing of parallel silicon carbide MOSFETs. Background Technology

[0002] Due to the superior material properties of silicon carbide, compared with silicon-based insulated gate bipolar transistors, silicon carbide-based power metal-oxide-semiconductor field-effect transistors have advantages such as lower switching losses, higher operating frequencies, and faster switching speeds. These characteristics make silicon carbide MOSFETs widely used in various high-frequency and high-capacity power electronic converters.

[0003] However, for high-capacity applications such as electric vehicles and photovoltaics, the current capacity of a single power device is insufficient to meet the system's high current requirements. Therefore, it is necessary to connect multiple discrete devices or modules in parallel to overcome the current bottleneck. For multi-chip parallel applications, uneven current distribution has always been a significant problem. Because the interface state density of the SiC / SiO2 system in silicon carbide MOSFETs is significantly higher than that of the Si / SiO2 system, and silicon carbide materials have a lower barrier height, when devices are subjected to high temperatures and electric field stress for extended periods, the degree of degradation between devices in parallel modules varies, causing uneven parallel current. Current imbalance is generally divided into static imbalance and transient imbalance; uneven transient current distribution can lead to device current overshoot, posing a risk of exceeding the safe operating range. Furthermore, differences in current distribution can also lead to inconsistent temperature rises between parallel devices, potentially inducing thermal runaway.

[0004] In recent years, many scholars have explored the influencing factors of current shunting in parallel devices. These factors are mainly categorized into three types: device parameters, power circuit parameters, and drive circuit parameters. While the influence of device parameters on current shunting in parallel devices has been extensively studied, some shortcomings remain. Many scholars have investigated the impact of initial threshold voltage mismatch on current shunting in parallel devices and proposed methods to screen chips with similar threshold voltages for parallel connection to reduce the impact of initial threshold voltage differences on parallel current shunting. While this classification is effective, it relies on the assumption that device parameters remain constant, which is unreasonable in practice. Electrical and thermal stresses can cause aging of the device's gate oxide layer, thereby altering the device parameters. Existing mainstream parallel device screening schemes rely solely on static parameters such as initial threshold voltage and transfer characteristics, or only supplement the threshold drift after short-term aging for clustering and sorting. This fails to fully characterize the dynamic current sharing evolution under long-term parallel operation, resulting in significant limitations in the sorting and matching effect. Summary of the Invention

[0005] This application addresses the problems existing in the prior art by providing a method that simultaneously incorporates threshold voltage drift induced by gate oxide aging and Ciss - V G The current sharing screening method for parallel silicon carbide MOSFETs based on two types of degradation characteristics of curve offset overcomes the limitations of existing studies that only analyze the influence of a single parameter. It has good sorting and matching effect, and the degradation degree of the screened silicon carbide MOSFETs has low dispersion. When used in parallel and subjected to high temperature and electric field stress for a long time, it can reduce the imbalance of parallel current and the device current overshoot caused by uneven transient current distribution, reduce the risk of the device exceeding the safe operating area, and reduce the risk of thermal runaway caused by inconsistent temperature rise due to current distribution differences in parallel devices.

[0006] To achieve the above objectives, the technical solution adopted in this application is as follows: a parallel silicon carbide MOSFET current sharing screening method, which obtains a set of devices to be screened, wherein the set of devices to be screened represents a collection of silicon carbide MOSFETs to be screened; and obtains the operating conditions, voltage range and distance threshold respectively. The threshold voltage and capacitive voltage curves of each device in the set of devices to be screened are obtained respectively. The capacitive voltage curve represents the curve of gate input capacitance changing with gate voltage. The device set to be screened is obtained by screening threshold voltage based on voltage range and capacitive voltage curve based on distance threshold from the set of devices to be screened. Based on the classification and screening of the device set, the threshold voltage change and capacitive voltage curve change of each device are obtained. The threshold voltage change represents the difference between the threshold voltage of the device in the aged state and the unaged state, and the capacitive voltage curve change represents the average offset of the capacitive voltage curve of the device in the aged state and the unaged state. Based on operating conditions, threshold voltage changes, and capacitive voltage curve changes, cluster analysis is used to classify the devices in the device set to obtain parallel device groups.

[0007] In some embodiments, the voltage range includes a first voltage range and a second voltage range, with the second voltage range located within the first voltage range; the distance threshold includes a first distance threshold and a second distance threshold, with the second distance threshold being less than the first distance threshold. The device set to be screened is obtained by screening threshold voltages based on voltage ranges and capacitive-voltage curves based on distance thresholds, including: The first threshold voltage and the first capacitive voltage curve of each device in the set of devices to be screened are obtained respectively. The first threshold voltage represents the threshold voltage in the unaged state, and the first capacitive voltage curve represents the capacitive voltage curve in the unaged state. The first threshold voltage is selected based on the first voltage range in the set of devices to be screened, and the first capacitive voltage curve is selected based on the first distance threshold. The intersection of these two curves is then used to obtain an intermediate set of devices to be screened. Short-term gate stress was applied to each device in the intermediate screening device set, and the second threshold voltage and the second capacitive voltage curve of each device were obtained. The second threshold voltage represents the threshold voltage after applying short-term gate stress, and the second capacitive voltage curve represents the capacitive voltage curve after applying short-term gate stress. The intermediate screening device set is used to screen the second threshold voltage based on the second voltage range and the second capacitive voltage curve based on the second distance threshold, and the intersection is taken to obtain the classified screening device set.

[0008] In some embodiments, the threshold voltage change of each device is obtained based on the classification and screening of the device set, including: In the categorized and screened device set, the difference between the second threshold voltage and the first threshold voltage of each device is used as the threshold voltage change of the corresponding device.

[0009] In some embodiments, the change in the capacitive voltage curve of each device is obtained based on the classification and screening of the device set, including: In the categorized and screened device set, the average offset of the second capacitive voltage curve of each device relative to the first capacitive voltage curve is taken as the change in the capacitive voltage curve of the corresponding device.

[0010] In some embodiments, the first voltage range includes 0.1V to 0.3V.

[0011] In some embodiments, the second voltage range includes 0.001V to 0.2V.

[0012] In some of these embodiments, the first distance threshold is 0.01.

[0013] In some of these embodiments, the second distance threshold is 0.002.

[0014] In some embodiments, based on operating conditions, threshold voltage changes, and capacitive voltage curve changes, cluster analysis is used to classify devices in a screening device set to obtain parallel device groups, including: A sample dataset is generated based on the classification and screening of device sets, threshold voltage changes, and capacitive voltage curve changes. The sample dataset represents a collection of sample data, with the threshold voltage changes and capacitive voltage curve changes of each device serving as a sample dataset. Each sample data in the classification and screening device set is used as an initial cluster; Use the initial cluster as the current cluster; Calculate the Euclidean distance between any two current clusters to obtain the inter-cluster distance; Merge the current clusters with the smallest inter-cluster distance differences to obtain the updated clusters and the current clustering phylogenetic tree; Check if the number of updated clusters is 1; When the number of updated clusters is not 1, the updated cluster is taken as the current cluster, and the Euclidean distance between any two current clusters is calculated repeatedly to obtain the inter-cluster distance. When the number of clusters to be updated is 1, the current clustering phylogenetic tree is used as the output clustering phylogenetic tree; The threshold voltage change step size and the capacitive voltage curve change step size are obtained based on the operating conditions. The merging distance threshold is obtained based on the step size of the threshold voltage change and the step size of the capacitive voltage curve change; At least one parallel device group is obtained by cross-cutting the output clustering phylogenetic tree based on the merged distance threshold.

[0015] In some embodiments, based on operating conditions, threshold voltage changes, and capacitive voltage curve changes, cluster analysis is used to classify devices in a screening device set to obtain parallel device groups, including: The threshold voltage change step size and the capacitive voltage curve change step size are obtained based on the operating conditions. The merging distance threshold is obtained based on the step size of the threshold voltage change and the step size of the capacitive voltage curve change; A sample dataset is generated based on the classification and screening of device sets, threshold voltage changes, and capacitive voltage curve changes. The sample dataset represents a collection of sample data, with the threshold voltage changes and capacitive voltage curve changes of each device serving as a sample dataset. Each sample data in the classification and screening device set is used as an initial cluster; Use the initial cluster as the current cluster; Calculate the Euclidean distance between any two current clusters to obtain the inter-cluster distance; Determine whether the distance between any clusters is greater than the merge distance threshold; When the distance between any two clusters is not greater than the merging distance threshold, the current cluster with the smallest Euclidean distance difference is merged to obtain the updated cluster. The updated cluster is used as the current cluster, and the process is repeated to calculate the Euclidean distance between any two current clusters to obtain the inter-cluster distance. When the distance between any clusters is greater than the merging distance threshold, the components of the device corresponding to the current cluster are treated as a parallel device group.

[0016] Compared with the prior art, this application has the following advantages: 1. This application incorporates both gate oxide aging-induced threshold voltage drift and current sharing in the screening of parallel silicon carbide MOSFETs. C iss - V G The study identifies two types of degradation characteristics: curve offset and curve deviation. This approach overcomes the limitations of existing studies that only analyze the influence of a single parameter. It also shows low dispersion in the degree of degradation among parallel devices and good sorting and matching performance.

[0017] 2. When parallel devices obtained by the parallel silicon carbide MOSFET current sharing screening method proposed in this application are used in parallel applications, they can reduce the imbalance of parallel current and the device current overshoot caused by uneven transient current distribution when subjected to high temperature and electric field stress for a long time. This reduces the risk of the device exceeding the safe operating area and also reduces the risk of thermal runaway caused by inconsistent temperature rise due to current distribution differences in parallel devices. Attached Figure Description

[0018] Figure 1 This is a flowchart illustrating the current sharing and screening method for parallel silicon carbide MOSFETs in the embodiments of the application. Figure 2 PBTI-type degradation of silicon carbide MOSFETs in the embodiments of this application C iss - V G Curve variation graph; Figure 3 NBTI-type degradation of silicon carbide MOSFETs in the embodiments of this application C iss - V G Curve variation graph; Figure 4 This is a parallel silicon carbide MOSFET device dual-pulse test circuit built in the Ltspice simulation software in the embodiments of this application; Figure 5 This is a graph showing the change of drain current over time during the turn-on process in the simulation experiment of the embodiments of this application; Figure 6 This is a comparison of the overshoot current changes during the opening process in the first group of control simulation experiments in the embodiments of this application; Figure 7 This is a comparison of the overshoot current changes during the start-up process in the second set of control simulation experiments in the embodiments of this application. Detailed Implementation

[0019] The reliability issues of SiC MOSFETs are mainly divided into chip-level failures and package-level failures, with chip-level failures primarily stemming from the gate oxide layer. In SiC MOSFETs, the gate oxide layer is a critical component, acting as an isolation layer between the gate and the channel to ensure normal device operation. However, due to the harsh operating conditions of SiC MOSFETs, the gate oxide layer is susceptible to degradation or damage from factors such as high temperature, electric field stress, and oxide defects, thus affecting device parameters. When the device is subjected to prolonged high temperature and electric field stress, the degradation of the gate oxide layer in the silicon carbide MOSFET can cause threshold voltage drift and... C iss - VG The displacement of the curve. Through numerous experiments, the inventors discovered that in parallel modules, the degree of degradation between devices exhibits dispersion, with the threshold voltage and... C iss - V G Inconsistent deviations in the curves can cause imbalances in parallel currents.

[0020] Compared to Si MOSFETs, SiC MOSFETs, due to their less mature manufacturing process, contain numerous traps in the gate oxide near the channel region. Charge is trapped or released within these traps, leading to unstable threshold voltage. The threshold voltage is: ; In the formula, Threshold voltage, It is a flat band voltage. For intrinsic Fermi level, The dielectric constant of silicon carbide is... For elementary charge, To achieve the effective channel doping concentration, The capacitance per unit area of ​​the gate oxide layer, The charge density of oxides, The difference in work function between the metal and the semiconductor; To address long-term gate oxide reliability issues under normal operating conditions, the device manufacturing industry widely employs bias temperature instability (BTI) testing to evaluate gate oxide reliability. Considering the stress the gate experiences during actual device operation, in addition to typical DC bias temperature instability testing, researchers have recently proposed AC bias temperature instability testing to assess gate oxide reliability under AC gate stress. Compared to DC bias instability testing, silicon carbide devices exhibit more severe threshold voltage instability under AC gate stress. Here, AC gate stress specifically refers to bipolar AC stress where the positive drive voltage is greater than the threshold voltage in the on-state and the negative drive voltage is lower than the flat-band voltage in the off-state. In bipolar gate switches, the gate oxide electric field is locally enhanced, thus accelerating the threshold voltage shift. This is because the threshold voltage is affected by trap density; as the positive gate bias increases, the valence band... E V This means that acceptor traps increase near the energy band corresponding to the outermost valence electron energy level of semiconductor atoms; when the negative gate voltage decreases, the conduction band above the JFET region... E CThis means an increase in donor traps near the lowest allowed energy band above the valence band; the higher the trap density, the higher the concentration of trapped holes or electrons, corresponding to an increase in the local electric field. In other words, according to the expression for the threshold voltage, an increase in trap density leads to an increase in oxide charge density. A more significant reduction leads to a greater increase in the threshold voltage.

[0021] The gate input capacitance of the SiC MOSFET is: ; In the formula, For the gate input capacitance, Gate-source capacitance, Gate-drain capacitance, The capacitance between the gate and source electrodes. This is the capacitance between the gate and the n+ source. The capacitance between the gate and the top of the p-well region. For the depletion layer capacitance of the p-well region, The oxide layer capacitance between the gate and drain electrodes. This is the drain depletion layer capacitance beneath the gate oxide layer; The gate input capacitance is strongly correlated with the gate voltage. When the gate oxide layer degrades under stress... C iss - V G The curve shifts. When PBTI-type degradation occurs, the voltage is positively biased, and negative charges are injected into the gate oxide layer. The total negative well charge injected into the gate oxide layer is equivalent to an additional negative voltage on the gate. This reduces the effective bias applied to the gate and results in a flat-band voltage. and interface trap offset voltage Forward shift. Correspondingly, C iss - V G The curve shifts to the right. Similarly, when NBTI-type degradation occurs, positive charges are injected into the gate oxide layer. The positive charges injected into the gate oxide layer increase the effective bias voltage on the gate, ultimately leading to... C iss - V G The curve shifts to the left. Based on the above analysis, Figure 2 , Figure 3 The degradation patterns of PBTI and NBTI types were plotted separately. C iss - V GThe theoretical changes in the curve characteristics are shown in the figure. S21 and S31 represent the unaged state, and S22 and S32 represent the aged state. When the silicon carbide MOSFET undergoes PBTI-type degradation... C iss - V G The curve shifts to the right when the silicon carbide MOSFET undergoes NBTI-type degradation. C iss - V G The curve shifts to the left.

[0022] Existing mainstream parallel device screening schemes rely solely on static parameters such as initial threshold voltage and transfer characteristics, or only supplement the threshold drift after short-term aging for clustering and sorting, completely ignoring the synchronous gate oxide degradation. C iss - V G This core degradation feature, curve offset, failed to... C iss - V G As a classification variable, curve offset cannot fully characterize the dynamic current sharing evolution law under long-term parallel operation of devices, resulting in obvious limitations in sorting and matching effects.

[0023] To clearly illustrate the technical features of this solution, the implementation methods of this application will be described in detail below with reference to the accompanying drawings and embodiments. This will allow for a full understanding and implementation of how this application uses technical means to solve technical problems and achieve corresponding technical effects. The embodiments of this application and the various features within them can be combined with each other without conflict, and the resulting technical solutions are all within the protection scope of this application.

[0024] A current sharing screening method for parallel silicon carbide MOSFETs is provided, which involves obtaining a set of devices to be screened, characterized by a collection of silicon carbide MOSFETs to be screened; and obtaining the operating conditions, voltage range, and distance threshold respectively. Obtain the threshold voltage and capacitive voltage curves for each device in the device set to be screened. C iss - V G The capacitive-voltage curve represents the change of gate input capacitance with gate voltage. The device set to be screened is obtained by screening threshold voltage based on voltage range and capacitive voltage curve based on distance threshold from the set of devices to be screened. Based on the classification and screening of the device set, the threshold voltage change and capacitive voltage curve change of each device are obtained. The threshold voltage change represents the difference between the threshold voltage of the device in the aged state and the unaged state, and the capacitive voltage curve change represents the average offset of the capacitive voltage curve of the device in the aged state and the unaged state. Based on operating conditions, threshold voltage changes, and capacitive voltage curve changes, cluster analysis is used to classify the devices in the device set to obtain parallel device groups.

[0025] Existing research has neglected the effects of gate oxide aging. C iss - V G The effect of curve offset on current distribution. C iss - V G The curve is not only one of the important indicators for monitoring grid oxide aging, but also C iss - V G The curve shift is caused by trapped charges at the gate oxide and oxide-semiconductor interfaces, which also cause fluctuations in the threshold voltage. Therefore, the threshold voltage caused by degradation is related to... C iss - V G The effect of curve offset coupling on current shunting of parallel devices remains to be elucidated.

[0026] To verify the effect of device parameter variations on current shunting, a dual-pulse test circuit for parallel silicon carbide MOSFET devices was constructed in the Ltspice simulation software, as follows: Figure 4 As shown, this double-pulse test circuit uses a diode-clamped inductive load circuit. All parasitic parameters in the double-pulse test circuit are derived from measured values ​​on the experimental platform. Since the load inductor and DC bus used in the actual platform are non-ideal components, an RLC equivalent circuit model is established to describe the inductor and capacitor bus over a wider frequency range.

[0027] Among them, SiC MOSFET1 and SiC MOSFET2 are two identical silicon carbide MOSFET devices under test. The two devices are connected in parallel on the lower arm and share a common gate drive circuit to ensure that the gate-source voltage waveforms of the two silicon carbide MOSFET devices are identical. The simulation conditions are set to bus voltage. =800V, =15 / -4v. It serves as a reverse voltage source for the gate drive voltage, used to simulate the increase in threshold voltage that occurs during the aging process of SiCMOSFET1.

[0028] This is the drain inductance of the actual external platform of SiC MOSFET1. This is the drain inductance of the actual external platform of the SiC MOSFET2. This is the gate drive resistor for SiC MOSFET1. This is the gate drive resistor for SiC MOSFET2. This is the gate inductor of the actual external platform of SiC MOSFET1. This is the gate inductor of the actual external platform of the SiC MOSFET2. This is the source inductor of the actual external platform for SiC MOSFET1. This is the source inductor of the actual external platform of the SiC MOSFET2. This is the source resistance of the actual external platform of SiC MOSFET1. This is the source resistance of the actual external platform of the SiC MOSFET2. This is the gate drive voltage shared by SiC MOSFET1 and SiC MOSFET2. During verification, Using a 15 / -4V square wave, For gate feedback inductance, The gate feedback resistor is used, and the SiC SBD is a silicon carbide Schottky barrier diode. Here, the SiC SBD is used as a freewheeling diode. The load inductor is connected in parallel with the freewheeling diode. The parasitic resistance of the load inductance. The parasitic capacitance of the load inductor. For the parasitic inductance of the DC bus, The parasitic resistance of the DC busbar. For bus capacitors, that is It can be a DC busbar or a capacitor busbar. This is the bus voltage.

[0029] By using the above dual-pulse test circuit, the degradation results of the threshold voltage and input capacitance under actual operating conditions can be substituted into the test circuit to study the effect of the coupling effect of the degradation of both threshold voltage and input capacitance on the shunting of SiC MOSFET parallel devices.

[0030] Two sets of comparative simulation experiments were conducted, using SiC MOSFET1 as the device under test in an aged state and SiC MOSFET2 as the device under test in an unaged state. In both sets of comparative simulation experiments, the threshold voltage, gate-source capacitance, and gate-drain capacitance of SiC MOSFET2 were set to the initial device parameters without gate oxide aging. That is, SiC MOSFET2 was used as the baseline healthy device, and two sets of values ​​were assigned to SiC MOSFET1 (see Table 1). Parameters not listed are the initial device parameters without gate oxide aging. The parameters after aging were all taken from the measured data after 175 hours of accelerated aging on the Buck converter platform. At this point, compared with the initial parameters of the device without gate oxide aging, the threshold voltage of SiC MOSFET1 increased by 0.28V, the gate-source capacitance decreased by 0.29nF, the gate-drain capacitance increased by 45.51pF, and the gate input capacitance... C iss Overall reduction.

[0031] Table 1. Value assignment of SiC MOSFET1 in the two sets of comparative simulation experiments.

[0032] After the first pulse triggers, the gate-source voltage Rise to drive forward bias voltage Drain-source voltage The voltage drops to the on-state voltage. During the first pulse, the energy stored in the DC bus capacitor charges the load inductor through the already turned-on DSD to establish the required test current for the DSD, the load inductor current, and the device's drain current. The average increase is linear.

[0033] After the first pulse ends, the load inductor current freewheels through the freewheeling diode and begins to decay slowly. Then, the second pulse triggers, the device under test (DUT) turns on again, the freewheeling diode enters the reverse recovery phase, the load inductor current flows to the DUT again, and the DC power supply charges the load inductor once more. The DUT turns off again at the end of the second pulse. To reasonably compare the device's turn-on and turn-off characteristics, it is necessary to ensure that the final steady-state drain current after turn-on is consistent with the initial steady-state drain current before turn-off. Therefore, the turn-off transient characteristics of the DUT are typically captured at the end of the first pulse, while the turn-on transient characteristics are captured at the beginning of the second pulse. Generally, the first pulse duration is set relatively long to meet the test current requirements. The second pulse duration is set relatively short to avoid the drain current of the DUT exceeding the device's safety threshold, but it must be longer than the turn-on time of the DUT, typically several times the turn-on time. The interval between the two pulses is also relatively short to avoid excessive freewheeling time, which could lead to excessive changes in the load inductor current and cause a large difference between the final steady-state current after the device under test (DUT) is turned on and the initial steady-state current before it is turned off. However, the shortest interval between the two pulses cannot be less than the turn-off time of the DUT, and is usually several times the turn-off time of the DUT.

[0034] The purpose of dual-pulse testing is to obtain the dynamic switching characteristics of the device under test (DUT), such as turn-on and turn-off waveforms, turn-on delay time, rise time, turn-off delay time, fall time, Miller plateau duration, and turn-on / turn-off losses. The principle of dual-pulse testing is to drive two pulse outputs, with one pulse in between for isolation and turn-off. In the comparative simulation experiment proposed in this application, the first pulse turns on, driving a 15V gate voltage output, turning on the DUT. The bus voltage is applied across the load inductor, which linearly stores energy. The duration of this pulse is controllable; the inductor current can be controlled by adjusting the duration to achieve the target test current value. Then, the first pulse turns off. At this point, the turn-off waveform of the DUT is observed; normally, it is the drain-source voltage. Rise, drain current The current decreases. During the turn-off period of the device under test (DUT), the inductor current continues through the freewheeling diode. The turn-off interval is short to ensure that the drain current is approximately equal to the target test current (i.e., the drain current at the end of the first pulse) when the second pulse turns on. Then, at the start of the second pulse, the drive outputs again, causing the DUT to turn on again. The freewheeling current is commutated back to the device by the freewheeling diode. At this point, observe the turn-on waveform of the DUT; normally, it should be the drain-source voltage. Drain current decreases The pulse rises. Finally, the double pulse ends, and the device under test is turned off.

[0035] Taking the turn-on process as an example, the turn-on delay time and turn-on current overshoot value are used as characteristic parameters to measure the degree of loss balance of parallel devices. During the turn-on delay stage, At any given moment, the applied pulse gate voltage changes from negative voltage. Suddenly switch to drive positive bias positive voltage hour, Start by applying a gate input capacitance through the drive resistor. Charge until gate-source voltage Rise to threshold voltage .

[0036] During the turn-on delay phase, the silicon carbide MOSFET operates in the cut-off region, and the drain current... The induced voltage drop across the common-source inductor of the device is very small, so the equivalent circuit of the silicon carbide MOSFET during the turn-on delay stage can be approximated as a RC circuit, and the gate-source voltage... It can be represented as: ; In the formula, To drive the forward bias voltage, It is negative pressure. To extend the service time, The moment when the applied pulse gate voltage becomes positive. Let be the RC time constant of the gate circuit. Gate drive resistor, Gate-source capacitance, Gate-drain capacitance; Therefore, when the gate-source voltage Rise to threshold voltage At that time, the turn-on delay time is the gate-source voltage. Rise to threshold voltage The time is: .

[0037] A higher threshold voltage for a silicon carbide MOSFET means a higher target voltage that the gate needs to be charged to reach, resulting in a longer turn-on delay under the same driving conditions. Similarly, a higher gate input capacitance for a silicon carbide MOSFET results in a longer turn-on delay.

[0038] Substitute the parameters from the first and second control simulation experiments into the double-pulse test circuit and run it to obtain... Figure 5 The results are shown in the figure. In the figure, S51 represents the curve of drain current of SiC MOSFET1 during turn-on process as a function of time in the first set of control simulation experiments; S52 represents the curve of drain current of SiC MOSFET2 during turn-on process as a function of time in the first set of control simulation experiments; S53 represents the curve of drain current of SiC MOSFET1 during turn-on process as a function of time in the second set of control simulation experiments; and S54 represents the curve of drain current of SiC MOSFET2 during turn-on process as a function of time in the second set of control simulation experiments.

[0039] During the voltage drop phase, due to the reverse bias of the freewheeling diode, the drain-source voltage of the silicon carbide MOSFET will no longer be clamped at the pre-turn-on drain-source voltage value and will begin to drop rapidly. The silicon carbide Schottky barrier diode begins reverse recovery. Although the recovery process is extremely short, it exhibits a capacitive load during this phase. The silicon carbide MOSFET at this time can be considered as having a constant rising slope equal to the drain current change rate. The current source charges the junction capacitance of the freewheeling diode and the inter-turn parasitic capacitance of the load inductor. This charging current flows through the silicon carbide MOSFET, causing a large overshoot during the turn-on process. The key information contained in this stage is the rising rate of change of the drain current. The value of the reverse recovery current spike, i.e., the overshoot current. The rate of change of the drain current in a silicon carbide MOSFET as it rises to near its steady-state value is: ; in, For transconductance, For the actual platform's source inductor; The overshoot current during the turn-on process of a silicon carbide MOSFET is: ; in, For overshoot current, The junction capacitance of the freewheeling diode is set in the simulation software. This is the total parasitic inductance of the power circuit.

[0040] The drain current change rate and overshoot current are both positively correlated with transconductance and negatively correlated with threshold voltage and gate input capacitance.

[0041] Substitute the parameters from the first and second control simulation experiments into the double-pulse test circuit and run it to obtain... Figure 6 , Figure 7 The comparison results of the overshoot current changes during the turn-on process are shown. In the figure, DUT1 represents SiC MOSFET1, and DUT2 represents SiC MOSFET2.

[0042] When activated: see Figure 6 In the first set of control simulation experiments, i.e., when only the threshold voltage of SiC MOSFET1 is modified, the difference in overshoot current between SiC MOSFET1 and SiC MOSFET2 is... See also Figure 7 In the second set of comparative simulation experiments, where the threshold voltage, gate-source capacitance, and gate-drain capacitance of SiC MOSFET1 are all modified simultaneously, the difference in overshoot current between SiC MOSFET1 and SiC MOSFET2 is... In an aged SiC MOSFET1, the gate input capacitance decreases and the threshold voltage increases. Furthermore, as shown in the overshoot current expression, the change in gate input capacitance has a more significant impact on the overshoot current.

[0043] A dual-pulse test circuit can reflect the switching characteristics of a device under actual application conditions. This application analyzes the turn-on process as an example, where the two analyzed parameters (turn-on delay time and turn-on overcurrent) are related to the threshold voltage and... C iss - V G The curves are all related. Different turn-on delay times can cause parallel devices to fail to conduct simultaneously, with the device that turns on first bearing the peak current alone, resulting in severe dynamic current imbalance. Uneven distribution of transient current can lead to increased current overshoot within the devices, creating a risk of exceeding the safe operating range. Furthermore, current imbalance can cause temperature differences between parallel devices, potentially inducing thermal runaway. These conditions are detrimental to parallel applications; therefore, to reduce the impact of threshold voltage and... C iss - V G The increasing dispersion of the curves during aging causes current shunting in parallel connections. Therefore, when screening parallel silicon carbide MOSFETs for current sharing, threshold voltage drift and other factors must be considered simultaneously. C iss - V G Curve offsetting two types of degradation features is used to improve current imbalance in parallel applications. C iss - V G The curve is not only one of the important indicators for monitoring grid oxide aging, but also C iss - V G The curve shift is caused by trapped charges at the gate oxide and oxide-semiconductor interfaces, which also cause fluctuations in the threshold voltage. Based on the physical nature of the unified effect of trapped charges at the gate oxide interface on the threshold voltage and gate input capacitance, this study clarifies the dynamic turn-on timing and transient current spike variations under the coupling effect of the threshold voltage and gate input capacitance. It fully elucidates the non-uniform current mechanism caused by the synergistic degradation of these two parameters, filling the technical gap in existing research that neglects the coupling effect of capacitance degradation.

[0044] Therefore, the coupling effect of threshold voltage and gate input capacitance degradation can more accurately reflect the difference in current shunting between parallel devices. By using the shift in threshold voltage and gate input capacitance caused by aging as characteristics that jointly determine the screening method, the problem of insufficient accuracy in analyzing the current sharing factors of parallel devices using a single parameter is solved, providing theoretical support for predicting the long-term reliability and life assessment of parallel power modules.

[0045] Advantageously, this application incorporates both gate oxide aging-induced threshold voltage drift and current sharing in the screening of parallel silicon carbide MOSFETs. C iss - V G The curve offset exhibits two types of degradation characteristics, overcoming the limitations of existing studies that only analyze the influence of a single parameter. After screening, the degradation degree dispersion among the silicon carbide MOSFET devices is low, and the sorting and matching effect is good. When parallel devices obtained using the parallel silicon carbide MOSFET current sharing screening method proposed in this application are used in parallel applications, they can reduce or avoid the imbalance of parallel currents among the parallel devices under long-term high temperature and electric field stress. This avoids device current overshoot caused by uneven transient current distribution, reduces the risk of devices exceeding the safe operating range, and also avoids inconsistent temperature rise caused by differences in current distribution among the parallel devices, reducing the risk of induced thermal runaway.

[0046] The total number of devices in the device set to be screened is determined based on the number of parallel silicon carbide MOSFETs and the device parameter dispersion. Optionally, the standard deviation of the threshold voltage is used to characterize the device parameter dispersion. The threshold voltage variation is one of the key factors in the current sharing screening of parallel silicon carbide MOSFETs. When selecting the scale of devices to be screened, the device parameter dispersion is characterized by the standard deviation of the threshold voltage. A reasonable scale of devices to be screened can ensure that the subsequent screening has small parameter deviations while ensuring screening efficiency. Specifically: Obtain the number of parallel silicon carbide MOSFETs; obtain the threshold voltage of devices in the same batch; Calculate the standard deviation of the threshold voltage of the same batch of devices; The current screening coefficient is determined based on the standard deviation; the current screening coefficient is: ; In the formula, This is the current screening coefficient. The standard deviation of the threshold voltage; The product of the current screening coefficient and the number of parallel silicon carbide MOSFETs is used as the current total number of devices in the device set to be screened. It is worth noting that after multiplying the current screening coefficient and the number of parallel silicon carbide MOSFETs, the decimal part is discarded and 1 is carried over to the integer part, and the result is forced to be an integer as the current total number of devices in the device set to be screened.

[0047] If the number of devices in the current parallel device group is less than the number of parallel silicon carbide MOSFETs, the screening coefficient is adjusted according to the difference in the number of devices. The current parallel device group represents the parallel device group obtained by classifying the devices in the classification screening device set based on the current total number of devices using cluster analysis. The difference in the number of devices represents the difference between the number of parallel silicon carbide MOSFETs and the number of devices in the current parallel device group. The maximum value within the adjusted screening coefficient interval is used as the current screening coefficient, and the process of multiplying the current screening coefficient by the number of parallel silicon carbide MOSFETs is repeated to obtain the current total number of devices in the device set to be screened. For example, when the adjusted screening coefficient interval is... The current total number of devices in the device set to be screened is recalculated using 4 as the current screening coefficient. The required number of devices is added on the basis of the already screened devices, and the screening and clustering are repeated to obtain the parallel device group.

[0048] Optionally, the screening coefficient can be adjusted based on the difference in the number of components, as follows: ; In the formula, This is the adjusted screening coefficient. For margin parameters, The parameter is related to the total number of devices in the current device set to be screened and the number of devices in the category-screened device set, and is related to the degree of device retention during the screening process, i.e., from the device set to be screened to the category-screened device set. The number of parallel silicon carbide MOSFETs, This represents the number of devices in the current parallel device group.

[0049] In some embodiments, the voltage range includes a first voltage range and a second voltage range, with the second voltage range located within the first voltage range; the distance threshold includes a first distance threshold and a second distance threshold, with the second distance threshold being less than the first distance threshold; in some embodiments, the range of the first voltage range includes 0.1V to 0.3V. The range of the second voltage range includes 0.001V to 0.2V. The first distance threshold is 0.01V. The second distance threshold is 0.002V.

[0050] The device set to be screened is obtained by screening threshold voltages based on voltage ranges and capacitive-voltage curves based on distance thresholds, including: The first threshold voltage and the first capacitive voltage curve of each device in the set of devices to be screened are obtained respectively. The first threshold voltage represents the threshold voltage in the unaged state, and the first capacitive voltage curve represents the capacitive voltage curve in the unaged state. The first threshold voltage is selected based on the first voltage range in the device set to be screened, and the first capacitive voltage curve is selected based on the first distance threshold. The intersection is then taken to obtain the intermediate device set. That is, the first threshold voltage of the devices in the intermediate device set is all within the first voltage range, and the average distance between the first capacitive voltage curves of any two devices in the intermediate device set is not greater than the first distance threshold. The first voltage range and the first distance threshold are used to coarsely screen the devices in the device set to be screened whose first threshold voltage and first capacitive voltage curve are significantly different, so as to ensure the effectiveness and efficiency of the screening. Short-term gate stress was applied to each device in the intermediate screening device set, and the second threshold voltage and second capacitive voltage curves of each device were obtained. The second threshold voltage represents the threshold voltage after applying short-term gate stress, and the second capacitive voltage curve represents the capacitive voltage curve after applying short-term gate stress. The short-term gate stress represents the short-term gate stress of dynamic switching type. Specifically, an AC bias voltage is applied between the gate and source terminals of the device, that is, a square wave alternating stress signal with a preset duration and covering both the positive and negative rated gate voltages is applied to the gate of the device. The stress frequency of the square wave alternating stress signal is usually 500kHz, and the duty cycle of the square wave alternating stress signal is between 5% and 95%. The preset duration is within one week, and the specific preset duration is adjusted according to different device models to ensure that potential defects of the gate interface are fully exposed without significantly increasing subsequent usage losses. Too short an aging time will result in a low threshold voltage drift of the device, and the small difference in threshold voltage drift between different devices may lead to a decrease in the accuracy of subsequent classification and screening. Excessive aging time leads to a large drift in threshold voltage. Although effective screening can be carried out based on the threshold voltage drift between devices, the large threshold voltage drift leads to increased losses in subsequent use of the devices. In addition, excessive stress time reduces screening efficiency.

[0051] The intermediate screening device set is divided into two groups: a second threshold voltage is selected based on the second voltage range, and a second capacitive voltage curve is selected based on the second distance threshold. The intersection of these two groups is used to obtain a classified screening device set. That is, the second threshold voltage of the devices in the classified screening device set is all within the second voltage range, and the average distance between the second capacitive voltage curves of any two devices in the classified screening device set is not greater than the second distance threshold. The second voltage range and the second distance threshold are used to finely screen the devices in the intermediate screening device set whose second threshold voltage and second capacitive voltage curve are different from most devices, so as to ensure the effectiveness and efficiency of the screening devices.

[0052] Optionally, the margin parameter is: ; In the formula, The total number of devices in the device set to be filtered. This represents the number of devices in the intermediate screening device set. To classify and filter the number of devices in a device set, a margin parameter is used in conjunction with voltage range and distance threshold for device screening, which can further ensure the effectiveness and efficiency of device screening.

[0053] In some embodiments, the threshold voltage change of each device is obtained based on the classification and screening of the device set, including: In the device classification and screening set, the difference between the second threshold voltage and the first threshold voltage of each device is taken as the threshold voltage change of the corresponding device. The threshold voltage change can be obtained by performing only one short-term gate stress aging treatment, which improves the screening efficiency.

[0054] In some embodiments, the change in the capacitive voltage curve of each device is obtained based on the classification and screening of the device set, including: In the device classification and screening set, the average offset of the second capacitive voltage curve of each device relative to the first capacitive voltage curve is taken as the change in the capacitive voltage curve of the corresponding device. The change in the capacitive voltage curve can be obtained by performing only one short-term gate stress aging treatment, thereby improving the screening efficiency.

[0055] In some embodiments, based on operating conditions, threshold voltage changes, and capacitive voltage curve changes, cluster analysis is used to classify devices in a screening device set to obtain parallel device groups, including: A sample dataset is generated based on the classification and screening of device sets, threshold voltage changes, and capacitive voltage curve changes. The sample dataset represents a collection of sample data, with the threshold voltage changes and capacitive voltage curve changes of each device serving as a sample dataset. Each sample data in the classification and screening device set is used as an initial cluster; Use the initial cluster as the current cluster; Calculate the Euclidean distance between any two current clusters to obtain the inter-cluster distance; Merge the current clusters with the smallest inter-cluster distance differences to obtain the updated clusters and the current clustering phylogenetic tree; Check if the number of updated clusters is 1; When the number of updated clusters is not 1, the updated cluster is taken as the current cluster, and the Euclidean distance between any two current clusters is calculated repeatedly to obtain the inter-cluster distance. When the number of clusters to be updated is 1, the current clustering phylogenetic tree is used as the output clustering phylogenetic tree; The threshold voltage change step size and the capacitive voltage curve change step size are obtained based on the operating conditions. Different operating conditions have different maximum permissible deviations for the threshold voltage change size and the capacitive voltage curve change size. The maximum permissible deviation of the threshold voltage change size and the maximum permissible deviation of the capacitive voltage curve change size are used as the threshold voltage change step size and the maximum permissible deviation of the capacitive voltage curve change size, respectively, according to the operating conditions.

[0056] The merging distance threshold is obtained based on the step size of the threshold voltage change and the step size of the capacitive voltage curve change; optionally, a weighted Euclidean distance is used to obtain the merging distance threshold based on the step size of the threshold voltage change and the step size of the capacitive voltage curve change, and the merging distance threshold is: ; in, To merge distance thresholds, For the normalized weights related to the change in threshold voltage, The degree of influence of the threshold voltage change on the shunting of the parallel current is related to the extent that the threshold voltage change affects the parallel current. The step size for the threshold voltage change. The normalized weights are related to the changes in the capacitive pressure curve. The degree of influence of the change in the capacitive-voltage curve on the shunting of the parallel current is related to the extent that the change in the capacitive-voltage curve affects the shunting of the parallel current. , This refers to the step size of the change in the capacitive pressure curve; In the proposed scheme of this application, optionally, the influence of the threshold voltage change and the capacitive voltage curve change on the parallel current shunting is set to be equivalent, that is, set... .

[0057] At least one parallel device group is obtained by cross-cutting the output clustering phylogenetic tree based on the merged distance threshold.

[0058] The advantage is that devices within the classification and screening device set can be clustered through a complete clustering process, and the corresponding cutting height can be obtained according to different operating conditions, thereby realizing the current sharing screening of parallel silicon carbide MOSFETs under different operating conditions.

[0059] In some embodiments, based on operating conditions, threshold voltage changes, and capacitive voltage curve changes, cluster analysis is used to classify devices in a screening device set to obtain parallel device groups, including: The threshold voltage change step size and the capacitive voltage curve change step size are obtained based on the operating conditions. The merging distance threshold is obtained based on the step size of the threshold voltage change and the step size of the capacitive voltage curve change; A sample dataset is generated based on the classification and screening of device sets, threshold voltage changes, and capacitive voltage curve changes. The sample dataset represents a collection of sample data, with the threshold voltage changes and capacitive voltage curve changes of each device serving as a sample dataset. Each sample data in the classification and screening device set is used as an initial cluster; Use the initial cluster as the current cluster; Calculate the Euclidean distance between any two current clusters to obtain the inter-cluster distance; Determine whether the distance between any clusters is greater than the merge distance threshold; When the distance between any two clusters is not greater than the merging distance threshold, the current cluster with the smallest Euclidean distance difference is merged to obtain the updated cluster. The updated cluster is used as the current cluster, and the process is repeated to calculate the Euclidean distance between any two current clusters to obtain the inter-cluster distance. When the distance between any clusters is greater than the merging distance threshold, the components of the device corresponding to the current cluster are treated as a parallel device group.

[0060] The advantage is that targeted clustering can be performed based on actual working conditions, eliminating the need for a complete clustering process and improving the efficiency of targeted screening.

[0061] Those skilled in the art will understand that embodiments of this application can be provided as methods, apparatus (systems), or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. The solutions in the embodiments of this application can be implemented in various computer languages, such as the object-oriented programming language Java and the interpreted scripting language JavaScript.

[0062] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce an instruction that executes via the processor of the computer or other programmable data processing apparatus to create an instruction for implementing the flowchart. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0063] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0064] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0065] Finally, it should be noted that the above content is only used to illustrate the technical solution of this application, and is not intended to limit the scope of protection of this application. Simple modifications or equivalent substitutions made by those skilled in the art to the technical solution of this application shall not depart from the substance and scope of the technical solution of this application.

Claims

1. A parallel silicon carbide MOSFET current sharing screening method, characterized by, This includes obtaining the operating conditions, voltage range, distance threshold, and the set of devices to be screened, wherein the set of devices to be screened represents a collection of silicon carbide MOSFETs to be screened; The threshold voltage and capacitive voltage curves of each device in the set of devices to be screened are obtained respectively. The capacitive voltage curve represents the curve of gate input capacitance changing with gate voltage. A classified and screened device set is obtained by filtering the threshold voltage based on the voltage range and the capacitive voltage curve based on the distance threshold from the set of devices to be screened. Based on the classified and screened device set, the threshold voltage change and capacitive voltage curve change of each device are obtained respectively. The threshold voltage change represents the difference between the threshold voltage of the device in the aged state and the unaged state, and the capacitive voltage curve change represents the average offset of the capacitive voltage curve of the device in the aged state and the unaged state. Based on the operating conditions, the threshold voltage change, and the capacitive voltage curve change, cluster analysis is used to classify the devices in the device set to obtain parallel device groups.

2. The parallel silicon carbide MOSFET current sharing screening method of claim 1, wherein, The voltage range includes a first voltage range and a second voltage range, with the second voltage range located within the first voltage range; the distance threshold includes a first distance threshold and a second distance threshold, with the second distance threshold being less than the first distance threshold. The process of classifying and screening devices by filtering the threshold voltage based on the voltage range and the capacitive-voltage curve based on the distance threshold from the set of devices to be screened includes: The first threshold voltage and the first capacitive voltage curve of each device in the set of devices to be screened are obtained respectively. The first threshold voltage represents the threshold voltage in the unaged state, and the first capacitive voltage curve represents the capacitive voltage curve in the unaged state. The first threshold voltage is selected based on the first voltage range in the set of devices to be screened, and the first capacitive voltage curve is selected based on the first distance threshold. The intersection of these two parameters is then used to obtain an intermediate set of devices to be screened. A short-term gate stress is applied to each of the devices in the intermediate screening device set, and a second threshold voltage and a second capacitive voltage curve are obtained for each device. The second threshold voltage represents the threshold voltage after applying the short-term gate stress, and the second capacitive voltage curve represents the capacitive voltage curve after applying the short-term gate stress. The classification and screening device set is obtained by screening the second threshold voltage based on the second voltage range and the second capacitive voltage curve based on the second distance threshold in the intermediate screening device set, and taking the intersection.

3. The parallel silicon carbide MOSFET current sharing screening method of claim 2, wherein, Based on the classified and screened device set, the threshold voltage change of each device is obtained, including: In the classified and screened device set, the difference between the second threshold voltage and the first threshold voltage of each device is used as the threshold voltage change of the corresponding device.

4. The parallel silicon carbide MOSFET current sharing screening method of claim 2, wherein, Based on the classified and screened device set, the capacitance-voltage curve change of each device is obtained, including: In the classified and screened device set, the average offset of the second capacitive voltage curve of each device relative to the first capacitive voltage curve is taken as the change in the capacitive voltage curve of the corresponding device.

5. The parallel silicon carbide MOSFET current sharing screening method of claim 2, wherein, The first voltage range includes 0.1V to 0.3V.

6. The parallel silicon carbide MOSFET current sharing screening method according to claim 5, characterized in that, The second voltage range includes 0.001V to 0.2V.

7. The parallel silicon carbide MOSFET current sharing screening method according to claim 2, characterized in that, The first distance threshold is 0.

01.

8. The parallel silicon carbide MOSFET current sharing screening method according to claim 7, characterized in that, The second distance threshold is 0.

002.

9. The parallel silicon carbide MOSFET current sharing screening method according to claim 1, characterized in that, Based on the operating conditions, the threshold voltage variation, and the capacitive-voltage curve variation, cluster analysis is used to classify the devices in the selected device set to obtain parallel device groups, including: A sample dataset is generated based on the classified and screened device set, the threshold voltage change, and the capacitive voltage curve change. The sample dataset represents a collection of sample data, and the threshold voltage change and capacitive voltage curve change of each device are considered as sample data. Each sample data in the classification and screening device set is used as an initial cluster; Use the initial cluster as the current cluster; Calculate the Euclidean distance between any two current clusters to obtain the inter-cluster distance; The current cluster with the smallest inter-cluster distance difference is merged to obtain the updated cluster and the current clustering phylogenetic tree; Determine whether the number of the updated clusters is 1; When the number of updated clusters is not 1, the updated cluster is taken as the current cluster, and the Euclidean distance between any two current clusters is calculated repeatedly to obtain the inter-cluster distance. When the number of updated clusters is 1, the current clustering phylogenetic tree is used as the output clustering phylogenetic tree; The threshold voltage change step size and the capacitive voltage curve change step size are obtained based on the aforementioned operating conditions; The merging distance threshold is obtained based on the step size of the threshold voltage change and the step size of the capacitive voltage curve change; At least one of the parallel device groups is obtained by transecting the output clustering phylogenetic tree according to the merged distance threshold.

10. The parallel silicon carbide MOSFET current sharing screening method according to claim 1, characterized in that, Based on the operating conditions, the threshold voltage variation, and the capacitive-voltage curve variation, cluster analysis is used to classify the devices in the selected device set to obtain parallel device groups, including: The threshold voltage change step size and the capacitive voltage curve change step size are obtained based on the aforementioned operating conditions; The merging distance threshold is obtained based on the step size of the threshold voltage change and the step size of the capacitive voltage curve change; A sample dataset is generated based on the classified and screened device set, the threshold voltage change, and the capacitive voltage curve change. The sample dataset represents a collection of sample data, and the threshold voltage change and capacitive voltage curve change of each device are considered as sample data. Each sample data in the classification and screening device set is used as an initial cluster; Use the initial cluster as the current cluster; Calculate the Euclidean distance between any two current clusters to obtain the inter-cluster distance; Determine whether any of the inter-cluster distances is greater than the merging distance threshold; When any of the inter-cluster distances is not greater than the merge distance threshold, the current cluster with the smallest Euclidean distance difference is merged to obtain an updated cluster. The updated cluster is used as the current cluster, and the process of calculating the Euclidean distance between any two current clusters is repeated to obtain the inter-cluster distance. When the distance between any of the clusters is greater than the merging distance threshold, the components of the device corresponding to the current cluster are taken as the parallel device group.

Images