A non-contact electric spark tool sharpening driving circuit based on state parameter self-adaptation

Abstract

The application discloses a kind of non-contact electric spark tool setting drive circuit based on state parameter self-adaption of precision machine tool, it is related to electric spark tool setting drive technical field, the circuit includes: current sampling circuit, contains Hall sensor branch and sampling resistance branch;Dynamic weight fusion module, according to the weight of two-way signal of real-time feature dynamic allocation discharge phase and is fused as synthesized current signal, as the input of overcurrent comparison and closed-loop regulation;Overcurrent comparison circuit, synthesized current signal is compared with adjustable threshold to generate overcurrent cut-off pulse signal;Multi-stage recovery state machine, after overcurrent cut-off pulse, three stages of arc extinguishing confirmation, tentative reignition and normal recovery are executed in turn;Threshold reference DAC circuit, by FPGA according to the output voltage of discharge state statistics result dynamic update.This application considers breakdown edge response speed and steady-state measurement accuracy by double-branch dynamic weight fusion, by threshold adaptive updating, protection threshold follows gap impedance drift automatically adjusts, significantly improves the adaptive ability and long-term operation stability of electric spark tool setting drive circuit.

Description

Technical Field

[0001] This invention relates to the field of electrical discharge machining (EDM) tool dressing technology, and in particular to a non-contact EDM tool dressing drive circuit for precision machine tools based on adaptive state parameters. Background Technology

[0002] Electrical discharge machining (EDM) is a special process that utilizes pulsed voltage to break down the 10–80 μm gap between the metal-bonded diamond tool / wheel and the electrode, generating instantaneous plasma discharge. This selectively vaporizes and melts the metal bond, causing the diamond abrasive grains to protrude and form the cutting edge. Related equipment is widely integrated into dicing machines, wire EDM machines, CNC machining centers, and semiconductor cutting equipment. The EDM drive circuit needs to complete a fully closed-loop control within a microsecond timescale, including gap state identification, current limiting, overcurrent pulse cutoff, short-circuit latch-up, and discharge recovery. Simultaneously, the load exhibits multiple complex characteristics: diamond abrasive grains possess insulating properties, the metal bond discharge exhibits negative resistance, and inter-electrode chips easily form conductive bridges and induce false short circuits, placing stringent requirements on the pulse drive control strategy.

[0003] Existing electrical discharge machining (EDM) dressing tools and similar EDM pulse drive circuits have formed a relatively complete functional module system around the control architecture of sampling, comparison, pulse cutoff, and latching. Representative disclosed technical solutions are as follows:

[0004] 1. Utility model patent CN216398324U discloses an EDM drive circuit with dual short-circuit protection, which sets up two hardware protection channels: one channel realizes drive shutdown through MCU interrupt, and the other channel uses the IPM fault output signal to control the enable terminal of 74HC245 through optocoupler to cut off the main oscillation signal in a high-impedance manner; at the same time, a comparator and an analog switch are configured to form a short-circuit latch and pulse reset circuit.

[0005] However, this solution only supports fixed-time delay recovery or manual reset after short-circuit pulse interruption. In micro-electrical discharge machining, the narrow chip removal channels between electrodes and the short circuits and arcing caused by the eroded particles building conductive bridges are high-frequency conditions. If only a fixed delay or manual intervention is used to restart the discharge, and the conductive bridge is not fully deionized and dissipated before a pulse is applied again, a continuous cycle of "pulse interruption-reset-short circuit" can easily occur. The power device is repeatedly subjected to high-current impacts and temperature cycles in a short period, continuously accumulating thermal stress.

[0006] In the field of electrical discharge machining (EDM), it is generally recognized that in the initial stage of a short circuit, the contact area of ​​the conductive bridge formed by the chips is relatively large. Applying discharge current immediately at this time can easily cause the conductive bridge to thicken further, which is not conducive to short circuit elimination. The appropriate control method should wait for the inter-electrode medium to deionize and the conductive bridge to weaken before attempting to resume discharge. Japanese Patent JPH07156019A for a power supply device for electrical discharge machining also describes a similar control approach, and does not recommend unconditionally resuming discharge immediately after a short circuit occurs. In their research on micro-EDM, Fu Xiuzhuo et al. from Shandong University proposed using the micro-vibration of piezoelectric actuator electrodes to achieve adaptive gap adjustment and assist in eliminating short circuits, confirming from the mechanical feed level that simply relying on a fixed timing sequence is insufficient to properly handle instantaneous short circuits. It is evident that this type of solution lacks a graded trial recovery mechanism based on inter-electrode electrical state criteria, and instantaneous short circuits can easily cause frequent start-stop cycles of the power circuit.

[0007] 2. Invention patent CN104702142B (Single Pulse Power Supply) and invention patent application CN104959689A (Wire Cutting Overcurrent Protection Scheme) disclose an architecture for generating the main pulse using an MCU, optocoupler isolation drive, and source power output. The analog front-end implements gap voltage partitioning identification (open circuit, short circuit, and discharge states), overcurrent comparison, and long / short circuit timing to turn off the main oscillation signal. Current detection uses only a sampling resistor or a single sampling branch of a Hall sensor. The current rise rate at the spark discharge breakdown edge can reach tens of A / μs. A closed-loop Hall sensor can adapt to high-speed current edge detection, but it suffers from temperature drift and zero drift issues, resulting in insufficient steady-state measurement accuracy. The detection link using a sampling resistor and operational amplifier has high steady-state accuracy, but it is constrained by the op-amp slew rate and common-mode voltage range, exhibiting tracking lag for hundreds of nanosecond-level discharge breakdown spike signals.

[0008] The aforementioned invention patents / patent applications only use a single current detection branch and do not construct a detection architecture that dynamically fuses multiple sensing signals based on the discharge stage, making it difficult to simultaneously take into account the dynamic response speed at the breakdown edge and the accuracy of steady-state current measurement.

[0009] 3. Invention patent CN115070142B discloses a three-level Buck topology peak current control EDM power supply, which uses an ACS732 Hall sensor and an AD9226 analog-to-digital converter to achieve dual-channel current sampling. The FPGA tracks the current reference value according to the single-cycle duty cycle control formula, and the high-power current limiting resistor is eliminated through the three-level Buck topology.

[0010] While this scheme achieves single-cycle peak current tracking control, the overcurrent protection threshold is fixed after a one-time configuration by the controller, and the discharge pulse issuance is not correlated with the mechanical spindle rotation status. During continuous EDM dressing, the tool bond layer is continuously worn down, the wheel / tool ​​rotation radius undergoes slight changes, and the average discharge gap gradually decreases (the inter-electrode equivalent impedance decreases slowly); under the same open-circuit voltage conditions, the steady-state discharge current baseline rises accordingly. A fixed overcurrent threshold leads to problems such as a lenient protection threshold in the early stages and frequent false triggering of protection after long-term operation.

[0011] The limitations of this scheme are that the protection threshold cannot be adaptively updated to follow the slow drift of the gap impedance, and the pulse delivery is not synchronized with the mechanical phase rotation.

[0012] In summary, existing representative publicly available technologies generally suffer from three common limitations:

[0013] First, the current detection only uses a single sampling branch and does not build a multi-channel sensing and detection architecture that dynamically integrates the discharge stages (breakdown edge, steady-state discharge, and arc extinction edge), making it difficult to balance the dynamic response speed of current detection with the steady-state measurement accuracy.

[0014] Second, after the short-circuit overcurrent pulse is cut off, the discharge is restored by fixed delay or manual reset. There is a lack of a multi-stage trial recovery state machine based on the inter-electrode electrical state. Instantaneous short circuits can easily induce frequent start-stop of the power circuit.

[0015] Third, the overcurrent protection threshold parameter is fixed and cannot be adaptively adjusted to follow the slow drift of the gap impedance during long-term maintenance. As a result, the probability of false triggering of the protection gradually increases during continuous operation of the equipment. Summary of the Invention

[0016] To address the aforementioned technical problems, this invention aims to propose a non-contact EDM tool dressing drive circuit for precision machine tools based on adaptive state parameters. This circuit retains existing power supply control, DAC threshold setting, comparator latching, dual-channel sampling, and gate driving modules, while introducing an adaptive control mechanism based on current characteristics as the control core. Specifically, it includes two modules: dual-sampling dynamic weight fusion and threshold adaptive update, which are used to solve the problems of the contradiction between sampling accuracy and bandwidth and the inability of the protection threshold to be adaptive.

[0017] To solve the above-mentioned technical problems, the present invention adopts the following technical solution: A precision machine tool non-contact EDM dressing drive circuit based on state parameter adaptation includes: The current sampling circuit includes a Hall sensor branch and a sampling resistor branch, which are used to output a first current signal and a second current signal, respectively. The dynamic weight fusion module, connected to the Hall sensor branch and the sampling resistor branch, is used to dynamically allocate the weights of the first current signal and the second current signal according to the real-time characteristics of the discharge stage and fuse them into a composite current signal. An overcurrent comparison circuit, connected to the dynamic weight fusion module, is used to compare the synthesized current signal with the overcurrent protection threshold voltage to generate an overcurrent cutoff signal. An FPGA controller, connected to the dynamic weight fusion module and the overcurrent comparison circuit, is used to output discharge pulses; A threshold reference DAC circuit, connected to the FPGA controller and the overcurrent comparator circuit, is used to output an adjustable overcurrent protection threshold voltage to the overcurrent comparator circuit. The FPGA controller is also used to dynamically update the output voltage of the threshold reference DAC circuit through the SPI interface based on the discharge state statistics.

[0018] In a preferred embodiment of the present invention, the driving circuit further includes a multi-level recovery state machine connected to the dynamic weight fusion module and the FPGA controller, for sequentially executing the following recovery stages after the overcurrent cutoff signal is triggered: Arc extinction confirmation phase: wait for the discharge current to drop below the preset arc extinction threshold and maintain the preset minimum deionization time; Trial reignition stage: Output a trial pulse with energy lower than the normal discharge pulse to detect whether the breakdown was successful; Normal recovery phase: After successful reignition test, normal discharge pulse parameter output is restored.

[0019] In a preferred embodiment of the present invention, the multi-stage recovery state machine is further configured to: when the test reignition stage is determined to be a test failure, return to the arc extinguishing confirmation stage and extend the deionization time.

[0020] In a preferred embodiment of the present invention, the dynamic weight fusion module is configured as follows: When the current rise slope is greater than a first set threshold, the weight of the first current signal is increased. When the rate of change of current is less than a second set threshold, the weight of the second current signal is increased; When the slope of the current falling edge is greater than the third set threshold, the average of the first current signal and the second current signal is taken.

[0021] In a preferred embodiment of the present invention, the FPGA controller is further configured to: When the average current shows a decreasing trend for M consecutive cycles, the overcurrent protection threshold voltage is reduced. When the number of short circuits or overcurrents exceeds the set value, the overcurrent protection threshold voltage is increased.

[0022] In a preferred embodiment of the present invention, a short-circuit state latching circuit is further included, which is connected to the current sampling circuit and is used to generate and latch a short-circuit latching signal when a short circuit or overcurrent is detected.

[0023] In a preferred embodiment of the present invention, the driving circuit further includes a main power supply on / off control circuit, comprising: An AND gate circuit, whose first input terminal is connected to the power enable signal output by the FPGA controller, and whose second input terminal is connected to the short-circuit latch signal; The switching transistor is controlled by the output of the AND gate circuit; The relay is connected in series in the main power supply circuit and is controlled by the switching transistor; An emergency switch, connected to the control electrode of the switching transistor, is used to forcibly shut down the switching transistor in an emergency.

[0024] In a preferred embodiment of the present invention, the driving circuit further includes a temperature monitoring circuit connected to the FPGA controller, used to monitor the temperature of the power device and trigger frequency reduction or pause discharge operation when the temperature exceeds a safety threshold.

[0025] In a preferred embodiment of the present invention, the driving circuit further includes a gate forced turn-off circuit, which is connected to the gate of the overcurrent comparator circuit and the power MOSFET, and is used to directly pull down the gate drive signal when the overcurrent cutoff signal is valid, thereby forcibly turning off the power MOSFET.

[0026] Beneficial effects of this invention: 1. Achieving both rapid response at the breakdown edge and high accuracy in steady-state measurement: Through a dynamic weighted fusion module, the Hall sensor branch signal (high bandwidth) is prioritized during the breakdown edge phase, while the sampling resistor branch signal (high accuracy) is prioritized during the steady-state phase. The average of the two signals is then used during the arc-extinguishing edge phase. This mechanism resolves the contradiction between rapid response and high-precision measurement that a single sampling branch cannot simultaneously satisfy. It enables the overcurrent comparator circuit to respond promptly at the moment of breakdown, while providing precise current feedback for closed-loop regulation during the steady-state phase.

[0027] 2. Automatic elimination of transient short circuits, reducing thermal stress on power devices: Through a multi-stage recovery state machine, after overcurrent pulse closure, three stages are sequentially executed: arc extinction confirmation, test reignition, and normal recovery. For transient short circuits such as chip bridging, discharge can be automatically eliminated and restored within hundreds of microseconds without manual intervention. For persistent short circuits, the system can identify and switch to an extended deionization state during the test reignition stage, avoiding repeated start-stop cycles of "pulse closure-reset-re-short circuit" and reducing the cumulative thermal stress on power devices.

[0028] 3. Controllable test pulse energy, no damage to the discharge gap: The pulse width of the test pulse is only about one-tenth that of the normal pulse, and the injected energy is extremely low. Even if the test fails, it will not cause additional damage to the discharge gap. After a successful test, the normal pulse is immediately restored, minimizing the processing time loss caused by short circuits.

[0029] 4. Adaptive Adjustment of Protection Threshold Following Gap Impedance Drift: Through an adaptive threshold update mechanism, the FPGA controller periodically collects discharge status data and dynamically adjusts the overcurrent protection threshold of the DAC output based on the changing trends of average current and short-circuit count. This mechanism enables the protection threshold to adaptively adjust following the slow drift of the gap impedance (such as binder thinning or grinding wheel radius reduction), preventing the fixed threshold from gradually changing from "too loose" to "frequent false triggering" during long-term operation, thus extending the maintenance-free cycle of the equipment.

[0030] 5. Statistically driven closed-loop regulation, eliminating the need for manual calibration: Threshold updates are automatically determined based entirely on statistical data during the discharge process, requiring no manual intervention for threshold calibration or periodic adjustment. The system can automatically converge to a suitable protection threshold under different operating conditions, reducing equipment commissioning and maintenance costs.

[0031] 6. Dual-branch protection with layered redundancy, backup in case of single-branch failure: In overcurrent protection mode, the sampling resistor branch compares the signal with the adjustable threshold OC_ADJ via comparator U14B. The generated OC_SHUT signal only turns off the gate without latching. In short-circuit latching mode, the Hall sensor branch holds the SHORT signal through a self-locking circuit once triggered, until the FPGA actively sends a reset pulse. The two branches, two comparators, and two sets of execution endpoints do not overlap and serve as backups for each other, resulting in higher protection reliability than a single-branch dual-threshold scheme.

[0032] 7. Two-tiered protection: Hardware latching and software strategy. Short-circuit latching is completed by hardware circuitry within nanoseconds, outputting a stable SHORT signal, independent of the FPGA's software polling cycle. The clearing timing is executed by the FPGA software issuing POW_RST after the deionization timer ends. The hardware is responsible for "remembering the fault," while the software is responsible for "clearing the fault at the opportune time." The two-tiered protection has a clear division of labor, ensuring that short-circuit events are not lost even when the FPGA is busy.

[0033] 8. Physical power-off of main power supply with high safety redundancy: The SHORT signal is sent to the main power supply on / off control circuit, and the main power supply is physically disconnected through AND gate logic and relays, ensuring that the power circuit is completely cut off in the event of a severe short circuit. The physical power-off works in conjunction with process timing to avoid the safety hazard of simply cutting off the pulse output while the main power supply remains on. The emergency switch provides a manual power-off channel independent of the FPGA, further enhancing system safety.

[0034] 9. Temperature monitoring and frequency reduction protection to extend the life of power devices: The temperature monitoring circuit monitors the temperature of power devices in real time. When the temperature exceeds the safety threshold, it triggers frequency reduction or pauses discharge to prevent the power devices from failing due to heat accumulation caused by long-term continuous discharge, thereby extending the service life of the power module and improving the long-term reliability of the equipment. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 Schematic diagram of the main power supply on / off control circuit; Figure 2 This is a schematic diagram of a threshold reference DAC circuit. Figure 3 This is a schematic diagram of the sampling signal conditioning circuit. Figure 4 This is the schematic diagram of the gate driver stage circuit; Figure 5 This is a schematic diagram of a gate forced turn-off circuit. Figure 6 This is a schematic diagram of a power discharge bridge circuit. Figure 7 This is a schematic diagram of an anomaly detection circuit. Figure 8 Schematic diagram of a short-circuit latch circuit; Figure 9 This is a schematic diagram of the main signal flow. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of the present invention more apparent, exemplary embodiments according to the present invention will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are merely a part of the embodiments of the present invention, and not all of the embodiments of the present invention. It should be understood that the present invention is not limited to the exemplary embodiments described herein. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention described herein without inventive effort should fall within the protection scope of the present invention.

[0038] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid obscuring the invention.

[0039] It should be understood that the invention can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0040] To fully understand this invention, a detailed structure will be presented in the following description to illustrate the technical solution proposed by this invention. Optional embodiments of the invention are described in detail below; however, in addition to these detailed descriptions, the invention may have other embodiments.

[0041] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0042] For ease of explanation, the overall circuit structure and signal flow of this invention will be introduced first.

[0043] The precision machine tool non-contact EDM tool dressing drive circuit disclosed in this invention includes: an FPGA controller and a main power supply on / off control circuit. Figure 1 Threshold reference DAC circuit ( Figure 2 ), sampling signal conditioning circuit ( Figure 3 ), gate drive stage circuit ( Figure 4 Gate forced turn-off circuit ( Figure 5 ), power discharge bridge circuit ( Figure 6 ), abnormal detection circuit ( Figure 7 ), short-circuit state latch circuit ( Figure 7 + Figure 8 ).

[0044] The signal flow of the entire system can be divided into two parallel links according to function: Link 1: Control and Drive Link (FPGA → Discharge Gap) The FPGA controller outputs a power enable signal POW_CTRL to the main power supply on / off control circuit to control the main power supply's on / off state; simultaneously, it outputs a PWM pulse signal POW_PWM to the gate driver stage circuit, which amplifies the signal and drives the power MOSFETs Q3 and Q4 in the power discharge bridge circuit to alternately turn on and off (see...). Figure 6 This allows a pulse voltage to be applied across the discharge gap, generating an electric spark discharge.

[0045] Link 2: Current sensing and feedback link (discharge gap → FPGA) The discharge current in the power discharge bridge circuit is collected simultaneously through two branches: The Hall sensor branch outputs the first current signal I_OUT (see...) Figure 6I_OUT is fed into the overcurrent comparator circuit. Figure 7 U14A in the circuit is used for fast protection. When I_OUT is too large, COMP_OUT is output at a low level. After passing through inverter U13, a high-level SHORT signal is output, which shuts off the main power supply.

[0046] The sampling resistor branch outputs a high-precision current signal OC_DET and a second current signal I_Sense via the sampling signal conditioning circuit (participating in...). Figure 3 OC_DET passes through the current comparator circuit ( Figure 3 The U14B in the FPGA controller generates an overcurrent cutoff signal OC_SHUT, and I_Sense is sent to the ADC pin of the FPGA controller for closed-loop regulation.

[0047] Link 3: Protection and latching link (overcurrent / short circuit → power failure) When the overcurrent comparator circuit ( Figure 3 When U14B detects an abnormal current, it outputs an overcurrent cutoff signal OC_SHUT to the gate forced turn-off circuit, directly pulling down the gate drive signal POW_OCP. See [link to relevant documentation]. Figure 5 This enables nanosecond-level hardware pulse interception.

[0048] At the same time, when the abnormality detection circuit detects an abnormal current, it activates the overcurrent comparator circuit ( Figure 7 The output COMP_OUT of U14A is latched to generate a short-circuit latch signal SHORT.

[0049] The following section will introduce each of the functional modules one by one.

[0050] I. Current Sampling Circuit The current sampling circuit comprises two parallel detection branches, each serving a different detection requirement. The two branches work together, providing the physical basis for dynamic weight fusion.

[0051] Hall sensor branch, see Figure 7 A Hall current sensor U12 is used, connected in series in the discharge circuit. Based on the Hall effect principle, U12 linearly converts the discharge current into a voltage signal I_OUT. This branch is characterized by extremely high bandwidth (up to the MHz level), enabling rapid response to transient changes in current, making it suitable for breakdown edge detection and rapid short-circuit determination. However, its accuracy is relatively low, and it is greatly affected by temperature, making it unsuitable for accurate measurement of steady-state current.

[0052] See the sampling resistor branch. Figure 3A precision sampling resistor (connected in series on the low-voltage side of the discharge circuit) is used. The voltage drop across its terminals is proportional to the discharge current. The sampled voltage signal Ton_Sense is fed into the non-inverting input of operational amplifier U16A via resistor R77. U16A forms a non-inverting amplifier circuit and outputs the signal OC_DET. OC_DET is divided into two paths: one path is fed into the inverting input of the overcurrent comparator circuit (comparator U14B) via resistor R66 and compared with OC_ADJ output by the threshold reference DAC circuit. When the OC_DET voltage exceeds OC_ADJ, comparator U14B outputs a high-level overcurrent cutoff pulse signal OC_SHUT; the other path is fed into the non-inverting input of operational amplifier U16B via resistor R76, and after further amplification, outputs the second current signal I_Sense. I_Sense is fed into the ADC pin of the FPGA controller for closed-loop regulation. This branch is characterized by high accuracy, good linearity, and low temperature drift, making it suitable for precise measurement of steady-state current and closed-loop control. However, its response speed is limited by the operational amplifier bandwidth and is not as fast as that of the Hall sensor branch.

[0053] II. Gate forced turn-off circuit The OC_SHUT signal is sent to the gate forced shutdown circuit. See also... Figure 5 The core of the gate forced turn-off circuit is the N-channel MOSFET Q5, whose gate receives the OC_SHUT signal through resistor R78. When OC_SHUT is high, Q5 turns on, pulling the gate drive signal POW_OCP low to DGND through resistor R73, thus causing OCP to output a low level, thereby forcibly turning off the subsequent power MOSFETs Q3 and Q4. This path does not pass through the FPGA, and the response time is in the nanosecond range, making it the first line of defense against instantaneous overcurrent in this invention. Capacitor C66 is used for filtering to prevent false triggering caused by noise.

[0054] The key technological advantage of this circuit lies in its nanosecond-level response time, which is far faster than the microsecond-level response time of FPGA software processing. This means that the hardware has already completed the pulse-cutting action before the FPGA detects an overcurrent event, effectively protecting the power devices from instantaneous high-current surges.

[0055] III. Short-circuit state latching circuit The core of the short-circuit state latch circuit is comparator U14A and inverter U13 (see Figure 7 ) and single-pole single-throw analog switch U10 (see Figure 8 ).

[0056] Under normal conditions, the output of comparator U14A is pulled up to a 5V high level by resistor R51. The non-inverting input (COMP+) of the comparator is connected to a reference voltage, which is obtained by voltage division by resistors R58, R59, and R62, and filtered by capacitors C61, C62, and C63. At this time, the reset signal POW_RST output by the FPGA is low or floating, and the NO pin of the short-circuit latch circuit U10 is connected to the COM pin, connecting the COMP+ node to the comparator output COMP_OUT.

[0057] When the discharge current is normal, the I_OUT signal output by the Hall current sensor U12 is small, the voltage at the inverting input of comparator U14A is lower than that at the non-inverting input, U14A outputs a high level, diode D15 is reverse cut off, and the output remains at a high level of 5V. After passing through inverter U13, a low-level SHORT signal is output, indicating that no short circuit has occurred.

[0058] When the discharge current increases abnormally, the I_OUT signal increases, causing the voltage at the inverting input of comparator U14A to exceed that at the non-inverting input, and the output of U14A jumps to a low level. At this time, since the COMP+ node is connected to COMP_OUT through the conducting short-circuit latch circuit U10, the potential of the COMP+ node is clamped to a low level of approximately 0.6V by diode D15. Even if the I_OUT signal subsequently falls back to zero, the voltage at the non-inverting input of comparator U14A remains lower than that at the inverting input, and the output is locked in a low level state. This low level is then output as a high-level SHORT signal by inverter U13.

[0059] The SHORT signal is sent to the second input of AND gate U18 in the main power supply on / off control circuit, forcibly disconnecting the main power supply. Simultaneously, the SHORT signal is fed back to the FPGA controller. Upon receiving the SHORT signal, the FPGA waits for a preset deionization time (e.g., 100μs) and then issues POW_RST to release the latch. If SHORT remains high after release, the waiting time is extended and the process is repeated.

[0060] IV. Main power supply on / off control circuit Main power supply on / off control circuit, such as Figure 1 As shown, its core is a power enable link consisting of AND gate U18, transistor Q6, relay K3, and emergency switch S5.

[0061] The first input of AND gate U18 is connected to the power enable signal POW_CTRL output from the FPGA controller, and the second input is connected to the short-circuit latch signal SHORT from the short-circuit state latch circuit. Under normal circumstances, POW_CTRL is high and COMP_OUT is high (indicating no short circuit). After passing through inverter U13, it outputs a low level SHORT. AND gate U18 outputs a high level, driving transistor Q6 to conduct, energizing the coil of relay K3, and connecting the main power supply, i.e., CV_Pow and +Pow are connected.

[0062] When a short circuit occurs, COMP_OUT jumps to a high level, which, after passing through inverter U13, outputs a low level (SHORT). AND gate U18 outputs a low level, transistor Q6 turns off, relay K3 releases, and the main power supply is physically disconnected. Emergency switch S5 is connected to the base of transistor Q6. Pressing S5 forces the base of Q6 low, achieving manual power-off independent of the FPGA.

[0063] Resistor R87 and capacitor C70 are connected to the base of transistor Q6 to ensure a stable control signal. Resistor R84 and LED D21 form an indicator light circuit, which lights up synchronously when the relay is energized. Diode D20 is a freewheeling diode for the relay coil to prevent high-voltage spikes when the relay is turned off.

[0064] The technical advantage of this circuit lies in its use of hardware AND gate logic to implement the AND control between the power enable signal and the short-circuit latch signal, ensuring that the main power supply is physically disconnected via a relay in the event of a short circuit or overcurrent, providing dual safety protection. This layer of protection is completed in milliseconds and serves as the second line of defense against persistent short circuits.

[0065] V. Threshold Reference DAC Circuit Threshold reference DAC circuit, such as Figure 2 As shown. The DAC chip U17 (such as TI's DAC7311 or an equivalent device) is connected to the FPGA controller via an SPI interface. The FPGA writes set values ​​to U17 via the SPI bus (OC_DATA, OC_CLK, OC_CS), and U17 outputs an analog voltage signal OC_ADJ. OC_ADJ serves as the reference threshold voltage for overcurrent comparison and is fed into the non-inverting input of the overcurrent comparator circuit (comparator U14B). See [link to relevant documentation]. Figure 3 .

[0066] Resistors R89, R90, and R91 are current-limiting resistors for the SPI signal line, resistor R81 is the current-limiting resistor for the DAC output, and capacitor C69 is the output filter capacitor used to filter out high-frequency interference.

[0067] The technical advantage of this circuit is that the overcurrent protection threshold can be set online by FPGA programming, providing a hardware basis for subsequent adaptive threshold updates.

[0068] VI. Gate Driver Circuit and Power Discharge Bridge Circuit Gate drive stage circuit such as Figure 4 As shown. The gate driver U15 (such as TI's UCC27524 or an equivalent device) receives the PWM signal POW_PWM from the FPGA controller and outputs an inverted drive signal OCP. The OCP signal passes through the power discharge bridge circuit ( Figure 6 The drive network (R57, R61, D14, etc.) in the discharge circuit drives two parallel power MOSFETs Q3 and Q4 (such as IRFP4668PBF, whose low on-resistance Rds(on) can reduce conduction loss) to alternately turn on and off, controlling the on and off of the discharge circuit.

[0069] In summary, the signal flow of this invention can be summarized into the following closed loop: 1. Overcurrent protection mode: Sampling resistor branch → Overcurrent comparator circuit → OC_SHUT → Gate forced turn-off circuit → Pull-down POW_OCP → Power MOSFET turn-off; 2. Short-circuit latching mode: Hall sensor branch → Short circuit state latching circuit → SHORT → Main power supply on / off control circuit → Relay disconnects main power supply.

[0070] Although the two closed loops share the same discharge current as the signal source, they are completely independent in four dimensions: branch selection, comparator configuration, actuator, and whether latching is used. This forms a protection architecture that separates fast and slow operation, light and heavy operation, and action and memory. The advantages of their combination are as follows: First, minor faults are quickly self-recovered, while major faults are hard-locked to prevent recurrence. The overcurrent protection mode uses a sampling resistor branch, comparing the signal with the adjustable threshold OC_ADJ via comparator U14B. The generated OC_SHUT signal only turns off the gate without latching. After the current returns to normal, the pulse cutoff signal is automatically canceled, suitable for rapid pulse cutoff and automatic recovery of high-frequency instantaneous overcurrents. The short-circuit latching mode uses a Hall sensor branch, utilizing its high bandwidth to capture the current spike at the moment of breakdown. Once triggered, the SHORT signal is maintained through a self-locking circuit until the FPGA actively sends a reset pulse. The former is gentle, can be triggered at high frequencies, and can automatically recover; the latter is severe and requires software confirmation before clearing. The combination of these two ensures that ordinary overcurrents will not escalate to a power outage, while truly severe short circuits are firmly latched, avoiding repeated oscillations of "pulse cutoff—reset—re-short circuit."

[0071] Second, the two branches are physically independent, with backup in case of single-layer failure. Overcurrent protection relies on the sampling resistor branch and comparator U14B, while short-circuit latching relies on the Hall sensor branch and comparator U14A. The two branches, two comparators, and two sets of execution endpoints do not overlap. If U14B or the sampling resistor branch fails for any reason, the Hall sensor branch can still trigger latching and disconnect the main relay via U14A; if Q5 sticks and causes gate turn-off failure, the relay can still physically cut off the main power supply. The two branches serve as backups for each other, resulting in higher protection reliability than a single-branch dual-threshold scheme.

[0072] Third, the Hall effect sensor branch is not used in closed-loop regulation; it is dedicated to fast hard latching. Similarly, the sampling resistor branch is not used in hard latching; it is dedicated to steady-state accurate comparison. Hall effect sensors have large temperature drift and high zero drift; including them in the steady-state closed loop would cause threshold reference drift. Therefore, this solution uses them only for fast hard latching of the U14A. The sampling resistor branch has high accuracy, but its response is limited by the op-amp bandwidth. This solution does not directly drive the latch circuit with it; instead, it feeds the signal to the U14B and ADC for steady-state overcurrent comparison and closed-loop regulation. The two branches are separated in the protection layer, achieving redundancy and division of labor.

[0073] Fourth, it achieves signal-level coordination with the multi-level recovery state machine. OC_SHUT serves as the state machine's entry trigger signal, initiating the arc extinction confirmation and trial reignition process; SHORT, as the state machine's "prohibition signal," prevents trial reignition while the latch is not released. If the state machine triggers OC_SHUT again during the trial reignition phase, it indicates that the gap has not yet returned to normal, reverting to the arc extinction phase and extending the deionization time; if SHORT is triggered, it indicates a hard short circuit rather than normal current flow, directly entering the extended deionization phase. These two signals enable the state machine to distinguish between "soft recovery failure" and "hard fault," which is impossible with a single-branch scheme.

[0074] Furthermore, in addition to the first and second layers of protection (i.e., defenses) mentioned above, this invention also includes a third layer of protection. This third layer consists of temperature monitoring and emergency power-off. The temperature monitoring circuit monitors the temperature of the power devices in real time and triggers frequency reduction or pauses discharge when the temperature exceeds a safe threshold. The emergency switch S5 provides a manual power-off channel independent of the FPGA, serving as the third line of defense against extreme faults.

[0075] Based on the aforementioned current sampling circuit (Hall sensor branch and sampling resistor branch), a dynamic weight fusion algorithm and a multi-level recovery state machine are further introduced. The dynamic weight fusion algorithm is used for fine control of the discharge current, and the multi-level recovery state machine is used to realize the automatic recovery of short-circuit faults.

[0076] I. Dynamic Weight Fusion of Two Branches The FPGA controller executes a dynamic weight fusion algorithm in each PWM cycle. The dynamic weight fusion algorithm is implemented in digital logic inside the FPGA controller, and its input comes from the two branches of the aforementioned current sampling circuit: Hall sensor branch signal I_OUT: High bandwidth, can quickly reflect transient changes in current, but relatively low accuracy and is greatly affected by temperature.

[0077] The sampling resistor branch signal I_Sense has high accuracy, good linearity, and low temperature drift, making it suitable for accurate measurement of steady-state current. However, its response speed is limited by the op-amp bandwidth, and it has a tracking lag for discharge breakdown spike signals at the level of hundreds of nanoseconds.

[0078] In conventional schemes, I_OUT and I_Sense are used independently. I_OUT is used for short-circuit latching, and I_Sense is used for closed-loop regulation. The advantages of the two signals cannot be simultaneously obtained in the same control loop. Based on this, the present invention introduces a dynamic weighted fusion algorithm to dynamically weight and fuse the two signals according to the discharge stage into a synthetic current signal I_synth, thereby obtaining both fast response capability at the breakdown edge and high-precision measurement capability in the steady state.

[0079] The signal flow of the dynamic weight fusion algorithm is as follows: The FPGA controller simultaneously acquires both I_OUT and I_Sense signals in each PWM cycle and dynamically calculates the fusion weight based on the real-time characteristics of the discharge phase. (a) Breakdown edge stage (current rise slope > set threshold K1) When the slope of the current rising edge is detected to be greater than the set threshold K1, it is determined to be the moment of breakdown. At this time, the impedance of the discharge gap changes abruptly from a high-resistance state to a low-resistance state, and the current rises from zero to its peak value in a very short time. During this stage, the response speed of the detection system is crucial—if the response is too slow, it may lead to pulse delay, resulting in excessive energy injection and damage to the workpiece or electrode.

[0080] Therefore, the dynamic weight fusion module increases the weight W_Hall of the Hall sensor branch signal I_OUT during the breakdown edge stage (e.g., W_Hall = 0.8, W_Res = 0.2), utilizing its high bandwidth characteristics to quickly capture the breakdown point and ensure that the overcurrent comparator circuit can respond in a timely manner.

[0081] (ii) Steady-state discharge stage (current change rate < set threshold K2) Once the current reaches a stable phase, the impedance of the discharge gap tends to stabilize, and the current fluctuation amplitude decreases. During this phase, detection accuracy becomes paramount—precise current measurement helps the closed-loop control system maintain stable discharge energy.

[0082] Therefore, the dynamic weight fusion module increases the weight W_Res of the sampling resistor branch signal I_Sense during the steady-state discharge phase (e.g., W_Hall = 0.1, W_Res = 0.9), utilizing its high-precision characteristics to accurately monitor the discharge state and provide accurate feedback signals for closed-loop regulation.

[0083] (iii) Arc extinction edge stage (current falling edge slope > set threshold K3) When the current drop slope is detected to be greater than the set threshold K3, the arc extinction phase is determined. At this time, the plasma channel in the discharge gap is dissipating, and the current drops from its peak value to zero. During this phase, it is necessary to accurately determine whether deionization is complete in order to decide whether to allow the next discharge.

[0084] Therefore, the dynamic weight fusion module takes the average of the two signals (e.g., W_Hall = 0.5, W_Res = 0.5) during the arc extinction edge stage as a synthesized current signal to determine whether the gap deionization is complete.

[0085] The formula for calculating the synthesized current signal is as follows: I_synth = W_Hall × I_OUT + W_Res × I_Sense; Among them, W_Hall + W_Res = 1, and the weight value is dynamically adjusted according to the discharge stage.

[0086] The synthesized current signal I_synth is used as input. One path is sent to the overcurrent comparator circuit (comparator U14B) to compare with the OC_ADJ output by the threshold reference DAC circuit to generate the overcurrent cutoff signal OC_SHUT. The other path is sent to the closed-loop adjustment algorithm of the FPGA controller to adjust the discharge pulse parameters.

[0087] II. Multi-level recovery state machine The multi-level recovery state machine is implemented as a finite state machine (FSM) inside the FPGA controller, and its trigger condition is the activation (high level) of the overcurrent cutoff pulse signal OC_SHUT.

[0088] When OC_SHUT is high, the gate forced turn-off circuit immediately activates, pulling the gate drive signal POW_OCP low, turning off power MOSFETs Q3 and Q4, and stopping the discharge. Simultaneously, the multi-stage recovery state machine starts, executing the following three stages sequentially: Phase 1: Arc Extinguishing Confirmation Phase After the state machine enters the arc extinction confirmation phase, the FPGA controller continuously monitors the I_Sense signal (sampling resistor branch) and waits for the discharge current to drop below the preset arc extinction threshold I_ext (e.g., 0.5A). When the current drops below I_ext, the state machine starts a timer to wait for the preset minimum deionization time T_deion (e.g., 50μs).

[0089] The purpose of this stage is to ensure that the plasma channel within the discharge gap is completely dissipated and the dielectric recovers its insulating strength. If the current rises again during the deionization time (possibly caused by residual plasma), the timer is reset and the timing restarts.

[0090] When the timer reaches T_deion, the state machine enters phase two.

[0091] Phase Two: Probing for Rekindling After the state machine enters the test reignition phase, the FPGA controller outputs a test pulse with extremely low energy through the gate driver stage circuit. The pulse width T_probe of this test pulse (e.g., 0.5μs) is much smaller than the pulse width of the normal discharge pulse (e.g., 5μs), so the injected energy is only about one-tenth of that of the normal pulse, and will not damage the discharge gap.

[0092] After the probe pulse is issued, the FPGA controller immediately monitors the change in the synthesized current signal I_synth: Scenario A: Probe successful (current rises rapidly but overcurrent is not triggered) If I_synth rises rapidly after the test pulse is issued (indicating that the gap has been broken down), but the current value after the rise does not exceed the overcurrent threshold OC_ADJ (indicating that the breakdown is normal and no short circuit has occurred), then the test is considered successful and the gap has returned to normal.

[0093] At this point, the state machine enters phase three.

[0094] Scenario B: Probe fails (current does not rise or overcurrent is triggered) If I_synth does not rise after the test pulse is issued (indicating that the gap has not been broken down and is still in an open circuit or high impedance state), or if I_synth rises rapidly and triggers OC_SHUT (indicating that the gap is still in a short circuit state), then the test is considered to have failed and the gap has not yet returned to normal.

[0095] At this point, the state machine returns to phase one, re-executes the arc extinguishing confirmation and deionization, and appropriately extends the deionization time (for example, increasing the deionization time by 20% for each failure until the maximum limit is reached).

[0096] Phase Three: Normal Recovery Phase After the state machine enters the normal recovery phase, the FPGA controller resumes the normal discharge pulse parameter output (e.g., pulse width 5μs, pause 6μs), and the discharge processing continues.

[0097] Meanwhile, the state machine records the success / failure statistics of this recovery for subsequent threshold adaptive updates.

[0098] III. Threshold Adaptive Update The threshold adaptive update mechanism is executed inside the FPGA controller via timed interrupts or event triggers. Its core is to dynamically adjust the output voltage OC_ADJ of the threshold reference DAC circuit through the SPI interface.

[0099] Update timing: The FPGA controller performs a threshold update once every N discharge pulses (e.g., N=1000).

[0100] Update basis: The FPGA controller collects discharge state data within this window or pulse sequence, mainly including: Average current value I_avg: The average value of the synthesized current signal I_synth within this period; Short circuit count N_short: The number of times OC_SHUT is triggered within this cycle; Overcurrent count N_over: The number of times the short-circuit state latch is triggered within this cycle.

[0101] Update Algorithm: The threshold adaptive update algorithm is based on the following principles: Principle 1: Follow the gap impedance drift As the dressing process progresses, the bonding agent between the grinding wheel and the cutting tool gradually thins, the wheel radius gradually decreases, and the impedance of the discharge gap slowly increases. This leads to a gradual decrease in the average current at the same discharge voltage. If the overcurrent threshold remains unchanged, what was originally a "normal" discharge may be misjudged as "undercurrent," causing the protection system to trigger falsely.

[0102] Therefore, when the statistical results show that the average current I_avg decreases for M consecutive cycles (M is the preset observation window length, such as 10 cycles), the FPGA controller writes a new setting value to the threshold reference DAC circuit through the SPI interface, appropriately reducing the OC_ADJ voltage (i.e. reducing the overcurrent threshold) so that it follows the change in gap impedance.

[0103] Principle Two: Prevent frequent false triggers If the statistical results show that the number of short circuits N_short or the number of overcurrents N_over is too high, it indicates that the current overcurrent threshold may be too lenient, causing some abnormal discharges to not be blocked in time. In this case, the FPGA controller appropriately increases the OC_ADJ voltage (i.e., increases the overcurrent threshold) to tighten the protection standard.

[0104] The above description is merely a specific embodiment of the present invention or an explanation of that embodiment. The scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. The scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A precision machine tool non-contact EDM dressing drive circuit based on state parameter adaptation, characterized in that, include: The current sampling circuit includes a Hall sensor branch and a sampling resistor branch, which are used to output a first current signal and a second current signal, respectively. The dynamic weight fusion module, connected to the Hall sensor branch and the sampling resistor branch, is used to dynamically allocate the weights of the first current signal and the second current signal according to the real-time characteristics of the discharge stage and fuse them into a composite current signal. An overcurrent comparison circuit, connected to the dynamic weight fusion module, is used to compare the synthesized current signal with the overcurrent protection threshold voltage to generate an overcurrent cutoff signal. An FPGA controller, connected to the dynamic weight fusion module and the overcurrent comparison circuit, is used to output discharge pulses; A threshold reference DAC circuit, connected to the FPGA controller and the overcurrent comparator circuit, is used to output an adjustable overcurrent protection threshold voltage to the overcurrent comparator circuit. The FPGA controller is also used to dynamically update the output voltage of the threshold reference DAC circuit through the SPI interface based on the discharge state statistics.

2. The precision machine tool non-contact EDM dressing drive circuit based on state parameter adaptation according to claim 1, characterized in that, It also includes a multi-level recovery state machine, connected to the dynamic weight fusion module and the FPGA controller, used to sequentially execute the following recovery stages after the overcurrent cutoff signal is triggered: Arc extinction confirmation phase: wait for the discharge current to drop below the preset arc extinction threshold and maintain the preset minimum deionization time; Trial reignition stage: Output a trial pulse with energy lower than the normal discharge pulse to detect whether the breakdown was successful; Normal recovery phase: After successful reignition test, normal discharge pulse parameter output is restored.

3. The precision machine tool non-contact EDM dressing drive circuit based on state parameter adaptation according to claim 2, characterized in that, The multi-level recovery state machine is also configured to: when the test reignition stage is determined to be a test failure, return to the arc extinguishing confirmation stage and extend the deionization time.

4. The precision machine tool non-contact EDM dressing drive circuit based on state parameter adaptation according to claim 1, characterized in that, The dynamic weight fusion module is configured as follows: When the current rise slope is greater than a first set threshold, the weight of the first current signal is increased. When the rate of change of current is less than a second set threshold, the weight of the second current signal is increased; When the slope of the current falling edge is greater than the third set threshold, the average of the first current signal and the second current signal is taken.

5. The precision machine tool non-contact EDM dressing drive circuit based on state parameter adaptation according to claim 1, characterized in that, The FPGA controller is also configured to: When the average current shows a decreasing trend for M consecutive cycles, the overcurrent protection threshold voltage is reduced. When the number of short circuits or overcurrents exceeds the set value, the overcurrent protection threshold voltage is increased.

6. The precision machine tool non-contact EDM dressing drive circuit based on state parameter adaptation according to claim 1, characterized in that, It also includes a short-circuit state latching circuit, which is connected to the current sampling circuit and is used to generate and latch a short-circuit latching signal when a short circuit or overcurrent is detected.

7. The precision machine tool non-contact EDM tool dressing drive circuit based on state parameter adaptation according to claim 6 further includes a main power supply on / off control circuit, comprising: An AND gate circuit, whose first input terminal is connected to the power enable signal output by the FPGA controller, and whose second input terminal is connected to the short-circuit latch signal; The switching transistor is controlled by the output of the AND gate circuit; The relay is connected in series in the main power supply circuit and is controlled by the switching transistor; An emergency switch, connected to the control electrode of the switching transistor, is used to forcibly shut down the switching transistor in an emergency.

8. The precision machine tool non-contact EDM dressing drive circuit based on state parameter adaptation according to claim 6 or 7, characterized in that, It also includes a temperature monitoring circuit, which is connected to the FPGA controller to monitor the temperature of the power devices and trigger frequency reduction or pause discharge operation when the temperature exceeds a safety threshold.

9. The precision machine tool non-contact EDM dressing drive circuit based on state parameter adaptation according to claim 1, characterized in that, It also includes a gate forced turn-off circuit, which is connected to the gate of the overcurrent comparator circuit and the power MOSFET, and is used to directly pull down the gate drive signal when the overcurrent cutoff signal is valid, thereby forcibly turning off the power MOSFET.

Images