A chemical mechanical polishing method for preparing a polycrystalline SiC article by CVD method and the article

Abstract

The present application relates to a kind of for the chemical mechanical polishing method and product for preparing polycrystalline SiC product by CVD method, and the chemical mechanical polishing method, including the following steps: using first chemical mechanical polishing fluid to the CVD method for preparing polycrystalline SiC substrate after topography modification processing is carried out topography modification rough polishing, first chemical mechanical polishing fluid includes colloidal silica, auxiliary abrasive, oxidizing agent, pH regulator and dispersing agent;Using second chemical mechanical polishing fluid carries out grain boundary homogenization polishing, and second chemical mechanical polishing fluid includes colloidal silica, oxidizing agent, complexing agent, surfactant and grain boundary corrosion inhibitor;Using third chemical mechanical polishing fluid carries out finishing, and third chemical mechanical polishing fluid includes the colloidal silica of particle size 10-80 nm, weak oxidizing agent and low metal ion complexing agent, after cleaning and drying, obtain CVD method for preparing polycrystalline SiC product.The present application reduces grain boundary depression and grain pull-out by grain boundary corrosion inhibitor, low selectivity oxidation and stage pressure control.

Description

Technical Field

[0001] This invention relates to the field of semiconductor precision ceramic component processing technology, and in particular to a chemical mechanical polishing method and product for preparing polycrystalline SiC products by CVD. Background Technology

[0002] Silicon carbide (SiC) possesses high hardness, high thermal conductivity, high wear resistance, high corrosion resistance, low coefficient of thermal expansion, and excellent stability in plasma environments, and has been widely used in third-generation semiconductor wafers, power device substrates, and core components of semiconductor process equipment. As advanced etching, deposition, epitaxy, and heat treatment processes place increasingly higher demands on cleanliness, particle control, plasma corrosion resistance, and dimensional stability, high-purity polycrystalline Bulk SiC prepared by CVD is increasingly being used in high-end components such as etching rings, spray heads, spray disks, and focusing rings.

[0003] Currently, the precision machining of single-crystal SiC wafers such as 4H-SiC and 6H-SiC has formed relatively mature grinding, polishing, CMP, and cleaning processes. CMP of single-crystal SiC wafers usually focuses on the crystal orientation difference of the Si or C face, oxidation reaction rate, subsurface damage removal, and epitaxial-level surface quality. Its main goal is to obtain a low-defect wafer surface that can be used for epitaxial growth and device fabrication.

[0004] However, polycrystalline Bulk SiC products prepared by CVD differ significantly from single-crystal SiC wafers, and the CMP process for single-crystal SiC wafers cannot be simply applied. Single-crystal SiC wafers have a continuous lattice and definite crystal orientation, and the removal behavior during CMP is mainly related to the Si plane, C plane, off-center angle, defects, and oxide layer formation; while CVD polycrystalline Bulk SiC consists of a large number of grains and grain boundaries, and different grain orientations, grain sizes, grain boundary phases, deposited layered structures, and residual stress all affect material removal.

[0005] From the perspective of mechanical properties, single-crystal SiC exhibits anisotropic hardness, elastic modulus and fracture behavior in different crystal orientations; while polycrystalline CVD-SiC may appear to be approximately isotropic macroscopically, but microscopically there are differences in hardness between grains, differences in grain boundary bonding strength, local porosity or deposition defects, and grain boundary depression, grain pull-out, local pitting and particle release are more likely to occur during CMP.

[0006] From the perspective of corrosion resistance mechanisms, the corrosion resistance of single-crystal SiC is mainly affected by crystal planes, defect density, surface damage, and impurities; while for polycrystalline CVD-SiC, in addition to the corrosion resistance of the grain itself, it is also affected by grain boundary continuity, grain boundary impurities, micropores, voids, and deposition interfaces. In a plasma etching environment, grain boundary regions may become the starting point for preferential corrosion and particle release. Therefore, CMP for components such as etching rings and spray heads must not only pursue low Ra, but also suppress preferential grain boundary corrosion and particle generation.

[0007] Existing mature single-crystal SiC CMP processes typically focus on wafer-level surface flatness and epitaxial-level damage removal. However, CVD polycrystalline Bulk SiC products also need to simultaneously meet requirements for component geometry, thickness consistency, hole region protection, inner and outer edge over-polishing control, grain boundary homogenization, and semiconductor cavity corrosion resistance. For example, for high-end etching rings, spray heads, and other products, some customers require them to achieve geometric and surface quality indicators similar to those of single-crystal SiC wafers: TTV≤3 μm, LTV≤1 μm, BOW≤10 μm, Warp≤20 μm, rough polishing Ra≤10 nm, and fine polishing Ra≤1 nm. Traditional mechanical grinding, free abrasive polishing, or directly replicating single-crystal SiC wafer CMP processes are difficult to reliably achieve these specifications. Summary of the Invention

[0008] The purpose of this invention is to provide a chemical mechanical polishing method and product for preparing polycrystalline SiC products by CVD, in order to solve the problems that the CMP process for single-crystal SiC wafers is difficult to directly adapt to the grain / grain boundary structure of polycrystalline CVD Bulk SiC, that polycrystalline SiC is prone to preferential grain boundary etching, grain pull-out, grain boundary depression and particle release in CMP, and that the pressure distribution of conventional wafer CMP is not applicable due to non-standard wafer shape, annular edges, hole areas, trenches and uneven thickness of components such as etching rings and spray heads.

[0009] To achieve the above objectives, the present invention adopts the following technical solution: A chemical mechanical polishing method for preparing polycrystalline SiC products by CVD includes the following steps: A first chemical mechanical polishing slurry was used to perform morphology correction and rough polishing on a polycrystalline SiC substrate prepared by CVD after morphology correction processing. The first chemical mechanical polishing slurry includes colloidal silica, auxiliary abrasive particles, oxidant and dispersant. Grain boundary homogenization polishing is performed using a second chemical mechanical polishing slurry, which includes colloidal silica, oxidant, complexing agent, surfactant, and grain boundary corrosion inhibitor. Fine polishing is performed using a third chemical mechanical polishing slurry, which includes colloidal silica with a particle size of 10-80 nm, a weak oxidant, and a low-metal ion complexing agent. After cleaning and drying, polycrystalline SiC products prepared by CVD method are obtained.

[0010] Preferably, the first chemical mechanical polishing slurry comprises, by weight, the following components: 5-35 parts colloidal silica, 0.01-5 parts auxiliary abrasive particles, 0.5-8 parts oxidant and 0.1-1 parts dispersant, with a pH of 7.5-11.5.

[0011] Preferably, in the morphology correction and rough polishing step, the polishing pressure is 10-40 kPa, and the surface roughness Ra after polishing is ≤10nm.

[0012] Preferably, the second chemical mechanical polishing solution comprises, by weight: 15-20 parts colloidal silica, 0.6-2 parts weak oxidant, 0.1-2 parts complexing agent and 0.1-2 parts grain boundary corrosion inhibitor, with a pH of 6.5-10.5.

[0013] Preferably, in the grain boundary homogenization polishing step, the polishing pressure is 5-25 kPa, and the grain boundary depression depth is controlled within 5 nm.

[0014] Preferably, the third chemical mechanical polishing slurry, by weight, comprises the following components: 5-10 parts of colloidal silica with a particle size of 10-80 nm, 0.1-1.5 parts of a weak oxidant, and 0.1-2 parts of a low-metal ion complexing agent.

[0015] Preferably, the metal impurity content of the third chemical mechanical polishing slurry is less than 100 ppb, and the particle size D50 is 10-60 nm; in the fine polishing step, the polishing pressure is 2-12 kPa, and the surface roughness Ra after fine polishing is ≤1 nm.

[0016] Preferably, a hard or medium-hard polyurethane polishing pad is used in the rough polishing stage for morphology correction, a medium-hardness porous polishing pad is used in the grain boundary homogenization polishing stage, and a soft or velvety polishing pad is used in the fine polishing stage.

[0017] Preferably, the chemical mechanical polishing method further includes the following steps: Provides CVD method for preparing polycrystalline SiC substrates; The polycrystalline SiC substrate prepared by the CVD method was characterized before processing to obtain its thickness distribution, local thickness variation, bending amount, warping amount, surface roughness, grain size, grain boundary exposure state and residual stress distribution, and a surface removal amount map was established based on this. The polycrystalline Bulk SiC substrate is subjected to morphology correction processing based on the surface removal amount map to obtain the CVD-prepared polycrystalline SiC substrate after morphology correction processing.

[0018] A CVD method for preparing polycrystalline SiC products using the above method is disclosed. The products are etching rings, spray heads, spray disks, focusing rings, or support rings, and their processed components meet the following specifications: TTV≤3 μm; LTV≤1 μm; BOW≤10 μm; Warp≤20 μm; rough polished surface Ra≤10 nm; fine polished surface Ra≤1 nm.

[0019] Compared with the prior art, the beneficial effects of the present invention are as follows: This invention designs a CMP process for CVD polycrystalline Bulk SiC, addressing issues related to grain size, grain boundaries, residual stress, and corrosion sensitivity. By employing grain boundary corrosion inhibitors, a low-selectivity oxidation system, and staged pressure control, it reduces grain boundary depressions and grain pull-out. It is particularly suitable for non-standard wafer products such as etching rings, spray heads, and spray disks. It not only achieves a finely polished surface with Ra≤1 nm but also controls TTV, LTV, BOW, and Warp. Furthermore, grain boundary homogenization and semiconductor-grade cleaning reduce particulate sources during plasma service.

[0020] This method enables CVD polycrystalline Bulk SiC products to achieve processing qualities of TTV≤3 μm, LTV≤1 μm, BOW≤10 μm, Warp≤20 μm, rough polishing Ra≤10 nm, and fine polishing Ra≤1 nm. This invention differs from the CMP process for single-crystal SiC wafers. Addressing the issues of random grain orientation, preferential grain boundary etching, localized hardness differences, and surface instability caused by porosity and internal stress in polycrystalline SiC, it establishes a high-precision, low-damage, and low-particle-release CMP process suitable for semiconductor cavity components. Attached Figure Description

[0021] Figure 1 This is a schematic flowchart of the chemical mechanical polishing method for preparing polycrystalline SiC products by CVD provided by the present invention. Detailed Implementation

[0022] The present invention will now be described in more detail with reference to the accompanying drawings. It should be noted that the following description of the present invention with reference to the accompanying drawings is merely illustrative and not restrictive. Various different embodiments can be combined with each other to form other embodiments not shown in the following description.

[0023] like Figure 1 As shown, this invention provides a chemical mechanical polishing method for preparing polycrystalline SiC products by CVD, comprising the following steps: A first chemical mechanical polishing slurry is used to perform rough polishing on a CVD-prepared polycrystalline SiC substrate after morphology correction processing. The first chemical mechanical polishing slurry includes colloidal silica, auxiliary abrasive particles, an oxidant, and a dispersant; it is used to remove the damage layer from previous machining and achieve a rough polished surface roughness Ra ≤ 10 nm. The auxiliary abrasive particles can be diamond, the oxidant can be hydrogen peroxide (with a concentration of 1-10%), and the dispersant can be polyvinylpyrrolidone (PVP) or polyethylene glycol (PEG).

[0024] A second chemical mechanical polishing (CMP) slurry is used for grain boundary homogenization polishing. This slurry comprises colloidal silica, an oxidant, a complexing agent, a surfactant, and a grain boundary corrosion inhibitor, maintaining the removal rate ratio between the polycrystalline SiC grain bulk and the grain boundary region between 0.75 and 1.30. The oxidant can be hydrogen peroxide, the complexing agent can be citric acid or disodium EDTA, and the surfactant can be alkylphenol polyoxyethylene ether or fatty alcohol polyoxyethylene ether. The grain boundary corrosion inhibitor is selected from nitrogen-containing heterocyclic compounds, carboxylates, phosphonates, silicates, polycarboxylic acid dispersants, nonionic surfactants, or combinations thereof, used to reduce the chemical reaction rate of the grain boundary region relative to the grain bulk. The pH of the second CMP slurry is 6.5-10.5. Preferably, the oxidant mass fraction is lower than that in the first CMP slurry to reduce preferential oxidation of grain boundaries and grain boundary corrosion depressions.

[0025] Fine polishing is performed using a third chemical mechanical polishing slurry, which comprises colloidal silica with a particle size of 10-80 nm, a weak oxidant, and a low-metal ion complexing agent. This results in a surface roughness Ra ≤ 1 nm after fine polishing. Following cleaning and drying, polycrystalline SiC products prepared by CVD are obtained. The weak oxidant can be peracetic acid or a low concentration of hydrogen peroxide (0.5%-1%), and the low-metal ion complexing agent can be citric acid or oxalic acid. Specifically, semiconductor-grade cleaning and drying are performed to remove residual polishing particles and metal ion contamination from grain boundaries, pores, micropores, spray holes, trenches, and edge regions. The method ensures that the processed CVD polycrystalline Bulk SiC products achieve a TTV ≤ 3 μm, LTV ≤ 1 μm, BOW ≤ 10 μm, and Warp ≤ 20 μm. The third chemical mechanical polishing slurry has a metal impurity content of less than 100 ppb, a particle size D50 of 10-60 nm, and does not contain hard agglomerates larger than 500 nm. The semiconductor-grade cleaning includes one or more of the following: mega-sound cleaning, circulating deionized water rinsing, weak alkali cleaning, weak acid cleaning, chelation cleaning, hot nitrogen drying, or vacuum drying. After cleaning, the surface particles, metal ion residues, and grain boundary residues meet the requirements for use in semiconductor plasma cavity components.

[0026] The CVD method for preparing polycrystalline Bulk SiC substrates differs from single-crystal SiC wafers. It features randomly or preferentially oriented polycrystalline grains, grain boundary networks, localized grain hardness differences, grain boundary corrosion-sensitive areas, and residual deposition stress. Grain boundary homogenization polishing is used to suppress preferential grain boundary corrosion, grain pull-out, grain boundary depressions, and grain release. Grain boundary homogenization polishing reduces the risks of preferential grain boundary corrosion, grain boundary depressions, and grain pull-out. Through a three-stage CMP process—rough polishing, grain boundary homogenization, and low-damage fine polishing—the rough polishing Ra is ≤10 nm, and the fine polishing Ra is ≤1 nm. Temporary protection of the via area and semiconductor-grade cleaning reduce particle residue in spray holes, grain boundaries, micropores, trenches, and edge regions. This method is suitable for high-end CVD polycrystalline Bulk SiC semiconductor equipment components such as etching rings, spray heads, spray disks, focusing rings, and support rings.

[0027] When the polycrystalline Bulk SiC product is a spray head or spray disc, the spray holes, micropores, countersunk holes or gas distribution holes are temporarily protected before CMP. The temporary protection includes removable polymer plugs, ceramic plugs, vacuum adsorption back supports, sacrificial filler layers or edge protection films to avoid excessive chamfering of the orifice, contamination of the orifice walls and embedding of polishing particles.

[0028] When the polycrystalline Bulk SiC product is an etching ring, a focusing ring, or a support ring, a ring carrier is used to provide differentiated support for its inner and outer edges, and edge over-polishing and circumferential TTV fluctuations are reduced through inner and outer diameter pressure compensation.

[0029] The polishing process is set to determine the endpoint online or offline. The endpoint determination criteria include one or more of the following: TTV, LTV, BOW, Warp, removal amount, friction force, motor current, polishing solution pH, redox potential, surface roughness, and grain boundary depression depth.

[0030] In a preferred embodiment, the present invention further includes the following steps: A polycrystalline Bulk SiC substrate prepared by chemical vapor deposition is provided, wherein the polycrystalline Bulk SiC substrate is used to prepare etching rings, spray heads, spray disks, focusing rings, carrier rings, liners or gas equalization components in semiconductor process cavities. The polycrystalline Bulk SiC substrate was characterized before processing to obtain its thickness distribution, local thickness variation, bending amount, warping amount, surface roughness, grain size, grain boundary exposure state and residual stress distribution, and a surface removal amount map was established based on this. Based on the surface removal amount map, the polycrystalline Bulk SiC substrate is subjected to double-sided or single-sided morphology correction processing, so that it enters the TTV, LTV, BOW and Warp pre-control window before chemical mechanical polishing.

[0031] Pre-processing characterization includes one or more of the following: white light interferometry, laser interferometry, contact profilometry, X-ray diffraction residual stress testing, Raman stress testing, scanning electron microscopy observation, electron backscatter diffraction analysis, and microhardness testing.

[0032] The surface removal map includes radial removal amount, circumferential removal amount, hole area avoidance removal amount, inner and outer edge compensation removal amount, and local high point correction removal amount, which are used to compensate for local pressure differences caused by the etched ring or spray head due to the annular structure, open structure, or asymmetric thickness distribution.

[0033] The above solution, through surface removal amount map and partition pressure compensation, enables irregularly shaped parts to still meet the TTV, LTV, BOW and Warp requirements close to those of single-crystal SiC wafers.

[0034] It should be noted that CVD polycrystalline Bulk SiC products cannot be simply processed using the CMP process for single-crystal SiC wafers. As shown in Table 1, the two types of materials have fundamental differences in crystal structure, mechanical behavior, corrosion resistance mechanisms, and processing targets. These differences necessitate a redesign of the CMP process window, polishing slurry system, pressure control, edge compensation, and cleaning methods.

[0035] Table 1. CMP Differences between Single-Crystal SiC Wafers and CVD Polycrystalline Bulk SiC Products project Single-crystal SiC wafers CVD polycrystalline bulk SiC products Impact on CMP Crystal structure Continuous lattice, well-defined crystal orientation Polycrystalline grains and grain boundary networks Polycrystalline materials carry the risk of preferential grain boundary corrosion and grain pull-out. Removal mechanism Affected by Si / C plane, off-angle, and oxidation rate Influenced by grain orientation, grain boundaries, pores, and sedimentary layer structure The selectivity ratio for grain and grain boundary removal needs to be controlled. Mechanical behavior Significant anisotropy in crystal orientation Macroscopic approximation is isotropic, microscopic non-uniformity Localized hardness differences lead to microscopic irregularities and grain boundary steps. Corrosion resistance mechanism Related to crystal planes, defects, and surface damage Related to grain boundaries, porosity, impurities, and grain size Grain boundaries may become a source of particles in a plasma environment. Processing objects Standard wafer Irregularly shaped parts such as etching rings, spray heads, and spray discs Hole area protection, edge compensation and local pressure control Process objectives Epitaxial surface, low-damage layer High flatness, low particle size, corrosion resistance, and long service life CMP needs to consider the service reliability of surface features, grain boundaries, and cavities. The present invention will be further described below with reference to embodiments.

[0036] Example 1

[0037] This embodiment describes the CMP processing of a CVD-etched polycrystalline Bulk SiC ring. A CVD-prepared Bulk SiC ring blank with an outer diameter of 350 mm, an inner diameter of 300 mm, and a thickness of 5 mm was selected. Before processing, its TTV was measured to be 12 μm, BOW to be 28 μm, and Warp to be 45 μm. After preliminary polishing, the Ra of the surface was 80 nm.

[0038] First, white light interferometry and three-coordinate thickness measurement were performed on the etched ring to obtain the thickness distribution of the inner edge, outer edge, and circumferential direction. Since the inner and outer edges of the ring-shaped product have different rigidities, there is a risk of edge over-polishing in the inner edge region; therefore, a radial pressure compensation model was established.

[0039] Subsequently, the etched ring was fixed in a ring-shaped carrier and rough polished for morphology correction using a first CMP polishing slurry. The first CMP polishing slurry consisted of 20 parts colloidal silica, 0.2 parts nanodiamond, 1.5 parts hydrogen peroxide, and 0.5 parts sodium hexametaphosphate, with the pH controlled at 9.5. The polishing pressure was 22 kPa, and the polishing pad was a medium-hard polyurethane pad. After rough polishing, Ra decreased to 8.5 nm, and TTV decreased to 5.2 μm.

[0040] Then, a second CMP polishing slurry was used for grain boundary homogenization CMP. The second CMP polishing slurry consisted of 15 parts colloidal silica, 0.6 parts hydrogen peroxide, 0.2 parts citric acid, 0.2-1 parts alkylphenol polyoxyethylene ether, and 0.1 parts benzotriazole, with the pH controlled at 8.6. The polishing pressure was reduced to 12 kPa. This stage focused on controlling the difference in removal rates between the grain boundary region and the grain bulk, ensuring the grain boundary depression depth was controlled within 5 nm.

[0041] Finally, a third CMP polishing slurry was used for low-damage fine polishing. The slurry consisted of 8 parts high-purity colloidal silica with a particle size of approximately 30 nm, 0.5 parts peracetic acid, and 0.5 parts citric acid, with a polishing pressure of 6 kPa. After fine polishing, the surface underwent megasonic cleaning, weak alkali cleaning, deionized water rinsing, and hot nitrogen drying. The final etched ring achieved a TTV of 2.6 μm, LTV of 0.8 μm, BOW of 8.5 μm, Warp thickness of 16.5 μm, and a fine polishing Ra of 0.65 nm. No continuous grain boundary corrosion trenches or obvious grain pull-out were observed on the surface.

[0042] Example 2

[0043] This embodiment describes the CMP processing of a CVD polycrystalline Bulk SiC spray head. A CVD polycrystalline Bulk SiC spray head substrate is selected, with multiple gas spray holes distributed on its surface. Unlike conventional wafers, the spray head's open areas are prone to excessive chamfering at the orifice openings, polishing slurry residue, and particle embedding within the orifice walls during the CMP process.

[0044] Before processing, a removable polymer temporary protective material is filled into the spray holes, and a vacuum adsorption support plate is installed on the back of the spray head. Local surface maps of the spray hole area and non-hole area are established using white light interference. In the rough polishing stage, a first CMP system with a low auxiliary abrasive content is used to avoid localized scratches at the hole openings. In the grain boundary homogenization stage, a second CMP system containing a grain boundary corrosion inhibitor is used to prevent preferential corrosion of the grain boundaries around the hole areas. After fine polishing, the temporary protective material is removed, and megasonic cleaning and circulating DI water rinsing are used to remove residual particles from the holes. The processing procedure and parameters are the same as in Example 1. The final spray head achieves a TTV of 2.9 μm, LTV of 0.9 μm, BOW of 9.2 μm, Warp of 18.0 μm, and a fine polishing Ra of 0.8 nm. There is no obvious edge collapse at the spray hole openings, and no obvious particle residue on the hole walls.

[0045] The above embodiments are merely preferred embodiments of the present invention and should not be construed as limiting the scope of protection of the present invention. Any non-substantial changes and substitutions made by those skilled in the art based on the present invention shall fall within the scope of protection claimed by the present invention.

Claims

1. A chemical mechanical polishing method for preparing polycrystalline SiC products by CVD, characterized in that, Includes the following steps: A first chemical mechanical polishing slurry was used to perform morphology correction and rough polishing on a polycrystalline SiC substrate prepared by CVD after morphology correction processing. The first chemical mechanical polishing slurry includes colloidal silica, auxiliary abrasive particles, oxidant and dispersant. Grain boundary homogenization polishing is performed using a second chemical mechanical polishing slurry, which includes colloidal silica, oxidant, complexing agent, surfactant, and grain boundary corrosion inhibitor. Fine polishing is performed using a third chemical mechanical polishing slurry, which includes colloidal silica with a particle size of 10-80 nm, a weak oxidant, and a low-metal ion complexing agent. After cleaning and drying, polycrystalline SiC products prepared by CVD method are obtained.

2. The chemical mechanical polishing method as described in claim 1, characterized in that, The first chemical mechanical polishing slurry comprises, by weight, the following components: 5-35 parts colloidal silica, 0.01-5 parts auxiliary abrasive particles, 0.5-8 parts oxidant and 0.1-1 parts dispersant, with a pH of 7.5-11.

5.

3. The chemical mechanical polishing method as described in claim 2, characterized in that, In the morphology correction and rough polishing step, the polishing pressure is 10-40 kPa, and the surface roughness Ra after polishing is ≤10 nm.

4. The chemical mechanical polishing method as described in claim 1, characterized in that, The second chemical mechanical polishing slurry, by weight, comprises the following components: 15-20 parts colloidal silica, 0.6-2 parts weak oxidant, 0.1-2 parts complexing agent, 0.2-1 parts surfactant and 0.1-2 parts grain boundary corrosion inhibitor, with a pH of 6.5-10.

5.

5. The chemical mechanical polishing method as described in claim 4, characterized in that, In the grain boundary homogenization polishing step, the polishing pressure is 5-25 kPa, and the grain boundary depression depth is controlled within 5 nm.

6. The chemical mechanical polishing method as described in claim 1, characterized in that, The third chemical mechanical polishing slurry, by weight, comprises the following components: 5-10 parts of colloidal silica with a particle size of 10-80 nm, 0.1-1.5 parts of a weak oxidant, and 0.1-2 parts of a low-metal ion complexing agent.

7. The chemical mechanical polishing method as described in claim 6, characterized in that, The third chemical mechanical polishing slurry has a metal impurity content of less than 100 ppb and a particle size D50 of 10-60 nm; in the fine polishing step, the polishing pressure is 2-12 kPa, and the surface roughness Ra after fine polishing is ≤1 nm.

8. The chemical mechanical polishing method as described in claim 1, characterized in that, The rough polishing stage for morphology correction uses hard or medium-hard polyurethane polishing pads, the grain boundary homogenization polishing stage uses medium-hard porous polishing pads, and the fine polishing stage uses soft or velvety polishing pads.

9. The chemical mechanical polishing method as described in claim 1, characterized in that, The chemical mechanical polishing method further includes the following steps: Provides CVD method for preparing polycrystalline SiC substrates; The polycrystalline SiC substrate prepared by the CVD method was characterized before processing to obtain its thickness distribution, local thickness variation, bending amount, warping amount, surface roughness, grain size, grain boundary exposure state and residual stress distribution, and a surface removal amount map was established based on this. The polycrystalline Bulk SiC substrate is subjected to morphology correction processing based on the surface removal amount map to obtain the CVD-prepared polycrystalline SiC substrate after morphology correction processing.

10. A CVD-prepared polycrystalline SiC product manufactured by the method according to any one of claims 1-9, characterized in that: The products are etching rings, spray heads, spray discs, focusing rings, or carrier rings, and their processed components meet the following specifications: TTV≤3 μm; LTV≤1 μm; BOW≤10 μm; Warp≤20 μm; rough polished surface Ra≤10 nm; fine polished surface Ra≤1 nm.

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