A speed regulation method of a cooling fan and a driving controller

Abstract

The application relates to the technical field of driving control, and discloses a heat dissipation fan speed regulation method and a driving controller. The method comprises the following steps: collecting a driving bus current signal in a normal operation stage of a heat dissipation fan and calculating a first harmonic distortion rate; after detecting a positive and negative rotation switching instruction jump edge and before executing phase sequence switching, calculating a first harmonic increment based on the first harmonic distortion rate; when the first harmonic increment is not lower than a preset harmonic early warning threshold, freezing a first PWM duty ratio and calculating an airflow speed deviation value and a second harmonic increment; compensating the first PWM duty ratio to obtain a second PWM duty ratio and outputting the second PWM duty ratio to the driving controller to drive the three-phase winding of the heat dissipation fan to realize chopping speed regulation. The application solves the technical problem that a single closed loop of temperature in the prior art cannot perceive the sudden change of airflow speed in a switching transient state, so that the controller can master the airflow speed deviation state and the harmonic disturbance intensity in the whole switching transient state in real time.

Description

Technical Field

[0001] This invention relates to the field of drive control technology, and in particular to a method for adjusting the speed of a cooling fan and a drive controller. Background Technology

[0002] As an indispensable thermal management component in electronic equipment and industrial machinery, the stability of the speed control of cooling fans directly affects the heat dissipation effect and operational reliability of the equipment. Current cooling fan speed control systems collect the temperature of the heat source through temperature sensors, output a PWM duty cycle based on the temperature curve, and drive the controller to adjust the fan speed accordingly.

[0003] However, in scenarios requiring forward / reverse switching, the phase sequence of the three-phase windings abruptly changes when the drive controller performs the switch. The induced back electromotive force in the stator windings is opposite in direction to the new phase sequence drive voltage, causing the winding current to fluctuate violently in a very short time, generating harmonic current components dominated by odd harmonics of the fundamental frequency. These harmonic currents are superimposed on the drive bus, interfering with the effective duty cycle of the PWM control signal and causing transient changes in fan speed and airflow velocity at the outlet. Existing single-loop temperature control is unable to detect such transient disturbances and can only passively wait for the speed to recover naturally after the switch is completed, leading to overheating of the equipment. Summary of the Invention

[0004] The main objective of this invention is to provide a cooling fan speed control method and drive controller. This invention solves the technical problem in the prior art where the single closed-loop temperature control is unaware of sudden changes in airflow speed during switching, enabling the controller to monitor the airflow speed deviation and harmonic disturbance intensity in real time throughout the switching transient process.

[0005] To achieve the above objectives, the present invention provides a method for adjusting the speed of a cooling fan, comprising the following steps: Collect the drive bus current signal during the normal operation of the cooling fan and calculate the first harmonic distortion rate; After detecting the rising edge of the forward / reverse switching command and before the phase sequence switching is executed, the first harmonic increment is calculated based on the first harmonic distortion rate; When the first harmonic increment is not lower than the preset harmonic warning threshold, freeze the first PWM duty cycle and calculate the airflow velocity deviation value and the second harmonic increment; Based on the airflow velocity deviation value and the second harmonic increment, the first PWM duty cycle is compensated to obtain the second PWM duty cycle, and the second PWM duty cycle is output to the drive controller to drive the three-phase winding of the cooling fan for chopping speed regulation.

[0006] Optionally, in a first implementation of the first aspect of the present invention, the step of acquiring the drive bus current signal during the normal operation of the cooling fan and calculating the first harmonic distortion rate includes: Collect the drive bus current signal during the normal operation of the cooling fan; The driving bus current signal is subjected to a fast Fourier transform to obtain the fundamental amplitude and the amplitudes of the 3rd, 5th and 7th harmonics; The first harmonic distortion rate is obtained by taking the square root of the sum of the squares of the amplitudes of the 3rd, 5th, and 7th harmonics and then dividing it by the fundamental amplitude.

[0007] Optionally, in a second implementation of the first aspect of the present invention, performing a fast Fourier transform on the drive bus current signal to obtain the fundamental amplitude and the amplitudes of the 3rd, 5th, and 7th harmonics includes: The drive bus current signal is sampled by an ADC to obtain the first current time-domain data; The first current time-domain data is multiplied point by point by the Hanning window coefficient to obtain the second current time-domain data; Perform a fast Fourier transform on the second current time-domain data to calculate the spectral resolution at each frequency point; The fundamental frequency and its corresponding fundamental amplitude and 3rd, 5th and 7th harmonic amplitudes are located sequentially according to integer multiples of the spectral resolution.

[0008] Optionally, in a third implementation of the first aspect of the present invention, the step of calculating the first harmonic increment based on the first harmonic distortion rate after detecting the rising edge of the forward / reverse switching command and before the phase sequence switching is executed includes: After detecting the rising edge of the forward / reverse switching command and before the phase sequence switching is executed, the second harmonic distortion rate of the drive bus current signal is recalculated; Subtracting the first harmonic distortion rate from the second harmonic distortion rate yields the first harmonic increment.

[0009] Optionally, in a fourth implementation of the first aspect of the present invention, the step of freezing the first PWM duty cycle and calculating the airflow velocity deviation value and the second harmonic increment when the first harmonic increment is not lower than a preset harmonic warning threshold includes: When the first harmonic increment is not lower than the preset harmonic warning threshold, the first PWM duty cycle is frozen and the first airflow velocity is recorded. After the phase sequence switching is performed, the second airflow velocity is collected. Calculate the airflow velocity deviation between the first airflow velocity and the second airflow velocity; The current signal of the drive bus after phase sequence switching is acquired and the second harmonic increment is calculated.

[0010] Optionally, in a fifth implementation of the first aspect of the present invention, the step of freezing the first PWM duty cycle and recording the first airflow velocity when the first harmonic increment is not lower than a preset harmonic warning threshold, and acquiring the second airflow velocity after performing phase sequence switching, includes: When the first harmonic increment is not lower than the preset harmonic warning threshold, the first PWM duty cycle is frozen, and the first airflow velocity is read from the airflow velocity sensor. Write the inverted flag bit to the drive controller direction control register to perform phase sequence switching, and collect the second airflow velocity after phase sequence switching through the airflow velocity sensor.

[0011] Optionally, in a sixth implementation of the first aspect of the present invention, the step of compensating the first PWM duty cycle based on the airflow velocity deviation value and the second harmonic increment to obtain a second PWM duty cycle, and outputting the second PWM duty cycle to the drive controller to drive the three-phase winding of the cooling fan for chopping speed regulation, includes: Calculate the first compensation amount of the airflow velocity deviation value and the second compensation amount of the second harmonic increment, and calculate the target compensation amount based on the first compensation amount and the second compensation amount; The second PWM duty cycle is calculated based on the target compensation amount and the first PWM duty cycle, and the second PWM duty cycle is loaded into the drive controller to drive the three-phase winding speed regulation of the cooling fan by chopping.

[0012] Optionally, in a seventh implementation of the first aspect of the present invention, the step of calculating a first compensation amount for the airflow velocity deviation value and a second compensation amount for the second harmonic increment, and calculating a target compensation amount based on the first compensation amount and the second compensation amount, includes: Calculate the first compensation amount for the airflow velocity deviation value, and calculate the second compensation amount for the second harmonic increment; The first compensation amount and the second compensation amount are summed to obtain the comprehensive compensation amount; When the comprehensive compensation amount exceeds the preset compensation limit, the comprehensive compensation amount is truncated to the boundary of the preset compensation limit, and the target compensation amount is output.

[0013] Optionally, in the eighth implementation of the first aspect of the present invention, after the three-phase winding speed regulation of the cooling fan is achieved by chopping, the method further includes: The FG pulse signal is acquired by the Hall sensor of the cooling fan, and the real-time speed is calculated based on the FG pulse signal; The difference between the real-time rotational speed and the target rotational speed is used to obtain the rotational speed tracking error; When the absolute value of the speed tracking error does not exceed the preset speed convergence threshold within a preset number of consecutive determinations, compensation convergence is determined and the integral accumulation term of the first compensation amount and the second compensation amount is cleared, and the third PWM duty cycle is determined. Based on the third PWM duty cycle, the first harmonic distortion rate is updated to the instantaneous harmonic distortion rate at the end of the switching transient, and the temperature and speed outer loop speed control is reactivated.

[0014] The present invention also provides a drive controller, comprising: The acquisition unit is used to acquire the drive bus current signal during the normal operation of the cooling fan and calculate the first harmonic distortion rate. The first calculation unit is used to calculate the first harmonic increment based on the first harmonic distortion rate after detecting the rising edge of the forward / reverse switching command and before the phase sequence switching is executed. The second calculation unit is used to freeze the first PWM duty cycle and calculate the airflow speed deviation value and the second harmonic increment when the first harmonic increment is not lower than the preset harmonic warning threshold. The compensation unit is used to compensate the first PWM duty cycle based on the airflow speed deviation value and the second harmonic increment to obtain the second PWM duty cycle, and output the second PWM duty cycle to the drive controller to drive the three-phase winding of the cooling fan to chop and regulate the speed.

[0015] In summary, this invention introduces a harmonic prediction and detection mechanism after the drive controller's forward / reverse switching command is triggered and before the actual phase sequence switching is executed. By moving the harmonic sensing node forward, and after the first harmonic increment triggers the compensation process, this invention simultaneously introduces two feedback dimensions: the airflow velocity deviation value and the second harmonic increment. This solves the technical problem in the prior art where the single closed-loop temperature control is unaware of sudden changes in airflow velocity during switching, enabling the controller to monitor the airflow velocity deviation and harmonic disturbance intensity in real time throughout the switching transient. Based on the above two-way normalized deviation, this invention employs a dual-channel adaptive compensation computation mechanism. By dynamically adjusting the proportional coefficient of each channel through real-time comparison of the amplitude ratio of the two channels, compensation resources are concentrated and allocated to the dominant disturbance source, avoiding the compensation efficiency loss of fixed gain control under different dominant disturbance conditions. At the same time, it introduces an integral anti-saturation processing and a dual duty cycle limiting mechanism to prevent integral saturation and duty cycle overshooting during the compensation process. After the switching transient ends, the present invention updates the steady-state reference with the converged second PWM duty cycle and simultaneously refreshes the first harmonic distortion rate to ensure the accuracy of the harmonic prediction threshold determination during the next forward and reverse switching, thereby realizing seamless connection and adaptive iterative update of the control state before and after switching. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the steps of a cooling fan speed adjustment method in one embodiment of the present invention; Figure 2 This is a schematic diagram illustrating the steps for calculating harmonic distortion rate in an embodiment of the present invention; Figure 3 This is a schematic diagram illustrating the steps for calculating the first harmonic increment in an embodiment of the present invention; Figure 4 This is a schematic diagram illustrating the steps for calculating the airflow velocity deviation and the second harmonic increment in an embodiment of the present invention; Figure 5 This is a schematic diagram of the steps for driving the three-phase winding of the cooling fan to adjust speed using chopper in an embodiment of the present invention; Figure 6 This is a schematic diagram illustrating the steps of reactivating the temperature and speed outer loop speed control in an embodiment of the present invention; Figure 7 This is a block diagram of the drive controller structure in an embodiment of the present invention.

[0017] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0019] Reference Figure 1 This embodiment provides a method for adjusting the speed of a cooling fan, including the following steps: S10: Collect the drive bus current signal during the normal operation of the cooling fan and calculate the first harmonic distortion rate; S20, after detecting the rising edge of the forward / reverse switching command and before the phase sequence switching is executed, calculate the first harmonic increment based on the first harmonic distortion rate; S30, when the first harmonic increment is not lower than the preset harmonic warning threshold, freeze the first PWM duty cycle and calculate the airflow speed deviation value and the second harmonic increment; S40, based on the airflow speed deviation value and the second harmonic increment, compensates the first PWM duty cycle to obtain the second PWM duty cycle, and outputs the second PWM duty cycle to the drive controller to drive the three-phase winding of the cooling fan for chopping speed regulation.

[0020] In this embodiment of the invention, a harmonic prediction and detection mechanism is introduced after the drive controller's forward / reverse switching command is triggered and before the actual phase sequence switching is executed. This brings the harmonic sensing node forward. After the first harmonic increment triggers the compensation process, the invention simultaneously introduces two feedback dimensions: airflow velocity deviation and the second harmonic increment. This solves the technical problem in the prior art where the single-loop temperature control is unaware of sudden changes in airflow velocity during switching, enabling the controller to monitor the airflow velocity deviation and harmonic disturbance intensity in real time throughout the switching transient. Based on the aforementioned two-way normalized deviation, this invention employs a dual-channel adaptive compensation computation mechanism. By dynamically adjusting the proportional coefficient of each channel through real-time comparison of the amplitude ratio of the two channels, compensation resources are concentrated and allocated to the dominant disturbance source, avoiding the loss of compensation efficiency under different dominant disturbance conditions with fixed gain control. Simultaneously, an integral anti-saturation processing and a dual duty cycle limiting mechanism are introduced to prevent integral saturation and duty cycle overshooting during the compensation process. After the switching transient ends, the present invention updates the steady-state reference with the converged second PWM duty cycle and simultaneously refreshes the first harmonic distortion rate to ensure the accuracy of the harmonic prediction threshold determination during the next forward and reverse switching, thereby realizing seamless connection and adaptive iterative update of the control state before and after switching.

[0021] In one example, such as Figure 2 S10 includes: S11, collect the drive bus current signal during the normal operation of the cooling fan; S12 performs a fast Fourier transform on the drive bus current signal to obtain the fundamental amplitude and the amplitudes of the 3rd, 5th, and 7th harmonics. S13. Take the square root of the sum of the squares of the amplitudes of the 3rd, 5th, and 7th harmonics and divide it by the fundamental amplitude to obtain the first harmonic distortion rate.

[0022] Specifically, the drive controller establishes a drive bus current acquisition link during the period when the cooling fan is running normally and before the forward / reverse switching occurs. The analog voltage output from the drive bus current sensor is connected to the operational amplifier and low-pass conditioning circuit, and then sent to the controller's ADC channel, for example, at a sampling period... Continuous current data is acquired with an ADC resolution of at least 12 bits. The sampling results are written into a 256-point circular buffer in chronological order. Since this sampling period corresponds to a sampling rate of 20kHz, it can cover the frequency range required for the analysis of the 7th harmonic, and the 256 data points form an analysis window for harmonic calculation. To avoid contaminating the first harmonic distortion rate due to non-steady-state conditions such as startup, rapid acceleration, and stall protection, the controller can update the buffer only when the temperature-speed outer loop output duty cycle remains stable, the FG speed fluctuation is less than a preset range, and no forward / reverse switching command edge is detected. Abnormal spike sampling values ​​are limited or discarded to ensure that the acquired drive bus current signal can represent the reference current state during normal operation.

[0023] The controller performs a Fast Fourier Transform (FFT) on the 256-point drive bus current time-domain data in the circular buffer, converting the time-domain current sequence into a frequency-domain amplitude spectrum. Then, based on the current fan electrical commutation frequency, it determines the fundamental frequency and reads the fundamental amplitude and the harmonic amplitudes corresponding to the 3rd, 5th, and 7th harmonic frequencies from the spectrum. For example, under rated operating conditions, if the current electrical fundamental frequency is 1.4kHz, the 3rd, 5th, and 7th harmonic frequencies are approximately 4.2kHz, 7.0kHz, and 9.8kHz, respectively, all falling within the 10kHz Nyquist frequency corresponding to a 20kHz sampling rate. The spectral resolution is calculated using a 256-point window and... The sampling period is calculated to be 78.125Hz, therefore the controller can search for local peaks within the adjacent frequency range to obtain the normalized peak value. , , , ,in The fundamental amplitude, , , These are the amplitudes of the 3rd, 5th, and 7th harmonics, respectively.

[0024] The controller calculates the first harmonic distortion rate by comparing the combined amplitude of the 3rd, 5th, and 7th harmonics with the fundamental amplitude. All amplitude values ​​in this formula adopt the same FFT amplitude normalization rule, so the calculation result is a dimensionless ratio, which can be directly used as a reference quantity for harmonic prediction before subsequent forward and reverse switching; for example, the normalized amplitude is preset to be within a certain normal operation window. , , , The first harmonic distortion rate is... This indicates that the combined amplitude of the 3rd, 5th, and 7th harmonics within the normal operating window is approximately 5.39% of the fundamental amplitude. The controller writes this calculation result into the harmonic reference register, along with status information such as the current speed, duty cycle, and sampling timestamp.

[0025] In one example, S12 includes: The drive bus current signal is sampled by an ADC to obtain the first current time-domain data. The first current time-domain data is multiplied point by point by the Hanning window coefficient to obtain the second current time-domain data; Perform a fast Fourier transform on the second current time-domain data to calculate the spectral resolution at each frequency point; The fundamental frequency and its corresponding fundamental amplitudes and 3rd, 5th, and 7th harmonic amplitudes are located sequentially according to integer multiples of the spectral resolution.

[0026] Specifically, the drive controller inputs the analog signal output from the drive bus current detection circuit into the ADC channel, and starts timing sampling under the conditions that the cooling fan is running normally, the PWM duty cycle does not change abruptly, and no forward / reverse switching command edge is detected. For example, the timer follows the... Generate a sampling trigger signal to enable the ADC to... The sampling rate continuously acquires the instantaneous value of the drive bus current. The sampling results are written into a 256-point circular buffer in chronological order. When the buffer is full, a set of first current time-domain data is obtained. In order to ensure that the data can reflect the current waveform characteristics during normal operation, the controller marks abnormal points that significantly exceed the current sensor range or ADC full range before writing, and resamples in the next window to avoid switching spikes, sampling glitches or power supply disturbances directly participating in spectrum calculation.

[0027] The controller reads 256 current sampling points from the circular buffer in a fixed order and multiplies each sampling point with the Hanning window coefficient of the same sequence number to obtain the second current time domain data. Since directly truncating the current waveform of a finite length will cause spectral leakage, and the Hanning window can reduce the impact of abrupt changes at both ends of the window on the frequency domain amplitude, the data after point-by-point windowing is more suitable for extracting the fundamental and harmonic amplitudes.

[0028] The controller performs a Fast Fourier Transform on the second current time-domain data, converting the time-domain current sequence into a discrete frequency-domain amplitude spectrum, and then applies it according to a 256-point window. The sampling period is used to calculate the spectral resolution, i.e. This indicates the phase difference between two adjacent frequency points. .

[0029] After calculating the spectral resolution, the controller determines the frequency index of the fundamental frequency based on the current fan electrical commutation frequency. It then continues to locate the positions of the 3rd, 5th, and 7th harmonic frequencies in integer multiples of this frequency. For example, when the fundamental frequency is approximately 1.4kHz, the 3rd, 5th, and 7th harmonic frequencies are approximately 4.2kHz, 7.0kHz, and 9.8kHz, respectively, all of which do not exceed the 10kHz Nyquist frequency corresponding to a 20kHz sampling rate. Therefore, they can be effectively resolved by the current sampling and FFT configuration. In actual positioning, if the target frequency cannot fall exactly on a discrete frequency point, the controller can select the spectral line with the largest amplitude near the target frequency point as the corresponding amplitude to reduce the amplitude error caused by frequency offset and obtain the fundamental amplitude. And the amplitudes of the 3rd, 5th, and 7th harmonics , , .

[0030] In one example, such as Figure 3S20 includes: S21, after detecting the rising edge of the forward / reverse switching command and before the phase sequence switching is executed, recalculate the second harmonic distortion rate of the drive bus current signal; S22, subtract the first harmonic distortion rate from the second harmonic distortion rate to obtain the first harmonic increment.

[0031] Specifically, the controller continuously monitors the forward / reverse switching command line, direction control command word, or the direction flag bit written by the upper-level control task. When a valid transition edge is detected, switching from forward to reverse or vice versa, this transition edge is used as a preprocessing trigger point, and the actual reverse flag bit is temporarily suspended from being written to the three-phase bridge direction control register. This ensures that the "recalculation of the second harmonic distortion rate of the drive bus current signal" occurs before the phase sequence switching is executed. At this time, the controller can first latch the current PWM duty cycle, the current FG speed, the current temperature-speed outer loop output state, and the first harmonic distortion rate. Then, it re-acquires a frame of drive bus current signal using the same ADC sampling, Hanning window, 256-point FFT, and frequency point positioning method as during normal operation. For example, the sampling period uses... This involves forming a 256-point time-domain window with a 20kHz sampling rate, and obtaining the instantaneous spectral state after the switching command is triggered within a data window of approximately 12.8ms. Since this calculation occurs before the phase sequence has actually changed, the second harmonic distortion rate reflects the harmonic level of the drive bus under the influence of pre-disturbance, control command update, bus current fluctuation, or motor back EMF change in the "about to switch" state, rather than the steady-state harmonic level after the switch. To avoid misjudgment caused by occasional sampling glitches, the controller can require that the current in the ADC sampling window does not saturate, the fundamental amplitude is not lower than the effective amplitude lower limit, and the 3rd, 5th, and 7th harmonic frequencies obtained by FFT calculation all fall within the effective frequency range. Only after these conditions are met will the result of this recalculation be recorded as the second harmonic distortion rate.

[0032] The controller calculates the difference between the second harmonic distortion rate and the stored first harmonic distortion rate to obtain the first harmonic increment, which can be written as: ,in This represents the baseline value of harmonic distortion rate formed during normal operation. This indicates the harmonic distortion rate recalculated after detecting the rising edge of the forward / reverse switching command and before executing the phase sequence switching. This represents the increment of the harmonic relative to the reference before the switching. If calculated during the preset normal operation phase... The result is recalculated after the switching command is triggered. ,but If the increment is higher than the preset harmonic warning threshold, for example, 0.05, it indicates that the drive bus has experienced significant pre-switching harmonic disturbance. The controller should then enter the compensation process of freezing the first PWM duty cycle, collecting the airflow velocity deviation value, and calculating the second harmonic increment. If the recalculation result is only... ,but If the value is below 0.05, it indicates that the current harmonic variation may still be within the normal operating fluctuation range, and the controller can execute the conventional phase sequence switching procedure without initiating adaptive compensation.

[0033] In one example, such as Figure 4 S30 includes: S31, when the first harmonic increment is not lower than the preset harmonic warning threshold, freeze the first PWM duty cycle and record the first airflow velocity, and collect the second airflow velocity after performing phase sequence switching; S32, Calculate the airflow velocity deviation between the first airflow velocity and the second airflow velocity; S33: Acquire the drive bus current signal after phase sequence switching and calculate the second harmonic increment.

[0034] Specifically, the first harmonic increment is compared with a preset harmonic warning threshold. For example, if the preset harmonic warning threshold is 0.05, when the first harmonic increment is not lower than the preset harmonic warning threshold, it indicates that the harmonic level of the drive bus after the forward / reverse switching command is triggered and before the actual phase sequence switching is significantly higher than the normal operating reference. If the phase sequence is switched directly according to the conventional process, it is easy to cause winding current fluctuations, actual torque deviations, and sudden drops in airflow speed at the outlet. Therefore, the controller enters the compensation preparation state. The controller first freezes the first PWM duty cycle of the current temperature-speed outer loop output so that it no longer changes temporarily with the temperature closed loop or speed closed loop, and synchronously reads the output value of the airflow speed sensor installed at the center of the fan outlet section. This value is recorded as the first airflow speed as a reference for the steady-state airflow speed before switching. Then, the controller writes the forward / reverse switching flag to the direction control register, so that the three-phase bridge drive circuit performs phase sequence switching according to the target direction, and continues to collect airflow speed according to the airflow speed sampling period of 1ms after switching to obtain the second airflow speed sequence.

[0035] The controller compares the first airflow velocity with the second airflow velocity to obtain the airflow velocity deviation value, which is expressed in a normalized form as follows: ,in This indicates the first airflow velocity recorded before the switch. Indicates the first The second airflow velocity collected at each sampling time. This indicates the deviation ratio relative to the steady-state airflow before the switch; for example, a preset value. At a certain sampling time after phase sequence switching ,but This indicates that the airflow speed has decreased by 10% compared to before the switch. Based on this, the controller can determine that positive compensation for the PWM duty cycle is needed in subsequent steps. Higher than If the deviation value is negative, it indicates that there is airflow overshoot, which needs to be suppressed.

[0036] During the transient process following phase sequence switching, the controller continues to acquire the drive bus current signal and calculates the current instantaneous harmonic distortion rate using ADC sampling, Hanning windowing, 256-point FFT, and frequency point positioning. The instantaneous harmonic distortion rate is then differentiated from the first harmonic distortion rate benchmark formed during normal operation to obtain the second harmonic increment, which can be written as: ,in The first harmonic distortion rate, The first one after phase sequence switching The instantaneous harmonic distortion rate corresponding to each calculation window. (If preset...) After switching, a certain window is calculated to obtain ,but This indicates that the harmonic disturbance after the switch is still relatively strong and needs to be included in the subsequent compensation calculation along with the airflow velocity deviation value.

[0037] In one example, S31 includes: When the first harmonic increment is not lower than the preset harmonic warning threshold, the first PWM duty cycle is frozen, and the first airflow velocity is read from the airflow velocity sensor; Write the inverted flag bit to the drive controller direction control register to perform phase sequence switching, and collect the second airflow velocity after phase sequence switching through the airflow velocity sensor.

[0038] Specifically, the drive controller compares the first harmonic increment with a preset harmonic warning threshold in real time. For example, if the threshold is set to 0.05, when the result indicates that the first harmonic increment is not lower than the preset harmonic warning threshold, the controller immediately enters the switching protection and compensation preparation state. It prioritizes freezing the first PWM duty cycle of the current temperature-speed outer loop output, keeping the duty cycle value in the timer capture comparison register unchanged. Simultaneously, it suspends the outer loop control task's update permission to the duty cycle register, preventing the duty cycle before and after the forward / reverse switching from being rewritten by the temperature closed loop, speed closed loop, or task scheduling process, thereby ensuring the stability of the control reference during the switching transient. At the same time, the controller reads the current airflow state through a bidirectional airflow velocity sensor or a differential pressure airflow detection unit. The sensor is installed on the effective measurement section of the fan duct and outputs directional airflow velocity with the target airflow direction as the positive direction. When using a unidirectional wind speed sensor, the controller uses the average wind speed at multiple points or the airflow converted from the differential pressure as the airflow feedback quantity to avoid misjudgment of speed deviation caused by the original air outlet becoming the air inlet after the forward / reverse switching. Its analog output is converted into a digital quantity after arithmetic amplification, filtering and ADC sampling. The controller latches this digital quantity as the first airflow speed in the same control cycle when the first PWM duty cycle is frozen, and writes the current duty cycle, speed and direction status into the temporary register area to ensure that the airflow speed corresponds to the steady-state airflow state before the phase sequence switching.

[0039] The controller writes the inversion flag to the direction control register. This write operation is performed atomically and cannot be interrupted. Before writing, low-priority tasks are briefly blocked from accessing the direction control register and PWM configuration register. Immediately after writing, the three-phase bridge drive logic is triggered to output U, V, and W three-phase PWM signals in reverse phase sequence, causing the cooling fan to switch from the current direction to reverse drive. After the phase sequence switch is executed, the controller reopens the airflow velocity acquisition task and continuously reads the airflow velocity sensor output at a fixed sampling period to obtain the second airflow velocity after the phase sequence switch. To avoid the influence of sensor noise or switching transient spikes on single-point sampling, the ADC results are simply limited and averaged within a short window in each cycle, without altering its millisecond-level response characteristics.

[0040] In one example, such as Figure 5 S40 includes: S41, calculate the first compensation amount of the airflow velocity deviation value and the second compensation amount of the second harmonic increment, and calculate the target compensation amount based on the first compensation amount and the second compensation amount; S42, calculate the second PWM duty cycle based on the target compensation amount and the first PWM duty cycle, and load the second PWM duty cycle to the drive controller to drive the three-phase winding of the cooling fan for chopping speed regulation.

[0041] Specifically, the controller uses the airflow velocity deviation value as a direct feedback quantity reflecting insufficient or overshooting airflow at the vent, and the second harmonic increment as an electrical feedback quantity reflecting the strength of the disturbance to the drive bus after phase sequence switching. Within the same control cycle, the controller calculates the corresponding first compensation quantity and second compensation quantity for both. The first compensation quantity is mainly used to correct the insufficient heat dissipation capacity caused by the decrease in airflow velocity, and the second compensation quantity is mainly used to suppress the influence of harmonic disturbance on the effective PWM duty cycle and output torque. The two are not mutually exclusive, but rather jointly describe the mechanical airflow side deviation and electrical drive side deviation under the transient state of forward and reverse switching. When calculating the first compensation amount, the controller can determine the compensation direction based on the positive or negative direction of the airflow velocity deviation value. If the airflow velocity after switching is lower than the reference airflow velocity before switching, a positive duty cycle compensation is generated. If the airflow velocity after switching is higher than the reference airflow velocity, a negative suppression compensation is generated. When calculating the second compensation amount, the controller can judge the harmonic disturbance intensity based on the amplitude of the second harmonic increment. If the second harmonic increment is large, it indicates that the bus current distortion is still affecting the drive stability, and the harmonic compensation weight needs to be increased. If the second harmonic increment gradually decreases, it indicates that the electrical disturbance caused by the phase sequence switching is attenuating, and the harmonic compensation amount should also be reduced accordingly. The controller combines the first compensation amount and the second compensation amount into a comprehensive compensation amount, and uses this as a candidate value for the target compensation amount. When the comprehensive compensation amount exceeds the preset compensation limit, it is truncated to the limit boundary before outputting the target compensation amount. For example, the compensation limit can be set to 0.20 to prevent excessive compensation during forward / reverse switching from causing PWM duty cycle jumps, winding current surges, or controller integral saturation. For example, if the preset first compensation amount is 0.08 and the second compensation amount is 0.05, the comprehensive compensation amount is 0.13. If it does not exceed 0.20, it can be directly used as the target compensation amount. If the first compensation amount is 0.16 and the second compensation amount is 0.09, the comprehensive compensation amount reaches 0.25. The controller should limit the target compensation amount to 0.20 to maintain the compensation capability while preserving the drive safety margin.

[0042] The controller adds the target compensation amount to the previously frozen first PWM duty cycle to obtain the second PWM duty cycle, and constrains the result within an allowable range using a duty cycle limiting function, for example, by using... ,in This is the duty cycle of the first PWM. For the target compensation amount, For the second PWM duty cycle, the limiting range For example, preset , ,but ,like , The values ​​are directly added together to get 1.08, but after limiting, the output is 0.95 to avoid PWM saturation causing the drive circuit to fail. After the second PWM duty cycle is determined, the controller writes the value into the timer capture comparison register and updates the three-phase PWM signal according to the 25kHz PWM carrier frequency. After dead time insertion, the PWM signal is sent to the three-phase full-bridge power switching circuit to perform chopping power supply to the three-phase windings of the cooling fan. During the transition transient, the controller collects the airflow speed at a 1ms period and updates the airflow speed deviation value. At the same time, it updates the harmonic distortion rate with a 256-point overlapping sliding window, recursive discrete Fourier algorithm, or fixed frequency Goertzel algorithm. When a 20kHz sampling rate and a 256-point FFT window are used, the complete window duration of the harmonic distortion rate is 12.8ms. The controller refreshes the second harmonic increment according to the window update result and keeps the previous effective harmonic increment participating in the compensation between two harmonic updates.

[0043] In one example, S41 includes: Calculate the first compensation amount for the airflow velocity deviation value, and calculate the second compensation amount for the second harmonic increment; The sum of the first compensation amount and the second compensation amount is used to obtain the comprehensive compensation amount; When the total compensation amount exceeds the preset compensation limit, the total compensation amount is truncated to the boundary of the preset compensation limit, and the target compensation amount is output.

[0044] Specifically, the drive controller sends the airflow velocity deviation value and the second harmonic increment to the corresponding compensation channels. The airflow velocity deviation channel reflects the decrease or overshoot of the actual airflow velocity at the outlet after phase sequence switching relative to the reference airflow velocity before switching. The harmonic increment channel reflects the enhancement of the drive bus current distortion relative to the normal reference. Since both are normalized dimensionless quantities, they can be combined and calculated within the same duty cycle compensation framework. The controller can calculate the first compensation amount according to the airflow velocity compensation channel, that is, convert the airflow velocity deviation into a duty cycle correction amount through proportional, integral, and derivative elements, which can be written as... And calculate the second compensation amount according to the harmonic compensation channel, which can be written as ,in This is the airflow velocity deviation value. For the second harmonic increment, both compensation quantities are expressed as PWM duty cycle increments; for example, within a preset control cycle... , And after compensation calculation following bench calibration, , The controller will then add the two together to obtain the comprehensive compensation amount. At this point, the preset compensation limit of 0.20 has not been exceeded, so 0.13 can be directly output as the target compensation value. If the first compensation value is 0.16 and the second compensation value is 0.09 in another control cycle, the combined compensation value is 0.25, which exceeds the preset compensation limit. The controller cannot directly output this value, otherwise it will cause a sudden increase in the PWM duty cycle, a surge in three-phase winding current, and excessive subsequent integral accumulation. Therefore, the combined compensation value is truncated to the limit boundary, i.e., the output is... If the overall compensation is negative and the amplitude exceeds the limit, for example... Then cut it into This is to achieve negative suppression of airflow overshoot or harmonic fallback. The first compensation amount quickly corrects the airflow-side deviation, the second compensation amount compensates for electrical-side harmonic disturbances, and the comprehensive compensation amount is output as the target compensation amount after being limited.

[0045] In one example, such as Figure 6 After the three-phase winding speed control of the cooling fan is achieved by chopping, it also includes: The S50 uses a Hall sensor on the cooling fan to collect FG pulse signals and calculates the real-time rotation speed based on the FG pulse signals. S60 calculates the difference between the real-time speed and the target speed to obtain the speed tracking error; S70, when the absolute value of the speed tracking error does not exceed the preset speed convergence threshold within the preset number of consecutive judgments, determine the compensation convergence and clear the integral accumulation term of the first compensation amount and the second compensation amount, and determine the third PWM duty cycle; S80, based on the third PWM duty cycle, updates the first harmonic distortion rate to the instantaneous harmonic distortion rate at the end of the switching transient, and reactivates the temperature and speed outer loop speed control.

[0046] Specifically, after the second PWM duty cycle has been applied and the three-phase winding chopper speed regulation has been driven, the drive controller enters the convergence confirmation process after switching. The FG pulse signal is collected by the Hall sensor built into the cooling fan. The arrival time of adjacent FG pulses is recorded by the input capture unit or the number of FG pulses is counted within a fixed counting window. The real-time speed is calculated by combining the number of FG pulses corresponding to each fan revolution. In order to avoid the impact of jitter on the single pulse interval after the forward and reverse switching, the controller can perform a sliding average on several consecutive FG cycles and remove abnormal capture values ​​that do not conform to the current speed change trend, so that the obtained real-time speed can reflect the true recovery state of the fan under the action of the compensation duty cycle.

[0047] The controller compares the real-time speed with the target speed, which is determined by the heat dissipation requirements maintained by the temperature-speed mapping curve before and after the switch. The speed tracking error can be expressed as a difference relationship. ,in For the target speed, For the first Real-time rotational speed at each sampling moment This is for the speed tracking error; for example, if the preset target speed is 3000 RPM, and the real-time speed at a certain sampling moment is 2940 RPM, then the speed tracking error is 60 RPM, which has not yet met the convergence threshold of 50 RPM. The controller continues to maintain the compensation closed-loop operation and continuously collects airflow speed, harmonic increment and FG pulse signal. If the real-time speed subsequently recovers to 2960 RPM, 2975 RPM, and 2988 RPM, the corresponding error gradually decreases to 40 RPM, 25 RPM, and 12 RPM, indicating that the compensation is converging.

[0048] The controller uses the criterion that "the absolute value of the error does not exceed 50 RPM within three consecutive FG sampling periods" for confirmation; that is, it only confirms if the absolute value of the error does not exceed 50 RPM. Only when the condition is met continuously within the preset number of consecutive judgments is the compensation action corresponding to the second PWM duty cycle considered to have brought the fan speed back to the vicinity of the target. After the compensation is determined to be converged, the controller clears the integral accumulation term in the first and second compensation amounts to prevent the residual integrals accumulated in the airflow speed channel and harmonic channel during the switching transient from continuing to affect normal speed regulation. The PWM duty cycle that has been converged at this time is determined as the third PWM duty cycle. The third PWM duty cycle is the stable benchmark that can maintain the current speed and airflow state when the switching compensation ends.

[0049] The controller uses the third PWM duty cycle as the new steady-state control reference, replacing the previously frozen first PWM duty cycle. This prevents secondary speed fluctuations caused by the duty cycle suddenly dropping back to the old reference after compensation exits. Simultaneously, at the end of the switching transient, the controller rereads or latches the current instantaneous harmonic distortion rate and updates the first harmonic distortion rate with this value, ensuring the new harmonic reference matches the motor's operating state after the forward / reverse switching. For example, if the first harmonic distortion rate is 0.054 before the switch, and the instantaneous harmonic distortion rate stabilizes at 0.061 at the end of the compensation switch, the controller writes 0.061 into the harmonic reference register for prediction during the next forward / reverse switching. After completing the above updates, the controller reopens the temperature-speed outer loop's access to update the duty cycle, allowing the system to smoothly return from the switching compensation closed loop to conventional speed control, continuing to determine the target speed based on temperature requirements and drive the three-phase winding chopper speed regulation using the PWM duty cycle.

[0050] Reference Figure 7 This embodiment provides a drive controller, including: The acquisition unit 701 is used to acquire the drive bus current signal during the normal operation of the cooling fan and calculate the first harmonic distortion rate. The first calculation unit 702 is used to calculate the first harmonic increment based on the first harmonic distortion rate after detecting the rising edge of the forward / reverse switching command and before the phase sequence switching is executed. The second calculation unit 703 is used to freeze the first PWM duty cycle and calculate the airflow speed deviation value and the second harmonic increment when the first harmonic increment is not lower than the preset harmonic warning threshold. The compensation unit 704 is used to compensate the first PWM duty cycle based on the airflow speed deviation value and the second harmonic increment to obtain the second PWM duty cycle, and output the second PWM duty cycle to the drive controller to drive the three-phase winding of the cooling fan for chopping speed regulation.

[0051] In this embodiment, the specific implementation of each unit in the above device embodiment is described in the above method embodiment, and will not be repeated here.

[0052] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, apparatus, article, or method that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, apparatus, article, or method. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, apparatus, article, or method that includes that element.

[0053] The above description is only a preferred embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A method of speed control of a heat dissipating fan, characterized by, include: Collect the drive bus current signal during the normal operation of the cooling fan and calculate the first harmonic distortion rate; After detecting the rising edge of the forward / reverse switching command and before the phase sequence switching is executed, the first harmonic increment is calculated based on the first harmonic distortion rate; When the first harmonic increment is not lower than the preset harmonic warning threshold, freeze the first PWM duty cycle and calculate the airflow velocity deviation value and the second harmonic increment; Based on the airflow velocity deviation value and the second harmonic increment, the first PWM duty cycle is compensated to obtain the second PWM duty cycle, and the second PWM duty cycle is output to the drive controller to drive the three-phase winding of the cooling fan for chopping speed regulation.

2. The heat dissipating fan speed regulation method according to claim 1, wherein The process of acquiring the drive bus current signal during the normal operation of the cooling fan and calculating the first harmonic distortion rate includes: Collect the drive bus current signal during the normal operation of the cooling fan; The driving bus current signal is subjected to a fast Fourier transform to obtain the fundamental amplitude and the amplitudes of the 3rd, 5th and 7th harmonics; The first harmonic distortion rate is obtained by taking the square root of the sum of the squares of the amplitudes of the 3rd, 5th, and 7th harmonics and then dividing it by the fundamental amplitude.

3. The cooling fan speed control method according to claim 2, characterized in that, The step of performing a Fast Fourier Transform on the drive bus current signal to obtain the fundamental amplitude and the amplitudes of the 3rd, 5th, and 7th harmonics includes: The drive bus current signal is sampled by an ADC to obtain the first current time-domain data; The first current time-domain data is multiplied point by point by the Hanning window coefficient to obtain the second current time-domain data; Perform a fast Fourier transform on the second current time-domain data to calculate the spectral resolution at each frequency point; The fundamental frequency and its corresponding fundamental amplitude and 3rd, 5th and 7th harmonic amplitudes are located sequentially according to integer multiples of the spectral resolution.

4. The cooling fan speed control method according to claim 1, characterized in that, The step of calculating the first harmonic increment based on the first harmonic distortion rate after detecting the rising edge of the forward / reverse switching command and before the phase sequence switching is executed includes: After detecting the rising edge of the forward / reverse switching command and before the phase sequence switching is executed, the second harmonic distortion rate of the drive bus current signal is recalculated; Subtracting the first harmonic distortion rate from the second harmonic distortion rate yields the first harmonic increment.

5. The cooling fan speed control method according to claim 1, characterized in that, When the first harmonic increment is not lower than the preset harmonic warning threshold, freezing the first PWM duty cycle and calculating the airflow velocity deviation value and the second harmonic increment includes: When the first harmonic increment is not lower than the preset harmonic warning threshold, the first PWM duty cycle is frozen and the first airflow velocity is recorded. After the phase sequence switching is performed, the second airflow velocity is collected. Calculate the airflow velocity deviation between the first airflow velocity and the second airflow velocity; The current signal of the drive bus after phase sequence switching is acquired and the second harmonic increment is calculated.

6. The cooling fan speed control method according to claim 5, characterized in that, When the first harmonic increment is not lower than the preset harmonic warning threshold, the first PWM duty cycle is frozen and the first airflow velocity is recorded. After the phase sequence switching is performed, the second airflow velocity is collected, including: When the first harmonic increment is not lower than the preset harmonic warning threshold, the first PWM duty cycle is frozen, and the first airflow velocity is read from the airflow velocity sensor. Write the inverted flag bit to the drive controller direction control register to perform phase sequence switching, and collect the second airflow velocity after phase sequence switching through the airflow velocity sensor.

7. The cooling fan speed control method according to claim 1, characterized in that, The step of compensating the first PWM duty cycle based on the airflow velocity deviation value and the second harmonic increment to obtain a second PWM duty cycle, and outputting the second PWM duty cycle to the drive controller to drive the three-phase winding speed regulation of the cooling fan by chopping, includes: Calculate the first compensation amount of the airflow velocity deviation value and the second compensation amount of the second harmonic increment, and calculate the target compensation amount based on the first compensation amount and the second compensation amount; The second PWM duty cycle is calculated based on the target compensation amount and the first PWM duty cycle, and the second PWM duty cycle is loaded into the drive controller to drive the three-phase winding speed regulation of the cooling fan by chopping.

8. The cooling fan speed control method according to claim 7, characterized in that, The calculation of the first compensation amount for the airflow velocity deviation value and the second compensation amount for the second harmonic increment, and the calculation of the target compensation amount based on the first compensation amount and the second compensation amount, includes: Calculate the first compensation amount for the airflow velocity deviation value, and calculate the second compensation amount for the second harmonic increment; The first compensation amount and the second compensation amount are summed to obtain the comprehensive compensation amount; When the comprehensive compensation amount exceeds the preset compensation limit, the comprehensive compensation amount is truncated to the boundary of the preset compensation limit, and the target compensation amount is output.

9. The cooling fan speed control method according to claim 7, characterized in that, After the three-phase winding speed control of the cooling fan is implemented using chopper, the following is also included: The FG pulse signal is acquired by the Hall sensor of the cooling fan, and the real-time speed is calculated based on the FG pulse signal; The difference between the real-time rotational speed and the target rotational speed is used to obtain the rotational speed tracking error; When the absolute value of the speed tracking error does not exceed the preset speed convergence threshold within a preset number of consecutive determinations, compensation convergence is determined and the integral accumulation term of the first compensation amount and the second compensation amount is cleared, and the third PWM duty cycle is determined. Based on the third PWM duty cycle, the first harmonic distortion rate is updated to the instantaneous harmonic distortion rate at the end of the switching transient, and the temperature and speed outer loop speed control is reactivated.

10. A drive controller, characterized in that, The steps for implementing the cooling fan speed control method according to any one of claims 1 to 9 include: The acquisition unit is used to acquire the drive bus current signal during the normal operation of the cooling fan and calculate the first harmonic distortion rate. The first calculation unit is used to calculate the first harmonic increment based on the first harmonic distortion rate after detecting the rising edge of the forward / reverse switching command and before the phase sequence switching is executed. The second calculation unit is used to freeze the first PWM duty cycle and calculate the airflow speed deviation value and the second harmonic increment when the first harmonic increment is not lower than the preset harmonic warning threshold. The compensation unit is used to compensate the first PWM duty cycle based on the airflow speed deviation value and the second harmonic increment to obtain the second PWM duty cycle, and output the second PWM duty cycle to the drive controller to drive the three-phase winding of the cooling fan to chop and regulate the speed.

Images