A method for preparing a semiconductor sample and use thereof

Abstract

The application relates to the technical field of semiconductor device testing and analysis, and discloses a preparation method of a semiconductor sample and application thereof. The method comprises the following steps: providing a semiconductor structure comprising a target layer and a surface layer, the target layer having a target structure; determining a predetermined positioning area of the target structure on the surface of the semiconductor structure; etching the semiconductor structure to form a positioning window exposing the target structure in the surface layer; determining the position of the target structure through the positioning window, and forming a positioning mark of the target structure in the semiconductor structure; and grinding the semiconductor structure to obtain a semiconductor sample. The application provides a position judgment basis for cross-section grinding of the inner-layer target structure through pre-positioning, forming of the positioning window and setting of the positioning mark, which is beneficial to improving the positioning accuracy of the target structure, improving the sample preparation efficiency and reducing the risk of damage to the target area.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device testing and analysis technology, specifically to a method for preparing semiconductor samples and its application. Background Technology

[0002] In the testing and analysis of semiconductor devices, it is often necessary to prepare cross-sections of the semiconductor device to observe or inspect specific internal structures. Semiconductor devices can be doped to create regions with different electrical properties. Scanning Capacitance Microscopy (SCM) can characterize the carrier types and doping distribution in semiconductor materials and can be used to observe doped regions and PN junctions in the cross-section of semiconductor devices. Therefore, before performing SCM testing, it is necessary to prepare a semiconductor sample cross-section that can reach the location to be inspected.

[0003] Cross-sectional preparation of SCM samples typically involves mechanical polishing. For semiconductor devices with multilayer structures, the target structure to be inspected may be located within an inner layer of the device and obscured by other structures above it, making it difficult to directly observe the specific location of the target structure from the semiconductor device surface. Especially when the target structure is small, relying solely on optical microscopy to observe the semiconductor device surface or the polished area is insufficient to obtain information that can accurately determine the location of the target structure. Current sample preparation processes do not allow the inner layer structure to be visible, and the resolution of optical microscopes is insufficient for the precise localization of tiny target structures.

[0004] During cross-sectional grinding, operators typically rely solely on observable features on the semiconductor device surface and prior experience to determine the current grinding position. When the target structure is located in an invisible inner layer, this method lacks a precise basis for determining the position, easily leading to inaccurate grinding position assessments. To gradually approach the target position, repeated grinding and observation are necessary, increasing sample preparation time and posing a risk of damaging the target area or even rendering the sample unusable due to grinding beyond the target position or deviations in the grinding position.

[0005] In existing SCM sample preparation methods, glass slides can be attached to the sample surface to improve the stress state of the sample during cross-section preparation and reduce the possibility of forming curved cross-sections. For example, the sample preparation method disclosed in patent CN107702962B uses a glass slide attached to the sample surface for protection. However, this type of method mainly addresses cross-sectional morphology and sample protection issues. For target structures located in the inner layers of semiconductor devices and difficult to observe directly from the surface, there is still a lack of positioning criteria to determine the accurate location of the target structure during cross-section grinding. Summary of the Invention

[0006] The present invention aims to provide a method for preparing semiconductor samples and its application, in order to solve the problem that when the target structure in a semiconductor device is located in the inner layer, it is difficult to directly determine the position of the target structure from the surface of the semiconductor structure, resulting in a lack of clear position judgment basis and difficulty in accurately locating the target position during the cross-sectional grinding process.

[0007] To address the aforementioned technical problems, this invention provides a method for preparing a semiconductor sample, comprising the following steps:

[0008] S1: A semiconductor structure is provided, the semiconductor structure including a target layer and a surface layer formed on the target layer, the target layer having a target structure;

[0009] S2: Determine a pre-positioning region of the target structure on the surface of the semiconductor structure;

[0010] S3: Etch the semiconductor structure to form a positioning window in the surface layer that exposes the target structure;

[0011] S4: Determine the position of the target structure through the positioning window, and form a positioning mark of the target structure in the semiconductor structure;

[0012] S5: Grind the semiconductor structure to obtain a semiconductor sample.

[0013] In some embodiments, in step S2, the surface of the semiconductor structure is provided with a feature pattern, and the pre-positioning region is determined according to a preset relative distance or relative position between the feature pattern and the target structure.

[0014] In some embodiments, in step S3, the semiconductor structure is placed in a plasma etching apparatus and an auxiliary etching gas is introduced to form a patterned positioning window.

[0015] In some embodiments, in the projection plane of the semiconductor structure along its thickness direction, the projection area of ​​the positioning window at least covers the projection area of ​​the target structure and extends beyond the projection area of ​​the target structure.

[0016] In some implementations, in step S4, a positioning mark is formed on one side of the target structure, penetrating the surface layer and extending to the target layer.

[0017] In some embodiments, the positioning mark is any one of a through hole, a groove, or a recess.

[0018] In some embodiments, before performing step S5, the method further includes: forming an adhesive layer on the semiconductor structure; and attaching a glass slide onto the adhesive layer.

[0019] In some embodiments, in step S4, the positioning mark includes a first positioning mark and a second positioning mark, the first positioning mark and the second positioning mark are located on opposite sides of the target structure and are in the same plane.

[0020] In some embodiments, in step S5, the semiconductor structure is ground to expose the positioning mark to obtain the semiconductor sample, wherein the ground surface of the semiconductor structure is parallel to the plane containing the positioning mark and the target structure.

[0021] The present invention also provides the application of the method described in any of the above embodiments in semiconductor device failure analysis.

[0022] Compared with the prior art, the technical solution provided by the present invention has the following beneficial effects:

[0023] This invention predetermines a pre-positioning region corresponding to a target structure on the surface of a semiconductor structure. By etching the semiconductor structure, a positioning window is formed in the surface layer, allowing for further determination of the target structure's position. After determining the target structure's position, a positioning mark is formed within the semiconductor structure. This transforms the inner-layer target structure, which was previously difficult to determine directly from the semiconductor surface, into a state with a clear basis for positional judgment, providing a positioning foundation for subsequent semiconductor structure polishing. Therefore, it reduces the need to repeatedly determine the polishing position based solely on surface observation and operational experience, improves the accuracy of inner-layer target structure positioning and semiconductor sample preparation efficiency, and reduces the risk of damage to the target area or sample rejection due to polishing position deviations. Attached Figure Description

[0024] Figure 1 The diagram shown is a flowchart illustrating a method for preparing a semiconductor sample provided by the present invention.

[0025] Figure 2 This is a schematic diagram of the semiconductor structure in an embodiment of the present invention;

[0026] Figure 3 This is a schematic diagram illustrating the determination of the pre-positioning region based on the relative distance between the feature pattern and the target structure according to the present invention;

[0027] Figure 4 This is a schematic diagram illustrating the determination of the prepositioning region based on the relative position between the feature graphic and the target structure according to the present invention;

[0028] Figure 5 This is a schematic diagram of the positioning window formed in the surface layer according to the present invention;

[0029] Figure 6This is a schematic diagram showing the positional relationship between the single-sided positioning mark and the target structure of the present invention;

[0030] Figure 7 This is a schematic diagram showing the positional relationship between the double-sided positioning marks and the target structure of the present invention;

[0031] Figure 8 This is a schematic diagram of the cross-sectional grinding process along the AA direction according to the present invention;

[0032] Figure 9 This is a diagram showing the correspondence between the positioning marks and the target structure in this invention;

[0033] Explanation of reference numerals in the attached figures:

[0034] 110. Surface layer; 120. Target layer; 130. Target structure; 140. Feature pattern; 150. Pre-positioning area; 160. Positioning window; 170. Adjacent structure; 180. Positioning mark; 181. First positioning mark; 182. Second positioning mark; 190. Grinding surface. Detailed Implementation

[0035] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0036] It should be understood that the illustrations provided in the embodiments of this invention are merely schematic representations of the basic concept of the invention. Although the illustrations only show components relevant to the invention and are not drawn according to the actual number, shape, and size of components in implementation, the shape, quantity, and proportion of each component can be arbitrarily changed in actual implementation, and the component layout may also be more complex. The structures, proportions, sizes, etc., shown in the accompanying drawings are only used to complement the content disclosed in the specification for those skilled in the art to understand and read, and are not intended to limit the conditions under which this application can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportional relationships, or adjustments to the size, without affecting the effects and objectives that the invention can produce, should still fall within the scope of the technical content disclosed in this application.

[0037] See Figure 1 This embodiment provides a method for preparing a semiconductor sample, including the following steps:

[0038] S1: A semiconductor structure is provided, the semiconductor structure including a target layer and a surface layer formed on the target layer, the target layer having a target structure;

[0039] S2: Determine a pre-positioning region of the target structure on the surface of the semiconductor structure;

[0040] S3: Etch the semiconductor structure to form a positioning window in the surface layer that exposes the target structure;

[0041] S4: Determine the position of the target structure through the positioning window, and form a positioning mark of the target structure in the semiconductor structure;

[0042] S5: Grind the semiconductor structure to obtain a semiconductor sample.

[0043] The aforementioned preparation method first utilizes positional reference information obtainable from the semiconductor structure surface to pre-position the target structure located inside the semiconductor structure, thereby determining the approximate region corresponding to the target structure. Subsequently, a positioning window is formed within this region to further determine the position of the target structure. After determining the position of the target structure, a positioning mark with a preset positional relationship to the target structure is formed. During the cross-sectional grinding process, the positioning mark is used to determine whether the current grinding position has reached or is close to the region where the target structure is located. Then, combined with microscopic observation and confirmation, the target structure is further observed and confirmed, thus gradually completing the cross-sectional positioning of the target structure.

[0044] In step S1, see Figure 2 A semiconductor structure is provided. The semiconductor structure includes a surface layer 110 and a target layer 120, wherein the surface layer 110 is formed on the target layer 120 and the target structure 130 is located in the target layer 120.

[0045] The surface layer 110 is located on the side of the target layer 120 closest to the surface of the semiconductor structure. It can be a single-layer structure or include multiple layers arranged along the thickness direction of the semiconductor structure. The specific number of layers and the specific materials of each layer can be determined according to the actual structure of the semiconductor structure. The target layer 120 is the layer structure containing the target structure 130. The target structure 130 is the target area that needs to be located in the cross-section in this embodiment and observed or detected after the cross-section is formed. The surface layer 110 and the target layer 120 are mainly used to indicate the hierarchical relationship between the relevant structure and the target structure 130, and do not limit the semiconductor structure to be composed only of the surface layer 110 and the target layer 120.

[0046] Since the target structure 130 is located inside the semiconductor structure and has a surface layer 110 on its surface side, it is usually difficult to directly and accurately identify the position of the target structure 130 from the surface of the semiconductor structure. Especially when the size of the target structure 130 is small, relying solely on surface observation is insufficient to provide a sufficiently accurate positional basis for subsequent cross-sectional grinding. Therefore, before forming the positioning window and performing cross-sectional grinding, the target structure 130 is pre-positioned on the surface.

[0047] In step S2, see Figure 3 and Figure 4 A pre-positioning region 150 corresponding to the target structure 130 is determined on the surface of the semiconductor structure.

[0048] The surface of the semiconductor structure is provided with identifiable feature patterns 140. Feature patterns 140 refer to graphic features disposed on or identifiable from the surface of the semiconductor structure and used to provide a positional reference. Feature patterns 140 can serve as a positional reference for pre-positioning the target structure 130. Based on a predetermined relative distance or position between feature patterns 140 and the target structure 130, the approximate position of the target structure 130 on the semiconductor structure surface can be determined, and the area corresponding to that position is designated as the pre-positioning area 150.

[0049] The pre-positioning region 150 is a region defined on the surface of the semiconductor structure based on the positional relationship between the feature pattern 140 and the target structure 130, and is used to determine the approximate formation location of the subsequent positioning window 160. Step S2 does not require direct identification of the target structure 130 from the semiconductor structure surface, but rather uses the identifiable feature pattern 140 on the semiconductor structure surface to narrow down the position range of the target structure 130 to a corresponding surface area, so that the subsequent positioning window 160 can be formed for this area, thereby providing a basis for further determining the position of the target structure 130.

[0050] In this embodiment, the relative distance refers to a predetermined distance relationship between the feature pattern 140 and the target structure 130. The position of the target structure 130 relative to the feature pattern 140 can be determined based on the interval or offset distance between them. The relative position refers to a predetermined positional correspondence between the feature pattern 140 and the target structure 130. It does not require a specific distance value as a necessary condition, but rather determines the corresponding position of the target structure 130 relative to the feature pattern 140 based on their layout relationship in the semiconductor structure. Therefore, the target structure 130 can be pre-positioned using distance or positional correspondence based on the available positional reference information.

[0051] See Figure 3In one embodiment, a pre-positioning region 150 can be determined based on a predetermined relative distance between the feature pattern 140 and the target structure 130. Specifically, a feature pattern 140 that can be identified on the surface of the semiconductor structure can be selected as a position reference, and the interval or offset distance between the feature pattern 140 and the target structure 130 can be determined. Based on the distance, the approximate position of the target structure 130 on the surface of the semiconductor structure can be calculated from the position of the feature pattern 140, and the area corresponding to this position can be determined as the pre-positioning region 150.

[0052] Figure 3 The target structure 130, indicated by the dashed line, is used to illustrate the corresponding position of the target structure 130 relative to the surface of the semiconductor structure, and does not indicate that the target structure 130 can be directly observed from the surface of the semiconductor structure during surface pre-positioning.

[0053] See Figure 4 In another embodiment, a pre-defined positioning region 150 can be determined based on a predetermined relative position between the feature pattern 140 and the target structure 130. When there is a definite positional correspondence between the feature pattern 140 and the target structure 130, the approximate position of the target structure 130 on the semiconductor structure surface can be further determined by identifying the position of the feature pattern 140.

[0054] Figure 4 The geometric figures in the figure are used to illustrate the feature figure 140 and its positional relationship with the target structure 130. Their specific shapes can be determined according to the actual pattern on the surface of the semiconductor structure and are not limited by the shape shown in the figure.

[0055] The two pre-positioning methods described above utilize the relative distance and relative position between the feature pattern 140 and the target structure 130 for position determination, enabling the target structure 130, located internally and difficult to observe directly, to establish a positional correspondence with the identifiable features on the semiconductor structure surface. In actual fabrication, the appropriate pre-positioning method can be selected based on the positional reference information obtainable from the semiconductor structure surface.

[0056] In step S3, see Figure 5 The semiconductor structure is etched to form a positioning window 160 in the surface layer 110. The positioning window 160 is a local window region formed by removing at least a portion of the surface layer 110 corresponding to the prepositioning region 150, and is formed at the position corresponding to the target structure 130.

[0057] The position of the positioning window 160 is determined based on the aforementioned pre-positioning region 150. Step S2 first determines the approximate position of the target structure 130, and step S3 then forms the positioning window 160 by locally etching the surface layer 110 corresponding to that position, thereby further narrowing the range of the target structure 130's position determination and providing a clearer positional basis for the subsequent formation of the positioning mark 180.

[0058] The specific shape, length, and width of the positioning window 160 are not particularly limited and can be set according to the size of the target structure 130 and the position of the target structure 130 in the semiconductor structure.

[0059] In the projection plane of the semiconductor structure along its thickness direction, the projection area of ​​the positioning window 160 at least covers the projection area of ​​the target structure 130 and extends beyond the projection area of ​​the target structure 130. Thus, in addition to covering the position corresponding to the target structure 130, the positioning window 160 also retains a certain range around the target structure 130.

[0060] The positioning window 160 has the aforementioned range, which on the one hand provides a sufficient observation area for further locating and confirming the target structure 130 through the positioning window 160; on the other hand, it leaves corresponding processing space for subsequently forming the positioning mark 180 in the vicinity of the target structure 130. Therefore, the positioning window 160 does not need to have a fixed absolute size, and its size can be adjusted accordingly based on the size and specific position of the target structure 130.

[0061] In one embodiment, a semiconductor structure can be placed in a plasma etching apparatus, and an auxiliary etching gas is introduced during the etching process to etch the surface layer 110 corresponding to the pre-positioning region 150 to form a patterned positioning window 160. By performing patterning processing within the pre-positioning region 150, the positioning window 160 can be formed in the region corresponding to the target structure 130, providing a structural basis for further determining the position of the target structure 130 through the positioning window 160.

[0062] In another specific embodiment, a focused ion beam (FIB) can be used for windowing. Specifically, FIB is used to remove layers at the location corresponding to the pre-positioning region 150, removing at least a portion of the surface layer 110 located on the surface side of the target structure 130 to form the positioning window 160.

[0063] During FIB layer-by-layer removal, an auxiliary etching gas can be introduced to increase the etching rate and improve the uniformity of the layer-by-layer removal process. Under specific preparation conditions, a gallium ion beam with an accelerating voltage of 30 kV can be used, along with an iodine-based auxiliary etching gas; alternatively, a halogen-based gas suitable for the corresponding etching process can also be used as the auxiliary etching gas.

[0064] After the positioning window 160 is formed, the target structure 130 is further observed and its position confirmed through the positioning window 160. Compared with the surface pre-positioning in step S2, the positioning window 160 allows the position of the target structure 130 to be confirmed within a smaller range, thereby providing a basis for setting positioning marks according to the specific position of the target structure 130.

[0065] In step S4, see Figure 6 and Figure 7 After determining the position of the target structure 130 through the positioning window 160, a positioning mark with a preset positional relationship to the target structure 130 is formed in the semiconductor structure. The positioning mark is an identifiable structure formed according to the determined position of the target structure 130 and having a preset positional relationship with the target structure 130, used to convert the position of the target structure 130 into a positional reference that can be identified in the subsequent cross-sectional grinding process.

[0066] See Figure 6 In one embodiment, the adjacent structure 170 is located on one side of the target structure 130 and has a defined positional relationship with the target structure 130, and the positioning mark 180 is formed at the position corresponding to the adjacent structure 170.

[0067] exist Figure 6 In the illustrated embodiment, adjacent structures 170 and target structures 130 extend in the same direction and have a parallel positional relationship. After the positioning mark 180 is formed at the corresponding position of the adjacent structure 170, a definite positional correspondence is formed between the positioning mark 180 and the target structure 130.

[0068] In some embodiments, the positioning mark 180 penetrates the surface layer 110 and extends to the target layer 120, such that the positioning mark 180 extends to the layer position corresponding to the target structure 130, so that it can be observed and identified during subsequent cross-sectional grinding.

[0069] The positioning mark 180 can take different structural forms. In some embodiments, the positioning mark 180 can be any of the following: a through hole, a groove, or a recess. Different forms of positioning marks are used to form observable and identifiable positional features during subsequent cross-sectional grinding, so that the position of the target structure 130 can be indirectly reflected through the positioning marks.

[0070] In one specific embodiment, FIB etching can be used to etch adjacent structural locations of the target structure 130 to form hole-shaped positioning marks 180. The formation depth of the hole-shaped positioning marks 180 can be controlled according to the layer position of the semiconductor structure and the depth of the target layer 120, extending it along the thickness direction to a position that can be identified during subsequent cross-sectional polishing. For example, under specific fabrication conditions, a deep hole with a depth of approximately 2 μm can be formed, and this deep hole can be used as the positioning mark 180.

[0071] Besides hole-shaped positioning marks, positioning marks 180 can also take the form of grooves or pits, which can be identified in the polished cross-section. In the actual fabrication process, the appropriate positioning mark form can be selected according to the specific structure of the semiconductor structure, the processing method of the positioning marks, and the subsequent cross-sectional observation conditions.

[0072] In addition to setting the positioning mark 180 at a structural position adjacent to the target structure 130, the positioning mark 180 can also be formed at a predetermined distance from the target structure 130 based on the already determined position of the target structure 130. In this case, the predetermined distance between the positioning mark 180 and the target structure 130 constitutes a positional correspondence between the two. In the subsequent grinding process, this positional relationship can also be used to determine the distance relationship between the current grinding position and the area where the target structure 130 is located.

[0073] See Figure 7 In another embodiment, the positioning markers include a first positioning marker 181 and a second positioning marker 182. The first positioning marker 181 and the second positioning marker 182 are located on opposite sides of the target structure 130 and are in the same plane.

[0074] The first positioning mark 181 and the second positioning mark 182 can be formed at corresponding positions on adjacent structures 170 on both sides of the target structure 130, so that the target structure 130 is located between the two positioning marks. By setting positioning marks on opposite sides of the target structure 130, the grinding position can be determined simultaneously or separately using the positioning marks on both sides during the subsequent cross-sectional grinding process, and the area where the target structure 130 is located can be confirmed by combining the positional relationship between the two positioning marks and the target structure 130.

[0075] In one specific embodiment, FIB etching can be used to form grooves on both sides of the target structure 130, and the two grooves can be used as the first positioning mark 181 and the second positioning mark 182, respectively. The two grooves provide position references from both sides of the target structure 130, so that the position determination during the grinding process no longer depends on a single positioning mark, which helps to improve the accuracy of the positioning determination.

[0076] Before performing step S5, in some embodiments, an adhesive layer may be formed on the semiconductor structure, and a glass slide may be attached to the adhesive layer. The adhesive layer is used to connect the semiconductor structure and the glass slide, and a transparent adhesive material may be used, so that the grinding position of the semiconductor structure can be observed through the glass slide and the adhesive layer during subsequent cross-sectional grinding.

[0077] In one specific embodiment, the adhesive layer can be formed using hot melt adhesive or a transparent adhesive such as cyanoacrylate adhesive. This adhesive material serves both to connect the glass slide to the semiconductor structure and, due to its transparency, to allow subsequent observation of the approximate location of the grinding process using an optical microscope.

[0078] The glass slide is mainly used to assist in observing the approximate position during the cross-sectional grinding process. In some embodiments, when the distance between the target structure 130 and the semiconductor structure surface is large, or when positional judgment information that meets the grinding requirements can be obtained through other means, a glass slide may not be used depending on the actual sample preparation conditions.

[0079] In step S5, see Figure 8 The semiconductor structure is subjected to cross-sectional grinding to obtain a semiconductor sample. The cross-section during the cross-sectional grinding process is the grinding surface at 190°.

[0080] Figure 8 The cross-sectional grinding process along the AA direction is demonstrated. The relevant structures in the semiconductor structure are arranged according to a predetermined hierarchy and orientation, and the positioning marks and target structure 130 have a pre-determined positional correspondence. During the cross-sectional grinding process, the grinding surface 190 remains parallel to the plane containing the positioning marks and target structure 130, and advances towards the positions of the positioning marks and target structure 130 as the semiconductor structure material is gradually removed.

[0081] By keeping the grinding surface 190 parallel to the plane containing the positioning mark and the target structure 130, the positioning mark and the target structure 130 can maintain a predetermined positional correspondence during the cross-sectional grinding process. During this parallel grinding process, an optical microscope (OM) can be used to observe the grinding cross-section to determine the approximate grinding position and progress. The OM is suitable for observing a relatively large grinding area, but when the target structure 130 is small, its resolution may be insufficient for precise positioning of the target structure 130.

[0082] Therefore, during the cross-section grinding process, an optical microscope (OM) can be used to roughly determine the grinding position, gradually bringing the grinding surface 190 closer to the area where the positioning mark or target structure 130 is located. When the OM observation determines that the current grinding position is close to the aforementioned area, a higher resolution observation method is then used to further observe and locate the grinding cross-section. Specifically, a scanning electron microscope (SEM) is used to identify smaller structures and the aforementioned positioning marks.

[0083] When the positioning mark is exposed in the polishing section and can be identified by SEM, the exposure of the positioning mark and the predetermined positional relationship between the positioning mark and the target structure 130 can be combined to determine that the current polishing position has reached or is close to the corresponding area where the target structure 130 is located. Based on this, the target structure 130 can be further observed and its position confirmed by SEM, and the semiconductor structure can be finely polished according to the observation results until a semiconductor sample containing the target structure 130 and meeting the requirements for subsequent observation or testing is obtained.

[0084] for Figure 6 The unilateral positioning method shown can determine the correspondence between the current grinding position and the area where the target structure 130 is located based on the exposure of the positioning mark 180 and the preset positional relationship between the positioning mark 180 and the target structure 130 during the above-mentioned cross-sectional grinding process. See Figure 9 , Figure 9 The positional correspondence between the positioning mark 180 and the target structure 130 is shown. In one specific embodiment, the positioning mark 180 can be a hole-shaped positioning mark formed using FIB. By identifying the positioning mark 180 and combining it with the predetermined positional relationship between the positioning mark 180 and the target structure 130, the position corresponding to the target structure 130 can be determined, providing a positional basis for further approaching and confirming the target structure 130 from the position of the positioning mark during the cross-section grinding process.

[0085] In Adoption Figure 7 In the dual-sided positioning method shown, the first positioning mark 181 and the second positioning mark 182 can be observed separately during the cross-section grinding process, and the current grinding position can be determined by combining the positional relationship between the two positioning marks and the target structure 130. When the two positioning marks are in a state that can be observed, the current grinding position can be further checked by using the position reference of the target structure 130 on both sides, and on this basis, the target structure 130 can be finely observed and confirmed by a microscope.

[0086] After obtaining the semiconductor sample, it can be further processed according to subsequent detection or analysis requirements. In one specific application, the ground cross-section can be treated with low-energy argon ion polishing to make the resulting semiconductor sample meet the sample preparation requirements for subsequent detection, and SCM can be used to observe or detect the area where the target structure 130 is located.

[0087] The above-described method for preparing semiconductor samples can also be applied to semiconductor device failure analysis. By using positioning marks during the cross-sectional grinding process to help determine the location of the target structure 130, and combining this with microscopy to further confirm the target structure 130, a sample basis can be provided for cross-sectional observation and subsequent analysis of specific target areas inside semiconductor devices.

[0088] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for preparing a semiconductor sample, characterized in that, include: S1: A semiconductor structure is provided, the semiconductor structure including a target layer and a surface layer formed on the target layer, the target layer having a target structure; S2: Determine a pre-positioning region of the target structure on the surface of the semiconductor structure; S3: Etch the semiconductor structure to form a positioning window in the surface layer that exposes the target structure; S4: Determine the position of the target structure through the positioning window, and form a positioning mark of the target structure in the semiconductor structure; S5: Grind the semiconductor structure to obtain a semiconductor sample.

2. The method for preparing a semiconductor sample according to claim 1, characterized in that, In step S2, the surface of the semiconductor structure is provided with a feature pattern, and the pre-positioning region is determined according to the preset relative distance or relative position between the feature pattern and the target structure.

3. The method for preparing a semiconductor sample according to claim 1, characterized in that, In step S3, the semiconductor structure is placed in a plasma etching apparatus and an auxiliary etching gas is introduced to form a patterned positioning window.

4. The method for preparing a semiconductor sample according to claim 1, characterized in that, In the projection plane of the semiconductor structure along its thickness direction, the projection area of ​​the positioning window at least covers the projection area of ​​the target structure and extends beyond the projection area of ​​the target structure.

5. The method for preparing a semiconductor sample according to claim 1, characterized in that, In step S4, a positioning mark is formed on one side of the target structure, penetrating the surface layer and extending to the target layer.

6. The method for preparing a semiconductor sample according to claim 1, characterized in that, The positioning mark is any one of a through hole, a groove, or a pit.

7. The method for preparing a semiconductor sample according to claim 1, characterized in that, Before performing step S5, the following is also included: An adhesive layer is formed on the semiconductor structure; A glass slide is attached to the adhesive layer.

8. The method for preparing a semiconductor sample according to claim 1, characterized in that, In step S4, the positioning marks include a first positioning mark and a second positioning mark, which are located on opposite sides of the target structure and are in the same plane.

9. The method for preparing a semiconductor sample according to claim 8, characterized in that, In step S5, the semiconductor structure is ground until the positioning mark is exposed to obtain the semiconductor sample, wherein the ground surface of the semiconductor structure is parallel to the plane containing the positioning mark and the target structure.

10. An application of the method according to any one of claims 1 to 9 in semiconductor device failure analysis.

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