Method and apparatus for measuring output capacitance hysteresis loss of power semiconductor switching device

Abstract

This invention discloses a method and apparatus for measuring the output capacitance hysteresis loss of power semiconductor switching devices, belonging to the field of power electronics testing and measurement technology. The method includes: constructing a half-bridge circuit comprising the device under test (DUT) and a sensing resistor; applying complementary drive signals to the upper and lower bridge arm switches in the half-bridge circuit, and applying a DC bus voltage to the upper bridge arm switch to execute a charging and discharging process; simultaneously acquiring the voltage between the first and second main electrodes of the DUT and the voltage across the sensing resistor, and calculating the charging and discharging current; and calculating the output capacitance hysteresis loss within a single charging and discharging cycle based on the voltage between the first and second main electrodes and the charging and discharging current. This method, by combining a half-bridge circuit with differential detection technology, possesses the ability to flexibly and independently adjust the Coss charging rate, providing more reliable test data for power device selection and circuit design, and has significant industrial application value.

Description

Technical Field

[0001] This invention belongs to the field of power electronic testing and measurement technology, specifically relating to a method and apparatus for measuring the output capacitance hysteresis loss of a power semiconductor switching device. Background Technology

[0002] Power semiconductor switching devices, especially high-voltage superjunction MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), are widely used in power conversion devices such as switching power supplies, adapters, and chargers due to their low on-resistance and excellent switching performance. To improve power density, these converters often employ high-frequency soft-switching technologies, such as zero-voltage switching (ZVS), to reduce switching losses. However, under ZVS operating conditions, the MOSFET's output capacitance (Coss) is not ideally lossless during charging and discharging. Its charge-voltage (QV) characteristic curve does not coincide during charging and discharging, exhibiting a significant hysteresis phenomenon. This results in an additional energy loss, namely Coss hysteresis loss (Eoss hys). Especially in high-frequency soft-switching applications, this loss increases linearly with the switching frequency and has become one of the main components of the total device loss, directly affecting the converter's efficiency and power density. Accurate measurement of Coss hysteresis loss is of great significance for device selection, loss assessment, thermal design, and verification of new materials and processes.

[0003] Currently, the mainstream methods for measuring Coss hysteresis loss in the industry mainly include two types. The first is the Sawyer-Tower method, which involves connecting a reference capacitor Cref in series in the test circuit. By measuring the charge Q of the reference capacitor and the drain-source voltage Vds of the transistor under test, a Coss charge-discharge QV curve is plotted, and the hysteresis loss is calculated from the area enclosed by the charge-discharge curve. The second method is the calorimetric method, which utilizes a full-bridge circuit topology. An inductor is connected in series at the midpoint of one bridge arm as an inductive load. One bridge arm is the MOSFET under test, and the other is the active switch. By controlling the drive timing of the active switch, the transistor under test undergoes only the Coss charge-discharge process without any conduction current flowing through the channel. The Coss hysteresis loss is then indirectly calculated by measuring the temperature rise or heat dissipation of the transistor under test.

[0004] However, both of the aforementioned existing methods have significant shortcomings. Specifically, the first method, based on the Sawyer-Tower method, suffers from non-ideal factors in the reference capacitor itself, including equivalent series resistance, parasitic inductance, and dielectric absorption effects. This directly affects the measurement accuracy of the charge Q, introducing systematic errors that are difficult to quantitatively correct. The second method, calorimetry, is essentially an indirect measurement method that infers electrical losses through thermal effects. Its measurement resolution is limited by the accuracy of the temperature sensor, the thermal time constant, and environmental thermal noise. Since Coss hysteresis losses are typically in the milliwatt range or even smaller, at such low power levels, the device temperature rise is extremely weak and easily masked by ambient temperature drift or fluctuations in the heat dissipation path, resulting in large measurement uncertainties and poor repeatability. Furthermore, calorimetry requires waiting for the device to reach thermal equilibrium for each test, making each measurement time-consuming and unsuitable for rapid comparative evaluation.

[0005] In summary, existing methods for measuring Coss hysteresis loss cannot simultaneously address the following aspects: first, the ability to flexibly and independently adjust the Coss charge and discharge rate to simulate the actual stress of the device under different switching frequencies and ZVS transition times; second, the direct acquisition of the charge and discharge voltage-current time-domain waveforms in a purely electrical sense, thereby accurately separating the charged energy from the released energy and avoiding cumulative errors introduced by thermal conversion or mathematical inversion; and third, ensuring high measurement accuracy while also considering the simplicity, repeatability, and rapid measurement capabilities of the test platform.

[0006] Therefore, there is a need for a Coss hysteresis loss measurement method that can overcome the above-mentioned defects and has high accuracy, good repeatability and practicality, so as to support the accurate evaluation and system optimization of power semiconductor devices in high-frequency power conversion applications. Summary of the Invention

[0007] To address the aforementioned problems in the prior art, this invention provides a method and apparatus for measuring the hysteresis loss of the output capacitance of a power semiconductor switching device. In a first aspect, the present invention provides a method for measuring the hysteresis loss of the output capacitor of a power semiconductor switching device, comprising the following steps: Step 1: Construct a half-bridge circuit; the half-bridge circuit includes an upper bridge arm switch and a lower bridge arm switch, and the connection point between the upper bridge arm switch and the lower bridge arm switch is the midpoint of the half-bridge; the power semiconductor switch device under test is connected in parallel across the two ends of the lower bridge arm switch, and the control electrode of the power semiconductor switch device under test is short-circuited with the first main electrode, so that its channel is always in the off state; a detection resistor is also connected in series in the first main electrode branch of the power semiconductor switch device under test; Step 2: Apply complementary drive signals to the upper and lower bridge arm switches and set the dead time; apply a DC bus voltage to the upper bridge arm switch. When the upper bridge arm switch is turned on, the DC bus voltage charges the output capacitor of the power semiconductor switching device under test through the upper bridge arm switch and the sensing resistor; when the lower bridge arm switch is turned on, the output capacitor of the power semiconductor switching device under test discharges through the sensing resistor and the lower bridge arm switch. Step 3: During a complete charge-discharge cycle, simultaneously acquire the voltage between the first main electrode and the second main electrode of the power semiconductor switching device under test, as well as the voltage across the detection resistor; Step 4: Calculate the charging and discharging current based on the resistance value of the detection resistor and the voltage across the detection resistor, and calculate the output capacitor hysteresis loss in a single charging and discharging cycle based on the voltage between the first main electrode and the second main electrode and the charging and discharging current.

[0008] In a second aspect, the present invention provides a device for measuring the output capacitance hysteresis loss of a power semiconductor switching device, used to implement the method proposed in the first aspect of the present invention, the device comprising: The half-bridge circuit includes an upper bridge arm switch and a lower bridge arm switch, with the connection point between the upper and lower bridge arm switches serving as the midpoint of the half-bridge. The power semiconductor switch under test is connected in parallel across the lower bridge arm switch, and the control electrode of the power semiconductor switch under test is short-circuited with the first main electrode, so that its channel is always in the off state. A detection resistor is also connected in series in the first main electrode branch of the power semiconductor switch under test. The drive signal generation unit is connected to the control terminals of the upper and lower bridge arm switches and is used to output complementary drive signals to the upper and lower bridge arm switches and set the dead time. A DC power supply, with its positive terminal connected to the first main electrode of the upper bridge arm switching transistor and its negative terminal grounded, is used to provide DC bus voltage to perform the charging and discharging process in step 2. The voltage acquisition unit is connected to the two ends of the detection resistor and the first main electrode and the second main electrode of the power semiconductor switching device under test. It is used to synchronously acquire the voltage between the first main electrode and the second main electrode of the power semiconductor switching device under test and the voltage across the detection resistor during a complete charge and discharge cycle, so as to execute step 3. The data processing unit, connected to the voltage acquisition unit, is used to calculate the charging and discharging current based on the resistance value of the detection resistor and the voltage across the detection resistor, and to calculate the output capacitor hysteresis loss in a single charging and discharging cycle based on the voltage between the first main electrode and the second main electrode and the charging and discharging current, so as to execute step 4.

[0009] Compared with the prior art, the beneficial effects of the present invention are as follows: The present invention provides a method for measuring the output capacitor hysteresis loss of power semiconductor switching devices. First, a half-bridge circuit is constructed, and the device under test (DUT) is connected in parallel across the lower arm switch of the half-bridge circuit. The control electrode of the DUT is short-circuited to the first main electrode, ensuring its channel remains in the off state. Simultaneously, a detection resistor is connected in series in the first main electrode branch of the DUT. Next, complementary drive signals are applied to the upper and lower arm switches of the half-bridge circuit, and a dead time is set. A DC bus voltage is applied to the upper arm switch to realize the charging and discharging process of the output capacitor. Then, within a complete charging and discharging cycle, the voltage between the first and second main electrodes of the DUT and the voltage across the detection resistor are simultaneously acquired. Finally, the output capacitor hysteresis loss is calculated based on the acquired data. This method combines a half-bridge circuit with differential detection technology, directly obtaining the charging and discharging current through only the half-bridge circuit and the detection resistor, and combining it with the electrode voltage. This enables adjustable, pure, and fast direct electrical measurement, fundamentally solving the comprehensive problems of existing methods in terms of accuracy, adjustability, measurement speed, and purity. It provides more reliable test data for the selection of power semiconductor switching devices and circuit design, and has significant industrial application value.

[0010] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0011] Figure 1 A schematic flowchart illustrating the method for measuring the output capacitance hysteresis loss of a power semiconductor switching device provided in an embodiment of the present invention; Figure 2 A schematic diagram illustrating the test principle of hysteresis loss of MOSFET device output capacitor provided in an embodiment of the present invention; Figure 3 The actual test waveforms of the voltage between the first main electrode and the second main electrode and the voltage across the detection resistor provided for embodiments of the present invention; Figure 4 This is a structural block diagram of the output capacitance hysteresis loss measurement device for power semiconductor switching devices provided in an embodiment of the present invention. Detailed Implementation

[0012] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described below are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0013] The first aspect of this invention provides a method for measuring the hysteresis loss of the output capacitor of a power semiconductor switching device. Please refer to [link to relevant documentation]. Figure 1 , Figure 1 A flowchart illustrating a method for measuring the output capacitance hysteresis loss of a power semiconductor switching device provided in an embodiment of the present invention. The method mainly includes the following steps: Step 1: Construct a half-bridge circuit; the half-bridge circuit includes an upper bridge arm switch and a lower bridge arm switch, and the connection point between the upper bridge arm switch and the lower bridge arm switch is the midpoint of the half-bridge; the power semiconductor switch device under test is connected in parallel across the two ends of the lower bridge arm switch, and the control electrode of the power semiconductor switch device under test is short-circuited with the first main electrode, so that its channel is always in the off state; a detection resistor is also connected in series in the first main electrode branch of the power semiconductor switch device under test.

[0014] Optionally, in this embodiment, the power semiconductor switching device (also referred to as the device in this embodiment) mainly refers to a controllable semiconductor switching device with three terminals: a control electrode, a first main electrode, and a second main electrode. It can be a MOSFET or an IGBT, etc. A common characteristic of these devices is that their output capacitance exhibits a hysteresis effect during charging and discharging, and this effect cannot be directly obtained from the device datasheet and requires actual measurement. When the device under test is a MOSFET, the corresponding control electrode is the gate, the first main electrode is the drain, and the second main electrode is the source; when the device under test is an IGBT, the corresponding control electrode is the gate, the first main electrode is the collector, and the second main electrode is the emitter.

[0015] In addition, the power semiconductor switching device in this invention can also be a SiC MOSFET (silicon carbide MOSFET) or a GaN HEMT (gallium nitride high electron mobility transistor), etc.

[0016] For example, this embodiment uses an N-channel enhancement-mode MOSFET as the power semiconductor switching device under test, but those skilled in the art should understand that this method is also applicable to other power semiconductor switching devices with output capacitor hysteresis effect.

[0017] For details, please see Figure 2 , Figure 2 This is a schematic diagram illustrating the test principle for the output capacitance hysteresis loss of a MOSFET device according to an embodiment of the present invention. The half-bridge circuit includes an upper bridge arm switch Q1 and a lower bridge arm switch Q2, both of which are MOSFETs. The drain of Q1 is connected to the positive terminal of the DC bus voltage +Vbus, i.e. Figure 2 The positive terminal of the DC power supply VDD is connected to the source of Q1 and the drain of Q2, and this connection point serves as the midpoint of the half-bridge. The source of Q2 is connected to the negative terminal (i.e., ground) of the DC bus.

[0018] MOSFET under test Figure 2The Device Under Test (DUT) is connected in parallel across the lower bridge arm switch Q2. Specifically, the drain of the DUT is connected to the midpoint of the half-bridge, and the source of the DUT is grounded. Thus, the DUT and the lower bridge arm switch Q2 form a parallel structure, and the drain-source voltage Vds of the DUT is always equal to the voltage between the midpoint of the half-bridge and ground.

[0019] like Figure 2 As shown, the gate and source of the DUT are shorted. In practice, the gate and source pins of the DUT can be directly electrically connected using a short wire, or the gate and source pins of the DUT can be connected to ground potential. In this way, the gate-source voltage Vgs is zero, the channel of the DUT is always in the off state, and only the output capacitance Coss (the equivalent capacitance including the junction capacitance, Miller capacitance, and other distributed capacitances of the device) exists between the drain and source of the DUT, without any conductive channel current flowing through it. This ensures that all currents during the charging and discharging process are the charge / discharge displacement current of Coss, guaranteeing the purity of the measured loss.

[0020] For further details, please continue to see Figure 2 A sensing resistor, Rsense, is connected in series in the drain branch of the DUT. Specifically, one end of Rsense is connected to the drain of the DUT, and the other end is connected to the midpoint of the half-bridge. Thus, Rsense is connected in series between the drain of the DUT and the midpoint of the half-bridge. When the upper bridge arm switch Q1 is turned on, the charging current flows from the positive terminal of the DC bus, through Q1 and Rsense, into the drain of the DUT, charging Coss. When the lower bridge arm switch Q2 is turned on, the discharging current flows from the output capacitor Coss of the DUT, through the drain of the DUT, Rsense, and Q2, back to ground. Therefore, regardless of whether it is charging or discharging, the entire charging and discharging current flows through Rsense. By measuring the voltage Vsense across Rsense, the magnitude and direction of the charging and discharging current Ids can be accurately determined according to Ohm's law.

[0021] Optionally, in this embodiment, two high-voltage differential probes can be connected to the two ends of Rsense and the source-drain terminals of the DUT, respectively, to measure the voltage Vsense across Rsense and the source-drain voltage Vds of the DUT. The measured waveforms of Vsense and Vds can be displayed using an oscilloscope.

[0022] In addition, it should be noted that a DC bus capacitor C is connected across the DC power supply VDD, such as... Figure 2 As shown, it is mainly used to stabilize the bus voltage and filter out AC noise from DC power supply and high-frequency spikes generated by switching action, hence it is also called filter capacitor or support capacitor.

[0023] This embodiment ensures the channel remains closed by short-circuiting the control electrode of the device under test to the first main electrode, achieving pure separation of Coss hysteresis loss. A detection resistor is connected in series in the drain branch, providing a physical basis for direct measurement of the subsequent charge and discharge current. Compared to the existing Sawyer-Tower method, which requires a large-capacity reference capacitor in series, the detection resistor in this invention has a very small value, avoiding significant parasitic effects and fundamentally preventing the influence of the equivalent series resistance, parasitic inductance, and dielectric absorption effect of the reference capacitor on measurement accuracy.

[0024] Step 2: Apply complementary drive signals to the upper and lower bridge arm switches and set the dead time; apply a DC bus voltage to the upper bridge arm switch. When the upper bridge arm switch is turned on, the DC bus voltage charges the output capacitor of the power semiconductor switching device under test through the upper bridge arm switch and the sensing resistor; when the lower bridge arm switch is turned on, the output capacitor of the power semiconductor switching device under test discharges through the sensing resistor and the lower bridge arm switch.

[0025] In this embodiment, complementary drive signals refer to two control signals that are logically inverses of each other, that is, when one is high, the other is low.

[0026] Optionally, the complementary drive signals used in this embodiment can be output by a signal generator or other PWM signal generation unit. It should be noted that the high level of the drive signal should be higher than the gate threshold voltage of the upper and lower bridge arm switches to ensure that the switches can be fully turned on; the low level should be lower than the gate threshold voltage to ensure that the switches can be reliably turned off.

[0027] Furthermore, dead time refers to a brief period inserted into the signal timing during the level transition of the complementary drive signal. This period is crucial to prevent a short circuit on the DC bus caused by simultaneous conduction of the upper and lower bridge arms. During the dead time, both the upper and lower bridge arms are in the off state, and the output capacitor of the device under test neither charges nor discharges, maintaining its current voltage. The length of the dead time should be appropriately set according to the switching speed of the switching transistors, typically ranging from tens of nanoseconds to several microseconds, for example, 200 ns. The setting of the dead time ensures the safe operation of the half-bridge circuit and prevents shoot-through short-circuit faults.

[0028] Furthermore, in this embodiment, charging refers to the process where, when the upper bridge arm switch is turned on and the lower bridge arm switch is turned off, the DC bus voltage injects charge into the output capacitor of the device under test (DUT) through the upper bridge arm switch and the sensing resistor, causing the voltage (Vds) between the first and second main electrodes of the DUT to gradually increase to near the bus voltage. Discharging refers to the process where, when the lower bridge arm switch is turned on and the upper bridge arm switch is turned off, the charge stored in the output capacitor of the DUT is released to ground through the sensing resistor and the lower bridge arm switch, causing the drain-source voltage of the DUT to gradually decrease to near 0V.

[0029] For example, taking a MOSFET as an example, turn on the DC power supply and set the DC bus voltage to the target voltage value (such as 400V). This voltage is applied to the upper arm of the half-bridge circuit, that is, between the drain of Q1 and ground.

[0030] Turn on the drive power and use a signal generator to output two complementary drive signals to the gates of Q1 and Q2. The two drive signals have the same frequency to ensure that the charging and discharging times are approximately equal; and a dead time is set between the two signals to prevent Q1 and Q2 from conducting simultaneously.

[0031] Under normal operating conditions of a half-bridge circuit, a complete charge-discharge cycle consists of two phases: the charging phase and the discharging phase.

[0032] During the charging phase, the gate of Q1 is at a high level, and the gate of Q2 is at a low level, so Q1 is turned on and Q2 is turned off. The DC bus voltage +Vbus applies a positive voltage to the drain of the DUT through Q1 and Rsense. Since the gate and source of the DUT are shorted and the channel is turned off, the current path is as follows: +Vbus, Q1, Rsense, the drain of the DUT, the output capacitor Coss of the DUT, the source of the DUT, and ground. This current is the charging current of Coss, and the drain-source voltage Vds of the DUT gradually rises from 0V until it reaches the bus voltage +Vbus.

[0033] During the discharge phase, the gate of Q1 is at a low level and the gate of Q2 is at a high level, so Q1 is turned off and Q2 is turned on. The charge stored in the DUT output capacitor Coss is released through the following path: the drain of the DUT, Rsense, Q2, and ground. This current is the discharge current of Coss, and Vds gradually decreases from the DC bus voltage until it approaches 0V.

[0034] Optionally, in this embodiment, the sensing resistor Rsense is an adjustable resistor. By adjusting the resistance value of the sensing resistor, the charging and discharging rate of the output capacitor is adjusted to simulate dynamic stress conditions under different switching frequencies. The larger the resistance value of the sensing resistor Rsense, the smaller the charging and discharging current, the smoother the rise and fall slopes (dv / dt) of Vds, and the cleaner the waveform, which helps to reduce test errors caused by oscillations. Conversely, the smaller the resistance value of Rsense, the larger the charging and discharging current, and the steeper the slope of Vds, which is closer to the actual switching conditions of the device.

[0035] Optionally, in this embodiment, the peak voltage of the power semiconductor switching device under test during the charging and discharging process of the output capacitor can be set by adjusting the DC bus voltage, thereby obtaining the hysteresis loss at the corresponding voltage level to simulate the dynamic stress conditions under different bus voltages.

[0036] Optionally, in this embodiment, the charging and discharging rate of the output capacitor can also be adjusted by regulating the frequency of the driving signal to simulate dynamic stress conditions at different switching frequencies. A higher driving signal frequency results in a faster charging and discharging rate, which can better simulate the dynamic stress conditions of the device in high-frequency switching applications; a lower driving signal frequency results in a slower charging and discharging rate, which helps reduce oscillations caused by circuit parasitic parameters and improves measurement accuracy.

[0037] This embodiment achieves flexible and independent control of the charging and discharging rate by adjusting the driving frequency and the resistance value of the sensing resistor. It can simulate the actual stress of the device under different switching frequencies and different ZVS transition times, which is not possible with the existing quasi-static measurement of the Sawyer-Tower method and the fixed resonance condition of the nonlinear resonance method.

[0038] Step 3: During a complete charge-discharge cycle, synchronously acquire the voltage between the first main electrode and the second main electrode of the power semiconductor switching device under test, as well as the voltage across the detection resistor.

[0039] Specifically, based on the above analysis, a complete charge-discharge cycle consists of two stages: the charging stage and the discharging stage. Taking a MOSFET as an example, a complete charge-discharge cycle corresponds to the entire process of Vds rising from 0V to the DC bus voltage +Vbus and then falling back to 0V. In this invention, the object of measurement is the magnitude of the Coss hysteresis loss within a single charge-discharge cycle.

[0040] Optionally, in this embodiment, the voltage across the detection resistor is acquired using a first voltage probe; and the voltage between the first main electrode and the second main electrode of the power semiconductor switching device under test is acquired using a second voltage probe.

[0041] Furthermore, in this embodiment, the waveforms of the voltage between the first main electrode and the second main electrode and the voltage across the detection resistor are simultaneously acquired and displayed using an oscilloscope.

[0042] Specifically, a first voltage probe is connected across the sensing resistor Rsense, and its output is connected to a channel of an oscilloscope, such as channel 1 (CH1), to measure the real-time voltage Vsense(t) across Rsense. A second voltage probe is connected between the drain and source of the MOSFET under test (i.e., the drain and source terminals of the DUT), and its output is connected to another channel of the oscilloscope, such as channel 2 (CH2), to measure the real-time drain-source voltage Vds(t) of the DUT.

[0043] After the measurement is started, channel 1 of the oscilloscope displays the voltage waveform of Vsense(t) in real time, and channel 2 displays the voltage waveform of Vds(t) in real time.

[0044] This embodiment achieves direct measurement of the charge / discharge voltage—a purely electrical quantity—by simultaneously acquiring Vds and Vsense. It eliminates the need for thermal conversion or complex mathematical inversion models, fundamentally avoiding the influence of non-electrical factors such as thermal time constants and ambient temperature drift on measurement accuracy in calorimetry. The measurement is fast and repeatable. Compared to the indirect charge measurement of the Sawyer-Tower method, this invention provides a more direct and accurate measurement, and eliminates the systematic error introduced by the parasitic effect of the reference capacitor, eliminating the need for a large-capacity reference capacitor.

[0045] Step 4: Calculate the charging and discharging current based on the resistance value of the detection resistor and the voltage across the detection resistor, and calculate the output capacitor hysteresis loss in a single charging and discharging cycle based on the voltage between the first main electrode and the second main electrode and the charging and discharging current.

[0046] Optionally, in this embodiment, the charging / discharging current and output capacitor hysteresis loss are calculated using the data calculation function of an oscilloscope; wherein, The charging and discharging current is calculated by dividing the voltage across the detection resistor by the resistance value of the detection resistor; The output capacitor hysteresis loss is calculated by integrating the product of the charging / discharging current and the voltage between the first and second main electrodes over a complete charging / discharging cycle.

[0047] Specifically, in the oscilloscope's data calculation function, edit formulas M1 and M2, and display the waveforms of M1 and M2 on the oscilloscope interface, respectively. M1 is the waveform of the Coss charge-discharge curve Ids(t), as shown below:

[0048] Since Rsense is a known constant, the oscilloscope will calculate the current value point by point based on the acquired Vsense(t) waveform and display the real-time waveform of Ids(t) on the screen.

[0049] Using the acquired Vds(t) and calculated Ids(t), the VI characteristic curves of Coss during the charging and discharging processes are plotted in a voltage-current coordinate system. These two curves form a closed loop. By integrating the area enclosed by this closed loop over time, the difference between the energy absorbed from the power source during charging and the energy fed back to the power source during discharging is calculated. This energy difference is the Coss hysteresis loss ΔE within a single charge-discharge cycle.

[0050] M2 represents the Coss charge / discharge energy curve waveform. Using the cursor function of an oscilloscope, a complete charge / discharge cycle of Coss is captured to obtain the Coss hysteresis loss ΔE at the corresponding voltage level. The formula is as follows:

[0051] This embodiment calculates the energy difference by directly integrating the instantaneous power waveform over time, without relying on any thermal model or mathematical inversion of the equivalent circuit model, resulting in purer and more accurate measurement results. Compared to the indirect calculation of losses using calorimetry, the calculation results of this method directly reflect electrical losses, are unaffected by environmental thermal noise, differences in heat dissipation paths, or thermal time constants, and exhibit good repeatability and consistency.

[0052] In summary, the proposed method for measuring the output capacitance hysteresis loss of power semiconductor switching devices combines a half-bridge circuit with differential detection technology. It directly obtains the charging and discharging current using only the half-bridge circuit and the sensing resistor, and combines this with the electrode voltage. This achieves adjustable operating conditions, pure separation, and rapid and accurate direct electrical measurement, fundamentally solving the comprehensive problems of existing methods in terms of accuracy, adjustability, measurement speed, and purity. It provides more reliable test data for the selection of power semiconductor switching devices and circuit design, and has significant industrial application value. The specific technical effects are as follows: (1) The charging and discharging rates can be adjusted flexibly and independently.

[0053] This invention achieves high-voltage controllable charging and discharging of the device under test using a half-bridge circuit. Furthermore, the magnitude of the Coss charging and discharging current and the dv / dt slope can be independently controlled by adjusting the frequency and duty cycle of the drive signal, the resistance of the sensing resistor Rsense, and the DC bus voltage. This allows the invention to simulate the real dynamic stress conditions of the device under different switching frequencies, different bus voltages, and different ZVS transition times, which is not possible with the quasi-static measurement of the existing Sawyer-Tower method and the fixed resonance conditions of the nonlinear resonance method.

[0054] (2) Direct electrical measurement, without the need for thermal conversion or complex mathematical inversion.

[0055] This invention obtains the charging and discharging current by directly detecting the voltage across a sensing resistor, and calculates the energy difference by synchronously integrating the drain-source voltage. This represents a direct measurement of purely electrical quantities. Compared to calorimetry, which indirectly estimates losses through temperature rise, this method does not require waiting for thermal equilibrium, has a short measurement time, and is unaffected by ambient temperature drift and differences in heat dissipation paths, resulting in high purity and repeatability of the measurement results. Furthermore, since a large-capacity reference capacitor is not required, the systematic error introduced by the parasitic effect of the reference capacitor is eliminated.

[0056] (3) No series reference capacitor is required, eliminating parasitic interference.

[0057] This invention does not introduce a large-value reference capacitor, fundamentally avoiding the adverse effects of the equivalent series resistance, parasitic inductance, and dielectric absorption effect of the reference capacitor on measurement accuracy in the Sawyer-Tower method. The detection resistor Rsense is much smaller than the equivalent impedance of the reference capacitor, and its parasitic parameters have negligible influence on charging and discharging behavior.

[0058] (4) The testing platform is simple and easy to implement.

[0059] This invention requires only a half-bridge circuit, a high-precision sensing resistor, and conventional voltage probes and data acquisition equipment, without the need for special high-voltage reference capacitors, precision calorimeters, or custom resonant inductors. The circuit structure is simple, the components are readily available, and it is suitable for batch testing and comparative evaluation of semiconductor switching devices of different voltage levels and package types, demonstrating good industrial practicality and widespread application value.

[0060] (5) Loss separation is pure.

[0061] This invention short-circuites the control electrode of the device under test with the first main electrode to ensure that the channel is always off. During the charging and discharging process, no channel conduction current is involved, and the measured loss comes entirely from the charging and discharging hysteresis effect of the output capacitor Coss. There is no conduction loss, gate drive loss or body diode reverse recovery loss mixed in, which realizes the pure separation of Coss hysteresis loss and can truly reflect the intrinsic QV hysteresis characteristics of the device.

[0062] (6) The method is highly versatile.

[0063] This invention is applicable to various semiconductor switching devices with output capacitance hysteresis effects, such as MOSFETs, IGBTs, SiC MOSFETs, and GaN HEMTs, and has broad application prospects.

[0064] Based on the same inventive concept, a second aspect of the present invention also provides a device for measuring the hysteresis loss of the output capacitor of a power semiconductor device. See also... Figure 4 , Figure 4 This is a structural block diagram of a power semiconductor switching device output capacitance hysteresis loss measuring device provided in an embodiment of the present invention. The device includes: The half-bridge circuit includes an upper bridge arm switch and a lower bridge arm switch, with the connection point between the upper and lower bridge arm switches serving as the midpoint of the half-bridge. The power semiconductor switch under test is connected in parallel across the lower bridge arm switch, and the control electrode of the power semiconductor switch under test is short-circuited with the first main electrode, so that its channel is always in the off state. A detection resistor is also connected in series in the first main electrode branch of the power semiconductor switch under test. The drive signal generation unit is connected to the control terminals of the upper and lower bridge arm switches and is used to output complementary drive signals to the upper and lower bridge arm switches and set the dead time. A DC power supply, with its positive terminal connected to the first main electrode of the upper bridge arm switching transistor and its negative terminal grounded, is used to provide DC bus voltage to perform the charging and discharging process in step 2. The voltage acquisition unit is connected to the two ends of the detection resistor and the first main electrode and the second main electrode of the power semiconductor switching device under test. It is used to synchronously acquire the voltage between the first main electrode and the second main electrode of the power semiconductor switching device under test and the voltage across the detection resistor during a complete charge and discharge cycle, so as to execute step 3. The data processing unit, connected to the voltage acquisition unit, is used to calculate the charging and discharging current based on the resistance value of the detection resistor and the voltage across the detection resistor, and to calculate the output capacitor hysteresis loss in a single charging and discharging cycle based on the voltage between the first main electrode and the second main electrode and the charging and discharging current, so as to execute step 4.

[0065] It should be noted that, for the device embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and relevant parts can be referred to in the description of the method embodiments. Therefore, all embodiments of the above-described method for measuring the output capacitance hysteresis loss of power semiconductor switching devices are applicable to this device and can achieve the same or similar beneficial effects.

[0066] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A method for measuring the hysteresis loss of the output capacitance of a power semiconductor switching device, characterized in that, Includes the following steps: Step 1: Construct a half-bridge circuit; the half-bridge circuit includes an upper bridge arm switch and a lower bridge arm switch, the connection point of the upper bridge arm switch and the lower bridge arm switch is the midpoint of the half-bridge; the power semiconductor switch device under test is connected in parallel across the two ends of the lower bridge arm switch, and the control electrode of the power semiconductor switch device under test is short-circuited with the first main electrode, so that its channel is always in the off state; a detection resistor is also connected in series in the first main electrode branch of the power semiconductor switch device under test; Step 2: Apply complementary drive signals to the upper bridge arm switch and the lower bridge arm switch, and set a dead time; apply a DC bus voltage to the upper bridge arm switch. When the upper bridge arm switch is turned on, the DC bus voltage charges the output capacitor of the power semiconductor switching device under test through the upper bridge arm switch and the detection resistor; when the lower bridge arm switch is turned on, the output capacitor of the power semiconductor switching device under test discharges through the detection resistor and the lower bridge arm switch. Step 3: During a complete charge-discharge cycle, simultaneously acquire the voltage between the first main electrode and the second main electrode of the power semiconductor switching device under test, as well as the voltage across the detection resistor; Step 4: Calculate the charging and discharging current based on the resistance value of the detection resistor and the voltage across the detection resistor, and calculate the output capacitor hysteresis loss in a single charging and discharging cycle based on the voltage between the first main electrode and the second main electrode and the charging and discharging current.

2. The method according to claim 1, characterized in that, In step 2, the detection resistor is an adjustable resistor. By adjusting the resistance value of the detection resistor, the charging and discharging rate of the output capacitor is adjusted to simulate dynamic stress conditions under different switching frequencies.

3. The method according to claim 1, characterized in that, In step 2, the peak voltage of the power semiconductor switching device under test during the charging and discharging process of the output capacitor is set by adjusting the DC bus voltage, so as to simulate the dynamic stress conditions under different bus voltages.

4. The method according to claim 1, characterized in that, In step 2, the charging and discharging rate of the output capacitor is adjusted by adjusting the frequency of the driving signal to simulate dynamic stress conditions under different switching frequencies.

5. The method according to claim 1, characterized in that, In step 2, the complementary drive signal is output by a signal generator.

6. The method according to claim 1, characterized in that, In step 3, the voltage across the detection resistor is acquired using a first voltage probe; and the voltage between the first main electrode and the second main electrode of the power semiconductor switching device under test is acquired using a second voltage probe.

7. The method according to claim 1, characterized in that, In step 3, the waveforms of the voltage between the first main electrode and the second main electrode, as well as the waveform of the voltage across the detection resistor, are simultaneously acquired and displayed using an oscilloscope.

8. The method according to claim 7, characterized in that, In step 4, the charging / discharging current and the output capacitor hysteresis loss are calculated using the data calculation function of an oscilloscope; wherein, The charging and discharging current is calculated by dividing the voltage across the detection resistor by the resistance value of the detection resistor; The output capacitor hysteresis loss is calculated by integrating the product of the charging / discharging current and the voltage between the first and second main electrodes over a complete charging / discharging cycle.

9. The method according to claim 1, characterized in that, The power semiconductor switching device under test is a MOSFET, the control electrode is the gate, the first main electrode is the drain, and the second main electrode is the source; or, the power semiconductor switching device is an IGBT, the control electrode is the gate, the first main electrode is the collector, and the second main electrode is the emitter.

10. A device for measuring the output capacitance hysteresis loss of a power semiconductor switching device, used to implement the method according to any one of claims 1-9, characterized in that, The device includes: A half-bridge circuit includes an upper bridge arm switch and a lower bridge arm switch, with the connection point between the upper and lower bridge arm switches serving as the midpoint of the half-bridge. A power semiconductor switch under test is connected in parallel across the lower bridge arm switch, and the control electrode of the power semiconductor switch under test is short-circuited to the first main electrode, ensuring that its channel is always in the off state. A detection resistor is also connected in series in the first main electrode branch of the power semiconductor switch under test. A drive signal generation unit is connected to the control terminals of the upper bridge arm switch and the lower bridge arm switch, and is used to output complementary drive signals to the upper bridge arm switch and the lower bridge arm switch and set the dead time. A DC power supply, with its positive terminal connected to the first main electrode of the upper bridge arm switching transistor and its negative terminal grounded, is used to provide DC bus voltage to perform the charging and discharging process in step 2. A voltage acquisition unit is connected to both ends of the detection resistor and between the first main electrode and the second main electrode of the power semiconductor switching device under test. It is used to synchronously acquire the voltage between the first main electrode and the second main electrode of the power semiconductor switching device under test and the voltage across the detection resistor during a complete charge and discharge cycle, so as to execute step 3. The data processing unit, connected to the voltage acquisition unit, is used to calculate the charging and discharging current based on the resistance value of the detection resistor and the voltage across the detection resistor, and to calculate the output capacitor hysteresis loss in a single charging and discharging cycle based on the voltage between the first main electrode and the second main electrode and the charging and discharging current, so as to execute step 4.

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