Test system, test method, device and readable storage medium for integrated circuit

Abstract

The application discloses a test system, a test method, a device and a readable storage medium of an integrated circuit. The method receives and transmits input data of a target test device through an external interface; selects a target test mode corresponding to a test mode selection signal in a test mode of the target test device and a target module to be tested through a selection module, and initializes the test mode, wherein the target test device comprises a plurality of different test modes; selects a routing channel for data interaction between the target module and the test mode based on a number corresponding to the target module carried by a channel selection signal through a multiplexer, and routes the test excitation signal to the target module through the routing channel for testing.

Description

Technical Field

[0001] This application relates to the field of integrated circuit testing technology, and in particular to an integrated circuit testing system, testing method, apparatus and readable storage medium. Background Technology

[0002] In the field of integrated circuit verification, existing integrated circuit testing schemes typically employ independent test mode selection mechanisms. Test mode selection is achieved through dedicated test pins or configuration registers, and the test mode is independent of the functional mode. For example, test mode selection using a JTAG TAP controller requires four additional dedicated pins: Test Clock (TCK), Test Mode Selection (TMS), Test Data Input (TDI), and Test Data Output (TDO), and test mode switching requires multiple clock cycles to complete.

[0003] For multiple modules under test, multiplexers typically employ fixed channel selection logic, using binary address lines to select channels. For example, a 4-channel module requires 2 address lines, and an 8-channel module requires 3 address lines. Furthermore, the test parameters for each channel need to be manually configured.

[0004] Thus, traditional integrated circuit testing methods result in wasted chip pin resources, high testing costs, and low testing efficiency. Summary of the Invention

[0005] The purpose of this application is to provide a test system, test method, apparatus, and readable storage medium for integrated circuits, in order to solve the problem of low test efficiency in integrated circuit test schemes.

[0006] To solve the above-mentioned technical problems, this specification is implemented as follows: Firstly, a test system for integrated circuits is provided, including an external interface, a selection module, and a multiplexer: The external interface is used to receive input data from the target test device, including a test mode selection signal and a test stimulus signal, and to send the test mode selection signal to the selection module and the test stimulus signal to the multiplexer. The selection module is used to select a test mode and the target module to be tested based on the test mode selection signal, and send a channel selection signal to the multiplexer. The multiplexer is used to select a routing channel based on the channel selection signal and send the test excitation signal to the target module through the routing channel.

[0007] Secondly, a testing method for integrated circuits is provided, applied to the system described in the first aspect, the method comprising: The external interface is used to receive and send input data from the target test device. The selection module selects the target test mode and the target module to be tested corresponding to the test mode selection signal in the test mode of the target test device, and initializes the test mode. The target test device includes multiple different test modes. The multiplexer selects a routing channel for data interaction with the target module in the target test mode based on the number corresponding to the target module carried by the channel selection signal, and routes the test excitation signal to the target module for testing through the routing channel.

[0008] Optionally, selecting the target test mode and the target module to be tested corresponding to the test mode selection signal in the test mode of the target test equipment, and initializing the test mode, includes: Based on the mode selection data carried by the test mode selection signal, the target test mode is determined and the preset state machine is triggered to switch from the idle state to the initialization state. Based on the test mode selection signal carrying mode code, the number of the target module is determined; In the initialization state, the counter of the preset state machine is initialized, and the counter is used to count the duration of different states of the target test mode.

[0009] Optionally, selecting the routing channel for data interaction with the target module under the target test mode includes: The target routing table is queried based on the number corresponding to the target module. The target routing table records the mapping relationship between the module number and the routing channel. Check whether the status of the target routing channel corresponding to the target module is idle; If the system is idle, a connection is established between the target module and the target routing channel, and a confirmation signal indicating successful channel establishment is returned.

[0010] Optionally, the preset state machine includes a finite state machine with 5 states, and the switching includes switching from the initialization state to the configuration state, switching from the configuration state to the test state, switching from the test state to the completion state, and switching from the completion state to the idle state; Initializing the counter of the preset state machine in the initialization state includes: When the counter used to count the duration of the initialization state reaches a preset first clock cycle, the finite state machine is triggered to switch from the initialization state to the configuration state. When the confirmation signal is received in the configuration state and the counter used to count the duration of the configuration state reaches a preset second clock cycle, the finite state machine is triggered to switch from the configuration state to the test state. When the test completion signal of the target module is received in the test state and the counter used to count the test state reaches the preset third clock cycle, the finite state machine is triggered to switch from the test state to the completion state. When the counter used to count the completed state reaches a preset fourth clock cycle, the finite state machine is triggered to switch from the completed state to the idle state.

[0011] Optionally, the input data further includes a display mode selection signal, which is used to define the display mode of the test progress and / or define the display mode of the test results; The method further includes: The display mode selection signal is sent to the selection module through the external interface; The selection module parses the display mode selection signal to obtain the corresponding defined display mode and sends it to the multiplexer. The multiplexer monitors the test progress of the target module and receives the test results returned by the target module through the routing channel after the test is completed. Based on the monitored test progress or the received test results, a control signal carrying the display mode is sent to the display module. The control signal is used to control the display module to display the test progress or test results according to the display mode.

[0012] Optionally, it also includes: The selection module outputs test feedback data to the target test device via the external interface. The test feedback data is obtained by the selection module summarizing the test results of multiple modules to be tested sent by the multiplexer.

[0013] Optionally, the target module is one of a plurality of modules to be tested, and the method further includes: After the target module test is completed, the routing channel corresponding to the target module is released through the multiplexer; The step of selecting the next module to be tested from the plurality of modules to be tested through the selection module and returning to the initialization test mode continues until the tests of the plurality of modules to be tested are completed.

[0014] Thirdly, an integrated circuit testing apparatus is provided, including a processor and a memory, the memory storing a program or instructions executable on the processor, the program or instructions, when executed by the processor, implementing the steps of the method described in the second aspect.

[0015] Fourthly, a readable storage medium is provided, on which a program or instructions are stored, which, when executed by a processor, implement the steps of the method described in the second aspect.

[0016] In this embodiment, input data from the target test device is received and sent via an external interface. A selection module selects the target test mode and the target module to be tested corresponding to the test mode selection signal in the test mode of the target test device, and initializes the test mode. The target test device includes multiple different test modes. A multiplexer selects the routing channel for data interaction with the target module in the test mode based on the number corresponding to the target module carried by the channel selection signal, and routes the test excitation signal to the target module for testing through the routing channel. Thus, by multiplexing a single external interface, the test input data of the target test device can be reused, avoiding waste of chip pin resources and reducing the testing cost of integrated circuits. Through the multiplexer and selection module 104 working together, the test channel path can be automatically optimized according to test requirements, enabling rapid switching and comprehensive testing of multiple modules under test, reducing the need for independent test pins, achieving high test coverage, improving test resource utilization and testing efficiency, and enhancing test quality and reliability. Attached Figure Description

[0017] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a structural block diagram of an integrated circuit testing system according to an embodiment of this application.

[0018] Figure 2 This is a flowchart illustrating the testing method for integrated circuits according to an embodiment of this application.

[0019] Figure 3 This is a schematic diagram illustrating the switching principle of a finite state machine according to an embodiment of this application.

[0020] Figure 4 This is a timing flowchart of a testing method for an integrated circuit according to an embodiment of this application.

[0021] Figure 5 This is a structural block diagram of an integrated circuit testing apparatus according to an embodiment of this application. Detailed Implementation

[0022] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. The drawing numbers in this application are only used to distinguish the various steps in the solution and are not used to limit the execution order of the various steps. The specific execution order is subject to the description in the specification.

[0023] To address the problems existing in the prior art, this application provides a test system for integrated circuits, including an external interface, a selection module, and a multiplexer: the external interface is used to receive input data from a target test device, including a test mode selection signal and a test stimulus signal, and to send the test mode selection signal to the selection module and the test stimulus signal to the multiplexer; the selection module is used to select a test mode and a target module to be tested based on the test mode selection signal, and to send a channel selection signal to the multiplexer; the multiplexer is used to select a routing channel based on the channel selection signal, and to send the test stimulus signal to the target module through the routing channel.

[0024] Figure 1 This is a structural block diagram of the integrated circuit testing system according to an embodiment of this application, as shown below. Figure 1 As shown, the integrated circuit test system 100 includes an external interface 102, a selection module 104, and a multiplexer 106.

[0025] The test system is integrated on the chip circuit. The external interface 102 is a metal contact point on the chip package surface used for soldering or connecting external target test equipment. It is the core interface for electrical connection between the internal circuit of the chip and external equipment, such as a pad.

[0026] External interface 102 receives input data from the target test device, including a test mode selection signal and a test excitation signal, and sends the test mode selection signal to selection module 104. Selection module 104 selects the test mode of the target test device and the target module among the multiple modules 10 to be tested based on the test mode selection signal, and generates a channel selection signal according to the selected test mode and target module, and then sends it to multiplexer 106.

[0027] The multiplexer 106 is connected to the external interface 102 and the selection module 104 respectively. The multiplexer 106 selects the routing channel based on the channel selection signal. The external interface 102 sends the test excitation signal in the input data to the multiplexer 106. The multiplexer 106 sends the test excitation signal to the target module through the selected routing channel to realize the test of the target module.

[0028] In this embodiment, by reusing a single external interface, all modules 10 to be tested can be tested as test pins, realizing the reuse of test input data of the target test device, avoiding waste of chip pin resources, and reducing the testing cost of integrated circuits.

[0029] For multiple modules under test, the multiplexer 106 uses the channel selection signal output by the selection module 104 to select the routing channel. Working in conjunction with the selection module 104, it can automatically optimize the test channel path according to test requirements, enabling rapid switching between multiple modules under test. This reduces the need for independent test pins, provides high test coverage, improves test resource utilization and test efficiency, and enhances test quality and reliability.

[0030] This application also provides a testing method for integrated circuits, applicable to, for example... Figure 1 The system described in the embodiments. (As...) Figure 2 As shown, the method includes steps 202 to 206.

[0031] Step 202: Receive and send input data from the target test device through the external interface.

[0032] As described above, the external interface 102 is the core interface for electrical connection between the internal circuitry of the chip containing the test system and the external target test equipment. The external interface 102 receives input data from the target test equipment, including test mode selection signals and test excitation signals, and sends the test mode selection signal to the selection module 104 and the test excitation signal to the multiplexer 106.

[0033] The selection module 104 and the external interface 102 adopt a bidirectional communication protocol, including: an input channel for receiving mode selection signals and test stimulus data from the external target test equipment; and an output channel for feeding back test progress, test results, and diagnostic information to the external target test equipment.

[0034] Correspondingly, the external interface 102 is also used to send the test data related to the target module to be tested transmitted through the output channel to the target test device.

[0035] The bidirectional communication protocol uses a custom frame format, including a frame header (2 bytes), a command word (1 byte), a data field (N bytes), a checksum (1 byte), and a frame trailer (2 bytes); timing requirements: input signal setup time ≥ 5ns, hold time ≥ 3ns.

[0036] For example, the frame format of the mode selection signal sent by the external interface 102 to the selection module 104 is: frame header 0xAA55 + command word 0x01 (mode selection) + data field (mode encoding) + checksum + frame tail 0x55AA.

[0037] The command word 0x01 is the mode selection data carried by the mode selection signal, which is used to select one of the various test modes of the target test equipment; the data field is the mode code carried by the mode selection signal, which is used to determine or select the number of a module to be tested.

[0038] Step 204: Through the selection module, select the target test mode and the target module to be tested corresponding to the test mode selection signal in the test mode of the target test device, and initialize the test mode. The target test device includes a variety of different test modes.

[0039] The target test equipment includes a variety of different test modes, such as eight test modes, including Functional Test Mode, Performance Test Mode, Boundary Scan Test Mode, Built-In Self Test Mode, Analog Module Test Mode, Power Consumption Test Mode, Reserved Mode, and System Diagnostic Mode.

[0040] The selection module 104 selects the test mode of the target test device and the target module from multiple modules 10 to be tested based on the test mode selection signal. The test mode initialization can be performed after the target module is selected and before the test is executed.

[0041] In one embodiment, selecting the target test mode and the target module to be tested corresponding to the test mode selection signal in the test mode of the target test device, and initializing the test mode includes: determining the target test mode and triggering a preset state machine to switch from an idle state to an initialization state based on the mode selection data carried by the test mode selection signal; determining the number of the target module based on the mode code carried by the test mode selection signal; and initializing the counter of the preset state machine in the initialization state, the counter being used to count the duration of different states of the target test mode.

[0042] Selection module 104 is the core control unit of the entire test system, implemented using a state machine architecture. Upon receiving mode selection data, selection module 104 triggers its state machine to transition from the idle state (IDLE) to the initialization state (INIT), initializing its internal registers and counters. The internal registers are used to configure parameters for the duration of different state transitions in the target test mode, and the counters are used to count the duration of different states, enabling automatic switching between them.

[0043] In one embodiment, the preset state machine includes a finite state machine with 5 states. The switching includes switching from the initialization state to the configuration state, from the configuration state to the test state, from the test state to the completion state, and from the completion state to the idle state. Initializing the counter of the preset state machine in the initialization state includes: triggering the finite state machine to switch from the initialization state to the configuration state when the counter used to count the duration of the initialization state reaches a preset first clock cycle; triggering the finite state machine to switch from the configuration state to the test state when the confirmation signal is received in the configuration state and the counter used to count the duration of the configuration state reaches a preset second clock cycle; triggering the finite state machine to switch from the configuration state to the test state when the test completion signal of the target module is received in the test state and the counter used to count the test state reaches a preset third clock cycle; and triggering the finite state machine to switch from the completion state to the idle state when the counter used to count the completion state reaches a preset fourth clock cycle.

[0044] like Figure 3As shown, in this embodiment, the state machine adopts a 5-state finite state machine (FSM) design, including: IDLE (idle state), INIT (initialization state), CONFIG (configuration state), TEST (test state), and COMPLETE (completion state). State transitions are jointly controlled by a mode selection signal and an internal counter. The state machine clock frequency is the system master clock and supports asynchronous reset.

[0045] The state transition logic is as follows: IDLE → INIT: Triggered when a valid mode selection signal is detected at the input of external interface 102 (e.g., a high level lasting ≥2 clock cycles); INIT → CONFIG: Automatically switches when the counter used to count the duration of the initialization state reaches a preset value (e.g., 16 clock cycles by default); CONFIG → TEST: When the confirmation signal confirming the successful establishment of the routing channel between the multiplexer 106 and the target module in the configuration state is valid, that is, when the confirmation signal is received and the counter used to count the duration of the configuration state reaches the preset value, it will automatically switch. TEST → COMPLETE: Automatically switches when the counter that counts the test status reaches the preset test duration or receives a test completion signal. COMPLETE → IDLE: When the counter that counts the completion state reaches a preset value, such as after the completion state has lasted for 8 clock cycles, it automatically switches to the idle state.

[0046] After selecting the target test mode and target module, the selection module 104 generates a channel selection signal and then sends the channel selection signal to the multiplexer 106.

[0047] Step 206: Using the multiplexer, select the routing channel for data interaction with the target module in the target test mode based on the number corresponding to the target module carried by the channel selection signal, and route the test excitation signal to the target module for testing through the routing channel.

[0048] The channel selection signal carries the number corresponding to the target module under test. The multiplexer 106 selects a matching routing channel based on the number to interact with the target module, including the test excitation signal input to the target module and the test response signal output by the target module.

[0049] In one embodiment, selecting a routing channel for data interaction with the target module under the target test mode includes: querying a target routing table based on the number corresponding to the target module, the target routing table recording the mapping relationship between the module number and the routing channel; checking whether the status of the target routing channel matching the number corresponding to the target module is idle; if idle, establishing a connection between the target module and the target routing channel and returning a confirmation signal indicating successful channel establishment.

[0050] The multiplexer 106 is the core module for test signal routing. It employs a dynamic routing algorithm to automatically optimize the test path based on test requirements, enabling multi-channel signal switching. The dynamic routing algorithm process is as follows: It receives the channel selection signal from the selection module 104; queries the routing table to determine the channel number of the target module; checks the status (idle / busy / faulty) of the target channel corresponding to the channel number; if the target channel is idle, it establishes a connection and returns an acknowledgment signal indicating successful channel establishment; if the target channel is busy, it returns a waiting signal and adds the channel to the queue; if the target channel is faulty, it returns an error signal and selects a backup channel.

[0051] The channel selection logic of the multiplexer 106 adopts a priority encoder structure, supporting flexible selection of n modules. The channel encoding adopts binary encoding, and the number of channels n supports powers of 2 such as 2, 4, 8, 16, etc.; the selection signal width is log2n bits (for example, 16 channels require 4 bits of selection signal), and the switching time is, for example, <50ns (from the selection signal being valid to the channel being turned on).

[0052] The multiplexer 106 and each module 10 adopt a bidirectional signal transmission mechanism, including: a direction bit control signal: 1 bit, 0 indicates input (test excitation signal), and 1 indicates output (test response signal).

[0053] In this embodiment, the selection module 104 sends a channel selection signal to the multiplexer 106, in the format: channel number (log2n bits) + enable bit (1 bit) + direction bit (1 bit). The channel number is the number corresponding to the target module carried by the channel selection signal; the enable bit indicates whether the signal is valid; and the direction bit indicates whether the signal is a test excitation signal input to the target module or a test response signal output by the target module.

[0054] The multiplexer 106 receives the channel selection signal, queries the routing table, establishes a routing channel for the signal connection with the target module, and returns a routing channel establishment confirmation signal to the selection module 104, including: channel status (idle / busy / fault), establishment time, signal integrity indicators, etc.

[0055] If the routing channel is successfully established, the multiplexer 106 configures the routing channel of the signal path and prepares to inject test excitation signals into the target module (input) and collect the response signals of the target module (output) based on the routing channel.

[0056] The steps for test stimulus injection and response acquisition are as follows: External interface 102 sends a test stimulus signal to multiplexer 106. The frame format is: frame header 0xAA55 + command word 0x02 (stimulus injection) + data field (vector of test stimulus signal) + checksum + frame tail 0x55AA.

[0057] The multiplexer 106 routes the test excitation signal to the target module through the established routing channel. The signal path is: external interface 102 → multiplexer 106 → input port of the target module.

[0058] The target module processes the test stimulus signal and generates a test response signal, with the response time recorded in a timestamp register. Multiplexer 106 acquires the test response signal from the target module, with the signal path being: target module output port → multiplexer 106 → external interface 102.

[0059] The multiplexer 106 preprocesses the test response signal, including filtering, amplification, and analog-to-digital conversion, and feeds back the response data to the external target test device through the external interface 102. The frame format is: frame header 0xAA55 + command word 0x03 (response feedback) + data field (response data) + checksum + frame tail 0x55AA.

[0060] In one embodiment, the input data further includes a display mode selection signal, which is used to define a display mode for test progress and / or a display mode for test results; the method further includes: sending the display mode selection signal to the selection module through the external interface; the selection module parsing the display mode selection signal to obtain the corresponding defined display mode and sending it to the multiplexer; the multiplexer monitoring the test progress of the target module and receiving the test results returned by the target module through the routing channel after the test is completed; and based on the monitored test progress or the received test results, sending a control signal carrying the display mode to the display module, which is used to control the display module to display the test progress or test results according to the display mode.

[0061] In this embodiment, the input data also includes a display mode selection signal. The external interface 102 can input the display mode selection signal and the test mode selection signal together into the selection module 104. The display mode selection signal is used to define the display mode of the target module at different test progresses during the test process, and / or define the display mode of the final test result. Different display modes are displayed through the display module.

[0062] The selection module 104 parses the received display mode selection signal, obtains the corresponding defined display mode, and sends it to the multiplexer 106. The multiplexer 106 communicates with the target module 10 via a corresponding established routing channel, monitors the test progress of the target module, and receives the test results returned by the target module through the routing channel after the test is completed. Test progress includes "test in progress" or "test completed," and test results include "test passed" and "test failed."

[0063] Based on the monitored test progress or the received test results, the multiplexer 106 sends a control signal to the display module. The control signal carries the corresponding display mode and is used to control the display module to display the test progress or test results according to the display mode.

[0064] The display module can be Figure 2 LED module 108, LED module 108 is the output indicator unit of the test system, for example including 5 LED output ports (such as... Figure 2 (Ports 1 to 5). Each LED output port of LED module 108 includes output enable control, supporting independent enabling / disabling of each port.

[0065] The display mode definition of LED module 108 is as follows: For example, Mode 0: All off (default state); Mode 1: All constantly on (test passed indicator); Mode 2: Ports 1-3 on, ports 4-5 off (partial pass indicator); Mode 3: Ports 1-5 flash sequentially (test in progress indicator); Mode 4: Ports 1-5 breathing light effect (system ready indicator); Mode 5: Ports 1-5 flashing alternately (fault warning indicator); Mode 6: Ports 1-5 flashing rapidly (emergency fault indicator); Mode 7: Custom mode for ports 1-5 (user-defined).

[0066] The timing parameters of LED module 108 include response time, for example, less than 100μs (when a control signal is sent from multiplexer 106 to LED module 108 to light up the LEDs of the corresponding display mode).

[0067] In this embodiment, the multiplexer 106 sends a control signal to the LED module 108 to achieve visual feedback on the test progress and test results.

[0068] The LED module 108 provides real-time visual indication of the testing process, featuring fast response and supporting eight predefined display modes to meet the needs of different testing scenarios. It can also provide fault indication, such as real-time indication of overcurrent, short circuit, and open circuit faults.

[0069] After the test begins, the multiplexer 106 sends a control signal to the LED module 108 indicating that the test has started, triggering the LED module 108 to enter the "Test in progress" display mode; after the test is completed, the multiplexer 106 sends a control signal to the LED module 108 indicating that the test is complete, triggering the LED module 108 to enter the "Test complete" display mode, and sends a control signal indicating the test result, triggering the LED module 108 to enter the "Test passed" or "Test failed" display mode.

[0070] LED module 108 receives control signals and drives the corresponding LED output ports (port 1 to port 5) to display the corresponding display mode.

[0071] In one embodiment, such as Figure 2 As shown, after the state machine switches to the initialization state, the selection module 104 also sends an initialization control signal to the LED module 108 to control the LED module 108 to enter the "system ready" display mode (breathing light effect).

[0072] In this embodiment, the LED module 108 is deeply integrated with the testing system, enabling real-time test status feedback in test mode. This improves the real-time observability of the testing process, allowing testers to intuitively understand the test progress and results. Furthermore, the feedback mechanism can reduce latency to the microsecond level, significantly improving test debugging efficiency.

[0073] Furthermore, the method also includes: outputting test feedback data to the target test device via the external interface through the selection module, wherein the test feedback data is obtained by the selection module summarizing the test results of multiple modules to be tested sent by the multiplexer.

[0074] In this embodiment, in addition to sending control signals to the LED module 108 to control the LED module 108 to display the test progress and test results according to the display mode, the multiplexer 106 sends the test results of the target module 10 to the selection module 104 after the target module 10 has been tested.

[0075] After receiving the test results of all modules to be tested, module 104 summarizes the test results of all modules 10, including: number of passes, number of failures, and fault type statistics, and generates a test report. For example, the format of the test report is: test timestamp + module number + test result + performance parameters. This yields the test feedback data for this test mode, and the test feedback data is sent to the external target test device through the output channel corresponding to external interface 102. For example, the frame format of the test feedback data is: frame header 0xAA55 + command word 0x04 (test report) + data field (test report) + checksum + frame tail 0x55AA.

[0076] In one embodiment, the target module is one of a plurality of modules to be tested, and the method further includes: after the target module is tested, releasing the routing channel corresponding to the target module through the multiplexer; selecting the next module to be tested among the plurality of modules to be tested through the selection module and returning to the initialization test mode, until the plurality of modules to be tested are tested.

[0077] In this embodiment, a cyclical testing process and pipeline testing mechanism are employed for multiple modules 10 to be tested. After completing the test of the current module 10, the selection module 104 can update the channel selection sequence pointer, send a new channel selection signal to the multiplexer 106, and switch to the routing channel selection of the next module 10. The multiplexer 106 releases the resources of the current routing channel and repeats the steps of establishing a new routing channel connection and routing the routing test stimulus signal to the next module 10 for testing.

[0078] All modules 10 were tested sequentially, and a pipeline mechanism was used to improve efficiency.

[0079] Below, in conjunction with Figure 4 The timing sequence of the integrated circuit testing method according to the embodiments of this application is described.

[0080] like Figure 4 As shown, it includes the following steps: Step 1: External interface 102 sends the test mode selection signal and display mode selection signal input by the target test device to selection module 104; Step 2: External interface 102 sends the test excitation signal input from the target test device to multiplexer 106; Step 3: The selection module 104 selects the test mode and the target module 10 to be tested based on the test mode selection signal, defines the display mode based on the display mode selection signal, and sends the channel selection signal and display mode to the multiplexer 106. Step 4: The multiplexer 106 selects a routing channel and establishes a connection with the target module 10 based on the channel selection signal; Step 5: Target module 10 returns a confirmation signal to multiplexer 106 confirming the successful establishment of the routing channel; Step 6: The multiplexer 106 injects a test excitation signal into the target module 10 via the routing channel; Step 7: The multiplexer 106 collects the test response signal from the target module 10 via the routing channel; Step 8: Based on the display mode and the test progress of the target module 10 being monitored, the multiplexer 106 sends a corresponding control signal to the LED module 20, and the LED module 20 displays the corresponding test progress. Step 9: Based on the display mode and the test results of the monitored target module 10, the multiplexer 106 sends the corresponding control signal to the LED module 20, and the LED module 20 displays the corresponding test results. Step 10: The multiplexer 106 sends the test results of the target module 10 to the selection module 104; Step 11: After receiving the test results of all templates, the selection module 104 summarizes the test feedback data and sends it to the external interface 102, which then outputs it to the target test device.

[0081] In this embodiment, input data from the target test device is received and sent via an external interface. A selection module selects the target test mode and the target module to be tested corresponding to the test mode selection signal in the test mode of the target test device, and initializes the test mode. The target test device includes multiple different test modes. A multiplexer selects the routing channel for data interaction with the target module in the test mode based on the number corresponding to the target module carried by the channel selection signal, and routes the test excitation signal to the target module for testing through the routing channel. Thus, by multiplexing a single external interface, the test input data of the target test device can be reused, avoiding waste of chip pin resources and reducing the testing cost of integrated circuits. Through the multiplexer and selection module 104 working together, the test channel path can be automatically optimized according to test requirements, enabling rapid switching and comprehensive testing of multiple modules under test, reducing the need for independent test pins, achieving high test coverage, improving test resource utilization and testing efficiency, and enhancing test quality and reliability.

[0082] Optionally, such as Figure 5As shown, this application embodiment also provides an integrated circuit testing apparatus 2000, including a processor 2400 and a memory 2200. The memory 2200 stores a program or instructions that can be run on the processor 2400. When the program or instructions are executed by the processor 2400, they implement the various steps of the above-described integrated circuit testing method embodiment and can achieve the same technical effect. To avoid repetition, they will not be described again here.

[0083] This application also provides a readable storage medium storing a program or instructions. When executed by a processor, the program or instructions implement the various processes of any of the above-described integrated circuit testing method embodiments and achieve the same technical effect. To avoid repetition, further details are omitted here. The readable storage medium includes computer-readable storage media, such as read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0084] This application also provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program. The computer program is operable to cause a computer to execute various processes of any of the above-described integrated circuit testing method embodiments and achieve the same technical effect. To avoid repetition, it will not be described again here.

[0085] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0086] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0087] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A testing system for integrated circuits, characterized in that, Includes external interfaces, selection modules, and multiplexers: The external interface is used to receive input data from the target test device, including a test mode selection signal and a test stimulus signal, and to send the test mode selection signal to the selection module and the test stimulus signal to the multiplexer. The selection module is used to select a test mode and the target module to be tested based on the test mode selection signal, and send a channel selection signal to the multiplexer. The multiplexer is used to select a routing channel based on the channel selection signal and send the test excitation signal to the target module through the routing channel.

2. A testing method for integrated circuits, characterized in that, Applied to the system of claim 1, the method comprises: The external interface is used to receive and send input data from the target test device. The selection module selects the target test mode and the target module to be tested corresponding to the test mode selection signal in the test mode of the target test device, and initializes the test mode. The target test device includes multiple different test modes. The multiplexer selects a routing channel for data interaction with the target module in the target test mode based on the number corresponding to the target module carried by the channel selection signal, and routes the test excitation signal to the target module for testing through the routing channel.

3. The method as described in claim 2, characterized in that, Selecting the target test mode and the target module to be tested corresponding to the test mode selection signal in the test mode selection of the target test equipment, and initializing the test mode, includes: Based on the mode selection data carried by the test mode selection signal, the target test mode is determined and the preset state machine is triggered to switch from the idle state to the initialization state. Based on the test mode selection signal carrying mode code, the number of the target module is determined; In the initialization state, the counter of the preset state machine is initialized, and the counter is used to count the duration of different states of the target test mode.

4. The method as described in claim 3, characterized in that, Selecting the routing channel for data interaction with the target module under the target test mode includes: The target routing table is queried based on the number corresponding to the target module. The target routing table records the mapping relationship between the module number and the routing channel. Check whether the status of the target routing channel corresponding to the target module is idle; If the system is idle, a connection is established between the target module and the target routing channel, and a confirmation signal indicating successful channel establishment is returned.

5. The method as described in claim 4, characterized in that, The preset state machine includes a finite state machine with 5 states, and the switching includes switching from the initialization state to the configuration state, switching from the configuration state to the test state, switching from the test state to the completion state, and switching from the completion state to the idle state. Initializing the counter of the preset state machine in the initialization state includes: When the counter used to count the duration of the initialization state reaches a preset first clock cycle, the finite state machine is triggered to switch from the initialization state to the configuration state. When the confirmation signal is received in the configuration state and the counter used to count the duration of the configuration state reaches a preset second clock cycle, the finite state machine is triggered to switch from the configuration state to the test state. When the test completion signal of the target module is received in the test state and the counter used to count the test state reaches the preset third clock cycle, the finite state machine is triggered to switch from the test state to the completion state. When the counter used to count the completed state reaches a preset fourth clock cycle, the finite state machine is triggered to switch from the completed state to the idle state.

6. The method as described in claim 5, characterized in that, The input data also includes a display mode selection signal, which is used to define the display mode of the test progress and / or define the display mode of the test results; The method further includes: The display mode selection signal is sent to the selection module through the external interface; The selection module parses the display mode selection signal to obtain the corresponding defined display mode and sends it to the multiplexer. The multiplexer monitors the test progress of the target module and receives the test results returned by the target module through the routing channel after the test is completed. Based on the monitored test progress or the received test results, a control signal carrying the display mode is sent to the display module. The control signal is used to control the display module to display the test progress or test results according to the display mode.

7. The method as described in claim 6, characterized in that, Also includes: The selection module outputs test feedback data to the target test device via the external interface. The test feedback data is obtained by the selection module summarizing the test results of multiple modules to be tested sent by the multiplexer.

8. The method as described in claim 2, characterized in that, The target module is one of multiple modules to be tested, and the method further includes: After the target module test is completed, the routing channel corresponding to the target module is released through the multiplexer; The step of selecting the next module to be tested from the plurality of modules to be tested through the selection module and returning to the initialization test mode continues until the tests of the plurality of modules to be tested are completed.

9. A testing apparatus for integrated circuits, characterized in that, It includes a processor and a memory, the memory storing a program or instructions that can run on the processor, the program or instructions being executed by the processor to implement the steps of the method as described in any one of claims 2-8.

10. A readable storage medium, characterized in that, The readable storage medium stores a program or instructions that, when executed by a processor, implement the steps of the method as described in any one of claims 2-8.

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